Driver and control of line power extension circuit for ac-DC converter

Abstract

A line power extension circuit and corresponding driving and control methods are proposed to reduce a capacitor requirement (e.g., size) of AC-DC converters. In particular, a low-side line power extension circuit is proposed (e.g., having a MOSFET switch Q), along with approaches for providing a sensing and control circuit to decide when to turn on and to turn off the switch Q. Relative to an alternate circuit, the Low-Side Line Power Extension Circuit (LS-LPEC) provides different technical characteristics that can be benefit in various scenarios as described herein.

Description

DRIVER AND CONTROL OF LINE POWER EXTENSION CIRCUIT FOR AC-DC CONVERTER CROSS-REFERENCE

[0001] This application claims all benefit, including priority to, US Application Nos. 63 / 602442 and 63 / 556988, filed 23-Nov-2023 and 23-Feb-2024, respectively. Both applications are entitled: DRIVER AND CONTROL OF LINE POWER EXTENSION CIRCUIT FOR AC-DC CONVERTER. FIELD

[0002] Embodiments of the present disclosure generally relate to the field of electronics, and more specifically, embodiments relate to devices, systems and methods for operating an AC-DC converter, and in particular, a line power extension circuit thereof. INTRODUCTION

[0003] Since 2012, the USB Power Delivery (USB PD) specification has standardized the charging protocols for a majority of consumer electronic devices. USB PD facilitates charger reusability across different devices and minimizes electronic waste. USB PD enables negotiation between the load and power source for multiple levels of power delivery. It proves to be highly advantageous in providing power to multiple devices, including smartphones, tablets, and laptops.

[0004] For USB-PD power adapters without PFC stage, it is common to adopt a single- stage architecture. The full-bridge diode rectifier converts the AC input <com:Math><semantics>Vac<annotation encoding="application / x-tex">V_{ac}< / annotation>< / semantics>< / com:Math> into a stable bus voltage <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> with the assistance of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. The subsequent DC-DC converter serves the purpose of delivering adjustable output voltages to the load.

[0005] USB-PD power adapters have significantly reduced in size over time to meet consumers' needs. Due to the implementations of fast-switching nature of wide-band-gap semiconductors, the size of the magnetic components within these adapters has been reduced significantly.

[0006] The input capacitor <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, which occupies roughly a quarter of the converter volume, barely reduces its size as compared to decades ago. SUMMARY

[0007] While many size aspects of the USB-PD power adaptors have been reduced significantly, the input capacitor <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, which occupies roughly a quarter of the converter volume has barely reduced in size as compared to decades ago. Accordingly, a proposed circuit is provided, which is adapted to reduce the required capacitance for <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> and improve the power density of the whole converter system.

[0008] The proposed circuit is denoted as a Low-Side Line Power Extension Circuit (LS- LPEC), and its accompanying driving and control method are described herein. It is important to note that each of these (extension circuit and driving / control approach) can be considered separate independent inventive aspects, and in some embodiments, are combined together for interoperation. Independent operation is also possible.

[0009] The circuit is denoted as a "low-side" line power extension circuit to differentiate from a "high-side" line power extension circuit.

[0010] The line power extension circuit is a power converter circuit that includes a rectifier circuit having first and second input terminals that receive an AC input voltage and first and second output terminals that output a DC bus voltage. There is a series circuit comprising a switch connected in series with an input capacitor connected across the first and second output terminals. A controller controls the switch so that the switch is on at least during a period when a magnitude of the AC input voltage is less than a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage. Power adapters incorporating these features benefit from low component count, reduced component voltage stress, reduced size and weight, and low cost, making then suitable for a range of portable devices such as laptop computers and cellphones.

[0011] "Low-side" refers to the proposed positioning of the switch and the capacitor, Cin, which is modified, and this modification includes connecting a drain terminal of the switch Q to the ground point, which is the negative terminal of the input diode bridge (anode terminal of diodes D3 and D4). The source terminal of MOSFET Q is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode of D1, D2).

[0012] Structurally, the circuit can include a number of diodes, D1-D4, similar to a full- bridge rectifier, and additionally, a switch (e.g., a N-channel MOSFET, but can also be a BJT, IGBT) is added in series with <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, positioned below it. This configuration allows for strategic adjustment of the AC power conduction angle, thereby maximizing the utilization of AC input power and reducing the required capacitance for <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>.

[0013] Corresponding driver and controller circuits are also proposed. The driver and controller circuits are configured to regulate the switching states of Q.

[0014] The control circuit is configured to decide the time instant when the MOSFET should be turned and the time instant when the MOSFET should be turned off. Its output is a logic signal (high and low). The drive circuit is used to convert the logic signal to the gate- source terminal of the MOSFET Q. As described herein, there are proposed a number of different variations of control circuits and a couple of driver circuits, and it is important to note the innovative features of these circuits and their corresponding control logic.

[0015] The voltage of gate <com:Math><semantics>(QG)<annotation encoding="application / x-tex">(Q_G)< / annotation>< / semantics>< / com:Math> is set to a high level with respect to the voltage of source <com:Math><semantics>(QS)<annotation encoding="application / x-tex">(Q_S)< / annotation>< / semantics>< / com:Math> to turn ON Q. Conversely, when Q needs to be turned OFF, the voltage of <com:Math><semantics>QG<annotation encoding="application / x-tex">Q_G< / annotation>< / semantics>< / com:Math> is set to a low level with respect to the voltage of Q<com:Sub>S< / com:Sub>. The ON or OFF logic of Q is determined by the controller circuit (the circuit is configured for determining whether Q should be in an ON or OFF state).

[0016] The underlying objective of line power extension control is to maximize the utilization of AC input power, as for a given minimum bus voltage <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, line power extension control can effectively reduce the required capacitance of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, and for a predetermined capacitance of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, line power extension control enables the boost of the minimum bus voltage <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math>. The approach is directed to an improved AC power conduction angle, and thus the total AC power conduction angle can be extended. During this extended angle, the DC-DC converter draws power directly from the AC input through the rectifier diodes, thereby significantly reducing the required discharge energy from the input capacitance <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>.

[0017] The line voltage and / or bus voltage is sensed in either analog or digital format, and this is used to determine an operational mode (i.e., whether LS-LPEC is required). LS-LPEC is activated when the magnitude of the AC voltage is low, i.e., below <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, such as 100 <com:Math><semantics>Vac<annotation encoding="application / x-tex">V_{ac}< / annotation>< / semantics>< / com:Math>.

[0018] In operation, the circuit imparts different control approaches during a number of different time periods, described herein, where different power conduction and extension angles are provided (States A, B, C), controlling operation in respect of different powering periods. To support these approaches, four sensing and control logic circuits are proposed in an embodiment, but it is important to note that other variations are possible. It is important to note that timing control variations are also described, including a simpler sensing circuit if a less accurate timing is acceptable in the practical usage scenario. The simpler sensing circuit utilizes a proposed delay circuit.

[0019] In operation, the approach includes turning off the switch Q when the input AC voltage is at peak, and it can be noted that Q can be turned off any time during State B.

[0020] Performance comparison results are provided, and improvements are described in relation to a simulation. In particular, reduction is possible either in a capacitor size (e.g., less Farads required), or if a capacitor size is held the same, then other parameters can be advantageously adjusted. In some embodiments, reduction in both capacitor size and other parameters are possible. From a practical perspective, these improvements allow for a reduction in cost or complexity, and these savings can then be utilized to improve other performance aspects of the circuit, or power adapter. For example, the circuit proposed herein can be used to improve the power adapter, which includes the DC-DC converter.

[0021] The circuit can be provided in different practical formats, such as a power adapter circuit module, such as one configured for USB type-C power delivery, having a reduced buffering capacitor or increased performance, or both. The accompanying circuits can be coupled together as part of or together as a single package.

[0022] The line power extension circuit can also be contemplated as a standalone circuit, and the accompanying driver and circuit circuits can also be contemplated as standalone circuits. In another embodiment, a plurality of line power extension circuits can be controlled by a central set of driver and control circuits.

[0023] The specific driver and control circuits may include on-board or be coupled with machine interpretable instructions, such as gate control instructions, stored thereon in the form of non-transitory computer readable media or instructions which are executed by a gating control microprocessor to perform the gating control methods.

[0024] Circuit control, for example, can be generated through pulse waveforms generated by a pulse width modulator device that are utilized to control gate operation through changing a voltage at a gate terminal of the switch. DESCRIPTION OF THE FIGURES

[0025] In the figures, embodiments are illustrated by way of example. It is to be expressly understood that the description and figures are only for the purpose of illustration and as an aid to understanding.

[0026] Embodiments will now be described, by way of example only, with reference to the attached figures, wherein in the figures:

[0027] FIG. 1 is a schematic diagram showing a conventional full bridge rectifier without a power factor correction (PFC) in accordance with the prior art.

[0028] FIG. 2 is a two-dimensional graph showing the waveform of the conventional full bridge rectifier shown in FIG. 1 in accordance with the prior art.

[0029] FIG. 3A is a schematic diagram showing an exemplary line power extension circuit, in which an N-channel MOSFET Q is added to the full bridge rectifier.

[0030] FIG. 3B is a schematic diagram showing an isolated view of the MOSFET Q in accordance with the prior art.

[0031] FIG. 4 is a two-dimensional graph showing the waveforms of the line power extension circuit. It is important to note that in the proposed approach, similar performance can be achieved, but the low side approach is able to simplify and improve control and operational aspects.

[0032] FIG. 5A is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State A.

[0033] FIG. 5B is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State B.

[0034] FIG. 5C is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State C.

[0035] FIG. 6 is a schematic diagram highlighting the line extension circuit together with its driver and the sensing circuit.

[0036] FIG. 7 is a two-dimensional graph showing the simulation results of the required capacitance for both the line power extension method and conventional full bridge for different <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> designs and 60 W load.

[0037] FIG. 8 is a two-dimensional graph showing the comparison of the minimum bus voltage between the conventional full bridge and the line extension circuit for different <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> values.

[0038] FIG. 9 is a schematic diagram of a conventional full-bridge diode rectifier.

[0039] FIG. 10 illustrates two-dimensional graphs showing the key waveforms of the conventional full-bridge diode rectifier shown in FIG. 9.

[0040] FIG. 11A is a schematic diagram showing an exemplary low-side line power extension circuit.

[0041] FIG. 11B is a schematic diagram showing the complete control and driving architecture of the low-side line power extension circuit shown in FIG. 11A.

[0042] FIG. 12 is a schematic diagram showing a conventional high-side line power extension circuit.

[0043] FIG. 13 illustrates two-dimensional graphs showing the key waveforms of the low- side line power extension circuit shown in FIGS. 11A and 11B.

[0044] FIG. 14 is a schematic diagram showing a driver circuit #1 for MOSFET Q.

[0045] FIG. 15 illustrates two-dimensional graphs showing the waveforms of the driver circuit #1 shown in FIG. 14.

[0046] FIG. 16 is a schematic diagram showing a driver circuit #2 for MOSFET Q.

[0047] FIG. 17 illustrates two-dimensional graphs showing the waveforms of the driver circuit #2 shown in FIG. 16.

[0048] FIG. 18 is a schematic diagram of an exemplary controller circuit #1.

[0049] FIG. 19 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 18.

[0050] FIG. 20 is a schematic diagram of an exemplary controller circuit #2.

[0051] FIG. 21 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 20.

[0052] FIG. 22 is a schematic diagram of an exemplary controller circuit #3.

[0053] FIG. 23 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 22.

[0054] FIG. 24 is a schematic diagram of an exemplary controller circuit #4.

[0055] FIG. 25 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 24.

[0056] FIG. 26 is a two-dimensional graph showing the simulation results of the required capacitance for both LS-LPEC and conventional full bridge for different Vbus min designs and 60 W load.

[0057] FIG. 27 is a two-dimensional graph comparing the minimum bus voltage between the conventional full bridge and LS-LPEC for different Cin values.

[0058] FIG. 28 is a two-dimensional graph showing the simulated dynamic performance of LS-LPEC when input AC voltage transitions from 190 Vac to 100 Vac under a constant load power of 65 W.

[0059] FIG. 29 is a two-dimensional graph showing the simulated dynamic performance of LS-LPEC when input AC voltage transitions from 100 Vac to 190 Vac under a constant load power of 65 W. DETAILED DESCRIPTION

[0060] The present application relates to a line power extension circuit and its driving and control method to reduce a capacitor requirement (e.g., size) of AC-DC converters. In particular, a low-side line power extension circuit is proposed (e.g., having a MOSFET switch Q), along with approaches for providing a sensing and control circuit to decide when to turn on and to turn off the switch Q. Relative to an alternate circuit, the Low-Side Line Power Extension Circuit (LS-LPEC) provides different technical characteristics that can be benefit in various scenarios as described herein.

[0061] As shown in FIG. 1, a diode bridge 100 plus a buffering capacitor is commonly used for AC-DC conversion with no power factor correction requirement. The circuit could be connected to a following stage of DC-DC converter as needed to have a regulated DC voltage. In such case, Cin value is a key design factor because it determines the input voltage range for the DC-DC converter. With a larger capacitor, the bus voltage will be higher, and the operation of DC-DC converter will be more optimized.

[0062] FIG. 2 is a plot 200 that illustrates the waveform of the conventional full bridge rectifier. |vac| is the absolute value of the AC line voltage. V<com:Sub>bus< / com:Sub> is the voltage on the input capacitor Cin, which is also the bus voltage for the following DC-DC converter. |iac is the absolute value of the input current from the AC line.

[0063] When V<com:Sub>bus< / com:Sub> is lower than the line voltage, the capacitor will be charged to the peak line voltage. After the peak, Cin will be discharged to power the load before its voltage drops below the line again in the next half line cycle.

[0064] It is noted that in the conventional circuit, the AC line provides power only before its peak, despite the fact that the line voltage remains sufficiently high for usability even after the peak. If the power after the peak can be used, effectively the capacitor discharging time is reduced. Therefore, the required capacitor value can be reduced as well as the size. Alternatively, with the same capacitor value, Vbus_min can be increased, from which the operation of DC-DC converter can benefit.

[0065] An Embodiment of Line Power Extension and its Driver Circuit

[0066] FIG. 3A shows one embodiment of the proposed line power extension circuit 300A, in which an N-channel MOSFET Q 302 is added to the conventional full bridge rectifier.

[0067] In a prior approach, MOSFET Q 302 is connected to the positive end of the bus, and the capacitor is connected to the negative end of the bus, as shown in FIG. 3B. With the connection as shown in FIG. 3B, the source of switch Q (S, as shown in FIG. 3B) is connected to the output of the diode bridge and the drain of switch S (D as shown in FIG. 3B) is connected to the positive terminal of the input capacitor, Cin.

[0068] It is observed that the source terminal of Q (S, as shown in FIG. 3B) is at the highest voltage potential. In order to turn on switch Q, the gate voltage of MOSFET Q 302 (G as shown in FIG. 3B) should be higher than the highest DC voltage. For a typical AC to DC application, this voltage would be close to 400V. Therefore, high voltage, such as 400V, is needed from the control circuit. This increases the circuit complexity and cost.

[0069] This present application contemplates using the circuit as shown in FIG. 3A instead to achieve the same objective with several benefits, as described below, yielding a different set of technical characteristics.

[0070] As shown in FIG. 3A, the positive terminal of input capacitor, C<com:Sub>in< / com:Sub>, is connected to the output of the diode bridge, (cathode of diode D1 and diode <com:Math><semantics>D2<annotation encoding="application / x-tex">D_2< / annotation>< / semantics>< / com:Math>), the negative terminal of Cin is connected to the source terminal of Q (S as shown in FIG. 3A). The drain terminal of Q (D as shown in FIG. 3A) is connected to the ground (negative voltage), or the anode of diode D<com:Sub>3< / com:Sub>, and diode D<com:Sub>4< / com:Sub>. Comparing FIG. 3A and FIG. 3B, the difference is that the MOSFET Q 302 is moved from the positive terminal of the input capacitor Cin to the negative terminal of the input capacitor Cin. Therefore, these two circuits will produce the same effect to the overall operation of the AC to DC rectifier, such as shown in FIG. 9, FIG. 11A.

[0071] In other words, the proposed circuit shown in FIG. 3A will achieve the same performance as the circuit shown in FIG. 3B. However, a core advantage of the circuit of FIG. 3A is that this change will significantly simplify the turn-on and turn-off circuit (also called driver circuit) for MOSFET Q 302, and this is a non-trivial change that yields specific technical benefits, improving the performance and operation of the circuit relative to the circuit of FIG. 3B.

[0072] It is noted that in the present application, a MOSFET is used as an example for the switch. Other switches, such as BJT with an anti-parallel diode, an IGBT with an anti- parallel diode, etc., can also be used.

[0073] An embodiment of a driver circuit 104 for Q is proposed as well consisting of two resistors <com:Math><semantics>R1<annotation encoding="application / x-tex">R_1< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math>, two Zener diodes <com:Math><semantics>Dz1<annotation encoding="application / x-tex">D_{z1}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Dz2<annotation encoding="application / x-tex">D_{z2}< / annotation>< / semantics>< / com:Math>, a low voltage low current switch, shown as MOSFET Q1 in FIG. 3A. A BJT can also be used as Q1. In other embodiments, R<com:Sub>2< / com:Sub> and <com:Math><semantics>Dz1<annotation encoding="application / x-tex">D_{z1}< / annotation>< / semantics>< / com:Math> can be optional, and Q1 can be other types of switching devices, including but not limited to an NPN BJT, etc.

[0074] FIG. 4 shows the key waveforms 400 of the line power extension circuit as shown in FIG. 3. V<com:Sub>bus< / com:Sub> is the output voltage of the line power extension circuit, as well as the input voltage for the next stage DC-DC stage, which is well known and is not shown in FIG. 3. |vac| is the absolute value of the AC input. <com:Math><semantics>iac<annotation encoding="application / x-tex">i_{ac}< / annotation>< / semantics>< / com:Math> is the AC input current. <com:Math><semantics>VQq<annotation encoding="application / x-tex">V_{Qq}< / annotation>< / semantics>< / com:Math> is the gate-source voltage of switch Q. <com:Math><semantics>VQ1g<annotation encoding="application / x-tex">V_{Q1g}< / annotation>< / semantics>< / com:Math> is the gate-source voltage switch Q1.

[0075] The detailed operation in the positive half line cycle is shown in FIG. 5A, FIG. 5B, and FIG. 5C, at 500A, 500B, and 500C. The operation waveforms are shown in FIG. 4. The negative half cycle has a similar operation. In operation, the approach includes turning off the switch Q when the input AC voltage is at peak (t1 in FIG. 13), and it can be noted that Q can be turned off any time during State B.

[0076] State A [t<com:Sub>0< / com:Sub>, t<com:Sub>1< / com:Sub>]: D<com:Sub>1< / com:Sub> and D<com:Sub>4< / com:Sub> start to conduct at t<com:Sub>0< / com:Sub>, at which time vac rises to equal of <com:Math><semantics>Vbus min<annotation encoding="application / x-tex">V_{\text{bus min}}< / annotation>< / semantics>< / com:Math> (as shown in FIG. 4). From <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, the capacitor voltage will increase with vac. During this process, S is preferred to be turned on to reduce the conduction loss. In an ideal case, MOSFET Q 302 should be turned off at t<com:Sub>1< / com:Sub>, at which the capacitor voltage reaches the peak value. However, in practical implementation, MOSFET Q 102 can be turned off any time between t<com:Sub>0< / com:Sub> and t<com:Sub>1< / com:Sub> to avoid late turn-off. Even when MOSFET Q 102 is turned off, the input capacitor, Cin, can still be charged through body diode of MOSFET Q 102 to the peak value of the AC line voltage. The power flow is shown in FIG. 5A as a solid line. The AC current flows through diode D₁ and D₄. Part of the AC current charges Cin and part of the AC current flows to the input of the DC-DC converter, which is not shown in FIG. 5A, but shown in FIG. 11B.

[0077] During this state, the gate of Q1 should remain low so that Q1 is off. The gate capacitor of MOSFET Q 102, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math>, as shown in FIG. 5A, will be charged by the bus voltage through R<com:Sub>1< / com:Sub>, Zener diode Dz2, and the channel of MOSFET Q 302 (if the MOSFET Q 302 is turned on), or through the body diode of MOSFET Q 302 (Ds, if MOSFET Q 302 is not turned on yet). The gate voltage of MOSFET Q 302 should be clamped by <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math> and / or <com:Math><semantics>Dz1<annotation encoding="application / x-tex">D_{z1}< / annotation>< / semantics>< / com:Math>. In case of startup or other cases that S is not conducting, Cgs will be charged through the body diode D<com:Sub>s< / com:Sub>, and eventually turn on MOSFET Q 302.

[0078] State B [t<com:Sub>1< / com:Sub>, t<com:Sub>2< / com:Sub>]: At t<com:Sub>1< / com:Sub>, MOSFET Q1 302 is turned on so that the gate capacitor of MOSFET Q 302, C<com:Sub>gs< / com:Sub>, will be discharged through Q<com:Sub>1< / com:Sub> and the channel of Q as long as Q conducts current. When the gate source voltage of Q, V<com:Sub>qs< / com:Sub>, reaches its threshold voltage, MOSFET Q 302 will be off. Then the gate capacitor will be discharged through R<com:Sub>2< / com:Sub>. When MOSFET Q is turned off at t<com:Sub>1< / com:Sub>, the capacitor is disconnected from the load, thus the capacitor voltage will remain at the peak value of the AC line voltage. The load is powered by the AC line voltage directly during t<com:Sub>1< / com:Sub> to t<com:Sub>2< / com:Sub>, and the AC current equals to the input current drawn by the DC-DC converter, Idc, as shown in FIG. 11A. Due to this extended conduction time of the line power, i<com:Sub>ac< / com:Sub> is lower than the conventional full bridge. During t<com:Sub>1< / com:Sub> to t<com:Sub>2< / com:Sub>, the body diode of S is reverse-biased. The peak voltage stress on MOSFET Q 102 is reached at t<com:Sub>2< / com:Sub>, whose value equals <com:Math><semantics>Vbus_max−Vbus_min<annotation encoding="application / x-tex">V_{bus\_max} - V_{bus\_min}< / annotation>< / semantics>< / com:Math>. The <com:Math><semantics>Vbus_max<annotation encoding="application / x-tex">V_{bus\_max}< / annotation>< / semantics>< / com:Math> equals to the peak AC line voltage. In practical designs, the voltage stress is below 60 V. Therefore, the voltage rating of MOSFET Q 102 can be as low as 100V or 150V. The voltage stress is much less than 400V, the maximum DC voltage.

[0079] State C [t<com:Sub>2< / com:Sub>, t<com:Sub>3< / com:Sub>]: After t<com:Sub>2< / com:Sub>, vac reduces below the designed Vbus min. Q<com:Sub>1< / com:Sub> is turned off at t<com:Sub>2< / com:Sub>, so that Cgs is charged again to turn on MOSFET Q 102, and the capacitor energy in Cin is released to load. As the capacitor voltage is maintained at the peak line voltage, D<com:Sub>1< / com:Sub> and D<com:Sub>4< / com:Sub> will be reverse-biased after t<com:Sub>2< / com:Sub>. The capacitor voltage will reduce until equal to vac again at t3, as shown in FIG. 4. In this case, the capacitor value is selected such that the minimum capacitor voltage at t<com:Sub>3< / com:Sub> is equal to the line voltage at t<com:Sub>2< / com:Sub>, both at V<com:Sub>bus min< / com:Sub>.

[0800] The operation will be repeated. MOSFET Q 102 is turned off again when the AC line voltage reaches its peak value at t<com:Sub>4< / com:Sub>, as shown in FIG. 4.

[0081] Sensing and Control Logic

[0082] To operate the line extension circuit, it is required to sense the line voltage and / or bus voltage in either analog or digital format. As an example, the sensing circuit 600 shown in FIG. 6 is used to explain the sensing and control strategies. A resistor divider circuit consists of <com:Math><semantics>Rs1<annotation encoding="application / x-tex">R_{s1}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Rs2<annotation encoding="application / x-tex">R_{s2}< / annotation>< / semantics>< / com:Math> can detect the instantaneous <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> voltage. With <com:Math><semantics>Ds1<annotation encoding="application / x-tex">D_{s1}< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Rs3<annotation encoding="application / x-tex">R_{s3}< / annotation>< / semantics>< / com:Math> (>> <com:Math><semantics>Rs2<annotation encoding="application / x-tex">R_{s2}< / annotation>< / semantics>< / com:Math>) and <com:Math><semantics>Cs1<annotation encoding="application / x-tex">C_{s1}< / annotation>< / semantics>< / com:Math>, it can be used to detect the peak of the line voltage. The time constant can be as slow as 100ms because the circuit generally does not require fast reaction.

[0083] With the sensed voltage information, the line extension functionality can be enabled when the AC voltage is low, e.g., 100 VAC. For normal operation at 120 VAC, the bus voltage should always be higher than the designed Vbus_min. Thus, there is no need to perform the control. The switch should remain as on, and the circuit is equivalent to the conventional full bridge rectifier.

[0084] While it is straightforward to implement with discrete components, a portion or the entire line extension circuit together with its driver 102, 104 and the sensing circuit, as shown in the box in FIG. 6, can be packaged into an IC with low cost to further improve the simplicity of applications. In practical implementation, there are different approaches, such as using an external MOSFET switch and integrated circuit can be used for all the other circuits.

[0085] Performance Comparison

[0086] With the AC line providing more power, the capacitor does not need to store as much energy as that in the conventional full bridge case, as shown in FIG. 1. Thus, the capacitor value can be reduced while achieving the same bus voltage range. FIG. 7 shows the simulation results 700 of the required capacitance for both the line power extension method 100 and conventional full bridge for different Vbus min designs and 60 W load.

[0087] If the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> is designed at 50 V, then 37 <com:Math><semantics>μF<annotation encoding="application / x-tex">\mu F< / annotation>< / semantics>< / com:Math> capacitance should be used for conventional full bridge rectifier, while only 15 µF is needed with the line power extension 100. Thus, 59% of capacitor reduction can be achieved for 50 V design. The capacitor reduction ratio will reduce with the V<com:Sub>bus_min< / com:Sub> increases, as the AC power conduction angle is reduced. In practice, a typical <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> design is 90 V-100 V, at which 1 / 3 of capacitance can be saved with the line extension method.

[8800] If the same capacitance is used, then the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> can be increased to relieve the wide gain requirement for the following stage. FIG. 8 is a diagram 800 that shows the comparison of the minimum bus voltage between the conventional full bridge rectifier and the line extension method for different <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> values. In some extreme case with a 39 <com:Math><semantics>μ<annotation encoding="application / x-tex">\mu< / annotation>< / semantics>< / com:Math>F capacitor used, then the Vbus min for the full bridge is only 55 V, while that for the line power extension method is 86 V. Referring to the same V<com:Sub>bus max< / com:Sub> of 340 V, the normalized voltage gain requirement is reduced from 6.2 to 4. In other words, the gain requirement reduces to only 64% of that in the full bridge. With the applied C<com:Sub>in< / com:Sub> increases, the conduction angle reduces, thus the line power shows less significance.

[0089] In a practical case, if an 82 µF capacitor is used, then the V<com:Sub>bus min< / com:Sub> can be increased from 99 V in conventional full bridge to 108 V with the line power extension circuit, which is ~10% of improvement. In some topologies, e.g. series resonant converter, this 10% voltage improvement indicates the same amount of current stress reduction. Then, the conduction loss can be reduced to only <com:Math><semantics>∼80%<annotation encoding="application / x-tex">\sim 80\%< / annotation>< / semantics>< / com:Math> (= 0.92) of the that in the full bridge case.

[0090] Operation of Conventional Full-Bridge Diode Rectifier

[0091] FIG. 10 is a diagram 1000 that illustrates the key waveforms of the conventional full-bridge diode rectifier 900 shown in FIG. 9. It can be observed that the AC input current conducts only during a portion of the AC half line cycle before it reaches the peak value, which is denoted by <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> in rad. <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> represents the AC power conduction angle. During [<com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math>1, <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math>2], the input AC voltage simultaneously provides the power for the DC-DC converter and charges Cin. During [φ2, φ3], the power of the DC-DC converter is supplied by Cin only and the discharging energy of Cin can be described as the following equation: [Image disponible dans le document PDF, Image available in the PDF document] (1) where <com:Math><semantics>Fac<annotation encoding="application / x-tex">F_{ac}< / annotation>< / semantics>< / com:Math> is the AC line frequency (50Hz in Europe, China, and 60Hz in Canada, US) and <com:Math><semantics>Pin<annotation encoding="application / x-tex">P_{in}< / annotation>< / semantics>< / com:Math> is the input power of the DC-DC converter, which is also the is the discharging power of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. By defining the voltage ratio <com:Math><semantics>h<annotation encoding="application / x-tex">h< / annotation>< / semantics>< / com:Math> as [Image disponible dans le document PDF, Image available in the PDF document] (2) <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> can be calculated by [Image disponible dans le document PDF, Image available in the PDF document] (3) The energy change in <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> within half line cycle of the AC voltage is [Image disponible dans le document PDF, Image available in the PDF document] (4) C<com:Sub>in< / com:Sub> can be calculated by [Image disponible dans le document PDF, Image available in the PDF document] (5)

[0092] It can be observed that the required capacitance for <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> is related to the values of maximum and minimum bus voltages (<com:Math><semantics>Vbus_max<annotation encoding="application / x-tex">V_{bus\_max}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math>), AC line frequency <com:Math><semantics>Fac<annotation encoding="application / x-tex">F_{ac}< / annotation>< / semantics>< / com:Math>, input power <com:Math><semantics>Pin<annotation encoding="application / x-tex">P_{in}< / annotation>< / semantics>< / com:Math>, and AC power conduction angle <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math>. Given a specific voltage ripple, increasing <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> lead to a reduced capacitance requirement for <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. Based on this conclusion, the Low-Side Line Power Extension Circuit (LS-LPEC) is proposed, which modifies the topology of the conventional full-bridge diode rectifier. Specifically, an N-channel MOSFET is added in series with <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, positioned below it, forming LS-LPEC. This configuration allows for strategic adjustment of the AC power conduction angle, thereby maximizing the utilization of AC input power and reducing the required capacitance for <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. Corresponding driver and controller circuits are also proposed, aiming to harness the potential of LS-LPEC in a simple, economical, and efficient manner.

[0093] Low-Side Line Power Extension Circuit (LS-LPEC)

[0094] Architecture of LS-LPEC

[0095] FIG. 11A shows the proposed low-side line power extension circuit (LS-LPEC) 1100A. In this figure, an N-channel MOSFET Q is added to the conventional full bridge diode rectifier. The drain terminal of MOSFET Q (D, as shown in FIG. 11A) is connected to the ground point, which is the negative terminal of the input diode bridge (anode terminal of D3 and D4). The source terminal of MOSFET Q (S, as shown in FIG. 11A) is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode terminal of D1, D2).

[0096] Furthermore, to achieve optimal operation of MOSFET Q, a complete control and driving architecture is also proposed, as depicted in 1100B in FIG. 11B.

[0097] The LS-LPEC and the control and driving architecture are not necessarily provided together in a package, and in a variant, they are provided as standalone circuit packages that can be coupled together. In a further variation, there may be a plurality of interconnected LS-LPEC modules being coupled together with a single control and driving circuit modules. For example, in a first implementation case, the MOSFET switch, control circuit, driver circuit are all integrated into an IC. In a second implementation case, the MOSFET switch is separate, and the control circuit and drivers are integrated into one IC.

[0098] As depicted, a non-isolated driver circuit, powered by the bus voltage <com:Math><semantics>(Vbus)<annotation encoding="application / x-tex">(V_{bus})< / annotation>< / semantics>< / com:Math>, is employed to regulate the switching states of Q. The voltage of gate <com:Math><semantics>(QG)<annotation encoding="application / x-tex">(Q_G)< / annotation>< / semantics>< / com:Math> is set to a high level with respect to the voltage of source <com:Math><semantics>(QS)<annotation encoding="application / x-tex">(Q_S)< / annotation>< / semantics>< / com:Math> to turn ON Q. Conversely, when Q needs to be turned OFF, the voltage of <com:Math><semantics>QG<annotation encoding="application / x-tex">Q_G< / annotation>< / semantics>< / com:Math> is set to a low level with respect to the voltage of <com:Math><semantics>QS<annotation encoding="application / x-tex">Q_S< / annotation>< / semantics>< / com:Math>. The ON or OFF logic of Q is determined by the controller circuit. By sampling the input AC voltage <com:Math><semantics>(Vacp<annotation encoding="application / x-tex">(V_{ac\ p}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vacn)<annotation encoding="application / x-tex">V_{ac\ n})< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math>, the controller circuit processes this information through logical operations and outputs control signal <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> to the driver circuit, thereby determining whether Q should be in an ON or OFF state.

[0099] In a prior approach, MOSFET Q is connected to the positive end of the bus, and the capacitor is connected to the negative end of the bus, as shown in 1200 at FIG. 12. With the connection as shown in FIG. 12, the source of Q (S, as shown in FIG. 12) is connected to the output of the diode bridge and the drain of Q (D, as shown in FIG. 12) is connected to the positive terminal of the input capacitor, <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. It is observed that the source terminal of Q (S, as shown in FIG. 12) is at the highest voltage potential. In order to turn ON Q, the gate voltage of Q (G as shown in FIG. 12) should be higher than the highest DC voltage. For a typical AC to DC application, this voltage would be close to 400 V. Therefore, high voltage, such as 400 V, is needed from the driver circuit of MOSFET Q. This increases the circuit complexity and cost.

[00100] One object of the present invention is to use LS-LPEC as shown in FIG. 11A to achieve the same objective described above. It is noted that in the present application, a MOSFET is used as an example for the switch Q. Other switches, such as a BJT with an anti-parallel diode, an IGBT with an anti-parallel diode, etc., can also be used. Comparing FIG. 11A and FIG. 12, the difference is that Q is moved from the positive terminal of the input capacitor <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> to the negative terminal of the input capacitor <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. Therefore, the operation of these two circuits will be the same. In other words, the proposed circuit shown in FIG. 11A will achieve the same performance as the circuit shown in FIG. 12.

[00101] In practical applications, the maximum value of the drain-source voltage of MOSFET Q in FIG. 11A is typically less than 50 V, representing a reduction from 400V to 50V, or a reduction of 87.5%. This change will significantly simplify the turn-on and turn-off circuit (i.e., driver circuit) for Q.

[00102] Operation Principle and Driver circuit

[00103] FIG. 13 shows the key waveforms 1300 of LS-LPEC as shown in FIG. 11. <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> is the output voltage of LS-LPEC, as well as the input voltage for the subsequent DC-DC converter. <com:Math><semantics>|vac|<annotation encoding="application / x-tex">|v_{ac}|< / annotation>< / semantics>< / com:Math> is the absolute value of the AC input voltage. <com:Math><semantics>VCin<annotation encoding="application / x-tex">V_{Cin}< / annotation>< / semantics>< / com:Math> is the voltage across the input capacitor <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. <com:Math><semantics>VQS<annotation encoding="application / x-tex">V_{QS}< / annotation>< / semantics>< / com:Math> is the voltage of the source terminal of MOSFET Q. Since the drain terminal of Q is connected to the ground, <com:Math><semantics>VQS<annotation encoding="application / x-tex">V_{QS}< / annotation>< / semantics>< / com:Math> indicates the voltage stress of Q. <com:Math><semantics>irec<annotation encoding="application / x-tex">i_{rec}< / annotation>< / semantics>< / com:Math> is the output current of the full bridge diode rectifier. <com:Math><semantics>Vgs<annotation encoding="application / x-tex">V_{gs}< / annotation>< / semantics>< / com:Math> Q is the gate-source voltage of Q.

[00104] State A [<com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>]: Before t0, the input AC voltage rises from 0V (at tx, the AC voltage is zero). AC voltage rises from zero (0) at tx, as shown in FIG. 13. <com:Math><semantics>D1<annotation encoding="application / x-tex">D_1< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>D4<annotation encoding="application / x-tex">D_4< / annotation>< / semantics>< / com:Math> start to conduct at <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, at which time <com:Math><semantics>vac<annotation encoding="application / x-tex">v_{ac}< / annotation>< / semantics>< / com:Math> rises to equal of <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math> (as shown in FIG. 13). From <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, the input capacitor voltage <com:Math><semantics>(VCin)<annotation encoding="application / x-tex">(V_{Cin})< / annotation>< / semantics>< / com:Math> will increase with <com:Math><semantics>vac<annotation encoding="application / x-tex">v_{ac}< / annotation>< / semantics>< / com:Math>. During this interval, MOSFET Q is preferred to be turned ON to reduce the conduction loss. In ideal case, Q should be turned OFF at <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, at which the AC voltage and <com:Math><semantics>VCin<annotation encoding="application / x-tex">V_{Cin}< / annotation>< / semantics>< / com:Math> reaches its peak value. However, in practical implementation, Q can be turned OFF any time between <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math> to avoid late turn-off. Even when Q is turned OFF, the input capacitor, <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, can still be charged through body diode of Q to the peak value of the AC line voltage. In this specification, the ideal condition is assumed. In other words, MOSFET Q is turned off at t1, when the AC voltage and Cin voltage reach peak value.

[00105] State B [<com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>]: When MOSFET Q is turned OFF at <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, when the input AC voltage is at its peak value, the input capacitor is disconnected from the DC-DC converter, thus the capacitor voltage will remain as the peak value of the AC line voltage. The DC-DC converter is powered by the AC line voltage directly during <com:Math><semantics>[t1,t2]<annotation encoding="application / x-tex">[t_1, t_2]< / annotation>< / semantics>< / com:Math>, and the AC current equals to the input current of DC-DC converter. Due to this extended conduction angle of the AC input power, <com:Math><semantics>irec<annotation encoding="application / x-tex">i_{rec}< / annotation>< / semantics>< / com:Math> is lower than the conventional full bridge diode rectifier. During <com:Math><semantics>[t1,t2]<annotation encoding="application / x-tex">[t_1, t_2]< / annotation>< / semantics>< / com:Math>, the body diode of Q is reverse-biased. The peak voltage stress across MOSFET Q (the drain to source voltage of Q) is reached at <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, whose value equals <com:Math><semantics>Vbus_max−Vbus_min<annotation encoding="application / x-tex">V_{bus\_max} - V_{bus\_min}< / annotation>< / semantics>< / com:Math>. <com:Math><semantics>Vbus_max<annotation encoding="application / x-tex">V_{bus\_max}< / annotation>< / semantics>< / com:Math> equals the peak AC line voltage. In practical designs, the voltage stress is below 50 V. Therefore, the voltage rating of Q can be as low as 100 V or 150 V. The voltage stress is much less than 400 V, the maximum DC voltage.

[00106] State C [<com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>t3<annotation encoding="application / x-tex">t_3< / annotation>< / semantics>< / com:Math>]: At <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, the AC voltage equals to <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, MOSFET Q is turned ON again. As the input capacitor voltage is maintained at the peak AC line voltage, <com:Math><semantics>D1<annotation encoding="application / x-tex">D_1< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>D4<annotation encoding="application / x-tex">D_4< / annotation>< / semantics>< / com:Math> will be reverse biased after <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>. The input capacitor, Cin, will provide the energy to DC-DC converter, and the input capacitor voltage will reduce until equal to <com:Math><semantics>vac<annotation encoding="application / x-tex">v_{ac}< / annotation>< / semantics>< / com:Math>. At t3, when the input capacitor voltage, V<com:Sub>Cin< / com:Sub> equals to the rectified AC voltage, as shown in FIG. 13. In this case, the capacitor value is selected such that the minimum capacitor voltage at <com:Math><semantics>t3<annotation encoding="application / x-tex">t_3< / annotation>< / semantics>< / com:Math> is equal to the line voltage at <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, both at <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>. It is noted that the best time (or the most optimal time) to turn on MOSFET Q again is at t2 when the rectified AC voltage value equals <com:Math><semantics>Vbusmin.<annotation encoding="application / x-tex">V_{bus\ min.}< / annotation>< / semantics>< / com:Math> In practical implementation, MOSFET Q will be turned on again before t2, but close to t2. For example, the MOSFET Q can be turned on 10 to 100 micro-seconds before t2. To summarize, the MOSFET Q will be turned off between t0 and t1. It is desired that MOSFET Q be turned off at t1 or just before t1, such as 10 to 100 micro-seconds before t1. MOSFET Q will be turned on again at t2, or just before t2, such as 10 to 100 micro-seconds before t2.

[00107] The operation will be repeated. MOSFET Q is turned OFF again when the AC line voltage reaches its peak value <com:Math><semantics>t4<annotation encoding="application / x-tex">t_4< / annotation>< / semantics>< / com:Math>, as shown in FIG. 13.

[00108] The above operation will be repeated at half the AC line cycles, which is 100Hz for 50Hz AC frequency, or 120Hz for 60H AC frequency.

[00109] It can be observed from conventional diode rectifier plus input capacitor circuit, as shown in FIG. 9 and its operating waveforms shown in FIG. 10, that when the magnitude of the instantaneous AC input voltage is higher than the voltage across the input capacitor, Vbus, input diode bridge (D1, D2, D3, and D4) will be forward biased and the input AC voltage will charge the input capacitor (Cin) and provide all the power drawn by the DC-DC converter. For the conventional full bridge diode rectifier circuit (as shown in FIG. 9), this AC powering period is from <com:Math><semantics>φ1<annotation encoding="application / x-tex">\varphi_1< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math>, as shown FIG. 10. At <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math>, the input AC voltage reaches its peak value and the input capacitor voltage Vbus also reaches the peak AC voltage value. After <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math>, the capacitor voltage Vbus will be higher than the instantaneous AC voltage and therefore, the diode bridge is turned off. Therefore, between <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>φ3<annotation encoding="application / x-tex">\varphi_3< / annotation>< / semantics>< / com:Math>, the power drawn by the DC-DC converter comes from the input capacitor and its voltage reduces, as shown FIG. 10. In other words, the input capacitor discharges during the time period between <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>φ3<annotation encoding="application / x-tex">\varphi_3< / annotation>< / semantics>< / com:Math>.

[00110] The underlying principle of line power extension control is to maximize the utilization of AC input power. For a given minimum bus voltage <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, the line power extension control can effectively reduce the required capacitance of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. For a predetermined capacitance of <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>, line power extension control enables the boost of the minimum bus voltage <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>. As shown in FIG. 13, <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> represents AC power conduction angle without using line power extension control, while <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math> represents the line power extension angle, introduced by the proposed line power extension control. With the help of the proposed technique, the total AC power conduction angle can be extended from <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>θ+ϕ<annotation encoding="application / x-tex">\theta + \phi< / annotation>< / semantics>< / com:Math>. During this extended angle <com:Math><semantics>(θ+ϕ)<annotation encoding="application / x-tex">(\theta + \phi)< / annotation>< / semantics>< / com:Math>, the DC-DC converter draws power directly from the AC input through the rectifier diodes, thereby significantly reducing the required discharge energy from the input capacitance <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math>. Ideally, the value of <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math> should be equal to that of <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math>, maximizing the energy extracted by the DC-DC converter from the AC input during a half line cycle. In practical applications, the value of <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math> may be slightly less than that of <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math>, depending on the specific implementation of the line power extension circuit.

[00111] It is normally required that an AC to DC power supply should operate normally when the input AC voltage is at 90V rms. The peak value for an 90Vrms AC voltage is 90 x 1.414 = 127V. Therefore, in this case, <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math> is 127V. For a typical design case, the value of <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> is varied between 85V to 100V. If we assume the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> value is set at 95V. This means that the DC-DC converter as shown in FIG. 9 should be designed to meet minimum input voltage of 95V.

[00112] As discussed earlier, the angle at t1 is 90 degrees, when the AC voltage reaches peak value. With the above example, when the input voltage reaches to 95V (if we neglect the forward voltage drop of the input diode bridge to simplify the analysis), the diode bridge will be turned on. For 90V rms AC voltage, when <com:Math><semantics>φ1<annotation encoding="application / x-tex">\varphi_1< / annotation>< / semantics>< / com:Math> equals to 48 degree, its instantaneous AC voltage value is 95V, = 127V x sin (49 degree) = 95.8V, which is very close to 95V. In other words, with the conventional diode bridge + rectifier circuit, as shown in FIG. 9, the input diode bridge will be turned on from 49 degree to 90 degree. The conduction time of the diode bridge is 90 – 49 = 41 degree. After <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math>. The diode bridge will be turned off because they are reverse biased. The input capacitor, Cin, will be discharged to provide the power for DC-DC converter. The discharging time is <com:Math><semantics>180−41=139<annotation encoding="application / x-tex">180 - 41 = 139< / annotation>< / semantics>< / com:Math> degree. In other words, for conventional circuit as shown in FIG. 9, the input capacitor discharges for 139 degree / 180 degree = 77% of the half AC line period. In this case, 180 degree is equivalent to half the AC line cycle.

[00113] As discussed earlier, with the proposed LS-LPEC circuit as shown in FIG. 11A, FIG. 11B, the diode bridge will be turned on from t0 to t2. Comparing between FIG. 10 and FIG. 13, t0 in FIG. 13 is equivalent to <com:Math><semantics>φ1<annotation encoding="application / x-tex">\varphi_1< / annotation>< / semantics>< / com:Math> in FIG. 10 and t1 in FIG. 13 is equivalent to <com:Math><semantics>φ2<annotation encoding="application / x-tex">\varphi_2< / annotation>< / semantics>< / com:Math> in FIG. 10.

[00114] If we assume that the minimum bus voltage, <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math> value is still set at 95V, to corresponds to 49 degree and t1 corresponds to 90 degree. Since at t2, the AC voltage is at <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> which is 95V, t2 corresponds to 131 degree. It is noted that 127V x sin(131 degree) = 95.8V, which is very close to 95V. Therefore, the <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math> (line power extension angle) value is 131 – 90 = 41 degrees. Therefore, with the LS-LPEC circuit, the diode bridge will be turned on from 49 degree to 131 degree. The conduction time of the diode bridge will be 131 – 49 = 82 degrees. From t2 to t3, the diode bridge will be off and input capacitor, Cin, will be discharged to provide power to DC-DC converter. The discharging time is <com:Math><semantics>180−82=98<annotation encoding="application / x-tex">180 - 82 = 98< / annotation>< / semantics>< / com:Math> degrees, as shown in FIG. 13 (from t2 to t3). In other words, for LS-LPEC circuit as shown in FIG. 11A, 11B, the input capacitor discharges for 98 degree / 180 degree = 54% of the half AC line period.

[00115] From the comparison using the above example, discharging time for the LS-LPEC circuit is 98 degrees / 139 degrees = 70% of the conventional diode bridge circuit. Since with same discharging voltage (from <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math> = 127V to <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> = 95V in the above example), the capacitor value depends on the discharging time. It can be concluded that with the LS-LPEX circuit, the input capacitor value, Cin, can be reduced to 70% of the original value when the conventional diode bridge circuit (FIG. 9) is used. In other words, the input capacitor value can be reduced by 30%.

[00116] Similar analysis can be performed for a different <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math> value, such as 90V. In this case, t0 in FIG. 13, corresponds to 45 degree and t2 corresponds to 135 degree. This means that with conventional diode bridge, the diode bridge conduction time is 45 degrees (90 – 45) and input capacitor discharging time is 135 degrees (180 – 45). With LS-LPEC circuit (FIG. 11), diode bridge conduction time is 90 degree (135 – 45) and input capacitor discharging time is 90 degrees (180 – 90). Therefore, with LS-LPEC technology proposed in this specification, the capacitor discharging time is 90 degrees / 135 degree = 67% of the conventional diode bridge circuit or the input capacitor value can be reduced by 33%.

[00117] Please note that the above analysis is approximate since it assumes that the capacitor reduction ratio is proportional to the capacitor discharging time. More accurately, the capacitor reduction ratio also depends on the absolute capacitor voltage value.

[00118] From the above discussion / analysis, it is demonstrated that with LS-LPEC technology, as shown in FIG. 11A, 11B, the conduction time of the diode bridge can be roughly doubled, and the input capacitor value can be reduced by 30 to 35%.

[00119] The term "AC Power Time Interval" is described as the time duration when the DC- DC converter receives the power from input AC voltage through diode bridge, not from the discharging of the input capacitor. For conventional diode bridge rectifier, as shown in FIG. 9, the AC Power Time Interval is shown as angle <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math> (Conventional AC Power Conduction Angle) in FIG. 10. While for the proposed LS-LPEC technology, as proposed in this application shown in FIG. 11, the AC Power Time Interval is shown as angle <com:Math><semantics>θ+ϕ<annotation encoding="application / x-tex">\theta + \phi< / annotation>< / semantics>< / com:Math>, as shown in FIG. 13. Considering that <com:Math><semantics>ϕ<annotation encoding="application / x-tex">\phi< / annotation>< / semantics>< / com:Math> (Line Power Extension Angle) is roughly same as the <com:Math><semantics>θ<annotation encoding="application / x-tex">\theta< / annotation>< / semantics>< / com:Math>, it can be observed that with LS-LPEC technology, the AC Power Time Interval is much longer than the conventional diode bridge rectifier. When AC Power Time Interval is increased the time interval that the DC-DC converter receives power from input capacitor, Cin, is significantly reduced. This is another understanding that the value of the input capacitor, Cin, can be significantly reduced with the proposed LS-LPEC technology.

[00120] Another observation from the above analysis / discussion is that when the rms value of the input AC voltage is higher than 90V, such as when the rms value of the AC voltage is 120V. With 120V rms value, the peak voltage is 120 x 1.414 = 170V. In this condition, <com:Math><semantics>Vbus_max<annotation encoding="application / x-tex">V_{bus\_max}< / annotation>< / semantics>< / com:Math> = 140 x 1.414 = 170V. With conventional diode bridge circuit, as shown in FIG. 9, The <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> is estimated at around 140V, which is higher than minimum input voltage of the DC-DC converter (90V or 95V in the above discussion). In other words, when input AC voltage is higher, LS-LPEC circuit is not needed. In this case, the MOSFET Q is turned on all the time. This will simplify the design and operation of the LS-LPEC circuit.

[00121] Therefore, one strategy in the practical operation is to disable the operation LS- LPEC circuit when the input AC voltage is higher, such as the input AC voltage is above 110V. Equivalently, when input AC voltage is higher than a design value, the MOSFET Q is turned on all the time.

[00122] The present application contemplates two major technology advancements and their corresponding sub-developments and variations.

[00123] The first technology is to move the MOSFET (Q) that is connected in series with the input capacitor from above the capacitor Cin to below Cin. With the new connection, the drain terminal of MOSFET Q (D, as shown in FIG. 11A) is connected to the ground point, which is the negative terminal of the input diode bridge (anode terminal of D3 and D4). The source terminal of MOSFET Q (S, as shown in FIG. 11A) is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode terminal of D1, D2). As discussed above, the major benefit is that we do not need a voltage higher than the peak value of the input AC voltage to turn on MOSFET Q. This can significantly reduce the complexity and cost of the driver circuit. In the present application, two possible driver circuits for MOSFET Q have been proposed. None of these two circuits requires a voltage higher than peak value AC voltage. Other similar driver circuits can be developed to achieve the same objective.

[00124] The second technology proposed is the method to generate the gate driver signal for MOSFET Q. Four sensing and control logic circuits are proposed in the present application. In order to achieve the optimal (desired) operation, the MOSFET Q (as shown in FIG. 11) is turned on for most of the AC line cycles. As shown in FIG. 12, it is optimal (desired) that the MOSFET Q is turned off at 90 degrees (t1 as shown in FIG. 13), when the AC voltage reaches the peak value. Under this condition, Cin is charged to the peak value of the AC voltage. It is also optimal (desired) that MOSFET Q is turned on again at t2 (as shown in FIG. 13), when the instantaneous AC voltage value falls to Vbus min. These four sensing and control logic circuits proposed in the present application use the information of the AC voltage value and DC bus voltage value (Vbus) to find the optimal (or near optimal) turn off and turn on time instant for MOSFET Q.

[00125] An embodiment including a driver circuit #1 for MOSFET Q is shown in circuit 1400 of FIG. 14. Terminal connections of <com:Math><semantics>QG<annotation encoding="application / x-tex">Q_G< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>QS<annotation encoding="application / x-tex">Q_S< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math>, GND, and <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> can be found in FIG. 11. In this embodiment, the driver circuit includes two resistors <com:Math><semantics>R1<annotation encoding="application / x-tex">R_1< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math>, two Zener diodes <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math>, and a low-voltage low-current switch, shown as N-channel MOSFET <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> in FIG. 14. A BJT can also be used as <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math>. In other embodiments, <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z_1}< / annotation>< / semantics>< / com:Math> can be optional, and <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> can be other types of switching devices, including but not limited to an NPN BJT, etc.

[00126] Turn-Off operation of Q in driver circuit #1: The ON and OFF states of MOSFET Q are controlled by the driver input signal <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math>, which is also the gate-source signal of MOSFET <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math>. As shown in the waveforms 1500 of FIG. 15, during <com:Math><semantics>[t0,t1]<annotation encoding="application / x-tex">[t_0, t_1]< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to high level to turn OFF Q. In this case, <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> is turned ON, and the gate capacitor of <com:Math><semantics>Q<annotation encoding="application / x-tex">Q< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math>, will be discharged through Q<com:Sub>1< / com:Sub> and the channel of Q as long as Q conducts current. When the gate- source voltage of Q, <com:Math><semantics>Vgs<annotation encoding="application / x-tex">V_{gs}< / annotation>< / semantics>< / com:Math> Q, falls below its threshold voltage, Q will be switched OFF. During <com:Math><semantics>[t0,t1],VQS<annotation encoding="application / x-tex">[t_0, t_1], V_{QS}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>VQG<annotation encoding="application / x-tex">V_{QG}< / annotation>< / semantics>< / com:Math> increase in the reverse direction, indicating that <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math> is reverse-biased when <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> is turned ON (i.e., Q is turned OFF). The voltage stress of <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math> reaches its maximum value at <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math> as shown in FIG. 15, which is <com:Math><semantics>Vbus_max−Vbus_min<annotation encoding="application / x-tex">V_{bus\_max} - V_{bus\_min}< / annotation>< / semantics>< / com:Math>. Hence, to ensure the reliable turn- off of Q, the minimum clamp voltage of <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math>, denoted by <com:Math><semantics>VDZ2_min<annotation encoding="application / x-tex">V_{DZ2\_min}< / annotation>< / semantics>< / com:Math>, should meet the following relationship: [Image disponible dans le document PDF, Image available in the PDF document] (6)

[00127] For example, if <com:Math><semantics>Vbus_max<annotation encoding="application / x-tex">V_{bus\_max}< / annotation>< / semantics>< / com:Math> - <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math> is 50V, the breakdown voltage of Zener diode Dz2 should be higher than 50V, such as 55V.

[00128] Turn-On operation of Q in driver circuit #1: As shown in FIG. 15, during [<com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>], <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to low level to turn ON MOSFET Q. The gate-source capacitor of Q, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math>, as shown in FIG. 14, will be charged by the bus voltage through <com:Math><semantics>R1<annotation encoding="application / x-tex">R_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math>, and the channel of Q (if Q is turned ON), or through the body diode of <com:Math><semantics>Q(Db)<annotation encoding="application / x-tex">Q(D_b)< / annotation>< / semantics>< / com:Math>, if <com:Math><semantics>Q<annotation encoding="application / x-tex">Q< / annotation>< / semantics>< / com:Math> is not turned ON yet). The gate-source voltage of Q should be clamped by <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math> and / or <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math>. FIG. 15, corresponds to the operating scenario where the gate-source voltage of Q is clamped by <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math>. In case of startup or other cases where Q is not conducting, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math> will be charged through the body diode <com:Math><semantics>Db<annotation encoding="application / x-tex">D_b< / annotation>< / semantics>< / com:Math>, and eventually turn ON Q. To ensure the reliable turn-on of Q, the maximum clamp voltage of <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math>, denoted by <com:Math><semantics>VDZ2 max<annotation encoding="application / x-tex">V_{DZ2 \text{ max}}< / annotation>< / semantics>< / com:Math>, should meet the following relationship: [Image disponible dans le document PDF, Image available in the PDF document] (7) When MOSFET <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> is in the OFF state, the voltage stress applied to <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> can be calculated as follows: [Image disponible dans le document PDF, Image available in the PDF document] (8)

[00129] In practical designs, the clamp voltage of <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math> is typically selected to be slightly higher than <com:Math><semantics>VDZ2 min<annotation encoding="application / x-tex">V_{DZ2 \text{ min}}< / annotation>< / semantics>< / com:Math>. For a 65 W USB-PD adapter, the maximum difference between <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> is below 50 V. Hence, a 60 V <com:Math><semantics>DZ2<annotation encoding="application / x-tex">D_{Z2}< / annotation>< / semantics>< / com:Math> can be employed to ensure the reliable turn- on and -off of MOSFET Q. In(8), the maximum value of <com:Math><semantics>VgsQ<annotation encoding="application / x-tex">V_{gs_Q}< / annotation>< / semantics>< / com:Math> is determined by the clamp voltage of <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math>, which is typically less than 15 V. Hence, the voltage rating of MOSFET <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> can be as low as 100 V or 150 V for a 65 W USB-PD adapter.

[00130] An embodiment including a driver circuit #2 for MOSFET Q 1600 is shown in FIG. 16. In this embodiment, the driver circuit includes two resistors, <com:Math><semantics>R1<annotation encoding="application / x-tex">R_1< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math>, a Zener diode <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math>, a low-voltage low-current diode <com:Math><semantics>D5<annotation encoding="application / x-tex">D_5< / annotation>< / semantics>< / com:Math>, and two low-voltage low-current switches represented by the N-channel MOSFET Q<com:Sub>2< / com:Sub> and the P-channel MOSFET Q<com:Sub>3< / com:Sub>. In other embodiments, <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z_1}< / annotation>< / semantics>< / com:Math> may be optional components, and <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> can be substituted with other types of switching devices, including but not limited to a BJT, etc.

[00131] Turn-Off operation of Q in driver circuit #2: FIG. 17 showing waveforms 1700 is used to help the explanation of this paragraph. The ON and OFF states of MOSFETs Q<com:Sub>2< / com:Sub> and <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> are controlled by the driver input signal <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math>. Due to the N-channel property of MOSFET <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math>, it will conduct when <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to a high level. Conversely, the P-channel nature of MOSFET <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> causes it to conduct when <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to a low level. In other words, a high- level <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> corresponds to the turning-on of <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math> and the turning-off of <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math>. Conversely, a low- level <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> corresponds to the turning-off of <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math> and the turning-on of <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math>. As shown in FIG. 17, during <com:Math><semantics>[t0,t1]<annotation encoding="application / x-tex">[t_0, t_1]< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to high level to turn OFF Q. In this case, <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math> is kept ON while <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> is kept OFF. The gate capacitor of Q, <com:Math><semantics>Cqs<annotation encoding="application / x-tex">C_{qs}< / annotation>< / semantics>< / com:Math>, will be discharged through <com:Math><semantics>Q1<annotation encoding="application / x-tex">Q_1< / annotation>< / semantics>< / com:Math> and the channel of Q as long as Q conducts current. When the gate source voltage of Q, <com:Math><semantics>VgsQ<annotation encoding="application / x-tex">V_{gs_Q}< / annotation>< / semantics>< / com:Math>, reaches its threshold voltage, Q will be switched OFF. As shown in FIG. 16, the Anode of <com:Math><semantics>D5<annotation encoding="application / x-tex">D_5< / annotation>< / semantics>< / com:Math> is connected to <com:Math><semantics>VQG<annotation encoding="application / x-tex">V_{QG}< / annotation>< / semantics>< / com:Math>, while its cathode is connected to <com:Math><semantics>VQ2<annotation encoding="application / x-tex">V_{Q2}< / annotation>< / semantics>< / com:Math>. Hence, during [<com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>], <com:Math><semantics>D5<annotation encoding="application / x-tex">D_5< / annotation>< / semantics>< / com:Math> is reverse- biased. The voltage stress of <com:Math><semantics>D5<annotation encoding="application / x-tex">D_5< / annotation>< / semantics>< / com:Math> reaches its maximum value at <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, which is <com:Math><semantics>Vbusmax−Vbusmin<annotation encoding="application / x-tex">V_{bus\ max} - V_{bus\ min}< / annotation>< / semantics>< / com:Math>. As mentioned earlier, the voltage stress is below 50 V in practical designs. Therefore, the voltage rating of <com:Math><semantics>D5<annotation encoding="application / x-tex">D_5< / annotation>< / semantics>< / com:Math> can be as low as 100V or 150V. The voltage rating of MOSFET <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> is dominated by <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math>, which is around 141 V when the AC input voltage is 100 Vac. As it is desired that LS-LPEC is only activated when the AC input voltage is low (e.g., 100 Vac), the voltage rating of <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> can be as low as 200 V.

[00132] Turn-On operation of Q in driver circuit #2: As shown in FIG. 17, during <com:Math><semantics>[t1,t2]<annotation encoding="application / x-tex">[t_1, t_2]< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to low level to turn ON MOSFET Q. In this case, MOSFET Q<com:Sub>2< / com:Sub> is kept in the OFF state, while MOSFET <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math> is kept in the ON state. The gate capacitor of <com:Math><semantics>Q<annotation encoding="application / x-tex">Q< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math>, as shown in FIG. 16, will be charged by the bus voltage through <com:Math><semantics>R1<annotation encoding="application / x-tex">R_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Q3<annotation encoding="application / x-tex">Q_3< / annotation>< / semantics>< / com:Math>, and the channel of Q (if Q is turned ON), or through the body diode of <com:Math><semantics>Q(Db)<annotation encoding="application / x-tex">Q(D_b)< / annotation>< / semantics>< / com:Math>, if <com:Math><semantics>Q<annotation encoding="application / x-tex">Q< / annotation>< / semantics>< / com:Math> is not turned ON yet). The gate voltage of Q should be clamped by <com:Math><semantics>R2<annotation encoding="application / x-tex">R_2< / annotation>< / semantics>< / com:Math> and / or <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z_1}< / annotation>< / semantics>< / com:Math>. FIG. 17 corresponds to the operating scenario where the gate-source voltage of Q is clamped by <com:Math><semantics>DZ1<annotation encoding="application / x-tex">D_{Z1}< / annotation>< / semantics>< / com:Math>. In case of startup or other cases where Q is not conducting, <com:Math><semantics>Cgs<annotation encoding="application / x-tex">C_{gs}< / annotation>< / semantics>< / com:Math> will be charged through the body diode <com:Math><semantics>Db<annotation encoding="application / x-tex">D_b< / annotation>< / semantics>< / com:Math>, and eventually turn ON Q. The peak voltage stress on Q<com:Sub>2< / com:Sub> is dominated by the gate-source voltage of Q <com:Math><semantics>(VgsQ)<annotation encoding="application / x-tex">(V_{gs} Q)< / annotation>< / semantics>< / com:Math>, which is less than 15 V. Hence, the voltage rating of <com:Math><semantics>Q2<annotation encoding="application / x-tex">Q_2< / annotation>< / semantics>< / com:Math> can be as low as 40 V or 60 V.

[00133] SENSING AND CONTROL LOGIC

[00134] To operate LS-LPEC, it is required to sense the line voltage and / or bus voltage in either analog or digital format. FIG. 18 gives the schematic diagram 1800 of the proposed controller circuit #1. In this figure, the circuit A in the controller circuit is used to determine the operation mode of the control circuit, i.e., whether LS-LPEC is required.

[00135] By sampling the bus voltage <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> and comparing it with a preset value <com:Math><semantics>Vref3<annotation encoding="application / x-tex">V_{ref3}< / annotation>< / semantics>< / com:Math>, the enable signal <com:Math><semantics>VEN<annotation encoding="application / x-tex">V_{EN}< / annotation>< / semantics>< / com:Math> for LS-LPEC is generated. Employing a low-bandwidth low-pass filter enables the detection of the peak of the line voltage. If an RC circuit is employed to implement the low-pass filter, the time constant can be as slow as 100 ms, as the circuit typically does not necessitate fast reactions. For normal operation at, e.g., 120 Vac, the bus voltage should always be higher than the designed <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math>. Thus, there is no need to activate LS-LPEC. In this scenario, the <com:Math><semantics>VEN<annotation encoding="application / x-tex">V_{EN}< / annotation>< / semantics>< / com:Math> signal is set high, maintaining MOSFET Q in the ON state, and the circuit functions identically to a conventional full-bridge diode rectifier.

[00136] LS-LPEC is activated when the magnitude of the AC voltage is low, i.e., below <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, such as 100 Vac. In this case, the <com:Math><semantics>VEN<annotation encoding="application / x-tex">V_{EN}< / annotation>< / semantics>< / com:Math> signal is set low, and circuit B in FIG. 18 is utilized to determine the ON / OFF timing of MOSFET Q. In other words, the output signal <com:Math><semantics>(Vdrv)<annotation encoding="application / x-tex">(V_{drv})< / annotation>< / semantics>< / com:Math> of the controller circuit is solely determined by <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> signal. FIG. 19 illustrates the conceptual waveforms 1900 of circuit B shown in FIG. 18.

[00137] The instantaneous value of AC input voltage, denoted as <com:Math><semantics>Vacinst<annotation encoding="application / x-tex">V_{ac inst}< / annotation>< / semantics>< / com:Math>, is sensed and compared with two reference values <com:Math><semantics>Vref1<annotation encoding="application / x-tex">V_{ref1}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vref2<annotation encoding="application / x-tex">V_{ref2}< / annotation>< / semantics>< / com:Math>. The outputs of two comparators are fed to a rising-edge-triggered RS flip-flop. As shown in FIG. 19, right after <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vacinst<annotation encoding="application / x-tex">V_{ac\ inst}< / annotation>< / semantics>< / com:Math> exceeds <com:Math><semantics>Vref2<annotation encoding="application / x-tex">V_{ref2}< / annotation>< / semantics>< / com:Math>, triggering the Reset of the flip-flop (<com:Math><semantics>V2<annotation encoding="application / x-tex">V_2< / annotation>< / semantics>< / com:Math>). This results in a low level of <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> and a high level of the controller output <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math>. With the help of the proposed driver circuit, MOSFET Q is turned OFF, allowing for an extended AC power conduction time until <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>. Right after <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vacinst<annotation encoding="application / x-tex">V_{ac\ inst}< / annotation>< / semantics>< / com:Math> falls below <com:Math><semantics>Vref1<annotation encoding="application / x-tex">V_{ref1}< / annotation>< / semantics>< / com:Math>, and the Set of the flip-flop <com:Math><semantics>(V1)<annotation encoding="application / x-tex">(V_1)< / annotation>< / semantics>< / com:Math> is triggered, leading to high level of <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> and low level of the controller output <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math>. With the help of the proposed driver circuit, MOSFET Q is turned ON, and the DC-DC converter is provided by input capacitor only until <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, at which point MOSFET Q is turned OFF once again.

[00138] Ideally, Q should be turned OFF at the line voltage peak (i.e., <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math>), after which the line will power the DC-DC converter directly. Hence, <com:Math><semantics>Vref2<annotation encoding="application / x-tex">V_{ref2}< / annotation>< / semantics>< / com:Math> should be selected as close to the peak value of <com:Math><semantics>Vacinst<annotation encoding="application / x-tex">V_{ac\ inst}< / annotation>< / semantics>< / com:Math> as possible while ensuring an adequate margin. The turn-on timing of Q occurs when the magnitude of the line voltage decreases to a predetermined <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, which can be adjusted by modifying the value of <com:Math><semantics>Vref1<annotation encoding="application / x-tex">V_{ref1}< / annotation>< / semantics>< / com:Math>.

[00139] FIG. 20 gives the schematic diagram 2000 of the proposed controller circuit #2. In this figure, the controller includes circuit A, which is the same as the one shown in FIG. 18. The difference between FIG. 20 and FIG. 18 in the controller circuit lies in the implementation of circuit B. The basic idea of circuit B in FIG. 20 involves estimating the moment when the AC input voltage equals its peak voltage and subsequently generating a fixed delay time to control the activation time of MOSFET Q (refer to <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math> in FIG. 13).

[00140] FIG. 21 illustrates the conceptual waveforms 2100 of circuit B shown in FIG. 20. <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> represents the output signal of the AC voltage sensing circuit, which reflects the instantaneous absolute value of the AC input voltage. After a peak detector circuit PD1, <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> is fed to the negative input of comparator U1, represented by <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math>. Simultaneously, it is also fed to the positive input of comparator U1. At <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, both <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> reach their maximum values.

[00141] Due to the voltage drop introduced by the diode within PD1, the maximum value of <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math> is slightly lower than that of <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math>. After <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> follows <com:Math><semantics>Vac<annotation encoding="application / x-tex">V_{ac}< / annotation>< / semantics>< / com:Math>, decreasing sinusoidally. Meanwhile, <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math> decreases very slowly due to the delay effect introduced by PD1. Typically, the RC circuit within PD1 should have a large time constant to effectively function as a sample and hold circuit. The time constant should be 3 to 5 times 1 / 120 Hz. At <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> reaches <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math>.

[00142] The delay time from <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math> is denoted as <com:Math><semantics>tdelay1<annotation encoding="application / x-tex">t_{delay1}< / annotation>< / semantics>< / com:Math>. Right after <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> becomes lower than <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math>, resulting in the low level of <com:Math><semantics>V13<annotation encoding="application / x-tex">V_{13}< / annotation>< / semantics>< / com:Math> (output signal of comparator U1). Following another peak detector circuit PD2, <com:Math><semantics>V13<annotation encoding="application / x-tex">V_{13}< / annotation>< / semantics>< / com:Math> is fed to the positive input of comparator U2, represented by <com:Math><semantics>V14<annotation encoding="application / x-tex">V_{14}< / annotation>< / semantics>< / com:Math>. By comparing <com:Math><semantics>V14<annotation encoding="application / x-tex">V_{14}< / annotation>< / semantics>< / com:Math> with a fixed reference voltage <com:Math><semantics>Vref4<annotation encoding="application / x-tex">V_{ref4}< / annotation>< / semantics>< / com:Math>, a fixed delay time, denoted as <com:Math><semantics>tdelay2<annotation encoding="application / x-tex">t_{delay2}< / annotation>< / semantics>< / com:Math>, is generated. After <com:Math><semantics>tdelay2<annotation encoding="application / x-tex">t_{delay2}< / annotation>< / semantics>< / com:Math>, at <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> is set to a low level, turning ON MOSFET Q, and the bus voltage is boosted to its maximum value <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math>. MOSFET Q remains ON until <com:Math><semantics>t3<annotation encoding="application / x-tex">t_3< / annotation>< / semantics>< / com:Math>, from which time <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> both begin to rise until <com:Math><semantics>t4<annotation encoding="application / x-tex">t_4< / annotation>< / semantics>< / com:Math> when <com:Math><semantics>V12<annotation encoding="application / x-tex">V_{12}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>V11<annotation encoding="application / x-tex">V_{11}< / annotation>< / semantics>< / com:Math> reach their maximum values once again. The time duration of <com:Math><semantics>t4<annotation encoding="application / x-tex">t_4< / annotation>< / semantics>< / com:Math> - <com:Math><semantics>t3<annotation encoding="application / x-tex">t_3< / annotation>< / semantics>< / com:Math>, as well as <com:Math><semantics>tdelay1<annotation encoding="application / x-tex">t_{delay1}< / annotation>< / semantics>< / com:Math>, can be considered equal due to the sample and hold nature of PD1. In practice, this time duration should be minimized so as to minimize the conduction time of MOSFET Q's body diode, thereby increasing circuit efficiency.

[00143] To make sure that MOSFET Q can be turned ON at the designed minimum bus voltage <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>tdelay1<annotation encoding="application / x-tex">t_{delay1}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>tdelay2<annotation encoding="application / x-tex">t_{delay2}< / annotation>< / semantics>< / com:Math> should be carefully addressed as the turn-on timing of Q is determined by <com:Math><semantics>tdelay1<annotation encoding="application / x-tex">t_{delay1}< / annotation>< / semantics>< / com:Math>+ <com:Math><semantics>tdelay2<annotation encoding="application / x-tex">t_{delay2}< / annotation>< / semantics>< / com:Math>. <com:Math><semantics>tdelay1<annotation encoding="application / x-tex">t_{delay1}< / annotation>< / semantics>< / com:Math> can be minimized by selecting a low forward voltage drop diode within PD1. <com:Math><semantics>tdelay2<annotation encoding="application / x-tex">t_{delay2}< / annotation>< / semantics>< / com:Math> can be adjusted by altering the time constant of the RC circuit within PD2 or by modifying the value of <com:Math><semantics>Vref4<annotation encoding="application / x-tex">V_{ref4}< / annotation>< / semantics>< / com:Math>.

[00144] While it is straightforward to implement with discrete components, the entire line extension circuit together with its driver and the controller can be packaged into an IC with low cost to further improve the simplicity of applications.

[00145] It is noted that the above two sensing and control logic circuits use the actual AC voltage value and the actual DC bus voltage value (V<com:Sub>bus< / com:Sub>) to determine the turn on and turn off time instant for MOSFET Q. They can achieve very accurate control of the timing. If a less accurate timing is acceptable, a third and much simpler sensing and control logic circuit can be proposed as shown in diagram 2200 of FIG. 22. In this figure, circuit B includes three control units: a peak detect circuit, a delay circuit, and a NOT gate. <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> represents the output signal of the peak detect circuit, indicating the moment when the input AC voltage reaches its peak value. <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> is typically a narrow pulse lasting from nanoseconds to microseconds. After passing through the delay circuit, the high-level duration of <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> is extended to the millisecond range. The specific delay time can be pre-set according to the requirements. <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> delay represents the output signal of the delay circuit, which is used to generate the <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> signal after passing through a NOT gate. FIG. 23 illustrates the conceptual waveforms 2300 of circuit B shown in FIG. 22. The working principle can be summarized as follows:

[00146] Step 1: At <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, the peak value of the AC voltage is detected. At this moment, <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> and <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> delay are set to high level, while <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> is set to low level. MOSFET Q is turned OFF at <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>.

[00147] Step 2: From <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> to <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, the delay circuit extends the high-level duration of <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> to the millisecond range, which is represented by the predetermined delay time shown in FIG. 23.

[00148] Step 3: At <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vpkdelay<annotation encoding="application / x-tex">V_{pk\ delay}< / annotation>< / semantics>< / com:Math> returns to the low level. At this point, the <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> signal is set to high level, and the <com:Math><semantics>Vdrv<annotation encoding="application / x-tex">V_{drv}< / annotation>< / semantics>< / com:Math> signal is set to low. The driving signal <com:Math><semantics>Vgs<annotation encoding="application / x-tex">V_{gs}< / annotation>< / semantics>< / com:Math> Q of MOSFET Q is set high, and MOSFET Q is turned on again. Because MOSFET Q remains OFF state during the delay time (from t0 to t1) generated by the delay circuit, line power extension can be achieved. The delay time generated by the delay circuit can be adjusted as needed, such as setting it to 2 milliseconds for a 60 Hz AC system.

[00149] In some cases, the NOT gate of circuit B in FIG. 22 can be removed, as shown in circuit 2400 of FIG. 24. FIG. 25 illustrates the conceptual waveforms 2500 of circuit B shown in FIG. 24. In this scenario, the falling edge of the <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> signal is utilized to signify the moment when the input AC voltage reaches its peak value. The duration of the <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> signal's low level typically ranges from nanoseconds to microseconds. The delay circuit is employed to prolong the low level duration of the <com:Math><semantics>Vpk<annotation encoding="application / x-tex">V_{pk}< / annotation>< / semantics>< / com:Math> signal to the millisecond range (such as 1 millisecond to 3 millisecond), thereby generating the <com:Math><semantics>Vctrl<annotation encoding="application / x-tex">V_{ctrl}< / annotation>< / semantics>< / com:Math> signal. As MOSFET Q remains OFF during the delay time generated by the delay circuit, line power extension can be achieved.

[00150] Simulation Verification

[00151] Performance Comparison Between Circuits with and without LS-LPEC

[00152] With the AC line providing more power, the capacitor does not need to store as much energy as that in the full bridge case. Thus, the capacitor value can be reduced while achieving the same bus voltage range. FIG. 26 shows the simulation results 2600 of the required capacitance for both LS-LPEC and conventional full bridge for different <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> designs and 60 W load.

[00153] If the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> is designed at 50 V, then 37 <com:Math><semantics>μ<annotation encoding="application / x-tex">\mu< / annotation>< / semantics>< / com:Math>F capacitance should be used for full bridge, while only 15 µF is needed with LS-LPEC. Thus, 59% of capacitor reduction can be achieved for 50 V design. The capacitor reduction ratio will reduce with the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> increases, as the AC power conduction angle is reduced. In practice, a typical <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> design is 90 V- 100 V, at which 1 / 3 of capacitance can be saved with LS-LPEC.

[00154] If the same capacitance is used, then the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> can be increased to relieve the wide gain requirement for the following DC-DC converter. FIG. 27 shows the comparison plot 2700 of the minimum bus voltage between the conventional full bridge and LS-LPEC for different <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> values. In some extreme case with a 39 <com:Math><semantics>μ<annotation encoding="application / x-tex">\mu< / annotation>< / semantics>< / com:Math>F capacitor used, then the <com:Math><semantics>Vbusmin<annotation encoding="application / x-tex">V_{bus\ min}< / annotation>< / semantics>< / com:Math> for the conventional full bridge is only 55 V, while that for LS-LPEC is 86 V. Referring to the same <com:Math><semantics>Vbusmax<annotation encoding="application / x-tex">V_{bus\ max}< / annotation>< / semantics>< / com:Math> of 340 V, the normalized voltage gain requirement is reduced from 6.2 to 4. In other words, the gain requirement reduces to only 64% of that in the full bridge. With the applied <com:Math><semantics>Cin<annotation encoding="application / x-tex">C_{in}< / annotation>< / semantics>< / com:Math> increases, the conduction angle reduces, thus the line power shows less significance.

[00155] In a practical case, if an 82 <com:Math><semantics>μ<annotation encoding="application / x-tex">\mu< / annotation>< / semantics>< / com:Math>F capacitor is used, then the <com:Math><semantics>Vbus_min<annotation encoding="application / x-tex">V_{bus\_min}< / annotation>< / semantics>< / com:Math> can be increased from 99 V in the conventional full bridge to 108 V with LS-LPEC, which is around 10% of improvement. In some topologies, e.g. series resonant converter, this 10% voltage improvement indicates the same amount of current stress reduction. Then, the conduction loss can be reduced to roughly <com:Math><semantics>80%<annotation encoding="application / x-tex">80\%< / annotation>< / semantics>< / com:Math> (= <com:Math><semantics>0.922<annotation encoding="application / x-tex">0.92^2< / annotation>< / semantics>< / com:Math>) of the that in the full bridge case.

[00156] Dynamic Simulation of LS-LPEC

[00157] FIG. 28 is a plot 2800 that illustrates the simulated dynamic performance of LS- LPEC when the input AC voltage transitions from 190 Vac to 100 Vac under a constant load power of 65 W. In this figure, <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math> represents the moment when the AC input voltage undergoes a step-down change. At <com:Math><semantics>t0<annotation encoding="application / x-tex">t_0< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> starts to decrease. By <com:Math><semantics>t1<annotation encoding="application / x-tex">t_1< / annotation>< / semantics>< / com:Math>, <com:Math><semantics>Vbus<annotation encoding="application / x-tex">V_{bus}< / annotation>< / semantics>< / com:Math> equals <com:Math><semantics>vac<annotation encoding="application / x-tex">v_{ac}< / annotation>< / semantics>< / com:Math>, from which point the circuit operates as a conventional full-bridge diode rectifier until time <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>. After <com:Math><semantics>t2<annotation encoding="application / x-tex">t_2< / annotation>< / semantics>< / com:Math>, LS-LPEC is activated, allowing for an increase in the minimum bus voltage from 85 V to 100 V.

[00158] FIG. 29 is a plot 2900 that gives the simulated dynamic performance of LS-LPEC when the input AC voltage jumps from 100 Vac to 190 Vac at a constant load power of 65 W. In this figure, <com:Math><semantics>tx<annotation encoding="application / x-tex">t_x< / annotation>< / semantics>< / com:Math> represents the moment when the AC input voltage undergoes a step-up change. After <com:Math><semantics>tx<annotation encoding="application / x-tex">t_x< / annotation>< / semantics>< / com:Math>, circuit A shown in FIG. 18 (or FIG. 20) operates to disable LS-LPEC. The circuit then operates equivalently to a conventional full-bridge diode rectifier.

[00159] Applicant notes that the described embodiments and examples are illustrative and non-limiting. Practical implementation of the features may incorporate a combination of some or all of the aspects, and features described herein should not be taken as indications of future or existing product plans. Applicant partakes in both foundational and applied research, and in some cases, the features described are developed on an exploratory basis.

[00160] The term "connected" or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[00161] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.

[00162] As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[00163] As can be understood, the examples described above and illustrated are intended to be exemplary only.

Claims

1. A power converter circuit, comprising: a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch Q, and a drain terminal of the switch Q is connected to the second output terminal.

2. The power converter circuit of claim 1, wherein the series circuit extends a total AC power conduction angle to θ + ϕ \theta + \phi where the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein θ \theta is defined as an AC power conduction angle, and ϕ \phi is defined as the line power extension angle introduced through switched control of the series circuit.

3. The power converter circuit of claim 2, wherein the value of ϕ \phi is approximately equal to θ.

4. The power converter circuit of claim 1, further comprising a controller circuit that controls the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch is turned off, and then decreases to the selected DC bus voltage when the switch is turned on; and wherein the switch has a gate terminal controlled by the controller circuit, the controller circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

5. The power converter circuit of claim 4, wherein the controller circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is at an on state during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus min.

6. The power converter circuit of claim 5, wherein the first, second, and third state of operation are repeated during operation.

7. The power converter circuit of claim 5, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

8. The power converter circuit of claim 5, wherein during the second state of operation, a line power extension angle ϕ \phi is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

9. The power converter circuit of claim 8, wherein the line power extension angle ϕ \phi is approximately equal to a AC power conduction angle θ \theta .

10. The power converter circuit of claim 5, further comprising a voltage sensing circuit configured to track an AC voltage value and a DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

11. A controller device configured for operation with one or more power converter circuits each including a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch, and a drain terminal of the switch is connected to the second output terminal; the controller device including a: a logic circuit that is configured to control the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch Q is turned on, and then decreases to the selected DC bus voltage.

12. The controller device of claim 11, wherein the series circuit extends a total AC power conduction angle to θ + ϕ \theta + \phi when the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein θ \theta is defined as an AC power conduction angle, and ϕ \phi is defined as the line power extension angle introduced through switched control of the series circuit.

13. The controller device of claim 12, wherein the value of ϕ \phi is approximately equal to θ \theta .

14. The controller device of claim 11, wherein the switch has a gate terminal controlled by the logic circuit, the logic circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

15. The controller device of claim 11, wherein the logic circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is switched on during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus_min.

16. The controller device of claim 15, wherein the first, second, and third state of operation are repeated during operation.

17. The controller device of claim 15, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

18. The controller device of claim 15, wherein during the second state of operation, a line power extension angle ϕ \phi is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

19. The controller device of claim 15, further comprising a voltage sensing circuit configured to track an actual AC voltage value and an actual DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

20. The controller device of claim 19, further comprising a voltage sensing circuit configured to track an estimated AC voltage value and an estimated DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation, the estimated AC voltage value and the estimated DC voltage value detected using a peak detection circuit, a delay circuit, and a NOT gate operating in concert.

21. A method for power conversion, comprising: operating a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and operating a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch Q, and a drain terminal of the switch Q is connected to the second output terminal.

22. The method of claim 21, wherein the series circuit extends a total AC power conduction angle to θ + ϕ \theta + \phi where the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein θ \theta is defined as an AC power conduction angle, and ϕ \phi is defined as the line power extension angle introduced through switched control of the series circuit.

23. The method of claim 22, wherein the value of ϕ \phi is approximately equal to θ \theta .

24. The method of claim 21, further comprising controlling the switch, using a controller circuit, so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch is turned off, and then decreases to the selected DC bus voltage when the switch is turned on; and wherein the switch has a gate terminal controlled by the controller circuit, the controller circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

25. The method of claim 24, wherein the controller circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is at an on state during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus min.

26. The method of claim 25, wherein the first, second, and third state of operation are repeated during operation.

27. The method of claim 25, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

28. The method of claim 25, wherein during the second state of operation, a line power extension angle ϕ \phi is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

29. The method of claim 28, wherein the line power extension angle ϕ \phi is approximately equal to a AC power conduction angle θ \theta .

30. The method of claim 25, further comprising tracking, by a voltage sensing circuit, an AC voltage value and a DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

31. A control method configured for operation with one or more power converter circuits each including a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch, and a drain terminal of the switch is connected to the second output terminal; the method including a: controlling, by a logic circuit, the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch Q is turned on, and then decreases to the selected DC bus voltage.

32. The method of claim 31, wherein the series circuit extends a total AC power conduction angle to θ + ϕ \theta + \phi when the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein θ \theta is defined as an AC power conduction angle, and ϕ \phi is defined as the line power extension angle introduced through switched control of the series circuit.

33. The method of claim 32, wherein the value of ϕ \phi is approximately equal to θ \theta .

34. The method of claim 31, wherein the switch has a gate terminal controlled by the logic circuit, the logic circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

35. The method of claim 31, wherein the logic circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is switched on during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus min.

36. The method of claim 35, wherein the first, second, and third state of operation are repeated during operation.

37. The method of claim 35, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

38. The method of claim 35, wherein during the second state of operation, a line power extension angle ϕ \phi is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

39. The method of claim 35, further comprising a voltage sensing circuit configured to track an actual AC voltage value and an actual DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

40. The method of claim 39, further comprising a voltage sensing circuit configured to track an estimated AC voltage value and an estimated DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation, the estimated AC voltage value and the estimated DC voltage value detected using a peak detection circuit, a delay circuit, and a NOT gate operating in concert.

41. The power converter circuit of any one of claims 1-10 further comprising a DC-DC converter.

42. The controller device circuit of any one of claims 11-20 further comprising a DC-DC converter.

43. A non-transitory machine readable medium storing machine interpretable instructions, which when executed by a processor, cause the processor to perform a method according to any one of claims 21-40.