For synchronization of multiple arbitrary waveform generators
By introducing a synchronization hub system into multiple arbitrary waveform generators, tight synchronization between AWGs is achieved using the main AWG clock and synchronization controller, the problems of start-up phase randomness and time delay are solved, and synchronization accuracy and stability are improved. .
Patent Information
- Application Number
- CN201510537912.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2014-12-19
- Filing Date
- 2015-08-28
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2035-08-28
AI Technical Summary
When synchronizing multiple arbitrary waveform generators, the phase relationship is random, resulting in complex clock adjustment and time lag, affecting synchronization accuracy and stability.
Using a synchronization hub system, the down-dividing clock is generated through the main AWG clock, combined with the synchronization controller and the synchronization phase detector, eliminate external device requirements, realize synchronization between AWGs, and use the Alignment Fiducial signal and Run signal for synchronization triggering to ensure all AWG starts playing waveforms on the same clock edge.
Reduces trigger delay and start delay, and the time-delay changes between AWGs are tighter, eliminating randomized trials and improving synchronization accuracy and stability.
Smart Images
Figure CN105391431B_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 043,991, filed on August 29, 2014, the contents of which are incorporated herein for all purposes. Technical Field
[0003] The present disclosure relates generally to synchronization of signal generators, and more particularly to synchronization for multiple arbitrary waveform generators. Background Art
[0004] The present disclosure relates generally to synchronization of signal generators, and more particularly to synchronization for multiple arbitrary waveform generators.
[0005] The traditional solution for synchronizing arbitrary waveform generator (AWG) outputs is to fan out a common clock and provide trigger signals to all AWGs from an external source. This approach has the disadvantage that the start-up phase relationship of the clock between the AWGs is random each time the clock is turned on or the frequency is changed. This also requires the use of a qualified oscilloscope and arbitrary function generator (AFG) or a user-provided clock and trigger.
[0006] In the traditional technical field, alignment between instruments is currently a three-step process:
[0007] First, set up the instrument with a common reference or external clock and set the sample rate.
[0008] Next, to start the waveforms simultaneously, both AWGs can be triggered with a common external trigger. The AWGs are both set to synchronous trigger mode, which starts the waveform output on the divided clock edge instead of the sampling clock edge. This provides a wider setup and hold window trigger timing. The trigger mode must be synchronous with the internal divided clock to synchronize the AWGs, and the trigger is provided from an external source such as the AFG or a client-provided clock signal. Each AWG is set up to start playing the output waveform when a trigger is received.
[0009] Finally, when both AWGs start up, the internal divided clocks start at random phases relative to each other. As a result, the outputs need to be aligned whenever the sample rate is changed or the clocks are stopped. In addition, there is a timing skew from the divided clock to the output that is unique to each instrument.
[0010] Alignment is done by observing the output signal or marker from each AWG and adjusting the clock phase until they line up. This is where there is a little random chance in the setup. If the initial startup is too far out of alignment, for example greater than 2ns, then there will not be enough range to adjust the phase of one AWG to line up with the other. In this case, one needs to change the clock and change it back to start at a different phase and restart the system with the common trigger sent again and check the skew between the outputs again to see if it is within adjustment.
[0011] It would therefore be desirable to be able to implement synchronization in a multi-AWG system that better addresses these and other limitations of the prior art. Summary of the invention
[0012] Embodiments of the present invention include a method and apparatus for synchronizing multiple AWGs so that the multiple AWGs operate as a single AWG from a user's perspective. The included synchronization hub eliminates the need for additional external equipment to perform synchronization and eliminates the random trial and error of existing synchronization methods. Embodiments provide smaller trigger delays, smaller delays to start playback, and tighter time lag variations between AWGs.
[0013] A system for synchronizing multiple arbitrary waveform generators is described in the present invention, the system comprising a master arbitrary waveform generator (AWG) having a master AWG clock and a master digital-to-analog converter (DAC). The system further comprises one or more slave arbitrary waveform generators (AWGs), each of which has a slave digital-to-analog converter (DAC). The synchronization hub of the system comprises a synchronization controller and a synchronization phase detector. The system is configured with signal paths between the master DAC and the synchronization phase detector, between the master DAC and the synchronization controller, and between the slave DAC and the synchronization phase detector. The master DAC is configured to generate a divided-down clock (SystemRefClock (system reference clock)) from the master AWG clock, and output the SystemRefClock to the synchronization hub. The outputs on the synchronization hub to the master AWG and the slave AWG are configured to output a clock signal (SystemClock (system clock)) derived from the SystemRefClock, wherein the SystemClock is used within the AWG to indicate when to start playing a waveform from the AWG.
[0014] Aspects of the present invention further include a method for synchronizing a type of multi-AWG system having a master arbitrary waveform generator, one or more slave AWGs, and a synchronization hub having a synchronization controller and a synchronization phase detector. The method operates by receiving a divided-down clock (SystemRefClock) signal from the master arbitrary waveform generator (AWG) at the synchronization hub. The method then derives a clock signal (SystemClock) from the SystemRefClock received from the master AWG, and outputs the SystemClock signal to the master AWG and to one or more slave AWGs. Finally, the SystemClock signal is used to time the synchronization trigger for the master AWG and one or more slave AWGs to play the waveform. In a preferred embodiment of the present invention, the synchronization trigger includes an AlignmentFiducial signal and a Run signal.
[0015] Other aspects of the invention further include a method for synchronizing multiple instruments, the multiple instruments including multiple arbitrary waveform generators (AWGs) using a type of synchronization hub having a synchronization controller and a synchronization phase detector. The method operates by setting the same sampling rate for each instrument and designating one of the AWGs as a master AWG, wherein the remaining AWGs are designated as slave AWGs. The method outputs a SystemRefClock signal from each AWG to the synchronization phase detector, compares the phase of the SystemRefClock signal received from the master AWG with the phase from each slave AWG, and aligns the phase of the SystemRefClock signal with a target. After the alignment step, a pulse signal (preferably an AlignmentFiducial signal) is output from the synchronization controller to each AWG so that the pulse signal is received simultaneously at the AWGs. The method then uses the pulse signal to simultaneously trigger a read command and a write command for the AWG (e.g., for a data FIFO) on the same clock edge. Before playing the waveform, but after triggering the FIFO, a Run pulse signal is sent to the AWG, which then begins playing the waveform.
[0016] The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention which proceeds with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a block diagram of a system including a synchronization hub for synchronizing output signals of two or more signal generators according to an embodiment of the present invention.
[0018] Figure 2is a flow chart illustrating an alignment process of an arbitrary waveform generator (AWG) system according to aspects of the present invention.
[0019] Figure 3 is a flow chart illustrating a calibration process of an AWG system according to aspects of the present invention. DETAILED DESCRIPTION
[0020] For ease of explanation, Figure 1 Two AWGs are shown, but embodiments of the present invention may include more than two AWGs. Generally, one of the AWGs 110 and 130 in the system 100 is set as the master device. Figure 1 In the example, AWG 110 is set as the master device and AWG 130 is set as the slave device. The master AWG 110 controls the synchronization of the system. Another AWG (such as AWG 130) is designated as the slave instrument.
[0021] Figure 1 Included are block representations of operations for synchronizing an AWG system. For example, these blocks may operate on specialized hardware such as an application specific integrated circuit (ASIC), on programmable hardware such as a field programmable gate array (FPGA), or on software operating on a specifically programmed general purpose processor. Other implementations are also possible. Different blocks may be configured to operate in any of these implementations.
[0022] The master AWG 110 controls the synchronization of the system 100. The synchronization process compares everything to the master AWG 110 clock.
[0023] The synchronization hub (or sync hub) 160 distributes the clock via a DAC clock fanout 166, which feeds 200, 300 the digital-to-analog converters (DACs) 112, 132 present within each of the AWGs 110, 130. The source of this clock may be generated from the master AWG 110 or an external signal generator. The DACs 112, 132 generate a divided-down clock, which is referred to and illustrated as SystemRefClock. The master and slave AWG SystemRefClocks feed 202, 302 back into the synchronization hub synchronization phase detector 164 for use in the synchronization process. The master SystemRefClock is also fed 204 into the hub synchronization controller 162, which distributes a derived clock from the SystemRefClock. The SystemRefClock is fed into a phase-locked loop (pll), and the output of the pll is distributed as the system clock for the system. This derived clock is Figure 1 Referred to as SystemClock in .
[0024] In the system 100, a SystemClock is assigned 206, 306 to each of the AWGs 110, 130. The SystemClock is used to clock the AlignmentFiducial 208, 308 and Run 210, 310 signals to the sequence waveform controller 114, 134 of each of the AWGs 110, 130, which is used to indicate to each instrument when to start playing the waveform. There is a second phase detector circuit in the sync backbone 160, referred to as the calibration phase detector 168, which is used together with the analog output 212, 312 of each of the AWGs 110, 130 to calibrate the sync phase detector 164 over its operating frequency range.
[0025] AWG Alignment Process
[0026] Embodiments of the present invention extend the synchronization process that occurs in a single instrument to multiple instruments. Embodiments work with any number of slave instruments. The AWGs in the system go through this alignment process every time the sampling rate changes. All instruments run the same sampling rate.
[0027] Figure 2 Illustration of the AWG alignment process.
[0028] The first step 402 is for the user to select a desired clock frequency by setting the desired rate in the main AWG 110 (step 404) or using an external signal generator (step 406).
[0029] After the clock has been set, the clock circuit of the DAC is reset 408 and the SystemRefClock of the slave is aligned 410 with the SystemRefClock of the master. This is done by using the synchronous phase detector 164 in the hub 160 to compare the phase between the master and slave SystemRefClock 202, 302 412. The slave AWG 130 clock phase is rotated 414 using an IQ modulator located within the DAC 112, 132 until the master and slave SystemRefClock phases reach a calibration target. One calibration target would be the desired phase difference between the master SystemRefClock and the slave SystemRefClock to produce zero skew on the master and slave DAC analog outputs.
[0030] After SystemRefClock alignment, each AWG in the system is set up to receive 416 the AlignmentFiducial pulse 208, 308. This is used to get all the data FIFOs feeding the DACs in the AWGs to start reading and writing on the same clock edge 418. AlignmentFiducial is a SystemClock unit width (tickwide) that is sent from the sync hub 160 so that all instruments receive the signal at the same time. AlignmentFiducial is time aligned with the SystemClock at each instrument so that the pulses are received on the same clock edge.
[0031] The final step is to cause the system 100 to start playing the waveform 422. This is accomplished by sending a SystemClock unit width pulse on the Run lines 210, 310 in block 420 to cause all AWGs 110, 130 to start playing the waveform.
[0032] Calibrating the Synchronous Phase Detector
[0033] The synchronous phase detector 160 is calibrated to remove cable and instrument-to-instrument skew variations. This is accomplished using a calibration phase detector 168. Each AWG 110, 130 is configured to output a square wave from its DAC analog output. The AWG system 100 is calibrated at multiple operating frequency points.
[0034] Figure 3 A process for calibrating AWGs within a multi-AWG system is illustrated.
[0035] The first step for calibration is to set the clock rate 502 by setting it in the main AWG 110 (step 504) or using an external signal generator (step 506).
[0036] After the clock has been set, the clock circuit of the DAC is reset 508 and the SystemRefClock of the slave device is aligned 510 with the SystemRefClock of the master device. This is done by comparing 512 the phase between the master and slave SystemRefClock using the synchronous phase detector 164 in the hub 160. The slave AWG clock phase is rotated 514 using the IQ modulator until the master and slave SystemRefClock phases have reached a default target. A preferred example of a default target is where the master and slave SystemRefClock have a zero (0) phase difference.
[0037] After SystemRefClock alignment, each of the AWGs 110, 130 in the system 100 is set up to receive 516 the AlignmentFiducial pulse 208, 308. This is used to get all the data FIFOs feeding the DACs in the AWG to start reading and writing on the same clock edge 518. The AlignmentFiducial is one SystemClock unit wide, which is sent from the sync hub 160 and received by all instruments simultaneously.
[0038] The next step is to cause the system to start playing the waveform 522. This is accomplished by sending a SystemClock unit width pulse on the Run lines 210, 310 in block 520 to cause all AWGs 110, 130 to start playing the square wave waveform.
[0039] After outputting the square wave, the slave device's DAC analog output 312 is aligned 524 with the master device's DAC analog output 212. This is done by comparing 526 the phase between the master and slave DAC analog outputs using the calibration phase detector 168 in the hub 160. The slave AWG clock phase is rotated 528 using an IQ modulator until the master and slave DAC analog output phases have alignment on the calibration phase detector.
[0040] Then, the synchronous phase detector 164 is read to obtain the target value to be used in the subsequent alignment after the calibration process, and then the target value is stored 530 so that it can be used in the subsequent alignment in block 532. A preferred example of a target value is the desired phase difference between the master SystemRefClock and the slave SystemRefClock, which is necessary to produce zero skew on the master and slave DAC analog outputs. This is the same value used in the alignment process mentioned above.
[0041] Having described and illustrated the principles of the invention in its preferred embodiments, it should be apparent that the invention can be modified in arrangement and detail without departing from these principles. Applicants claim to protect all modifications and variations within the spirit and scope of the following claims.
Claims
1. A system for synchronizing a plurality of arbitrary waveform generators, comprising: a master arbitrary waveform generator having a master arbitrary waveform generator clock and a master digital-to-analog converter; one or more slave arbitrary waveform generators, each having a slave digital-to-analog converter; a synchronization hub having a synchronization controller and a synchronization phase detector; signal paths between the master DAC and the synchronous phase detector and between the master DAC and the synchronous controller, and between the slave DAC and the synchronous phase detector; wherein the master DAC is configured to generate a divided-down clock master SystemRefClock signal from the master AWG clock and output the master SystemRefClock signal to the synchronization hub, wherein the phases of the master SystemRefClock signal and the slave SystemRefClock signal are compared by using a synchronization phase detector in the synchronization hub, and the slave AWG clock phase is rotated using an IQ modulator until the master SystemRefClock signal and the slave SystemRefClock signal phase reach a calibration target; and The output terminal on the synchronization hub leading to the master arbitrary waveform generator and the slave arbitrary waveform generator is configured to output a clock signal SystemClock derived from the master SystemRefClock signal, and the SystemClock is used in the master arbitrary waveform generator and the slave arbitrary waveform generator to indicate when to start playing the waveform from the master arbitrary waveform generator and the slave arbitrary waveform generator.
2. The system of claim 1, wherein the master AWG clock is generated internally within the master AWG.
3. The system as recited in claim 1, wherein the master AWG clock is provided to the master AWG from an external signal generator.
4. The system of claim 1 , wherein the synchronization hub further comprises a calibration phase detector configured to receive analog outputs of the master arbitrary waveform generator and the one or more slave arbitrary waveform generators and to calibrate the synchronization phase detector over an operating frequency range.
5. The system of claim 1, wherein the slave DAC is configured to output a slave SystemRefClock signal to the synchronization hub along the signal path between the slave DAC and the synchronization phase detector.
6. The system of claim 1 , further comprising an output line pair from the synchronization controller to each of the plurality of arbitrary waveform generators, the output line pair being configured to carry an AlignmentFiducial signal and a Run signal operating with a SystemClock signal to start playing a waveform from the corresponding arbitrary waveform generator.
7. The system of claim 1, wherein the synchronization hub further comprises a DAC clock fan-out configured to output a DAC clock signal to a master DAC and a slave DAC of each slave AWG.
8. A method for synchronizing a multi-AWG system, the multi-AWG system having a master AWG, one or more slave AWGs, and a synchronization hub, the synchronization hub having a synchronization controller and a synchronization phase detector, the method comprising: receiving a divided-down clock master SystemRefClock signal from a master arbitrary waveform generator at the synchronization hub, wherein the phase between the master SystemRefClock signal and the slave SystemRefClock signal is compared by using a synchronization phase detector in the synchronization hub, and the slave arbitrary waveform generator clock phase is rotated using an IQ modulator until the master SystemRefClock signal and the slave SystemRefClock signal phase reach a calibration target; deriving a clock signal SystemClock from a master SystemRefClock signal received from a master arbitrary waveform generator, and outputting the SystemClock signal to the master arbitrary waveform generator and to the one or more slave arbitrary waveform generators; and The SystemClock signal is used to time synchronization trigger signals for the master arbitrary waveform generator and one or more slave arbitrary waveform generators to play waveforms.
9. The method of claim 8, wherein the synchronization trigger signal comprises an AlignmentFiducial signal and a Run signal.
10. The method of claim 8, further comprising the steps of: Analog outputs of a master arbitrary waveform generator and each slave arbitrary waveform generator in the multiple arbitrary waveform generator system are received at the synchronization hub, and the synchronized phase detector is calibrated over an operating frequency range.
11. The method of claim 8, wherein the master AWG includes a master digital-to-analog converter, and the method further comprises outputting the master SystemRefClock signal from the master digital-to-analog converter of the master AWG to the synchronization hub.
12. The method of claim 11, further comprising generating a clock at the master arbitrary waveform generator and feeding the clock to a master digital-to-analog converter of the master arbitrary waveform generator.
13. The method of claim 8, further comprising generating a clock from an external signal generator and feeding the clock to a master digital-to-analog converter of the master arbitrary waveform generator.
14. The method of claim 8, wherein the synchronization hub comprises a synchronization controller and a synchronization phase detector, the method further comprising receiving the master SystemRefClock signal from the master arbitrary waveform generator at the synchronization controller and receiving the master SystemRefClock signal from the master arbitrary waveform generator in the multi-arbitrary waveform generator system and receiving the slave SystemRefClock signal from each slave arbitrary waveform generator in the multi-arbitrary waveform generator system at the synchronization phase detector.
15. A method for synchronizing a plurality of instruments using a synchronization hub, the plurality of instruments comprising a plurality of arbitrary waveform generators, the synchronization hub having a synchronization controller and a synchronization phase detector, the method comprising: setting the same sampling rate for each of said instruments; designating one of the arbitrary waveform generators as a master arbitrary waveform generator and the remaining arbitrary waveform generators as slave arbitrary waveform generators; outputting a master SystemRefClock signal from the master arbitrary waveform generator to a synchronous phase detector, and outputting a slave SystemRefClock signal from each slave arbitrary waveform generator to a synchronous phase detector, comparing a phase of the master SystemRefClock signal received from the master arbitrary waveform generator with a phase from each slave arbitrary waveform generator, and aligning the phases of the master SystemRefClock signal of the master arbitrary waveform generator and the slave SystemRefClock signal of the slave arbitrary waveform generator with a target; After the alignment step, outputting a pulse signal from the synchronization controller to the master arbitrary waveform generator and each slave arbitrary waveform generator, and simultaneously receiving the pulse signal at the master arbitrary waveform generator and the slave arbitrary waveform generator; using the pulse signal to simultaneously trigger read and write commands for a master arbitrary waveform generator and the slave arbitrary waveform generator on the same clock edge; as well as Plays waveforms on the master and slave AWGs.
16. The method of claim 15, wherein the step of playing the waveform comprises: deriving a clock signal SystemClock from the master SystemRefClock signal received from the master arbitrary waveform generator, and outputting the SystemClock signal to the master arbitrary waveform generator and the slave arbitrary waveform generator; Receiving a clock alignment signal AlignmentFiducial having a width of a SystemClock unit at the master arbitrary waveform generator and each slave arbitrary waveform generator simultaneously; and Receives a Run signal with a width of SystemClock units to enable the master arbitrary waveform generator and each slave arbitrary waveform generator to start playing waveforms.
17. The method as claimed in claim 15, wherein the step of simultaneously triggering comprises: using the pulse signal to simultaneously trigger reading and writing of data FIFOs for the master arbitrary waveform generator and the slave arbitrary waveform generator on the same clock edge; as well as After the data FIFO is triggered, a Run signal is sent to the master arbitrary waveform generator and the slave arbitrary waveform generator as a trigger for playing the waveform.
18. The method of claim 15, wherein the target is a default target.
19. The method of claim 18, wherein the waveform is a square waveform.
20. The method of claim 19, wherein the master AWG includes a master DAC and each slave AWG includes a slave DAC, the method further comprising aligning an analog output of the slave DAC of each slave AWG with an analog output of the master DAC of the master AWG by: comparing a phase of an analog output of the master arbitrary waveform generator with a phase of an analog output of each slave arbitrary waveform generator; Using an IQ modulator to rotate the phase of each analog output from the arbitrary waveform generator until the master DAC and slave DAC analog output phases are aligned on a calibration phase detector; as well as Use the target as a calibration target in subsequent alignments.