Implementing Floating-Point Trigonometric Functions in Integrated Circuit Devices

Abstract

This embodiment relates to an integrated circuit having circuitry for implementing floating-point trigonometric functions. The circuitry may include approximation circuitry for generating approximations of the outputs of the trigonometric functions, storage circuitry for storing predetermined output values of the trigonometric functions, and selector circuitry for selecting between different possible output values based on control signals from control circuitry. In some embodiments, the circuitry may include mapping circuitry and restoration circuitry. The mapping circuitry may map input values from an original quadrant of the trigonometric circle to a predetermined input interval, and the restoration circuitry may map output values selected by the selection circuitry back to the original quadrant of the trigonometric circle. If desired, the circuitry may be implemented in a dedicated processing block.

Description

Technical Field

[0001] The present embodiments relate to integrated circuits, and more particularly, to implementing floating-point trigonometric functions in integrated circuit devices. Background Art

[0002] As application complexity increases, it becomes more common to include specialized arithmetic circuits, sometimes arranged in dedicated processing blocks within an integrated circuit. Such specialized processing blocks may be partially or completely hardwired to perform one or more specific tasks, such as logical or mathematical operations. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements.

[0003] Examples of structures typically implemented in such dedicated processing blocks include: multipliers, adders, accumulators, arithmetic logic units (ALUs), barrel shifters, various memory elements or storage circuits, logical AND, logical NAND, logical OR, logical NOR arrays, etc., or combinations thereof, various memory elements or storage circuits such as first-in-first-out (FIFO) circuits, last-in-first-out (LIFO) circuits, serial-in-parallel-out (SIPO) shift register circuits, parallel-in-serial-out (PISO) shift register circuits, random access memory (RAM) circuits, read-only memory (ROM) circuits, content addressable memory (CAM) circuits, and register files.

[0004] One particularly useful specialized processing block, sometimes referred to as a digital signal processing (DSP) block, can be used to process digital signals such as video signals, audio signals, etc. Such blocks are also often referred to as multiply-accumulate (MAC) blocks because they include structures for performing multiplication operations and summing and / or accumulating the multiplications.

[0005] Integrated circuits, such as programmable integrated circuits, often include specialized processing blocks. Each of those specialized processing blocks includes multipliers, adders, and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways.

[0006] Until recently, the arithmetic operators (adders and multipliers) in such dedicated processing blocks have been exclusively fixed-point operators. More recently, circuits that perform floating-point arithmetic have been introduced into dedicated processing blocks, sometimes in combination with general-purpose programmable logic external to the dedicated processing blocks.

[0007] Many scientific applications utilize the trigonometric functions sine (sin), cosine (cos), and tangent (tan), as well as their reciprocals cosecant (csc), secant (sec), and cotangent (cot). Trigonometric functions are typically defined for relatively small angular ranges, such as 0-360 degrees or 0-2π radians. For angles greater than 2π, the values of the trigonometric functions repeat. The tangent function is special in that it repeats on both the left and right sides of the interval [-π / 2, π / 2]. Trigonometric functions often require the use of floating-point numbers.

[0008] Floating-point trigonometric functions are part of the math.h programming library and are available in all major programming languages. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A diagram of an illustrative integrated circuit, such as a programmable integrated circuit, is shown in accordance with some embodiments.

[0010] Figure 2 is a diagram of an exemplary binary floating point number representation, according to some embodiments.

[0011] Figure 3 is a diagram of an illustrative plot of a tangent function in the interval between -π / 2 and π / 2, according to some embodiments.

[0012] Figure 4 is a diagram of an illustrative floating-point tangent operator circuit, in accordance with some embodiments.

[0013] Figure 5 is a diagram of an exemplary binary fixed-point number representation according to some embodiments.

[0014] Figure 6 is a diagram of an illustrative approximation circuit in a floating-point tangent operator circuit, according to some embodiments.

[0015] Figure 7 is a diagram of an illustrative extraction circuit that generates two parts of a fixed-point number based on a floating-point number, according to some embodiments.

[0016] Figure 8 is a diagram of an illustrative extraction circuit that generates a portion of a fixed-point number based on a floating-point number, according to some embodiments.

[0017] Figure 9 is a diagram of two exemplary last position units (ULPs) before π / 2, according to some embodiments.

[0018] Figure 10 is a diagram of an illustrative floating-point tangent operator circuit that selects between three approximations in accordance with some embodiments.

[0019] Figure 11 is a flow chart of illustrative operations for computing trigonometric functions of floating-point numbers in an integrated circuit, according to some embodiments.

[0020] Figure 12 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for configuring an integrated circuit to perform arithmetic operations on first and second floating-point numbers, according to some embodiments.

[0021] Figure 13 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine-executable instructions for configuring an integrated circuit to perform arithmetic operations on first and second floating-point numbers, according to some embodiments. DETAILED DESCRIPTION

[0022] The present embodiments presented herein relate to integrated circuits, and more particularly, to implementing floating-point trigonometric functions in integrated circuit devices.

[0023] Many scientific applications utilize the trigonometric functions sine (sin), cosine (cos), and tangent (tan), and their reciprocals cosecant (csc), secant (sec), and cotangent (cot). Trigonometric functions often require the use of floating-point numbers, and many hardware implementations of trigonometric functions use algorithms from the Coordinate Rotation Digital Computer (CORDIC) family of algorithms, which compute trigonometric results through iterative approximations.

[0024] Iterative implementations consume fewer resources and are preferred when implemented in a processor's floating point unit (FPU). Unrolled implementations are often encountered in computational data paths that target high throughput and feature multiple deep arithmetic structures with each level containing wide adders. Unrolled implementations can require significant resources (e.g., chip area) and can result in long delays (e.g., due to register pipelining). When resources are limited, some unrolled implementations may encounter difficulties with closing timing.

[0025] Architectures based on polynomial approximations can be used, for example, to implement sine, cosine, and division using inverse functions. However, these approaches are often wasteful when implementing tangent operations using operator components, as this involves coupling the sine and cosine operator circuits with a divider operator circuit.

[0026] Therefore, it may be desirable to provide a tangent operator circuit in an integrated circuit device that consumes relatively few resources and has high throughput combined with low latency.

[0027] Those skilled in the art will recognize that the exemplary embodiments can be practiced without some or all of these specific details.In other instances, well-known operations are not described in detail to avoid unnecessarily obscuring the embodiments.

[0028] Figure 1 A diagram of an illustrative integrated circuit device, such as programmable integrated circuit 100 , is shown in accordance with some embodiments.

[0029] Programmable integrated circuit 100 may have input / output circuitry 102 for driving signals out of programmable integrated circuit 100 and for receiving signals from other devices. Input / output circuitry 102 may include conventional input / output circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry for connecting one integrated circuit to another.

[0030] As shown, the input-output circuits 102 can be located near the periphery of the programmable integrated circuit 100. If desired, the programmable integrated circuit 100 can have the input-output circuits 102 arranged in a different manner. For example, the input-output circuits 102 can form one or more columns of input-output circuits that can be located anywhere on the programmable integrated circuit (e.g., evenly distributed across the entire width of the programmable integrated circuit). If desired, the input-output circuits 102 can form one or more rows of input-output elements (e.g., distributed across the entire height of the programmable integrated circuit). Alternatively, the input-output circuits 102 can form islands of input-output elements that can be distributed across the surface of the programmable integrated circuit or clustered in selected areas.

[0031] Vertical interconnect resources 140 and horizontal interconnect resources 150 (e.g., global and local vertical and horizontal conductive lines and buses) may be used to route signals on programmable integrated circuit 100. Vertical and horizontal interconnect resources 140 and 150 include conductive lines and programmable connections between corresponding conductive lines, and are therefore sometimes referred to as programmable interconnects, configurable interconnects, or configurable interconnect circuits.

[0032] The programmable logic region may include programmable components such as digital signal processing circuitry 120 and memory circuitry 130, which may be organized in dedicated blocks, or other combinational and sequential logic circuits may be organized in logic array block 110. The programmable logic region may be configured to perform custom logic functions.

[0033] If desired, digital signal processing circuitry 120 and memory circuitry 130 may have limited configurability. In some embodiments, the programmable logic region may include additional specialized blocks, such as programmable phase-locked loop circuitry, programmable delay-locked loop circuitry, or other specialized blocks with limited configurability.

[0034] In some embodiments, the digital signal processing circuit 120 may be adapted to efficiently perform floating-point trigonometric operations. For example, the digital signal processing circuit 120 may include storage circuits to store the results of trigonometric operations or barrel shifter circuits to assist in the encoding and decoding processes described below.

[0035] Programmable integrated circuit 100 may include programmable memory elements. These memory elements may be loaded with configuration data (sometimes also referred to as programming data) using input / output circuitry 102. If desired, these memory elements may provide control signals to multiplexers in digital signal processing circuitry 120.

[0036] Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of the associated logic components in the programmable logic region. In a typical scenario, the output of the loaded memory element is applied to the gate of the transistor in the programmable logic region to turn on or off certain transistors, and thereby configure the logic and routing paths in the programmable logic region. Programmable logic circuit elements that can be controlled in this manner include portions of multiplexers (e.g., multiplexers for forming routing paths in programmable interconnects), lookup tables, logic arrays, XOR, AND, OR, NAND, and NOR logic gates, transmission gates, inverters, and the like.

[0037] The memory elements may use any suitable volatile and / or nonvolatile memory structures such as random access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memories, configuration RAM, or programmable memory elements.

[0038] The circuitry of programmable integrated circuit 100 can be organized using any suitable architecture. As an example, the logic of programmable integrated circuit 100 can be organized in a series of rows and columns in larger programmable logic regions, where each region contains multiple smaller logic regions.

[0039] The smaller regions may be, for example, logic regions sometimes referred to as logic elements (LEs), each of which includes a lookup table, one or more registers, and a programmable multiplexer circuit. The smaller regions may also be, for example, logic regions sometimes referred to as adaptive logic modules (ALMs) or slices. Each logic region may include a pair of adders, a pair of associated registers, a shift register, and one or more lookup tables or other shared combinational logic blocks (i.e., resources from a pair of LEs, sometimes referred to as adaptive logic elements (ALEs) in the current context). The larger region may be, for example, a logic array block (LAB) or a configurable logic block (CLB) containing multiple logic elements, multiple ALMs, or multiple slices.

[0040] During device programming, configuration data is loaded into programmable integrated circuit 100, which configures the programmable logic regions to cause their logic resources to perform desired logic functions.

[0041] In some embodiments, programmable integrated circuit 100 can be configured to implement trigonometric functions. For example, digital signal processing circuit 120, memory circuit 130, and other resources in the programmable logic region can be configured to implement a floating-point tangent operation (i.e., a circuit that receives a floating-point number and generates the tangent of the floating-point number in a floating-point format).

[0042] Floating-point numbers are commonly used in computing systems to represent real numbers in scientific notation. They are designed to cover a wide range of values and various precision requirements. IEEE Standard 754, ANSI / IEEE Standard 754-2008, published on August 29, 2008, is commonly used for floating-point numbers. Figure 2 The representation of floating point numbers is shown in .

[0043] like Figure 2 As shown, a floating-point number consists of three different parts: a sign, a mantissa, sometimes also called a significant number, and an exponent. Each of these parts can be represented by a binary number in the format of the IEEE 754 standard, with different bit sizes depending on the precision. For example, a single-precision floating-point number requires 32 bits, which are distributed as follows: one sign bit (bit 31), eight exponent bits (i.e., m=8, which uses bits [30:23]) and 23 mantissa bits (i.e., n=23, which uses bits [22:0]). For example, a double-precision floating-point number requires 64 bits, including one sign bit (bit 63), 11 exponent bits (i.e., m=11, which uses bits [62:52]) and 52 mantissa bits (i.e., n=52, which uses bits [51:0]). A half-precision floating point number requires 16 bits, including a sign bit (bit 15), five exponent bits (ie, m=5, which uses bits [14:10]), and 10 mantissa bits (ie, n=10, which uses bits [9:0]).

[0044] The mantissa can also have extra bits according to IEEE standard 754. A mantissa with extra bits is sometimes called an extended mantissa.

[0045] According to the IEEE 754 standard, the sign of a floating-point number is represented using a single bit, where zero represents a positive number and one represents a negative number.

[0046] The exponent of a floating-point number is preferably represented as an unsigned binary number, with a range of 0 to 255 for single-precision format. To map negative exponents to the representable exponent range, a positive bias is used. For single-precision floating-point numbers, the bias is preferably +127. For example, for a represented exponent, a value of 140 actually represents an exponent of (140-127)=13, while a value of 100 represents (100-127)=-27. For double-precision and half-precision floating-point numbers, the exponent bias is preferably +1023 and +15, respectively.

[0047] Thus, a binary floating point number of a given precision having a bias value of "bias", a sign field having a value of "sign", an exponent field having a value of "exponent", and a mantissa having a value of:

[0048] (-1) '符号' ×('end')× 2('指数'-'偏差') (1)

[0049] As described above, according to the IEEE 754 standard, the mantissa is a normalized number whose value is in the interval [1, 2) (i.e., greater than or equal to 1 and less than 2) and represents the precision component of the floating-point number as shown in equation (1). Because the mantissa is stored in binary format, the leading bit can be 0 or 1, but for normalized numbers, it will always be 1. Therefore, in a system where numbers are always normalized, the leading bit is not necessarily stored and can be implicit, effectively giving the mantissa an extra bit of precision.

[0050] The IEEE 754 standard also defines special cases. For example, a zero exponent with a zero mantissa represents "0", an all-ones exponent with a zero mantissa represents infinity, an all-ones exponent with a non-zero mantissa represents Not a Number (NaN), and a zero exponent with a non-zero mantissa represents a subnormal number.

[0051] A subnormal number, also known as a denormal number or a denormalized number, or a number that gradually underflows, is a number whose mantissa value is less than one and whose exponent is equal to the smallest representable exponent, in the single-precision floating-point format of 1-127=-126.

[0052] Figure 3is a diagram of an illustrative drawing of the tangent function in the interval between -π / 2 and π / 2 according to some embodiments. Each π / 2±kπ repeats the same shape (i.e., the interval between -3π / 2 and -π / 2, the interval between -5π / 2 and -3π / 2, etc., and also repeats the same shape in the interval between π / 2 and 3π / 2, the interval between 3π / 2 and 5π / 2, etc.). In other words, the tangent function is periodic. In addition, the tangent function is symmetric with respect to the origin (i.e., tan(x) = -tan(-x)). Therefore, the input range of the tangent function can be limited to 0 to π / 2, and the value of the tangent function at any angle can be derived from the tangent function of the angle between 0 and π / 2.

[0053] The Taylor expansion of the tangent function around the point x = 0 is:

[0054]

[0055] The input range of 0 to π / 2 can be divided into two or more sub-ranges where the tangent function exhibits certain characteristics. As an example, if x is very small (e.g., less than 2 -m / 2 , where m is Figure 2 The number of mantissa bits), a good approximation of the tangent function is x (i.e., for x < 2 -m / 2 , tan(x)=x). This is due to the fact that the higher-order terms in Equation 2 are weighted less than the least significant bit (LSB) of x and are shifted out in the final summation. As another example, if x approaches π / 2, the tangent function has asymptotic properties.

[0056] Figure 4 FIG4 is a diagram of an exemplary floating-point tangent operator circuit according to some embodiments. Floating-point tangent operator circuit 400 may receive a floating-point number x and generate a floating-point number that is the tangent of x (i.e., tan(x)). As shown, floating-point tangent operator circuit 400 may include an optional mapping circuit 405 and an optional restoration circuit 445, an approximation circuit 410, a storage circuit 420, a control circuit 430, and a selector circuit 440.

[0057] The mapping circuit can map input values from the original quadrant of the trigonometric circle to a predetermined input interval, and the restoration circuit can map the output value selected by the selection circuit back to the original quadrant of the trigonometric circle. For example, the optional mapping circuit 405 can map a floating point number x to an interval between zero and π / 2. For example, the mapping circuit 405 can receive the floating point number x and recursively subtract π from the absolute value of the floating point number x until the absolute value of the result is less than π / 2. The mapping circuit 405 can then provide the absolute value of the result to the approximation circuit 410, the storage circuit 420, and the control circuit 430, and send the sign of the result to the optional restoration circuit 445.

[0058] As shown, selector circuit 440 can output the tangent of the absolute value of the result of the mapping function. Thus, if the recursive subtraction in mapping circuit 405 results in a number in the interval between -π / 2 and zero, restoration circuit 445 can restore the correct sign of the output to obtain the symmetry tan(x)=-tan(-x). For example, restoration circuit 445 can replace the sign of the floating-point number outside of selector circuit 440 with the sign received from mapping circuit 405.

[0059] For the remainder of this application and without loss of generality, a floating point number x is meant to have been mapped to the interval between zero and π / 2.

[0060] Storage circuit 420 may be any addressable memory circuit, such as a lookup table (LUT), a random access memory (RAM) circuit, a read-only memory (ROM) circuit, a content addressable memory (CAM) circuit, and a register file, or any combination thereof. If desired, storage circuit 420 may store a predetermined number of values of the tangent function for a predetermined number of input values. For example, storage circuit 430 may include q values of the tangent function for floating point numbers within q last place units (ULPs) less than π / 2. As an example, Figure 9 Three floating point numbers that are less than π / 2 and within three ULPs of π / 2 are shown.

[0061] The storage circuit 420 may receive an address signal based on the input signal x and provide a corresponding value of tan(x) to the selector circuit 440 in response to receiving the address signal.

[0062] Approximation circuit 410 may receive an input value x and generate a signal that approximates tan(x) and provide the signal to selector circuit 440. Approximation circuit 410 may generate an approximation of the tangent of the input value using any polynomial approximation method, such as the Taylor expansion or Chebyshev expansion of equation (2), to name a few. As another example, if desired, approximation circuit 410 may implement a CORDIC algorithm. As yet another example, the approximation circuit 410 may be implemented as follows: Figure 6 The implementation shown approximates circuit 410 .

[0063] The floating point tangent operator circuit 400 may utilize the specific characteristics of the tangent function described above. For example, if x is below a first predetermined threshold (e.g., less than or equal to 2 -m / 2 or any other predetermined threshold that may or may not be based on the number of mantissa bits), then control circuit 430 may instruct selector circuit 440 to output x.

[0064] Similarly, if x is above a second predetermined threshold (e.g., greater than or equal to π / 2-q*ULP), control circuit 430 may instruct selector circuit 440 to output the signal received from storage circuit 420. In other words, if x is less than or equal to the distance q*ULP is from π / 2, control circuit 430 may instruct selector circuit 440 to output the stored signal of tan(x).

[0065] If x is between the first and second thresholds (e.g., greater than 2 -m / 2 and is less than π / 2-q*ULP), the control circuit 430 may instruct the selector circuit 440 to select the signal from the approximation circuit 410.

[0066] For the tangent function, the trigonometric identity for the tangent of a sum of values can be used to decompose the input value x into the sum of different ranges of bits of the input value x. Because some component ranges are small, the identity will be simplified relative to these component ranges. The identity can be implemented in appropriate circuits. The following identity applies to the tangent function:

[0067]

[0068] Substituting equation (3) into itself further decomposes the input variable yields:

[0069]

[0070] Although equation (4) looks complicated, the properties of the tangent function and the accuracy of single-precision arithmetic can be used to greatly simplify the calculation.

[0071] As shown above, when x is small, tan(x) ≈ x. In single-precision floating-point arithmetic (e.g., under the IEEE 754 standard), the exponent is offset by 127 (i.e., 1 = 2° is represented by an exponent value of 127 in the single-precision floating-point format). If the input exponent is 115 or less (i.e., a true exponent of -12 or less), the error between tan(x) and x is below the precision of the number format, so below this value, tan(x) can be considered equal to x.

[0072] For single-precision floating-point formats, the approximation of the tangent function can therefore be limited to a relatively narrow exponent range, between 115 and 127, or a dynamic range of 12 bits. For arithmetic operations, according to the IEEE 754 standard, the precision is 24 bits (23 bits of mantissa plus an implicit leading bit). Therefore, the input number can be accurately represented as a 36-bit fixed-point number (24 bits of precision + 12 bits of dynamic range).

[0073] Similar estimates can be made for half-precision floating-point numbers, double-precision floating-point numbers, and quad-precision floating-point numbers.

[0074] Such a fixed-point number may then be divided into a predetermined number of components. Figure 5 It shows that the fixed-point number is divided into components a, b and c. If x=a+b+c as described above, the i high-order bits can be designated as the c component, the next j bits can be designated as the a component, and the k least significant bits (LSBs) can be designated as the b component.

[0075] As mentioned above, for less than 2 -m / 2 For any value of x, tan(x) = x, where m is Figure 2 Consider the case where i and j are chosen so that m / 2<(i+j-1). In this case, b<2 -m / 2 , and the tangent of b can be approximated as tan(b)=b, and equation (4) can be simplified as follows:

[0076]

[0077] Based on the choice of i, the tangent of a (i.e., tan(a)) may be relatively small. As an example, for i=j=9 and x is a single-precision floating point number, the maximum value of a is slightly less than 0.0039062510 (tan(a)=0.0039062710), and the maximum value of b is 0.0000152610, which is also its tangent.

[0078] Therefore, the maximum value of tan(a)×b is 5.96×10 -8 , and the minimum value of 1-tan(a)×b is 0.9999999410. The maximum value of tan(a)+b is 0.0039215286610. The difference between the maximum value of tan(a)+b and the maximum value of tan(a)+b divided by the minimum value of 1-tan(a)×b is 2.35×10 -10 In other words, the error is 32 digits to the right of the decimal point. In the worst case, where c is zero, the error does not appear in the precision of the result, which is only 24 digits in single-precision floating-point format. Therefore, using the approximation 1-tan(a)b=1, equation (5) can be further simplified to:

[0079]

[0080] As long as a and c are represented by i and j bits respectively, the tangent of all possible bit combinations can be stored in the memory circuit. An embodiment of the tangent calculation is shown in Figure 6 is implemented in the approximation circuit 410 .

[0081] like Figure 6 As shown, approximation circuit 410 may include extraction circuit 610 , storage circuits 620 and 630 , and arithmetic circuit 640 .

[0082] The extraction circuit 610 may receive an input value x in the form of a floating point number having an exponent, a leading bit, and a mantissa. Based on the received input value x, the extraction circuit 610 may generate numbers c and a in fixed point format (i.e., c and a) and generate number b in floating point format (i.e., FP b). If desired, c, a, and b may be Figure 5 The components c, a, and b of the fixed-point number shown in . Figure 7 and Figure 8 An illustrative embodiment of extraction circuit 610 is shown.

[0083] Based on the values of c and a, the address signal can access the corresponding storage circuits 630 and 620 during a read access operation to retrieve the corresponding tangents of c and a in floating point format (i.e., FP tan(c) and FP tan(a)). The arithmetic circuit 640 can receive the tangents of c and a and b in floating point format (i.e., FP b, FP tan(c), and FP tan(a)) and implement either equation (5) or (6) to determine an approximate value of the tangent of x in floating point format (i.e., tan(x)).

[0084] Figure 7 1 shows an illustrative diagram of an extraction circuit according to some embodiments. Figure 7 As shown, the extraction circuit can be based on Figure 2 The floating-point number format shown in takes a floating-point number and a leading bit between the exponent and mantissa bits and generates the Figure 5 The i and j bits of the fixed-point number parts c and a are shown in .

[0085] like Figure 7 As shown, the extraction circuit may include an encoder circuit 710 and a right shift circuit 720. The encoder circuit 710 may receive p bits from the exponent and determine the number of bits to be shifted right in the right shift circuit 720.

[0086] The number of bits p that the encoder receives from the exponent can be selected based on the numbers i and j. For example, p can be determined such that 2 p ≥(i+j). In fact, shifting the leading bit of the floating-point number to the right by (i+j) bits may result in c and a being zero. Therefore, further shifting and adding more zeros is unnecessary.

[0087] The encoder circuit 710 may be responsible for the deviation of the floating point format. For example, consider the case where i=j=9, p=5, and the exponent is 120 (i.e., 011110002 in single-precision floating-point arithmetic under the IEEE 754 standard), which corresponds to a true exponent of -7 because the exponent is offset by 127. In this case, the encoder circuit 710 may receive the five LSBs of the exponent (i.e., 110002) and output the number 7 (i.e., 001112).

[0088] For tangent function, floating-point number may be limited to the interval between zero and π / 2. Therefore, the true exponent of binary number format is less than or equal to zero. According to IEEE 754 standard, the exponent deviation of floating-point number is selected to have all one except MSB (that is, 011111112 for single-precision floating-point number format), and in all bits except MSB of the exponent of floating-point number, zero is used instead of one and one is used instead of zero to encode the true exponent that is less than or equal to zero. For example, the true exponent of -24 can be encoded as 011001112 with single-precision floating-point number format. Therefore, in some embodiments, encoder circuit 710 may include an inverter that will reverse the p-bit received from the exponent bit by bit, and if desired, these inverters can be built into right shift circuit 720.

[0089] The right shift circuit 720 may receive the leading bits and the next (i+j-1) most significant bits (MSBs) of the mantissa and right shift these bits according to the number determined in the encoder circuit 710. The right shift circuit 720 may be a barrel shifter that inserts a zero in the most significant bit position for each bit that is right shifted.

[0090] The i MSBs out of right shift circuit 720 may be assigned to c, and the next j bits out of right shift circuit 720 may be assigned to a.

[0091] Figure 8 1 shows an illustrative diagram of an extraction circuit according to some embodiments. Figure 8 As shown, the extraction circuit can receive Figure 2 The floating point format shown and generates a floating point number represented in floating point format Figure 5 The floating point number b (ie, FP b) of the portion b of the fixed point number shown in .

[0092] like Figure 8 As shown, the extraction circuit may include an optional encoder circuit 810, a mask table 820, an application mask circuit 830, and a floating point subtractor 840. The encoder circuit 810 may receive p bits from the exponent and generate an address signal to retrieve a k-bit binary mask stored in the mask table 820. The mask table 820 may be one or more storage circuits that are capable of storing 2 pMask table 820 may be implemented by a predetermined number of lookup tables (LUTs) or random access memories (RAMs), for example.

[0093] As an example, consider the case where the mask table 820 is a storage circuit that stores at address zero the mask to be applied when the true exponent is zero (i.e., the exponent is 127 for a single precision floating point number or 011111112 in single precision floating point format), and stores at address one the mask to be applied when the true exponent is negative one (i.e., 126 10 or 0111111102 in single-precision floating point format, etc. In this case, encoder circuit 810 can be a bit-by-bit inverter circuit, or, if desired, a subtractor that subtracts the exponent bit from the corresponding bias bit. Alternatively, encoder circuit 810 can be any circuit that receives p bits and generates another p bits in response. For example, encoder circuit 810 can include a barrel shifter, a storage circuit, or combinational logic, to name a few.

[0094] As an example, the mask that needs to be applied when the true exponent is zero may include (i+j-1) MSBs of zero and (ni-j+1) LSBs of one, and the mask that needs to be applied when the true exponent is one may include (i+j-2) MSBs of zero and (ni-j+2) LSBs of one, ..., and the mask that needs to be applied when the true exponent is (i+j-1) or greater may not include zero and all n bits may be one.

[0095] Note that in this example, the (ni-j+1) LSBs of the mask that needs to be applied are all ones, independent of the value of the true exponent. Therefore, in some embodiments, the mask table 820 may store only the (i+j-1) MSBs of the mask that needs to be applied, and concatenate the (i+j-1) bits retrieved from the mask table 820 with the (ni-j+1) bits that are all ones.

[0096] Apply mask circuit 830 may apply the mask retrieved from mask table 820 to the n-bit mantissa, thereby generating (1+b)*2 指数 For example, a bitwise logical AND circuit may implement the application mask circuit 830 .

[0097] The floating point subtractor 840 can subtract 1.0*2 from this number 指数 to generate b in floating point format (ie, FP b).

[0098] Figure 101 is a diagram of an illustrative floating-point tangent operator circuit for selecting between three approximations according to some embodiments. As shown, the floating-point tangent operator circuit includes a control circuit 1002, which may include a threshold indicator circuit 1115, a comparator 1030, and an upper threshold check circuit 1040; an extraction circuit 1005, which may include a right shift circuit 1010, a fixed-point subtractor 1020, a mask table 1050, an apply mask circuit 1060, and a floating-point subtractor 1070; a fixed-point subtractor 1075; storage circuits 1082, 1084, and 1086; a floating-point adder 1071; a floating-point subtractor 1074; floating-point multipliers 1072 and 1076; a mantissa inversion circuit 1088; and a multiplexer 1090.

[0099] Extraction circuit 1005 can receive a floating point number x and generate fixed point numbers c and a and floating point number FPb. If desired, extraction circuit 1005 can extract fixed point numbers c and a from input value x using right shift circuit 1010 and fixed point subtractor 1020 (e.g., Figure 5 In some embodiments, the extraction circuit 1005 may be Figure 6 The extraction circuit 610.

[0100] If desired, the floating point tangent operator may use mask table 1050, apply mask circuit 1060, and floating point subtractor 1070 to extract b (e.g., Figure 5 In some embodiments, the mask table 1050, the application mask circuit 1060 and the floating point subtractor 1070 may be respectively Figure 8 The mask table 820, the application mask circuit 830 and the floating point subtractor 840 in.

[0101] The floating-point tangent operator circuit can retrieve tan(c) and tan(a) in floating-point format based on c and a from storage circuits 1082 and 1084, respectively. Floating-point adder 1071 can add tan(a) and FP b, and floating-point adder 1073 can add the sum from floating-point adder 1071 to tan(c) to generate the numerator of equation (6).

[0102] The floating-point multiplier 1072 may multiply tan(c) by the sum from the floating-point adder 1071, and the floating-point subtractor 1074 may subtract the previous result from one to generate the denominator of equation (6).

[0103] The output of floating point subtractor 1074 may be inverted using fixed point subtractor 1075 and mantissa inversion circuit 1088. For example, fixed point subtractor 1075 may generate the exponent and mantissa inversion circuit 1088 may generate the mantissa of the inverted denominator of equation (6).

[0104] For example, the mantissa reversal circuit 1088 can calculate the reciprocal of the mantissa of the floating-point number from the floating-point subtractor 1074. If desired, the mantissa reversal circuit 1088 can receive only a portion of the mantissa (i.e., FRAC) and account for the implicit leading bit. In other words, the mantissa reversal circuit 1088 can calculate the function 1 / 1.FRAC. Since the denominator is in the interval [1, 2] (i.e., the interval includes all values greater than or equal to 1.0 and less than 2.0), the output of the mantissa reversal circuit 1088 can be in the interval (0.5, 1] (i.e., the interval includes all values greater than 0.5 and less than or equal to 1.0).

[0105] The reciprocal of the denominator in the floating point format may require a normalized mantissa and an appropriate exponent. For example, if the output of the mantissa inversion circuit 1088 is less than 1.0 (i.e., if the MSB of the mantissa of the reciprocal of the denominator is 0), the normalization of the output of the mantissa inversion circuit 1088 may be shifted left one bit and the exponent may be reduced by one.

[0106] The exponent of the reciprocal of the denominator in a floating point format may require the sign of the real exponent to be reversed to the opposite of the bias exponent. Consider the case where the real exponent, bias exponent, reversed bias exponent, and bias are represented as EXPREAL, EXP, INVEXP, and BIAS, respectively. Further consider that before the inversion, the bias exponent is EXP=EXPREAL+BIAS and therefore EXPREAL=EXP-BIAS. In this case, the reversed bias exponent (i.e., the exponent of the reciprocal of the denominator) is INVEXP=-EXPREAL+BIAS=2*BIAS-EXP. In other words, the reversed bias exponent is equal to the difference between twice the bias (i.e., 2*BIAS) and the exponent of the denominator (i.e., EXP).

[0107] In the IEEE 754 standard, the bias for all floating-point precisions (i.e., half-precision, single-precision, double-precision, and quad-precision) is zero at the MSB position, followed by ones at all other bit positions (e.g., 011111112 in the single-precision floating-point format according to the IEEE 754 standard). Therefore, twice the bias (i.e., 2*BIAS) is zero at the LSB position and ones at all other bit positions (e.g., 111111102 in the single-precision floating-point format according to the IEEE 754 standard).

[0108] As described above, normalization of the output of the mantissa inversion circuit 1088 may involve reducing the inverted bias exponent by one if the MSB of the mantissa of the reciprocal of the denominator is zero. This may be accomplished in the same operation as determining the exponent of the reciprocal of the denominator in floating point format.

[0109] For example, consider the case where the MSB of the mantissa of the reciprocal of the denominator is one (i.e., M = 1). In this case, the mantissa has already been normalized, no left shift is required, and the exponent of the reciprocal of the denominator can be determined by subtracting EXP from 2*BIAS (i.e., 111111102 in single-precision floating point format).

[0110] As another example, consider the case where the MSB of the mantissa of the reciprocal of the denominator is zero (i.e., M = 0). In this case, the mantissa needs to be normalized, needs to be shifted left by one bit, and the exponent of the reciprocal of the denominator can be determined by subtracting EXP from 2*BIAS-1 (i.e., 111111012 in single-precision floating point format).

[0111] Therefore, for any precision in the IEEE 754 standard, if desired, the two LSBs of 2*BIAS (i.e., 102) or the two LSBs of 2*BIAS-1 (i.e., 012) can be replaced by M!M (i.e., the concatenation of the MSB and the inverse of the MSB of the mantissa of the reciprocal of the denominator) to take care of the normalization operation.

[0112] In some embodiments, the mantissa reversal circuit 1088 may implement piecewise polynomial approximation, Newton-Raphson iteration, or any other technique related to computing the reciprocal of a mantissa. Additionally, the mantissa reversal circuit 1088 may include a 1-position normalization circuit that may be implemented using a multiplexer.

[0113] According to equation (6), the floating point multiplier 1076 may multiply the inverted denominator by the numerator to determine the tangent of the input value.

[0114] The control circuit 1002 may determine whether x is lower than a first predetermined threshold (eg, less than or equal to 2 -m / 2 or any other predetermined threshold that may or may not be based on the number of mantissa bits.) For example, threshold indicator circuit 1115 and comparator 1030 may determine whether the input value is less than a first predetermined threshold.

[0115] Similarly, the control circuit 1002 may determine whether x is greater than a second predetermined threshold (eg, greater than or equal to π / 2-q*ULP). For example, the upper threshold check circuit 1040 may determine whether the input value is greater than the second predetermined threshold.

[0116] Multiplexer 1090 may select to output tan(x) based on a control signal from control circuit 1002. For example, if control circuit 1002 determines that the input value is less than a first predetermined threshold, control circuit 1002 may instruct multiplexer 1090 to select the input value as the output (i.e., tan(x)=x), if control circuit 1002 determines that the input value is above a second predetermined threshold, control circuit 1002 may instruct multiplexer 1090 to select the output of storage circuit 1086 as the output tan(x), storage circuit 1086 may store tangent values for a predetermined range of input values (e.g., for input values within an interval bounded by π / 2-q*ULP and π / 2), and if control circuit 1002 determines that the input value is greater than or equal to the first predetermined threshold and less than or equal to the second predetermined threshold, control circuit 1002 may instruct multiplexer 1090 to select the output of floating-point multiplier 1076.

[0117] Figure 11 is a flow chart of illustrative operations for computing trigonometric functions of floating-point numbers in an integrated circuit, according to some embodiments.

[0118] At 1110, the integrated circuit may receive a first floating point number at an input port of an approximation circuit. For example, Figure 1 The programmable integrated circuit 100 may include Figure 4 Floating-point tangent operator circuit 400 with an approximation circuit 410 that receives a floating-point number x as a first floating-point number at an input port.

[0119] At 1120, the integrated circuit may generate first and second fixed-point numbers and a second floating-point number based on the first floating-point number using an extraction circuit in the approximation circuit. Figure 6 The extraction circuit 610 of the approximation circuit 410 can generate fixed-point numbers a and c and a floating-point number FP b.

[0120] At 1130, the integrated circuit may retrieve third and fourth floating point numbers of predetermined floating point numbers from first and second storage circuits storing predetermined floating point numbers of output values of the trigonometric function in the approximation circuit based on the first and second fixed point numbers, respectively. Figure 6 The storage circuits 620 and 630 of the approximation circuit 410 in can store predetermined floating-point numbers of output values of the trigonometric functions, and the fixed-point numbers a and c can access the storage circuits 620 and 630 to retrieve floating-point numbers FP TAN(a) and FP TAN(b), respectively.

[0121] At 1140, the integrated circuit may use the arithmetic circuit in the approximation circuit to perform floating-point arithmetic operations on the second, third, and fourth floating-point numbers to generate a fifth floating-point number as an approximation of a trigonometric function of the first floating-point number. For example, Figure 6Arithmetic circuit 640 may perform floating point arithmetic operations on FP b, FP TAN(a), and FPTAN(c) to generate a floating point number at the output of arithmetic circuit 640 that is an approximation of a trigonometric function of the floating point number x.

[0122] Although operations 1110, 1120, 1130, and 1140 are described in a particular order, it should be understood that other operations may be performed between the described operations, that the described operations may be adjusted so that they occur at slightly different times, or that the operations may be distributed in a system that allows processing operations to occur at various intervals associated with the processing. For example, operation 1120 may be performed before, after, or simultaneously with operation 1130.

[0123] According to some embodiments, a machine-readable medium may encode instructions for performing a method on an integrated circuit (e.g., instructions for configuring an arithmetic circuit to generate the tangent of a floating-point number). A suitable computer or similar device may execute these instructions, thereby implementing the method in the integrated circuit. For example, a personal computer may be equipped with an interface that can be connected to the integrated circuit, and a suitable software tool and / or a user with the help of the personal computer may program the method into the integrated circuit through the interface.

[0124] In some embodiments, the instructions for performing the method may be generated from other instructions encoded on the same or additional machine-readable medium. In other words, a first set of instructions (e.g., a C language compiler or an electronic design automation (EDA) tool) executed on a computer or similar device may generate a second set of instructions (e.g., assembler code or a series of bits for programming a configurable circuit), whereby the second set of instructions is included in an integrated circuit (e.g., a microprocessor or a processor such as a microprocessor). Figure 1 A method performed on a programmable integrated circuit device of a programmable integrated circuit 100).

[0125] Machine-readable media may include any type of device or technology that allows for storage of instructions, including semiconductor memory that may be volatile (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or non-volatile (e.g., programmable read-only memory (PROM), flash memory, etc.), magnetic storage devices, optical storage devices, or a combination thereof.

[0126] Figure 12A cross-section of a magnetic data storage medium 1200 is shown that may be encoded with a machine-executable program that can be executed by a system such as the aforementioned personal computer or other computer or similar device. The medium 1200 may be a floppy disk, a hard disk, or a magnetic tape having a substrate 1210 that may be conventional and a coating 1220 on one or both sides that may be conventional and that contains magnetic domains whose polarity or orientation can be magnetically altered. Except in the case of magnetic tape, the medium 1200 may also have an opening for receiving the spindle of a disk drive or other data storage device.

[0127] According to some embodiments, the magnetic domains of the coating 1220 of the medium 1200 may be polarized or oriented so as to encode a machine executable program in a manner that may be conventional for execution by a programming system such as a personal computer or other computer or similar system having a socket or peripheral accessory into which the integrated circuit to be configured may be inserted for configuring the appropriate portion of the integrated circuit, including its dedicated processing blocks (if any).

[0128] Figure 13 A cross-section of an optically readable data storage medium 1300 that may be encoded with the aforementioned machine-executable program is shown, and the machine-executable program is to be executed by a system such as the aforementioned personal computer or other computer or similar device. The medium 1300 may be a Blu-ray disc (BD), a conventional compact disc (CD) read-only memory (ROM), or a digital versatile disc (DVD, sometimes also called a digital video disc) read-only memory (ROM), or any rewritable medium such as a CD R, CD RW, DVD R, DVD RW, DVD+R, DVD+RW, or DVD-RAM, or an optically readable and magneto-optically rewritable magneto-optical disc. The medium 1300 may have a suitable substrate 1310 and a suitable coating 1320, typically on one or both sides of the substrate 1310.

[0129] As is well known, in the case of CD-based or DVD-based media, the coating 1320 is reflective and printed with a plurality of pits 1330 arranged in one or more layers to encode a machine-executable program. The arrangement of the pits is read by reflecting laser light off the surface of the coating 1320. A protective coating 1340 may be provided on top of the coating 1320.

[0130] As is well known, in the case of a magneto-optical disk, the coating 1320 does not have pits 1330 but instead has multiple magnetic domains. When heated above a certain temperature, for example, by laser light, the polarity or orientation of the magnetic domains can be magnetically altered. The orientation of the magnetic domains can be read by measuring the polarization of the laser light reflected from the coating 1320. As described above, the arrangement of the magnetic domains can encode a program.

[0131] The methods and apparatus described herein can be incorporated into any suitable circuit or circuit system. For example, the methods and apparatus can be incorporated into many types of devices, such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPGA), electrically programmable logic device (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), field programmable gate array (FPGA), coarse-grained reconfigurable architecture (CGPA), digital signal processing (DSP) circuits, application specific standard products (ASSP), and application specific integrated circuits (ASICs), to name a few.

[0132] The integrated circuits described herein may be part of a data processing system that includes one or more of the following components: a processor; memory; I / O circuitry; and peripherals. The data processing system may be used in a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application that requires the advantages of a circuit that efficiently generates the tangent of a floating-point number.

[0133] An integrated circuit device can be configured to perform a variety of different logic functions. For example, an integrated circuit device can be configured as a processor or controller that works in conjunction with a system processor. An integrated circuit can also be used as an arbitrator to arbitrate access to shared resources in a data processing system. In yet another example, an integrated circuit can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the integrated circuit can be one of a family of devices owned by the assignee.

[0134] Although the method operations are described in a particular order, it should be understood that other operations may be performed between the described operations, that the described operations may be adjusted so that they occur at slightly different times, or that the described operations may be distributed in a system that allows processing operations to occur at intervals associated with the processing.

[0135] The above description is merely illustrative of the principles of the embodiments, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the embodiments disclosed herein. The above embodiments may be implemented individually or in any combination.

[0136] The following examples relate to other embodiments.

[0137] Example 1 is a circuit for calculating a trigonometric function of a first floating-point number, comprising: an approximation circuit that receives the first floating-point number at an input port, and the approximation circuit includes: an extraction circuit coupled to the input port, generating first and second fixed-point numbers and a second floating-point number based on the first floating-point number; first and second storage circuits coupled to the extraction circuit, which store predetermined floating-point numbers of output values of the trigonometric function and output third and fourth floating-point numbers of the predetermined floating-point number based on the first and second fixed-point numbers, respectively; and an arithmetic circuit coupled to the extraction circuit and the first and second storage circuits, the arithmetic circuit performing floating-point arithmetic operations on the second, third, and fourth floating-point numbers to generate a fifth floating-point number as an approximation of the trigonometric function of the first floating-point number.

[0138] Example 2 is the circuit of Example 1, further including: a third storage circuit that stores additional predetermined floating-point numbers of additional output values of the trigonometric function and outputs a sixth floating-point number of the additional predetermined floating-point numbers based on the first floating-point number; and a selection circuit coupled to the third storage circuit and the approximation circuit that selects the trigonometric function of the first floating-point number among the first, fifth, and sixth floating-point numbers based on a control signal.

[0139] Example 3 is the circuit of Example 2, further comprising: a control circuit that receives the first floating-point number and generates a control signal such that the control signal instructs the selection circuit to select the first floating-point number when the first floating-point number is in a first interval, select the fifth floating-point number when the first floating-point number is in a second interval, and select the sixth floating-point number when the first floating-point number is in a third interval, wherein the first, second, and third intervals are disjoint.

[0140] Example 4 is the circuit of Example 2, wherein the third storage circuit stores additional predetermined floating-point numbers for additional output values of the trigonometric function for a predetermined input interval, and wherein, when the first floating-point number is within the predetermined input interval, a sixth floating-point number is retrieved from the third storage circuit based on a read address of the first floating-point number during a read access operation.

[0141] Example 5 is the circuit of Example 2, further comprising: a mapping circuit that receives a seventh floating point number and maps the seventh floating point number to an interval between 0 and π / 2 to generate a first floating point number.

[0142] Example 6 is the circuit of Example 5, further comprising: a restoration circuit coupled to the mapping circuit and the selection circuit, the restoration circuit restoring the trigonometric function of the first floating point number from the selection circuit to an interval between -π / 2 and π / 2 based on the seventh floating point number.

[0143] Example 7 is the circuit of any of Examples 1 to 6, wherein the first floating-point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: right-shift circuitry that shifts a first number of bits of the mantissa to the right by a second number of bits to generate the first and second fixed-point numbers, wherein the second number of bits is based on the exponent.

[0144] Example 8 is the circuit of any of Examples 1 to 6, wherein the first floating-point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: a third storage circuit that provides a mask based on a first number of bits of the exponent; a mask application circuit that applies the mask from the third storage circuit to the mantissa to generate an intermediate floating-point number; and a floating-point subtractor that subtracts an additional predetermined floating-point number from the intermediate floating-point number to generate a second floating-point number.

[0145] Example 9 is the circuit of any one of Examples 1 to 8, wherein the arithmetic circuit further comprises: a first floating-point arithmetic circuit that generates a numerator of a fifth floating-point number based on floating-point addition of the second, third, and fourth floating-point numbers; and a second floating-point arithmetic circuit that generates a denominator of the fifth floating-point number based on floating-point addition of the second and third floating-point numbers, floating-point multiplication with the fourth floating-point number, and floating-point subtraction from one.

[0146] Example 10 is the circuit of Example 9, wherein the arithmetic circuit further comprises: a mantissa inversion circuit coupled to the second floating-point arithmetic circuit, the mantissa inversion circuit generating a reciprocal of the denominator of the fifth floating-point number; and a floating-point multiplier circuit that multiplies the numerator of the fifth floating-point number from the floating-point arithmetic circuit by the reciprocal of the denominator of the fifth floating-point number from the mantissa inversion circuit to generate the fifth floating-point number.

[0147] Example 11 is the circuit of Example 10, wherein the mantissa reversal circuit performs a piecewise polynomial approximation.

[0148] Example 12 is the circuit of Example 10, wherein the mantissa reversal circuit performs a Newton-Raphson iteration.

[0149] Example 13 is the circuit of any one of Examples 10 to 12, wherein the mantissa reversal circuit further comprises a left shift circuit that shifts the mantissa of the reciprocal of the denominator one bit to the left if the most significant bit before the shift operation is zero.

[0150] Example 14 is the circuit of any of Examples 10 to 13, wherein the mantissa inversion circuit further comprises a barrel shifter that shifts the bias of the floating-point exponent one bit to the left to generate twice the bias.

[0151] Example 15 is the circuit of Example 14, wherein the barrel shifter replaces the second least significant bit and the least significant bit of twice the deviation with the most significant bit of the reciprocal of the denominator and the inverse of the reciprocal of the denominator, respectively, to generate the normalized exponent.

[0152] Example 16 is the circuit of Example 15, further comprising: a fixed-point subtractor that subtracts the exponent of the denominator from the normalized exponent to generate an exponent of the reciprocal of the denominator.

[0153] Example 17 is the circuit of any of Examples 9 to 16, wherein the second floating-point arithmetic circuit further comprises a floating-point adder circuit that adds the second and third floating-point numbers to generate the first sum.

[0154] Example 18 is the circuit of Example 17, wherein the second floating-point arithmetic circuit further comprises: an additional floating-point multiplier circuit that multiplies the first sum and a fourth floating-point number to generate a product.

[0155] Example 19 is the circuit of Example 18, wherein the second floating-point arithmetic circuit further comprises a floating-point subtractor circuit that subtracts the product from one to generate a denominator of the fifth floating-point number.

[0156] Example 20 is a method for calculating a trigonometric function of a first floating-point number, comprising: receiving the first floating-point number at an input port of an approximation circuit; generating first and second fixed-point numbers and a second floating-point number based on the first floating-point number using an extraction circuit in the approximation circuit; retrieving third and fourth floating-point numbers of predetermined floating-point numbers from first and second storage circuits of predetermined floating-point numbers storing output values of trigonometric functions in the approximation circuit, respectively, based on the first and second fixed-point numbers; and performing floating-point arithmetic operations on the second, third, and fourth floating-point numbers using an arithmetic circuit in the approximation circuit to generate a fifth floating-point number as an approximation of the trigonometric function of the first floating-point number.

[0157] Example 21 is the method of Example 20, further comprising: retrieving a sixth floating-point number of additional predetermined floating-point numbers from a third storage circuit storing additional predetermined floating-point numbers of additional output values of trigonometric functions based on the first floating-point number; generating a control signal using a control circuit that receives the first floating-point number so that the control signal has a first value when the first floating-point number is in a first interval, a second value when the first floating-point number is in a second interval, and a third value when the first floating-point number is in a third interval, wherein the first, second, and third intervals are disjoint; and instructing a selection circuit coupled to the third storage circuit and the approximation circuit to select the trigonometric function of the first floating-point number from the first, fifth, and sixth floating-point numbers using the control signal.

[0158] Example 22 is the method of Example 21, wherein retrieving the sixth floating point number further comprises: generating a read address based on the first floating point number; and performing a read access operation of the third storage circuit using the read address when the first floating point number is within a predetermined input interval.

[0159] Example 23 is the method of Example 20, wherein the first floating-point number has a mantissa and an exponent, and wherein generating the first and second fixed-point numbers and the second floating-point number using the extraction circuit in the approximation circuit further comprises: shifting a first number of bits of the mantissa to the right by a second number of bits to generate the first and second fixed-point numbers using the right shift circuit, wherein the second number of bits is based on the exponent; retrieving a mask from a third storage circuit using a third number of bits of the exponent; applying the mask from the third storage circuit to the mantissa to generate a sixth floating-point number; and subtracting an additional predetermined floating-point number from the sixth floating-point number to generate the second floating-point number.

[0160] Example 24 is the method of Example 23, further comprising: generating a fifth floating-point number by performing a floating-point arithmetic operation on the second, third, and fourth floating-point numbers using an arithmetic circuit in the approximation circuit.

[0161] Example 25 is the method of Example 24, wherein performing floating-point arithmetic operations on the second, third, and fourth floating-point numbers further comprises: generating a numerator of a fifth floating-point number based on floating-point addition of the second, third, and fourth floating-point numbers; generating a denominator of a fifth floating-point number based on the floating-point addition of the second and third floating-point numbers, a floating-point multiplication with the fourth floating-point number, and a floating-point subtraction from one; generating a reciprocal of the denominator of the fifth floating-point number; and multiplying the numerator of the fifth floating-point number by the reciprocal of the denominator of the fifth floating-point number to generate the fifth floating-point number.

[0162] Example 26 is a non-transitory machine-readable storage medium encoded with instructions for configuring a circuit to calculate a trigonometric function of a first floating-point number, wherein the circuit includes a first storage circuit, an approximation circuit, and a selection circuit coupled to the storage circuit and the approximation circuit, and wherein the approximation circuit includes an extraction circuit, second and third storage circuits, and an arithmetic circuit, the instructions including: instructions for configuring the extraction circuit to generate first and second fixed-point numbers and a second floating-point number based on the first floating-point number; instructions for configuring the second and third storage circuits storing predetermined floating-point numbers of output values of the trigonometric function to output third and fourth floating-point numbers of the predetermined floating-point number based on the first and second fixed-point numbers, respectively; and instructions for configuring the arithmetic circuit to perform floating-point arithmetic operations on the second, third, and fourth floating-point numbers to generate a fifth floating-point number as an approximation of the trigonometric function of the first floating-point number.

[0163] Example 27 is the non-transitory machine-readable storage medium of Example 26, further comprising: instructions for configuring a first storage circuit storing additional predetermined floating-point numbers of additional output values of a trigonometric function to output a sixth floating-point number that is an additional predetermined floating-point number based on the first floating-point number; and instructions for configuring a selection circuit to select the trigonometric function of the first floating-point number among the first, fifth, and sixth floating-point numbers based on a control signal.

[0164] Example 28 is the non-transitory machine-readable storage medium of Example 26, further comprising: instructions for generating the instructions of Example 16.

[0165] Example 29 is the non-transitory machine-readable storage medium of Example 26, wherein the arithmetic circuit includes first and second floating-point arithmetic circuits, the storage medium further comprising: instructions for configuring the first floating-point arithmetic circuit to generate a numerator of a fifth floating-point number based on a floating-point addition of the second, third, and fourth floating-point numbers; and instructions for configuring the second floating-point arithmetic circuit to generate a denominator of a fifth floating-point number based on a floating-point addition of the second and third floating-point numbers, a floating-point multiplication with the fourth floating-point number, and a floating-point subtraction from one.

[0166] Example 30 is the non-transitory machine-readable storage medium of Example 29, wherein the arithmetic circuit further includes a mantissa inversion circuit and a floating-point multiplier circuit, and the storage medium further includes: instructions for configuring the mantissa inversion circuit to generate a reciprocal of the denominator of a fifth floating-point number; and instructions for configuring the floating-point multiplier circuit to multiply the numerator of the fifth floating-point number from the first floating-point arithmetic circuit by the reciprocal of the denominator of the mantissa-inverted fifth floating-point number to generate a fifth floating-point number.

[0167] Example 31 is an integrated circuit for calculating a trigonometric function of a first floating-point number, comprising: a storage circuit that stores a predetermined floating-point number of an output value of a trigonometric function and outputs a second floating-point number of a predetermined floating-point number based on the first floating-point number; an approximation circuit that approximates the trigonometric function of the first floating-point number to generate a third floating-point number; and a selection circuit coupled to the storage circuit and the approximation circuit that selects the trigonometric function of the first floating-point number from among the first, second, and third floating-point numbers based on a control signal.

[0168] Example 32 is the integrated circuit of Example 31, further comprising: a control circuit that receives the first floating-point number and generates a control signal such that the control signal instructs the selection circuit to select the first floating-point number when the first floating-point number is in a first interval, to select the second floating-point number when the first floating-point number is in a second interval, and to select the third floating-point number when the first floating-point number is in a third interval, wherein the first, second, and third intervals are disjoint.

[0169] Example 33 is the integrated circuit of Example 31, wherein the storage circuit stores predetermined floating-point numbers of output values of the trigonometric function for a predetermined input interval, and wherein when the first floating-point number is within the predetermined input interval, a second floating-point number is retrieved from the storage circuit during a read access operation based on a read address of the first floating-point number.

[0170] Example 34 is the integrated circuit of any of Examples 31 to 33, wherein the approximation circuit further comprises: an extraction circuit that receives the first floating point number and generates the first and second fixed point numbers and the fourth floating point number based on the first floating point number.

[0171] Example 35 is the integrated circuit of Example 34, wherein the first floating-point number has a mantissa and an exponent, and wherein the extraction circuitry further comprises: right-shift circuitry that shifts a first number of bits of the mantissa to the right by a second number of bits to generate the first and second fixed-point numbers, wherein the second number of bits is based on the exponent.

[0172] Example 36 is the integrated circuit of Example 34, wherein the first floating-point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: additional storage circuitry that provides a mask based on a first number of bits of the exponent; a mask application circuit that applies the mask from the additional storage circuitry to a second number of bits of the mantissa to generate an intermediate floating-point number; and a floating-point subtractor that subtracts an additional predetermined floating-point number from the intermediate floating-point number to generate a fourth floating-point number.

[0173] Example 37 is the integrated circuit of Example 34, wherein the approximation circuit further comprises: a first additional storage circuit that stores a first additional predetermined floating-point number of the output value of the trigonometric function and outputs a fifth floating-point number that is the first additional predetermined floating-point number based on the first fixed-point number; and a second additional storage circuit that stores a second additional predetermined floating-point number of the output value of the trigonometric function and outputs a sixth floating-point number that is the second additional predetermined floating-point number based on the second fixed-point number.

[0174] Example 38 is the integrated circuit of Example 37, wherein the approximation circuit further comprises: an arithmetic circuit that receives the fourth, fifth, and sixth floating point numbers and performs a floating point arithmetic operation on the fourth, fifth, and sixth floating point numbers to generate a third floating point number.

[0175] Example 39 is the integrated circuit of Example 38, wherein the operation circuit further includes: a first floating-point arithmetic circuit that generates a numerator of a third floating-point number based on floating-point addition of the fourth, fifth, and sixth floating-point numbers; a second floating-point arithmetic circuit that generates a denominator of the third floating-point number based on floating-point addition of the fourth and fifth floating-point numbers, floating-point multiplication with the sixth floating-point number, and floating-point subtraction from one; a divider circuit that generates a reciprocal of the denominator of the third floating-point number; and a floating-point multiplier circuit that multiplies the numerator of the third floating-point number from the first floating-point arithmetic circuit by the reciprocal of the denominator of the third floating-point number from the divider to generate the third floating-point number.

[0176] Example 40 is the integrated circuit of Example 31, wherein the storage circuit is selected from the group consisting of a first-in, first-out circuit, a last-in, first-out circuit, a serial-in, parallel-out shift register circuit, a parallel-in, serial-out shift register circuit, a random access memory circuit, a read-only memory circuit, a content addressable memory circuit, and a register file.

[0177] Example 41 is the integrated circuit of any of Examples 31 to 40, further comprising: a pin; and a serial receiver circuit that receives the serialized data signal from the pin and parallelizes at least a portion of the serialized data signal.

[0178] Example 42 is an integrated circuit of any one of Examples 31 to 40, further comprising: a pin; and a serial transmitter circuit that receives a parallel data signal from the selection circuit, serializes the parallel data signal to generate a serialized data signal, and transmits the serialized data signal to the pin.

[0179] Example 43 is the integrated circuit of any of Examples 31 to 40, further comprising: a programmable logic region coupled to the selection circuit.

[0180] Example 44 is the integrated circuit of Example 43, wherein the programmable logic region further comprises: a plurality of lookup table circuits.

[0181] Example 45 is the integrated circuit of any of Examples 31 to 40, further comprising: an interconnect resource coupled to the output port of the selection circuit.

[0182] Example 46 is the integrated circuit of Example 45, wherein the interconnect resources further comprise: horizontal interconnect resources; and vertical interconnect resources.

[0183] Example 47 is the integrated circuit of Example 45, wherein the interconnect resources further comprise: a plurality of conductive lines.

[0184] Example 48 is the integrated circuit of Example 47, further comprising a programmable connection between a first conductive line in the plurality of conductive lines and a second conductive line in the plurality of conductive lines.

[0185] Example 49 is the integrated circuit of any of Examples 31 to 40, wherein at least a portion of the approximation circuit is implemented in a dedicated processing block.

[0186] The embodiments described above are presented for purposes of illustration and not limitation.

Claims

1. A circuit for calculating a trigonometric function of a first floating-point number, comprising: an approximation circuit that receives the first floating-point number at an input port, and that includes: an extraction circuit coupled to the input port, the extraction circuit generating a first fixed-point number and a second fixed-point number and a second floating-point number based on the first floating-point number, a first storage circuit and a second storage circuit coupled to the extraction circuit, the first storage circuit and the second storage circuit storing predetermined floating-point numbers of output values of the trigonometric function and outputting third and fourth floating-point numbers of the predetermined floating-point numbers based on the first and second fixed-point numbers, respectively; and an arithmetic circuit coupled to the extraction circuit and the first and second storage circuits, the arithmetic circuit performing a floating-point arithmetic operation on the second, third, and fourth floating-point numbers to generate a fifth floating-point number as an approximation of the trigonometric function of the first floating-point number, the arithmetic circuit comprising: a first floating-point arithmetic circuit that generates a numerator of the fifth floating-point number based on a floating-point addition of the second floating-point number, the third floating-point number, and the fourth floating-point number; and a second floating-point arithmetic circuit that generates a denominator of the fifth floating-point number based on a floating-point addition of the second floating-point number and the third floating-point number, a floating-point multiplication with the fourth floating-point number, and a floating-point subtraction from one; a mantissa inversion circuit coupled to the second floating-point arithmetic circuit, the mantissa inversion circuit generating a reciprocal of the denominator of the fifth floating-point number; and A floating-point multiplier circuit multiplies the numerator of the fifth floating-point number from the first floating-point arithmetic circuit by the reciprocal of the denominator of the fifth floating-point number from the mantissa inversion circuit to generate the fifth floating-point number.

2. The circuit according to claim 1, further comprising: a third storage circuit configured to store an additional predetermined floating-point number of an additional output value of the trigonometric function and output a sixth floating-point number of the additional predetermined floating-point number based on the first floating-point number; as well as A selection circuit is coupled to the third storage circuit and the approximation circuit, the selection circuit selecting the trigonometric function of the first floating point number among the first floating point number, the fifth floating point number, and the sixth floating point number based on a control signal.

3. The circuit according to claim 2, further comprising: a control circuit that receives the first floating-point number and generates the control signal so that the control signal instructs the selection circuit to select the first floating-point number when the first floating-point number is within a first interval, select the fifth floating-point number when the first floating-point number is within a second interval, and select the sixth floating-point number when the first floating-point number is within a third interval, wherein the first interval, the second interval, and the third interval are disjoint.

4. The circuit according to claim 2, wherein The third storage circuit stores additional predetermined floating-point numbers for additional output values of the trigonometric function for a predetermined input interval, and wherein the sixth floating-point number is retrieved from the third storage circuit during a read access operation based on a read address of the first floating-point number when the first floating-point number is within the predetermined input interval.

5. The circuit according to any one of claims 1 to 4, wherein The first floating point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: Right shift circuitry shifts a first number of bits of the mantissa right a second number of bits to generate the first fixed point number and the second fixed point number, wherein the second number of bits is based on the exponent.

6. The circuit according to any one of claims 1 to 4, wherein: The first floating point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: a third storage circuit that provides a mask based on a first number of bits of the exponent; a mask application circuit that applies the mask from the third storage circuit to the mantissa to generate a sixth floating point number; and A floating-point subtractor subtracts an additional predetermined floating-point number from the sixth floating-point number to generate the second floating-point number.

7. The circuit according to claim 1, wherein The mantissa reversal circuit performs a piecewise polynomial approximation.

8. A method for calculating a trigonometric function of a first floating-point number in an integrated circuit, comprising: receiving the first floating-point number at an input port of the approximation circuit; generating a first fixed-point number and a second fixed-point number and a second floating-point number based on the first floating-point number using an extraction circuit in the approximation circuit; Retrieving a third floating-point number and a fourth floating-point number of the predetermined floating-point number from a first storage circuit and a second storage circuit storing predetermined floating-point numbers of output values of the trigonometric function in the approximation circuit based on the first fixed-point number and the second fixed-point number, respectively; as well as performing a floating-point arithmetic operation on the second floating-point number, the third floating-point number, and the fourth floating-point number using an arithmetic circuit in the approximation circuit to generate a fifth floating-point number as an approximation of the trigonometric function of the first floating-point number, comprising: generating a numerator of the fifth floating-point number based on floating-point addition of the second floating-point number, the third floating-point number, and the fourth floating-point number; generating a denominator of the fifth floating-point number based on floating-point addition of the second floating-point number and the third floating-point number, floating-point multiplication with the fourth floating-point number, and floating-point subtraction from one; generating a reciprocal of the denominator of the fifth floating-point number; and The numerator of the fifth floating-point number is multiplied by the reciprocal of the denominator of the fifth floating-point number to generate the fifth floating-point number.

9. The method according to claim 8, further comprising: retrieving a sixth floating point number of the additional predetermined floating point numbers from a third storage circuit storing additional predetermined floating point numbers of additional output values of the trigonometric function based on the first floating point number; generating a control signal using a control circuit that receives the first floating-point number so that the control signal has a first value when the first floating-point number is within a first interval, a second value when the first floating-point number is within a second interval, and a third value when the first floating-point number is within a third interval, wherein the first interval, the second interval, and the third interval are disjoint; as well as A selection circuit coupled to the third storage circuit and the approximation circuit is instructed using the control signal to select the trigonometric function of the first floating-point number among the first floating-point number, the fifth floating-point number, and the sixth floating-point number.

10. The method according to claim 9, wherein: Retrieving the sixth floating point number further includes: generating a read address based on the first floating-point number; and When the first floating-point number is located in a predetermined input interval, a read access operation of the third storage circuit is performed using the read address.

11. The method according to claim 8, wherein The first floating point number has a mantissa and an exponent, and wherein generating the first fixed point number and the second fixed point number and the second floating point number using the extraction circuit in the approximation circuit further comprises: shifting a first number of bits of the mantissa right a second number of bits using right shift circuitry to generate the first fixed-point number and the second fixed-point number, wherein the second number of bits is based on the exponent; retrieving a mask from a third storage circuit using a third number of bits of the exponent; applying the mask from the third storage circuit to the mantissa to generate a sixth floating point number; and An additional predetermined floating point number is subtracted from the sixth floating point number to generate the second floating point number.

12. A non-transitory machine-readable storage medium comprising code which, when executed, causes a machine to perform the method according to any one of claims 8 to 11.

13. An integrated circuit for calculating a trigonometric function of a first floating-point number, comprising: a storage circuit that stores a predetermined floating-point number of an output value of the trigonometric function and outputs a second floating-point number of the predetermined floating-point number based on the first floating-point number; an approximation circuit that approximates the trigonometric function of the first floating-point number to generate a third floating-point number; as well as a selection circuit coupled to the storage circuit and the approximation circuit, the selection circuit selecting the trigonometric function of the first floating point number among the first floating point number, the second floating point number, and the third floating point number based on a control signal, Wherein, the approximate circuit includes: an arithmetic circuit that receives a fourth floating-point number, a fifth floating-point number, and a sixth floating-point number and performs a floating-point arithmetic operation on the fourth floating-point number, the fifth floating-point number, and the sixth floating-point number to generate the third floating-point number; an extraction circuit that receives the first floating-point number and generates a first fixed-point number, a second fixed-point number, and a fourth floating-point number based on the first floating-point number; a first additional storage circuit that stores a first additional predetermined floating-point number of an output value of the trigonometric function and outputs a fifth floating-point number of the first additional predetermined floating-point number based on the first fixed-point number; and a second additional storage circuit that stores a second additional predetermined floating-point number of the output value of the trigonometric function and outputs a sixth floating-point number of the second additional predetermined floating-point number based on the second fixed-point number, and Wherein, the arithmetic circuit includes: a first floating-point arithmetic circuit that generates a numerator of the third floating-point number based on a floating-point addition of the fourth floating-point number, the fifth floating-point number, and the sixth floating-point number; a second floating-point arithmetic circuit that generates a denominator of the third floating-point number based on a floating-point addition of the fourth floating-point number and the fifth floating-point number, a floating-point multiplication with the sixth floating-point number, and a floating-point subtraction from one; a divider circuit that generates a reciprocal of the denominator of the third floating-point number; and A floating-point multiplier circuit multiplies the numerator of the third floating-point number from the first floating-point arithmetic circuit by a reciprocal of the denominator of the third floating-point number from the divider to generate the third floating-point number.

14. The integrated circuit of claim 13 , further comprising: a control circuit that receives the first floating-point number and generates the control signal so that the control signal instructs the selection circuit to select the first floating-point number when the first floating-point number is within a first interval, select the second floating-point number when the first floating-point number is within a second interval, and select the third floating-point number when the first floating-point number is within a third interval, wherein the first interval, the second interval, and the third interval are disjoint.

15. The integrated circuit of claim 13, wherein: The storage circuit stores the predetermined floating-point number of the output value of the trigonometric function for a predetermined input interval, and wherein the second floating-point number is retrieved from the storage circuit during a read access operation based on a read address of the first floating-point number when the first floating-point number is within the predetermined input interval.

16. The integrated circuit of claim 13, wherein: The first floating point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: A right shift circuit shifts a first number of bits of the mantissa right a second number of bits to generate the first fixed-point number and the second fixed-point number, wherein the second number of bits is based on the exponent.

17. The integrated circuit of claim 13, wherein: The first floating point number has a mantissa and an exponent, and wherein the extraction circuit further comprises: additional storage circuitry for providing a mask based on a first number of bits of the exponent; a mask application circuit that applies the mask from the additional storage circuit to a second number of bits of the mantissa to generate an intermediate floating point number; and A floating-point subtractor subtracts an additional predetermined floating-point number from the intermediate floating-point number to generate the fourth floating-point number.

Images