Semiconductor devices

Abstract

This invention provides a semiconductor device. The resistance variation rate of polysilicon resistors is large after the molding and packaging process. To achieve high-precision adjustment, it is desirable to realize a resistor that is almost unaffected by the stress generated on the substrate due to the molding and packaging process. The resistive element is formed on multiple wiring layers, having a repeating pattern of a first conductive layer (51), a second conductive layer (52), and an interlayer conductive layer (53). The first conductive layer (51) is formed on a first wiring layer, the second conductive layer (52) is formed on a second wiring layer, and the interlayer conductive layer (53) connects the first conductive layer (51) and the second conductive layer (52).

Description

Technical Field

[0001] This invention relates to a semiconductor device having a trimming circuit using resistive elements. Background Technology

[0002] When an oscillation circuit is provided in a semiconductor device, a tuning circuit is generally provided to adjust the frequency characteristics of the oscillation circuit. The tuning circuit has a resistor, and by adjusting the resistance value of this resistor, the oscillation frequency of the oscillation circuit can be set to a desired value for each semiconductor device (chip). As a resistive element used in the tuning circuit, polysilicon resistors used in the formation of circuit elements such as transistors are known. It is known that polysilicon resistors can be formed without complicating the manufacturing process of the semiconductor device, and they are excellent in that they have high resistivity, small area, and can achieve high resistance. However, the resistance value changes after the molding and packaging process. This is because the resistive element (polysilicon resistor) on the silicon chip is subjected to stress from the molding resin, and the resistance value changes due to shape changes, piezoelectric effects, etc. In Patent Document 1, the location of the polysilicon resistor is determined in order to minimize the stress on the polysilicon resistor from the molding resin.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-229509 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] According to Patent Document 1, the goal is to suppress the resistance variation rate of the polysilicon resistor from the wafer state (trimming completed state) to the end of the molding and packaging process to within approximately ±0.5%. However, in recent years, the required accuracy of trimming circuits has increased, and it is desirable to reduce the resistance variation rate as much as possible. In addition, in the technology disclosed in Patent Document 1, the locations where the polysilicon resistor can be placed are restricted, thus reducing the flexibility of layout.

[0008] Other topics and novel features will become clear from the description in this specification and the accompanying drawings.

[0009] Technical solutions for solving the problem

[0010] As a resistor element suitable for adjusting circuits, a resistor element is realized that is formed on multiple wiring layers and the direction perpendicular to the semiconductor substrate surface is set as the main resistance.

[0011] Invention Effects

[0012] A resistor that can achieve a small resistance change rate after the molding and packaging process is completed. Attached Figure Description

[0013] Figure 1 This is a block diagram of a semiconductor device.

[0014] Figure 2 This is the circuit diagram of an oscillating circuit.

[0015] Figure 3 This is a conceptual diagram of a resistive element.

[0016] Figure 4 This is an example of mounting a resistive element.

[0017] Figure 5A This is a circuit diagram of a resistive element.

[0018] Figure 5B This is a top view of the layout of the resistive elements.

[0019] Figure 6A This is a circuit diagram of a tuning circuit that uses resistive elements.

[0020] Figure 6B This is the layout (top view) of the adjustment circuit.

[0021] Figure 7 It is the relief process.

[0022] Figure 8 This is a graph showing the rate of change of the characteristics of a resistive element relative to package stress.

[0023] Figure 9 This is a diagram showing the distribution of packaging stress within the chip.

[0024] Figure 10 It is a linear solenoid drive circuit. Detailed Implementation

[0025] The implementation method will now be described with reference to the accompanying drawings. First, in Figure 1 The diagram shows a block diagram of the semiconductor device 1 according to this embodiment. Active components such as transistors and passive components such as resistors and capacitors are formed on the substrate of the semiconductor device 1. Various functional modules are formed using these components in the semiconductor device 1. Figure 1In the diagram, examples of functional modules include a CPU (Central Processing Unit) 2, RAM 3, peripheral IP 4, and non-volatile memory 5. Peripheral IP can be exemplified by components such as A / D converters. Addresses and data are exchanged between these functional modules via bus 10. A clock generation circuit 7 generates a clock from the oscillation signal of an on-chip oscillator 8 and distributes it to these functional modules. The on-chip oscillator 8 has a resistor 9. By adjusting the resistance value of resistor 9 to a predetermined value, the oscillation frequency of the on-chip oscillator 8 is set to the desired value for each semiconductor device 1. The required adjustment code is written to the non-volatile memory 5 or RAM 3, and based on the adjustment code read via register 6, the resistance value of resistor 9 is adjusted to the predetermined value.

[0026] exist Figure 2 The diagram shows a circuit diagram of an oscillator circuit as an example of an on-chip oscillator 8. The oscillator circuit includes a trimming circuit 20, a constant current generation circuit 21, capacitors 22 and 23, a capacitor drive circuit 24 and 25, comparators 26 and 27, and a latch circuit 28. The capacitor drive circuit 24 has a PMOS transistor 31 and an NMOS transistor 32 connected in series with their source and drain paths. The source of the NMOS transistor 32 is connected to the ground terminal, and its drain is connected to the drain of the PMOS transistor 31. The contact point between the drain of the PMOS transistor 31 and the drain of the NMOS transistor 32 is the output node of the capacitor drive circuit 24, and a capacitor 22 is connected thereto. The output current Ir0×m from the constant current generation circuit 21 is input to the source of the PMOS transistor 31. Furthermore, the current flowing through the source-drain path of the PMOS transistor 41 in the constant current generation circuit 21 is Ir0, and the transistor size of the PMOS transistor 42 (43) in the constant current generation circuit 21 is m times the transistor size of the PMOS transistor 41. Therefore, the output current Ir0×m is input to the source of PMOS transistor 31. The gate of PMOS transistor 31 is connected to the gate of NMOS transistor 32 and is input to the output signal Q of latch circuit 28. Capacitor 22 is connected between the output node of capacitor drive circuit 24 and the ground terminal, thereby generating a voltage at the output node of capacitor drive circuit 24 corresponding to the amount of charge stored in capacitor 22. The same applies to capacitor drive circuit 25, which has capacitor 23 connected to its output node; detailed description omitted, but the gate of PMOS transistor 33 is connected to the gate of NMOS transistor 34 and is input to the output signal QN of latch circuit 28.

[0027] The oscillation reference voltage V REF The input to the non-inverting input terminal (+) of comparator 26 converts the output node voltage V of capacitor drive circuit 24 into an inverting input. CP0 Input to the inverting input terminal (-). Comparator 26 operates based on the oscillation reference voltage V.REF With output node voltage V CP0 The magnitude of the signal determines the logic level of the set signal S, which is switched accordingly. Specifically, comparator 26 switches the logic level of the set signal S based on the magnitude of the voltage at the output node V. CP0 Greater than the oscillation reference voltage V REF In this case, the set signal S is set to high level, and the output node voltage V CP0 Less than the oscillation reference voltage V REF In this case, the set signal S is set to low. The comparator 27, which switches the logic level of the reset signal R, is similarly set (details omitted), and the oscillation reference voltage V... REF The input to the non-inverting input terminal (+) of comparator 27 converts the output node voltage V of capacitor drive circuit 25. CP1 Input to the inverting input terminal (-).

[0028] Furthermore, comparator 26(27) is preferably a hysteresis comparator in order to stably switch the logic level of the output set signal S (reset signal R). If the hysteresis comparator has a hysteresis amplitude set to dh, then at the output node voltage V CP0 (V CP1 > Oscillation reference voltage V REF In this case, the set signal S (reset signal R) is switched from low level to high level, and the output node voltage V... CP0 (V CP1 )+dh<oscillation reference voltage V REF In this case, the set signal S (reset signal R) will be switched from high level to low level.

[0029] Resistor 9 is connected in series with the source-drain path of PMOS transistor 41 in constant current generation circuit 21. The resistance value of resistor 9 is adjusted by adjustment circuit 20. The adjustment code stored in register 6 is input to adjustment circuit 20, and the resistance value of resistor 9 is adjusted according to the adjustment code, thereby adjusting the current Ir0 flowing through the source-drain path of PMOS transistor 41. This adjusts the frequency of the output clock.

[0030] exist Figure 3 The diagram shows a conceptual diagram of the resistive element used in the resistor 9 of this embodiment. The resistive element is formed on the wiring layer of the semiconductor device. The surface of the semiconductor substrate on which the semiconductor element is formed is designated as the XY plane, and the direction perpendicular to the XY plane is designated as the Z direction. The resistive element has a lower conductive layer 51 and an upper conductive layer 52 extending in the X or Y direction, respectively, and an interlayer conductive layer 53 connected at both ends to the lower conductive layer 51 and the upper conductive layer 52 and extending in the Z direction. The lower conductive layer 51, the interlayer conductive layer 53, and the upper conductive layer 52 are connected in series.

[0031] Here, the resistance value of the resistive element is set to R, and the resistive element is made into k+1 lower conductive layers 51, k upper conductive layers 52, and 2k interlayer conductive layers 53 connected in series. Furthermore, the resistance value of one lower conductive layer 51 is set to Rxy_lower, the resistance value of one upper conductive layer 52 is set to Rxy_upper, and the resistance value of one interlayer conductive layer 53 is set to Rz. At this time, the resistance value R of the resistive element is represented by (Equation 1).

[0032] R = (k+1)×Rxy_lower + 2k×Rz + k×Rxy_upper (Equation 1)

[0033] This is the formula for the case where the resistive element is connected to other elements at the upper conductive layer 52. Similarly, when it is connected to other elements at the lower conductive layer 51, it is represented by (Equation 2).

[0034] R = k × Rxy_lower + 2k × Rz + (k+1) × Rxy_upper (Equation 2)

[0035] Furthermore, if the Z-direction component of the resistive element is set as the main resistance, then the following relationship (Equation 3) holds:

[0036] Rz>Rxy_lower+Rxy_upper (Formula 3)

[0037] As described below, the resistor element of this embodiment, which is formed on the wiring layer and has its Z-direction component set as the main resistance, is almost unaffected by the stress generated on the semiconductor substrate due to the molding and packaging process. Therefore, there are no restrictions on the placement of the resistor element in this embodiment. Furthermore, the lower conductive layer 51, the interlayer conductive layer 53, and the upper conductive layer 52 can be connected in series to achieve the desired resistance value of the resistor element. There are no restrictions on the arrangement or number of each conductive layer.

[0038] exist Figure 4 The figure shows an example of mounting a resistor. The figure shows... Figure 3The images show a top view and a cross-sectional view of a resistive element mounted in a semiconductor device. In this mounting example, a wiring layer structure formed in the semiconductor device is used for the resistive element. The lower conductive layer 51 is formed by wiring layer M1, the upper conductive layer 52 is formed by wiring layer M4, and the interlayer conductive layer 53 is formed by vias V1 to V3 and wiring layers M2 and M3. The interlayer conductive layer 53 is formed by multiple conductive layers to obtain the maximum possible resistance value of the interlayer conductive layer 53 and is formed using the same process as a normal wiring layer. The interlayer conductive layer 53a is composed of vias 61 connected in series, bonding pads 62 and 63 formed in wiring layer M2, bonding pads 64 and 65 formed in wiring layer M3. By mounting the interlayer conductive layer 53 in this way, the resistive element can be formed without modifying the wiring process of the semiconductor device.

[0039] For example, wiring layer M1 can be formed from a W (main conductive layer) / TiN laminate, and wiring layers M2 to M4 can be formed from a TiN / AlCu (main conductive layer) / TiN / Ti laminate. Furthermore, vias V1 to V3 are configured such that a W layer 73 is buried after depositing a Ti layer 71 and a TiN layer 72, and the resistance value of the vias mainly depends on the contact resistance between the W layer and the TiN layer. Moreover, this example is not limited to wiring layers M1 to M4; it can be implemented using at least two wiring layers and a buried layer for vias connecting these two wiring layers. Furthermore, the buried layer for vias and the bonding pads formed in wiring layers M2 and M3 are not limited to the above; other resistive materials such as polysilicon can also be used. Furthermore, typically, vias V1 to V3 are formed by embedding metal into contact holes drilled in the interlayer insulating film, but any one of vias V1 to V3 can also be formed by pre-laminating resistive materials such as metal or polysilicon and filling the insulating layer in between.

[0040] Thus, in this embodiment, resistor 9 is formed using a wiring layer structure, resulting in relatively low resistance values ​​for each conductive layer constituting the resistive element. Therefore, it is necessary to achieve the desired resistance value by obtaining a large number of conductive layers connected in series as resistive elements. Figure 5A The resistor element 91 is shown in the circuit diagram. The resistor element 91 is formed by a repeating pattern of a lower conductive layer, an interlayer conductive layer and an upper conductive layer. Therefore, one unit of this repeating pattern is analogously referred to as the unit resistance 81. Figure 5B It is Figure 5A The diagram shows the layout (top view). The unit resistors, connected in series, are arranged compactly as winding pathways. To achieve the highest possible resistance in a small area, it is desirable to arrange the interlayer conductive layers as densely as possible. Therefore, in Figure 5BIn the layout, in the area where the resistive element 91 is formed, vias forming interlayer conductive layers are arranged in a matrix pattern in the X direction (here, the length direction of the upper and lower conductive layers is defined as the X direction) and Y direction, and the interlayer conductive layers are connected by the lower and upper conductive layers. Furthermore, adjacent interlayer conductive layers are expected to be arranged in a manner that constitutes the minimum spacing between vias specified in the layout rules of a semiconductor device (chip). Further, in Figure 5B In the example, both the upper conductive layer and the lower conductive layer have the X direction set as the length direction (except for the upper conductive layer configured in the folded-back section). However, it is also possible to set the length direction of the upper conductive layer as the X direction and the length direction of the lower conductive layer as the Y direction and connect them in a zigzag pattern to form a winding path layout.

[0041] exist Figure 6A The diagram shows a circuit diagram of a trimming circuit 20 using the resistive elements 91 of this embodiment. The trimming circuit 20 has N resistive elements 91 connected in series and a bypass switch 92-i (i = 1 to N) connected in parallel with the resistive elements 91-i (i = 1 to N) for bypassing the resistive elements 91-i (i = 1 to N). Figure 5A As shown, the resistor element 91 is composed of unit resistors 81 connected in series. The ON / OFF state of the bypass switch 92-i of the adjustment circuit 20 is determined according to the adjustment code, thereby setting the resistance of the adjustment circuit 20 to the desired resistance value, and a potential corresponding to the resistance value appears at node NF. Furthermore, since there are many resistor elements 91 connected in series in this embodiment, defects caused by non-conduction may lead to a deterioration in yield. Therefore, by always setting the corresponding bypass switch 92-i to ON for resistor elements 91-i that produce manufacturing defects, yield deterioration can be prevented.

[0042] exist Figure 6B The middle shows Figure 6A The layout of the adjustment circuit 20 shown is a top view. The layout of the resistor elements 91-i (i = 1 to N) is similar to... Figure 5B The layout shown is the same. Figure 6B The wiring 93W, wiring 94W, wiring 95W, and wiring 96W are respectively equivalent to Figure 6ANodes 93, 94, 95, and 96 are shown in the diagram. The structure of the bypass switch will be explained using bypass switch 92-1 as an example. Since it is desirable to set the resistance to be low when the bypass switch is on, a comb-shaped gate electrode 102 is formed on the diffusion region 101 formed on the semiconductor substrate. The drain electrode 103 is connected by wiring 93W and a contact portion (not shown), and is connected to the high-concentration region (drain region, not shown) of the diffusion region 101. On the other hand, on the diffusion region 101, the source electrode 104 is positioned opposite the drain electrode 103 with the gate electrode 102 as the axis of symmetry, connected by wiring 94W and a contact portion (not shown), and is connected to the high-concentration region (source region, not shown) of the diffusion region 101.

[0043] exist Figure 7 The relief process of the trimming circuit 20 is shown. As described above, in the case of a defective resistor 91, the corresponding bypass switch 92 is always set to ON to remove it from the trimming resistor beforehand, thereby suppressing a decrease in yield. Figure 7In the process, even if only one defective resistor element is found, the repair circuit 20 is rectified. Furthermore, control table 110 shows the ON(1) / OFF(0) control of bypass switches SW_i (i = 1 to N) for repetition number i, taking the case where the second resistor element 2 (91-2) of resistor element 91 is defective as an example. First, i = 0 (S111), at this time, all bypass switches SW are set to OFF (S112). If the resistance value of the repair circuit 20 at this time (i.e., the sum of the resistance values ​​of resistor elements 1 to N) is within the expected range (S113), then information that resistor elements 1 to N are all normal is written to the memory (S114). On the other hand, if the sum of the resistance values ​​of resistor elements 1 to N exceeds the expected range (S113), then a defective resistor element is included among resistor elements 1 to N. Therefore, the value of i is increased (S115), and the bypass switch SW is switched ON (1) / OFF (0) according to the control table 110 (S116). If the resistance value of the adjustment circuit 20 under the repetition number i is within the expected value range (S117), the resistor element i is considered to be a faulty resistor element, and the information that the bypass switch SW_i is always set to ON is written to the memory (S118). In addition, the expected value in step S117 is the expected value for the sum of N-1 resistors, and the value is different from the expected value in step S113. On the other hand, if the resistance value of the resistor still exceeds the expected value range (S117), the resistor element i is considered to be a normal resistor element, and the information that the bypass switch SW_i is set to OFF is written to the memory (S119). The value of i is increased until the repetition number i reaches N (S115), and the determination of the resistance value of the adjustment circuit 20 is repeated. If more than two resistors are faulty, and the faulty resistor cannot be identified even if the number of repetitions i reaches N, then it can be determined that the repair circuit 20 is faulty beyond repair.

[0044] pass Figure 7 The process involves storing information in the non-volatile memory or RAM of the semiconductor device that the bypass switch corresponding to the defective resistor element in the adjustment circuit 20 is always set to ON, and the bypass switch corresponding to the normal resistor element is set to OFF. By reading this information during user operation (S122), the normal resistor element used in the adjustment can be selected (S123).

[0045] In addition, Figure 7 In step S117, if the resistance value is within the expected range, it can be determined that only resistor element i is defective, and therefore the process can be terminated at this stage. Furthermore, based on the viewpoint of determining the defect of individual resistor elements, the resistance value of each resistor element can be measured, but by... Figure 7The relief is implemented by controlling the ON(1) / OFF(0) of the bypass switch in the same way as the control table 110. The determination can be made based on the resistance value of the actual use of the adjustment circuit 20, which can further improve the reliability of the relief process.

[0046] exist Figure 8 The diagram shows the rate of change of the resistive element's characteristics relative to packaging stress. The black circle represents the resistive element of this embodiment, and the white circle represents a P-type polysilicon resistor shown as a comparative example. During packaging, a large stress of 250 MPa or more is applied to the center of the chip. P-type polysilicon resistors, as a comparative example compared to the resistive element of this embodiment, are formed at multiple locations on the chip. The horizontal axis shows the stress generated at the location where the resistor is formed (the substrate), and the vertical axis shows the actual measured rate of change of resistance value before and after packaging. The results show that, in the case of the resistive element of this embodiment, regardless of where it is formed on the chip, the rate of change of resistance can be suppressed to less than 0.2%.

[0047] Figure 9 This is a diagram showing the distribution of packaging stress within the chip. Figure 140 is generated by simulation, using the center of chip 130 as the origin, and plotting the X-direction, Y-direction, and Z-direction packaging stresses produced by molding along the X-axis from the origin to the chip edge using arrow 131. In Figure 140, the packaging stress generated in the X-direction is waveform 141, the packaging stress generated in the Y-direction is waveform 142, and the packaging stress generated in the Z-direction is waveform 143. According to the simulation, the following results were obtained: strong compressive stresses are generated in both the X and Y directions over approximately the entire area of ​​the chip; conversely, no stress is generated in the Z direction over approximately the entire area of ​​the chip. Therefore, in the resistive element of this embodiment, it is assumed that no resistance change occurs before and after packaging.

[0048] The invention described above, based on the embodiments, is a concrete example of the invention made by the inventors of this application. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit. For example, the component using the resistive element in this embodiment is not limited to an oscillation circuit, but can also be... Figure 10 The semiconductor device 150 shown is equipped with a linear solenoid drive circuit. An inductor (not shown) is connected between terminals 151 and 152 of the semiconductor device 150. By allowing current to flow through the inductor, a magnetic field corresponding to the magnitude of the current is generated. At this time, in order to monitor the current flowing through the inductor by measuring the voltage generated across resistor 153, an A / D converter 154 detects the voltage across resistor 153 and feeds it back to the control circuit 155. Regarding resistor 153, a resistor adjustment circuit using the resistive element of this embodiment is also applied, thereby enabling accurate control of the current flowing through the inductor.

[0049] Label Explanation

[0050] 1: Semiconductor device; 2: CPU; 3: RAM; 4: Peripheral IP; 5: Non-volatile memory; 6: Register; 7: Clock generation circuit; 8: On-chip oscillator; 9: Resistor; 10: Bus; 20: Tuning circuit; 21: Constant current generation circuit; 22, 23: Capacitors; 24, 25: Capacitor drive circuit; 26, 27: Comparator; 28: Latch circuit; 51: Lower conductive layer; 52: Upper conductive layer; 53: Interlayer conductive layer; 91: Resistor element.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor substrate; as well as Multiple wiring layers are formed on the semiconductor substrate, including at least a first wiring layer and a second wiring layer. Resistive elements are formed in the plurality of wiring layers. The resistive element has a repeating pattern of a first conductive layer, a second conductive layer, and an interlayer conductive layer. The first conductive layer is formed on the first wiring layer, the second conductive layer is formed on the second wiring layer, and the interlayer conductive layer connects the first conductive layer and the second conductive layer. In the first wiring layer, the length direction of the first conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. The plurality of interlayer conductive layers contained in the resistive element are arranged in a matrix in the first direction and the second direction, and are formed into a meandering path structure at the ends of the matrix, whereby the repeating pattern folds back. The resistance value of the interlayer conductive layer is greater than the sum of the resistance values ​​of the first conductive layer and the second conductive layer.

2. The semiconductor device according to claim 1, characterized in that, The interlayer conductive layer includes a metal layer or a polysilicon layer formed between the first conductive layer and the second conductive layer.

3. The semiconductor device according to claim 1, characterized in that, The plurality of wiring layers have a third wiring layer between the first wiring layer and the second wiring layer. The interlayer conductive layer has a bonding pad formed on the third wiring layer, a first via connecting the first conductive layer to the bonding pad, and a second via connecting the second conductive layer to the bonding pad.

4. The semiconductor device according to claim 3, characterized in that, The first guide hole and the second guide hole are formed with embedded layers by embedding the W layer into the TiN layer.

5. The semiconductor device according to claim 1, characterized in that, The adjacent interlayer conductive layers contained in the resistive element are configured with the minimum spacing between them as vias in the semiconductor device.

6. The semiconductor device according to claim 1, characterized in that, It has a trimming circuit that uses multiple of the aforementioned resistive elements.

7. A semiconductor device, characterized in that, have: Semiconductor substrate; Multiple wiring layers are formed on the semiconductor substrate, including at least a first wiring layer and a second wiring layer; as well as The adjustment circuit includes resistive elements formed in the plurality of wiring layers. The resistive element has a repeating pattern of a first conductive layer, a second conductive layer, and an interlayer conductive layer. The first conductive layer is formed on the first wiring layer, the second conductive layer is formed on the second wiring layer, and the interlayer conductive layer connects the first conductive layer and the second conductive layer. In the first wiring layer, the length direction of the first conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. The plurality of interlayer conductive layers contained in the resistive element are arranged in a matrix in the first direction and the second direction, and are formed into a meandering path structure at the ends of the matrix, whereby the repeating pattern folds back. The resistance value of the interlayer conductive layer is greater than the sum of the resistance values ​​of the first conductive layer and the second conductive layer.

8. The semiconductor device according to claim 7, characterized in that, The adjustment circuit has a plurality of resistive elements connected in series and a switch connected in parallel with each of the plurality of resistive elements.

9. The semiconductor device according to claim 7, characterized in that, The interlayer conductive layer includes a metal layer or a polysilicon layer formed between the first conductive layer and the second conductive layer.

10. The semiconductor device according to claim 7, characterized in that, The plurality of wiring layers have a third wiring layer between the first wiring layer and the second wiring layer. The interlayer conductive layer has a bonding pad formed on the third wiring layer, a first via connecting the first conductive layer to the bonding pad, and a second via connecting the second conductive layer to the bonding pad.

11. The semiconductor device according to claim 7, characterized in that, The adjacent interlayer conductive layers contained in the resistive element are configured with the minimum spacing between them as vias in the semiconductor device.

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