Semiconductor Devices

Abstract

The present invention provides a semiconductor device. A semiconductor device of one embodiment comprises: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a first wiring and a second wiring arranged on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate comprises a source region, a drain region, a drift region, and a body region. The drift region is arranged to surround the body region when viewed from above. The first wiring is arranged to cross the boundary between the drift region and the body region when viewed from above, and has a first portion electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from the second wiring and is opposite to the second wiring.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] As a power semiconductor device, for example, a trench gate vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been conventionally known.

[0003] When noise is generated in such a trench gate vertical MOSFET, the noise passes through the junction capacitance of the pn junction formed between the drift region and the base region. However, when the frequency of the noise is low, the impedance of the junction capacitance becomes large. As a result, there is a problem that it becomes difficult for the noise to pass through the junction capacitance.

[0004] As semiconductor devices for solving this problem, a semiconductor device described in Japanese Patent Application Laid-Open No. 2009-260271 (Patent Document 1) and a semiconductor device described in US Pat. No. 5,998,833 (Patent Document 2) have been proposed.

[0005] The semiconductor substrate of the semiconductor device described in Patent Document 1 has a trench MOS region in which a trench-type vertical MOSFET is formed, and a capacitor forming region. In the capacitor forming region, the semiconductor substrate has a trench formed from the main surface toward the back side in the drift region, an insulating film formed on the surface of the trench, and a conductive film formed on the insulator film. The conductive film becomes the source potential. Therefore, a source-drain capacitance is formed between the conductive film and the drift region.

[0006] The semiconductor device described in Patent Document 2 has a gate electrode insulated from a local base region sandwiched between a source region and a drift region and opposite to the base region, and a conductive film insulated from the drift region and opposite to the drift region in a semiconductor substrate. The gate electrode and the conductive film are formed in a groove formed from the main surface of the semiconductor substrate toward the back side. The conductive film becomes a source potential and is arranged on the back side compared to the gate electrode. Therefore, a source-drain capacitance is formed between the conductive film and the drift region.

[0007] According to the semiconductor devices described in Patent Documents 1 and 2, an additional capacitance is formed between the source and the drain, so the influence of noise is reduced. However, the semiconductor device described in Patent Document 1 has a problem of increasing the chip area.

[0008] Furthermore, the semiconductor device described in Patent Document 2 has problems such as the need to form a deeper trench than a conventional trench-gate vertical MOSFET and the need to repeat formation and etching of an insulating film in the trench multiple times, which complicates the process. Summary of the invention

[0009] Other objects and new features will become apparent from the description of this specification and the accompanying drawings.

[0010] A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a first wiring and a second wiring, which are arranged on the first surface; a first conductive film, which is electrically connected to the first wiring; and a gate electrode. The semiconductor substrate includes a source region of a first conductivity type located on the first surface, a drain region of the first conductivity type located on the second surface, a drift region of the first conductivity type located above the drain region, and a body region of a second conductivity type sandwiched between the source region and the drift region, the second conductivity type being a conductivity type opposite to the first conductivity type. The drift region is arranged to surround the body region when viewed from above. The first wiring is arranged to cross the boundary between the drift region and the body region when viewed from above, and has a first portion electrically connected to the drift region. The gate electrode is insulated from the body region sandwiched between the source region and the drift region and is opposite to the body region. The second wiring is electrically connected to the source region. The first conductive film is insulated from the second wiring and is opposite to the second wiring.

[0011] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view of the semiconductor device according to the first embodiment.

[0013] Figure 2 yes Figure 1 Cross-sectional view taken at II-II.

[0014] Figure 3 yes Figure 1 Cross-sectional view at III-III.

[0015] Figure 4 yes Figure 1 Cross-sectional view taken at IV-IV.

[0016] Figure 5 is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0017] Figure 6 The following are process diagrams showing the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Figure 7 It is a cross-sectional view of the semiconductor device according to the first embodiment in the element region in the front-end process.

[0019] Figure 8 It is a cross-sectional view of the semiconductor device according to the first embodiment in the peripheral region during a front-end process.

[0020] Fig. 9 FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during the first interlayer insulating film forming step.

[0021] Fig.10 FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during the first interlayer insulating film forming step.

[0022] Fig.11 FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during a first contact plug forming step.

[0023] Fig.12 FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during a first contact plug forming step.

[0024] Fig.13 It is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during the second interlayer insulating film forming step.

[0025] Fig.14 It is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during the second interlayer insulating film forming step.

[0026] Fig.15 It is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during the second contact plug forming step.

[0027] Fig.16 It is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during the second contact plug forming step.

[0028] Fig.17 It is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during the third interlayer insulating film forming step.

[0029] Fig.18 It is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during the third interlayer insulating film forming step.

[0030] Fig.19 It is a cross-sectional view of the semiconductor device according to the first embodiment in the element region during the third contact plug forming step.

[0031] Fig. 20FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment in the outer peripheral region during a third contact plug forming step.

[0032] Fig.21 4 is a cross-sectional view of a semiconductor device of a comparative example near a boundary between a body region and a drift region.

[0033] Fig. 22 It is a top view of the semiconductor device according to the second embodiment.

[0034] Fig.23 yes Fig. 22 Cross-sectional view at XXIII-XXIII.

[0035] Fig.24 yes Fig. 22 Cross-sectional view at XXIV-XXIV.

[0036] Fig.25 yes Fig. 22 Cross-sectional view taken at XXV-XXV of FIG.

[0037] Fig.26 It is a top view of the semiconductor device according to the third embodiment.

[0038] Fig. 27 yes Fig.26 Cross-sectional view at XXVII-XXVII.

[0039] Fig.28 yes Fig.26 Cross-sectional view at XXVIII-XXVIII.

[0040] Fig.29 yes Fig.26 Cross-sectional view at XXIX-XXIX of FIG. DETAILED DESCRIPTION

[0041] In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0042] (First Embodiment)

[0043] Hereinafter, the structure of the semiconductor device according to the first embodiment will be described.

[0044] like Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, the semiconductor device of the first embodiment has a semiconductor substrate SUB, a gate insulating film GO, a gate electrode GE, an interlayer insulating film ILD, a contact plug CP1, a contact plug CP2, a contact plug CP3, a first conductive film FCL, a first wiring WL1, a second wiring WL2 and a third wiring WL3.

[0045] The semiconductor substrate SUB has an element region ER and a peripheral region PER. The peripheral region PER is located at the periphery of the semiconductor substrate SUB. The element region ER is a region inside the boundary between the source region SR and the body region BR when viewed from above. The semiconductor substrate SUB has a first surface FS and a second surface SS. The second surface SS is the opposite surface of the first surface FS. The semiconductor substrate SUB uses, for example, single crystal silicon (Si). However, the material used for the semiconductor substrate SUB is not limited thereto.

[0046] The semiconductor substrate SUB has a source region SR, a drain region DRA, a drift region DRI, and a body region BR. The semiconductor substrate SUB may also have a contact region CNR1, a contact region CNR2, and a column region CR.

[0047] The conductivity type of the source region SR is the first conductivity type. The conductivity type of the drain region DRA is the first conductivity type. The conductivity type of the drift region DRI is the first conductivity type. The conductivity type of the body region BR is the second conductivity type. The conductivity type of the contact region CNR1 is the second conductivity type. The conductivity type of the contact region CNR2 is the first conductivity type. The conductivity type of the column region CR is the second conductivity type.

[0048] The second conductivity type is a conductivity type opposite to the first conductivity type. For example, when the first conductivity type is n-type, the second conductivity type is p-type. In this case, the regions of the semiconductor substrate SUB that become the first conductivity type (source region SR, drain region DRA, drift region DRI, and contact region CNR2) contain acceptor elements such as phosphorus (P) and arsenic (As) as impurities. The regions of the semiconductor substrate SUB that become the second conductivity type (body region BR, contact region CNR1, and column region CR) contain acceptor elements such as boron (B) and aluminum (Al) as impurities.

[0049] The impurity concentration of the drift region DRI is preferably lower than the impurity concentrations of the source region SR and the drain region DRA. The impurity concentration of the contact region CNR1 is preferably higher than the impurity concentration of the body region BR. The impurity concentration of the contact region CNR2 is preferably higher than the impurity concentration of the drift region DRI.

[0050] The source region SR is arranged on the first surface FS. The drain region DRA is arranged on the second surface SS. The drift region DRI is arranged above the drain region DRA. More specifically, the drift region DRI is arranged above the surface of the drain region DRA on the first surface FS side. The body region BR is sandwiched between the source region SR and the drift region DRI. The contact region CNR1 is arranged on the first surface FS. The contact region CNR1 is surrounded by the body region BR.

[0051] When viewed from above (from a direction orthogonal to the first surface FS), the source region SR is surrounded by the body region BR. When viewed from above, the body region BR is surrounded by the drift region DRI. When viewed from above, the source region SR is arranged in the element region ER. The body region BR and the drift region DRI are arranged to reach the peripheral region PER when viewed from above. The contact region CNR2 is arranged on the first surface FS located in the peripheral region PER. The contact region CNR2 is surrounded by the drift region DRI. The column region CR is arranged in the drift region DRI. The column region CR extends from the body region BR toward the second surface SS side.

[0052] A trench TR1 is provided on the first surface FS. The trench TR1 extends from the first surface FS toward the second surface SS. The trench TR1 reaches the drift region DRI. From another point of view, the source region SR, the body region BR, and the drift region DRI are exposed from the sidewall of the trench TR1.

[0053] The gate insulating film GO is arranged on the side walls and bottom wall of the trench TR1. The gate insulating film GO uses, for example, silicon dioxide (SiO2). The gate electrode GE is arranged on the gate insulating film GO. The gate electrode GE is buried in the trench TR1. That is, the gate electrode GE is insulated from the body region BR sandwiched between the source region SR and the drift region DRI and is opposite to the body region BR. The gate electrode GE uses, for example, polycrystalline silicon doped with impurity elements. The gate electrode GE is preferably arranged in a comb-tooth shape when viewed from above.

[0054] The interlayer insulating film ILD is arranged on the first surface FS. The interlayer insulating film ILD includes a first interlayer insulating film ILD1, a second interlayer insulating film ILD2, and a third interlayer insulating film ILD3. The second interlayer insulating film ILD2 is arranged on the first interlayer insulating film ILD1. The third interlayer insulating film ILD3 is arranged on the second interlayer insulating film ILD2. The interlayer insulating film ILD uses SiO2, for example. More specifically, the first interlayer insulating film ILD1 uses BPSG (Boron Phosphorous Silicate Glass). The second interlayer insulating film ILD2 and the third interlayer insulating film ILD3 use p-SiO2.

[0055] The interlayer insulating film ILD is provided with a contact hole CH1, a contact hole CH2, and a contact hole CH3. The contact hole CH1, the contact hole CH2, and the contact hole CH3 penetrate the interlayer insulating film ILD in the thickness direction.

[0056] The contact hole CH1 includes a first portion CH1a, a second portion CH1b, and a third portion CH1c. The first portion CH1a is located in the first interlayer insulating film ILD1. In addition, the source region SR and the contact region CNR1 are exposed from the first portion CH1a. The second portion CH1b is located in the second interlayer insulating film ILD2. The third portion CH1c is located in the third interlayer insulating film ILD3.

[0057] The contact hole CH2 has a first portion CH2a, a second portion CH2b, and a third portion CH2c. The first portion CH2a is located in the first interlayer insulating film ILD1. In addition, the contact region CNR2 is exposed from the first portion CH2a. The second portion CH2b is located in the second interlayer insulating film ILD2. The third portion CH2c is located in the third interlayer insulating film ILD3.

[0058] The contact hole CH3 has a first portion CH3a, a second portion CH3b, and a third portion CH3c. The first portion CH3a is located in the first interlayer insulating film ILD1. The gate electrode GE is exposed from the first portion CH3a. The second portion CH3b is located in the second interlayer insulating film ILD2. The third portion CH3c is located in the third interlayer insulating film ILD3.

[0059] The contact plug CP1 electrically connects the second wiring WL2 to the source region SR and the body region BR. The contact plug CP1 has a first portion CP1a arranged in the first portion CH1a, a second portion CP1b arranged in the second portion CH1b, and a third portion CP1c arranged in the third portion CH1c.

[0060] The contact plug CP2 electrically connects the first wiring WL1 (first portion WL1a) to the contact region CNR2. Thus, the first wiring WL1 is electrically connected to the drift region DRI and the drain region DRA. The contact plug CP2 has a first portion CP2a arranged in the first portion CH2a, a second portion CP2b arranged in the second portion CH2b, and a third portion CP2c arranged in the third portion CH2c.

[0061] The contact plug CP3 electrically connects the third wiring WL3 and the gate electrode GE. The contact plug CP3 includes a first portion CP3a arranged in the first portion CH3a, a second portion CP3b arranged in the second portion CH3b, and a third portion CP3c arranged in the third portion CH3c.

[0062] The contact plug CP1 , the contact plug CP2 , and the contact plug CP3 are made of, for example, tungsten (W).

[0063] A trench TR2 is provided in the second interlayer insulating film ILD2. The trench TR2 extends from the surface of the second interlayer insulating film ILD2 on the side of the third interlayer insulating film ILD3 toward the surface of the second interlayer insulating film ILD2 on the side of the first interlayer insulating film ILD1. The trench TR2 may also penetrate the second interlayer insulating film ILD2 in the thickness direction. The first conductive film FCL is buried in the trench TR2. The material used for the first conductive film FCL is preferably the same material as the material used for the contact plug CP1, the contact plug CP2, and the contact plug CP3. That is, the first conductive film FCL uses W, for example. The first conductive film FCL is insulated from the contact plug CP1 and the second wiring WL2 by the interlayer insulating film ILD and is opposite to them. The first conductive film FCL is arranged in the element region ER when viewed from above. The first conductive film FCL is arranged to overlap with the second wiring WL2 when viewed from above. The first conductive film FCL is preferably arranged to cross the source region SR when viewed from above. It is preferable that the first conductive film FCL is arranged so as to overlap with the gate electrode GE in a plan view.

[0064] The first wiring WL1 is arranged on the first surface FS. The first wiring WL1 is arranged on the interlayer insulating film ILD. More specifically, the first wiring WL1 is arranged on the third interlayer insulating film ILD3. The first wiring WL1 has a first portion WL1a and a second portion WL1b. The first portion WL1a is arranged to cross the boundary between the body region BR and the drift region DRI when viewed from above. The second portion WL1b is arranged to surround the source region SR when viewed from above.

[0065] The first wiring WL1 is arranged on the third interlayer insulating film ILD3, while the first conductive film FCL is arranged in the second interlayer insulating film ILD2. Therefore, the distance between the first wiring WL1 (first portion WL1a) and the first surface FS is greater than the distance between the first conductive film FCL and the first surface FS.

[0066] The second wiring WL2 is arranged on the first surface FS. The second wiring WL2 is arranged on the interlayer insulating film ILD. More specifically, the second wiring WL2 is arranged on the third interlayer insulating film ILD3. The second wiring WL2 is arranged so as to overlap with the source region SR in a plan view.

[0067] The third wiring WL3 is arranged on the first surface FS. The third wiring WL3 is arranged on the interlayer insulating film ILD. More specifically, the third wiring WL3 is arranged on the third interlayer insulating film ILD3. The third wiring WL3 has a third end WL3a and a fourth end WL3b. The third end WL3a and the fourth end WL3b are separated from each other. The third wiring WL3 is arranged to cross the boundary between the body region BR and the drift region DRI when viewed from above. The third wiring WL3 extends from the third end WL3a toward the fourth end WL3b. The third wiring WL3 preferably extends along the boundary between the body region BR and the drift region DRI. The first portion WL1a passes between the third end WL3a and the fourth end WL3b.

[0068] The first wiring WL1 , the second wiring WL2 , and the third wiring WL3 are made of, for example, aluminum (Al), an Al alloy, or the like.

[0069] A via hole VH1 is provided in the third interlayer insulating film ILD3. The via hole VH1 penetrates the third interlayer insulating film ILD3 in the thickness direction. A via plug VP1 is arranged in the via hole VH1. The via plug VP1 electrically connects the first wiring WL1 (the second portion WL1b) to the first conductive film FCL. As described above, the first wiring WL1 is electrically connected to the drain region DRA. Therefore, the first conductive film FCL is electrically connected to the drain region DRA. The via plug VP1 uses, for example, W.

[0070] As described above, the first conductive film FCL is electrically connected to the drain region DRA, and is insulated from and opposed to the second wiring WL2 (and the contact plug CP1). Figure 5 As shown, in the semiconductor device of the first embodiment, the source-drain capacitance C is formed by the first conductive film FCL, the second wiring WL2, and the contact plug CP1.

[0071] Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0072] like Figure 6 As shown in FIG. 1 , the method for manufacturing a semiconductor device according to the first embodiment includes a front-end process S1 and a back-end process S2. In the front-end process S1, as shown in FIG. Figure 7 and Figure 8 As shown, a semiconductor substrate SUB, a gate insulating film GO, and a gate electrode GE are formed.

[0073] The drift region DRI is formed, for example, by epitaxial growth. The body region BR, the source region SR, the contact region CNR1, the contact region CNR2, and the column region CR are formed, for example, by ion implantation. The trench TR1 is formed, for example, by anisotropic etching such as RIE (Reactive Ion Etching). The gate insulating film GO is formed, for example, by thermal oxidation. The gate electrode GE is formed, for example, by CVD.

[0074] The back-end process S2 includes a first interlayer insulating film forming process S21 , a first contact plug forming process S22 , a second interlayer insulating film forming process S23 , a second contact plug forming process S24 , a third interlayer insulating film forming process S25 , a third contact plug forming process S26 , and a wiring forming process S27 .

[0075] like Fig. 9 and Fig.10 As shown, in the first interlayer insulating film forming step S21 , the first interlayer insulating film ILD1 is formed. The first interlayer insulating film ILD1 is formed by, for example, CVD (Chemical Vapor Deposition).

[0076] like Fig.11 and Fig.12 As shown, in the first contact plug forming step S22, the first portion CP1a and the first portion CP2a are formed. Fig.11 and Fig.12 Although not shown in the figure, the first portion CP3a is also formed in the first contact plug forming step S22.

[0077] In the first contact plug forming step S22, first, the first portion CH1a, the first portion CH2a, and the first portion CH3a are formed by anisotropically etching the first interlayer insulating film ILD1 by RIE or the like. Second, the material constituting the first portion CP1a, the first portion CP2a, and the first portion CP3a is embedded in the first portion CH1a, the first portion CH2a, and the first portion CH3a by, for example, CVD.

[0078] Third, the material constituting the first portion CP1a, the first portion CP2a and the first portion CP3a overflowing from the first portion CH1a, the first portion CH2a and the first portion CH3a is removed by, for example, CMP (Chemical Mechanical Polishing). The first portion CP1a, the first portion CP2a and the first portion CP3a are formed by the above steps.

[0079] like Fig.13 and Fig.14 As shown, in the second interlayer insulating film forming step S23, the second interlayer insulating film ILD2 is formed. The second interlayer insulating film ILD2 is formed by, for example, CVD.

[0080] like Fig.15 and Fig.16 As shown, in the second contact plug forming step S24, the second portion CP1b, the second portion CP2b and the first conductive film FCL are formed. Fig.15 and Fig.16 Although not shown in the figure, the second portion CP3b is also formed in the second contact plug forming step S24.

[0081] In the second contact plug forming step S24, first, the second portion CH1b, the second portion CH2b, the second portion CH3b and the trench TR2 are formed by anisotropically etching the second interlayer insulating film ILD2 by RIE or the like. Second, the material constituting the second portion CP1b, the second portion CP2b, the second portion CP3b and the first conductive film FCL is embedded in the second portion CH1b, the second portion CH2b, the second portion CH3b and the trench TR2 by, for example, CVD.

[0082] Third, the material constituting the second portion CP1b, the second portion CP2b, the second portion CP3b and the first conductive film FCL overflowing from the second portion CH1b, the second portion CH2b, the second portion CH3b and the trench TR2 is removed by, for example, CMP. The second portion CP1b, the second portion CP2b, the second portion CP3b and the first conductive film FCL are formed through the above steps.

[0083] like Fig.17 and Fig.18 As shown, in the third interlayer insulating film forming step S25, the third interlayer insulating film ILD3 is formed. The third interlayer insulating film ILD3 is formed by, for example, CVD.

[0084] like Fig.19 and Fig. 20 As shown, in the third contact plug forming step S26, the third portion CP1c, the third portion CP2c and the via plug VP1 are formed. Fig.19 and Fig. 20 Although not shown in the figure, the third portion CP3c is also formed in the third contact plug forming step S26.

[0085] In the third contact plug forming step S26, first, the third portion CH1c, the third portion CH2c, the third portion CH3c and the via hole VH1 are formed by anisotropically etching the third interlayer insulating film ILD3 by RIE or the like. Second, the material constituting the third portion CP1c, the third portion CP2c, the third portion CP3c and the via plug VP1 is embedded in the third portion CH1c, the third portion CH2c, the third portion CH3c and the via hole VH1 by, for example, CVD.

[0086] Third, the materials constituting the third portion CP1c, the third portion CP2c, the third portion CP3c and the via plug VP1 overflowing from the third portion CH1c, the third portion CH2c, the third portion CH3c and the via hole VH1 are removed by, for example, CMP. The third portion CP1c, the third portion CP2c, the third portion CP3c and the via plug VP1 are formed by the above steps.

[0087] In the wiring forming step S27, the first wiring WL1, the second wiring WL2, and the third wiring WL3 are formed. In the wiring forming step S27, first, the material constituting the first wiring WL1, the second wiring WL2, and the third wiring WL3 is formed into a film by sputtering or the like. In the wiring forming step S27, second, the material constituting the first wiring WL1, the second wiring WL2, and the third wiring WL3 after the film formation is patterned by photolithography and etching. Through the above steps, the first wiring WL1, the second wiring WL2, and the third wiring WL3 are formed. Figure 1 to Figure 4 The structure of the semiconductor device according to the first embodiment is shown.

[0088] Hereinafter, the effects of the semiconductor device according to the first embodiment will be described.

[0089] First, the general effects of the semiconductor device of the first embodiment are described. In the semiconductor device of the first embodiment, the first conductive film FCL is insulated from and faces the second wiring WL2. In addition, in the semiconductor device of the first embodiment, the first conductive film FCL is electrically connected to the drain region DRA, and the second wiring WL2 is electrically connected to the source region SR. That is, in the semiconductor device of the first embodiment, the source-drain capacitor C is arranged inside the element region ER when viewed from above. Therefore, in the semiconductor device of the first embodiment, it is not necessary to increase the chip area in order to form the source-drain capacitor.

[0090] Furthermore, the first conductive film FCL can be formed by, for example, a common process for forming a contact plug, and therefore, the process is not complicated by the formation of the first conductive film FCL. Therefore, according to the semiconductor device of the first embodiment, the influence of noise can be reduced without causing complication of the process or increase in chip area.

[0091] Next, the detailed effects of the semiconductor device of the first embodiment will be described by comparison with a comparative example. Fig.21 As shown, in the semiconductor device of the comparative example, the first wiring WL1 does not have the first portion WL1a. In addition, in the semiconductor device of the comparative example, the first conductive film FCL extends across the boundary between the body region BR and the drift region DRI and has a portion connected to the contact region CNR2. The semiconductor device of the comparative example is different from the semiconductor device of the first embodiment in these aspects.

[0092] The interface of the pn junction of the body region BR and the drift region DRI is exposed on the first surface FS. Therefore, the depletion layer of the pn junction is difficult to extend on the first surface FS. In the semiconductor device of the comparative example, as described above, the first conductive film FCL extends in a manner that crosses the boundary between the body region BR and the drift region DRI. That is, in the semiconductor device of the comparative example, the first conductive film FCL is electrically connected to the drain region DRA, and the distance between the portion thereof that crosses the boundary between the body region BR and the drift region DRI and the first surface FS becomes relatively close. As a result, due to the influence of the drain potential, it is more difficult for the depletion layer to extend.

[0093] On the other hand, in the semiconductor device of the first embodiment, the first wiring WL1 has a first portion WL1a. The first conductive film FCL is electrically connected to the drain region DRA by extending across the boundary between the body region BR and the drift region DRI through the first portion WL1a. Therefore, in the semiconductor device of the first embodiment, the first conductive film FCL is electrically connected to the drain region DRA, and the distance between the portion thereof that crosses the boundary between the body region BR and the drift region DRI and the first surface FS becomes relatively far. As a result, in the semiconductor device of the first embodiment, the phenomenon that the depletion layer is difficult to extend due to the influence of the drain potential is alleviated, and the off withstand voltage can be improved.

[0094] Next, the effects of the semiconductor device of the first embodiment will be described in more detail. The third wiring WL3 is insulated from the first surface FS by the interlayer insulating film ILD. The third wiring WL3 is configured to cross the boundary between the body region BR and the drift region DRI. Therefore, a MOS (Metal Oxide Semiconductor) structure is formed by the drift region DRI located at the boundary with the body region BR, the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 located on the drift region DRI, and the third wiring WL3.

[0095] The third wiring WL3 is electrically connected to the gate electrode GE. Therefore, the third wiring WL3 is reverse biased relative to the drift region DRI located at the boundary with the body region BR in the off state. As a result, the depletion layer easily extends to the drift region DRI adjacent to the body region BR and located on the first surface FS. That is, the third wiring WL3 brings a field plate effect relative to the drift region DRI located at the boundary with the body region BR.

[0096] Therefore, in the semiconductor device according to the first embodiment, when the third wiring WL3 straddles the boundary between the body region BR and the drift region DRI and extends along the boundary, the off-state breakdown voltage can be further improved.

[0097] The first conductive film FCL is embedded in the trench TR2. Therefore, even if the trench TR2 and the second portion CH1b are over-etched or under-etched in the second contact plug forming step S24, since the second interlayer insulating film ILD2 remains between the trench TR2 and the second portion CH1b, it is still easy to ensure the insulation between the first conductive film FCL serving as the drain potential and the second portion CP1b serving as the source potential.

[0098] (Second Embodiment)

[0099] Hereinafter, the structure of the semiconductor device of the second embodiment will be described. Hereinafter, the structure of the semiconductor device of the second embodiment will be mainly described with respect to the differences from the structure of the semiconductor device of the first embodiment, and the description will not be repeated.

[0100] like Fig. 22 , Fig.23 , Fig.24 and Fig.25 As shown, the semiconductor device of the second embodiment includes a semiconductor substrate SUB, a gate insulating film GO, a gate electrode GE, an interlayer insulating film ILD, a contact plug CP1, a contact plug CP2, a contact plug CP3, a first wiring WL1, a second wiring WL2, a third wiring WL3, a via plug VP1, and a first conductive film FCL. In this regard, the semiconductor device of the second embodiment is the same as the semiconductor device of the first embodiment.

[0101] The semiconductor device of the second embodiment further includes a second conductive film SCL, a via-plug VP2, and a via-plug VP3. In this point, the semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment.

[0102] A trench TR3 is provided in the second interlayer insulating film ILD2. The trench TR3 extends from the surface of the second interlayer insulating film ILD2 on the third interlayer insulating film ILD3 side toward the surface of the second interlayer insulating film ILD2 on the first interlayer insulating film ILD1 side. The trench TR3 may also penetrate the second interlayer insulating film ILD2 in the thickness direction. The second conductive film SCL is buried in the trench TR3. The second conductive film SCL uses W, for example. From another point of view, the second conductive film SCL is formed using the same material as the first conductive film FCL and is arranged in the same layer as the first conductive film FCL.

[0103] Preferably, the trench TR3 may also extend in a direction along the boundary between the body region BR and the drift region DRI. That is, the second conductive film SCL may also extend along the boundary between the body region BR and the drift region DRI.

[0104] The number of the grooves TR3 may be multiple. The grooves TR3 are respectively arranged to be separated from each other in the direction intersecting the boundary between the body region BR and the drift region DRI. The groove TR3 located closest to the drift region DRI is arranged at a position overlapping with the drift region DRI when viewed from above. The groove TR3 located closest to the body region BR is arranged at a position overlapping with the body region BR when viewed from above. That is, the second conductive film SCL is arranged to cross the boundary between the body region BR and the drift region DRI.

[0105] At the boundary between the body region BR and the drift region DRI, the second conductive film SCL and the first conductive film FCL are arranged to overlap with each other in a plan view.

[0106] The trench TR3 has a width L. The width L is a distance between side walls of the trench TR3 that face each other in a direction intersecting the boundary between the body region BR and the drift region DRI. The width L is preferably not less than 0.2 μm and not more than 0.4 μm.

[0107] The adjacent trenches TR3 are arranged to be separated from each other by a distance S in a direction intersecting the boundary between the body region BR and the drift region DRI. A value obtained by dividing the width L by the distance S is preferably not less than 0.5 and not more than 1.

[0108] The second conductive film SCL has a first end SCLa and a second end SCLb. The first end SCLa and the second end SCLb are ends of the second conductive film SCL in a direction intersecting the boundary between the body region BR and the drift region DRI. The first end SCLa is located at a position overlapping with the drift region DRI when viewed from above. The second end SCLb is located at a position overlapping with the body region when viewed from above. The first end SCLa and the boundary between the body region BR and the drift region DRI are separated by only a distance L1. The second end SCLb and the boundary between the body region BR and the drift region DRI are separated by only a distance L2. The distance L1 is preferably greater than 3 μm. The distance L2 is preferably greater than 3 μm.

[0109] The second conductive film SCL is electrically connected to the third wiring WL3. The third wiring WL3 is connected to the second conductive film SCL at the third end WL3a through the via plug VP2. The third wiring WL3 is connected to the second conductive film SCL at the fourth end WL3b through the via plug VP3. Thus, the second conductive film SCL is electrically connected to the third wiring WL3.

[0110] Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment will be described. Hereinafter, the differences from the method for manufacturing a semiconductor device according to the first embodiment will be mainly described, and the description will not be repeated.

[0111] The method for manufacturing a semiconductor device of the second embodiment includes a front-end process S1 and a back-end process S2. In addition, the back-end process S2 includes a first interlayer insulating film forming process S21, a first contact plug forming process S22, a second interlayer insulating film forming process S23, a second contact plug forming process S24, a third interlayer insulating film forming process S25, a third contact plug forming process S26, and a wiring forming process S27. In these aspects, the method for manufacturing a semiconductor device of the second embodiment is the same as the method for manufacturing a semiconductor device of the first embodiment.

[0112] The method for manufacturing a semiconductor device according to the second embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in a second contact plug forming step S24 and a third contact plug forming step S26 .

[0113] In the second contact plug forming step S24 , in addition to the second portion CP1 b , the second portion CP2 b , the second portion CP3 b , and the first conductive film FCL, the second conductive film SCL is formed.

[0114] In the process of forming the second conductive film SCL, first, the trench TR3 is formed. The trench TR3 is formed, for example, by anisotropic etching such as RIE. Second, the material constituting the second conductive film SCL is buried in the trench TR3. The material constituting the second conductive film SCL is buried in the trench TR3, for example, by CVD. Third, the material constituting the second conductive film SCL overflowing from the trench TR3 is removed. Through the above steps, the second conductive film SCL is formed. The second conductive film SCL is preferably formed simultaneously with the first conductive film FCL, the second portion CP1b, the second portion CP2b, and the second portion CP3b.

[0115] In the third contact plug forming step S26, in addition to the third portion CP1c, the third portion CP2c and the via plug VP1, the via plug VP2 and the via plug VP3 are formed in the same manner as the via plug VP1.

[0116] The effects of the semiconductor device according to the second embodiment will be described below. The effects of the semiconductor device according to the first embodiment will be mainly described below, and the description will not be repeated.

[0117] The second conductive film SCL is insulated from the first surface FS by the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2. The second conductive film SCL is configured to cross the boundary between the body region BR and the drift region DRI. Therefore, a MOS structure is formed by the drift region DRI located at the boundary with the body region BR, the first interlayer insulating film ILD1 located on the drift region DRI, and the second conductive film SCL.

[0118] The second conductive film SCL is electrically connected to the gate electrode GE. Therefore, the second conductive film SCL is reverse biased relative to the drift region DRI located at the boundary with the body region BR in the off state. As a result, the depletion layer becomes easy to extend to the drift region DRI located at the boundary with the body region BR. That is, the second conductive film SCL brings a field plate effect relative to the drift region DRI located at the boundary with the body region BR. Therefore, according to the semiconductor device of the second embodiment, the off-state withstand voltage can be further improved.

[0119] Sometimes, when the width L is less than 0.2 μm, the process conditions for forming the trench TR3 become harsh. When the width L is greater than 0.4 μm, in order to bury the material constituting the second conductive film SCL in the trench TR3, the material constituting the second conductive film SCL needs to be formed thicker, so the process time becomes longer. Therefore, when the width L is greater than 0.2 μm and less than 0.4 μm, the efficiency of the manufacturing process can be improved.

[0120] When the value obtained by dividing the width L by the interval S is less than 0.5, the interval between adjacent trenches TR3 becomes wider, and thus the field plate effect based on the second conductive film SCL becomes relatively smaller. Sometimes, when the value obtained by dividing the width L by the interval S is greater than 1, the interval between adjacent trenches TR3 becomes narrower, and thus the process conditions for forming the trench TR3 become harsh. Therefore, when the value obtained by dividing the width L by the interval S is greater than 0.5 and less than 1, the efficiency of the manufacturing process can be improved, and the cut-off withstand voltage can be improved.

[0121] When the distance L1 and the distance L2 are 3 μm or more, the width of the MOS structure including the drift region DRI located at the boundary with the body region BR, the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 located on the drift region DRI, and the second conductive film SCL can be ensured in the direction intersecting the boundary between the body region BR and the drift region DRI. Therefore, in this case, the off-state withstand voltage can be further improved.

[0122] When the second conductive film SCL is arranged to overlap with the first portion WL1a in a plan view, the second conductive film SCL shields the influence of the drain potential caused by the first portion WL1a. Therefore, in this case, the off-state withstand voltage can be further improved.

[0123] In the case where the second conductive film SCL extends along the boundary between the body region BR and the drift region DRI, a MOS structure composed of the drift region DRI located at the boundary with the body region BR, the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 located on the drift region DRI, and the second conductive film SCL is formed along the boundary between the body region BR and the drift region DRI. That is, the field plate effect based on the second conductive film SCL is brought along the boundary between the body region BR and the drift region DRI. Therefore, in this case, the turn-off withstand voltage can be further improved.

[0124] When the third wiring WL3 is connected to the second conductive film SCL at the third end WL3a and the fourth end WL3b via the via plug VP2 and the via plug VP3, a gate potential can be supplied to the second conductive film SCL and wiring resistance of the third wiring WL3 can be reduced.

[0125] (Third Embodiment)

[0126] Hereinafter, the structure of the semiconductor device according to the third embodiment will be described. Hereinafter, the structure of the semiconductor device according to the third embodiment will be mainly described with respect to points that are different from those of the semiconductor device according to the second embodiment, and the description will not be repeated.

[0127] like Fig.26 , Fig. 27 , Fig.28 and Fig.29 As shown, the semiconductor device of the third embodiment includes a semiconductor substrate SUB, a gate insulating film GO, a gate electrode GE, and an interlayer insulating film ILD. The semiconductor device of the third embodiment includes contact plugs CP1, contact plugs CP2, contact plugs CP2, first wirings WL1, second wirings WL2, third wirings WL3, via plugs VP1, via plugs VP2, via plugs VP3, a first conductive film FCL, and a second conductive film SCL. In these aspects, the semiconductor device of the third embodiment is the same as the semiconductor device of the second embodiment.

[0128] The semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in the detailed structure of the second conductive film SCL.

[0129] The second conductive film SCL is disposed on the first interlayer insulating film ILD1. The second conductive film SCL is formed integrally. The material used for the second conductive film SCL is, for example, Al, Al alloy, etc. The material used for the second conductive film SCL is preferably the same as the material used for the first conductive film FCL, and the material used for the second portion CP1b, the second portion CP2b, and the second portion CP3b.

[0130] Hereinafter, a method for manufacturing a semiconductor device according to a third embodiment will be described. Hereinafter, points different from the method for manufacturing a semiconductor device according to the second embodiment will be mainly described, and description will not be repeated.

[0131] The method for manufacturing a semiconductor device according to the third embodiment includes a front-end process S1 and a back-end process S2. In addition, the back-end process S2 includes a first interlayer insulating film forming process S21, a first contact plug forming process S22, a second interlayer insulating film forming process S23, a second contact plug forming process S24, a third interlayer insulating film forming process S25, a third contact plug forming process S26, and a wiring forming process S27. In these aspects, the method for manufacturing a semiconductor device according to the third embodiment is the same as the method for manufacturing a semiconductor device according to the second embodiment.

[0132] In the method for manufacturing a semiconductor device of the third embodiment, the second contact plug forming step S24 is performed after the first contact plug forming step S22 and before the second interlayer insulating film forming step S23. In this respect, the method for manufacturing a semiconductor device of the third embodiment is different from the method for manufacturing a semiconductor device of the second embodiment.

[0133] In the second contact plug forming step S24, the second portion CP1b, the second portion CP2b, the second portion CP3b, the first conductive film FCL and the second conductive film SCL are formed. In the second contact plug forming step S24, first, the material constituting the second portion CP1b, the second portion CP2b, the second portion CP3b, the first conductive film FCL and the second conductive film SCL is formed into a film by sputtering or the like. Second, the material constituting the second portion CP1b, the second portion CP2b, the second portion CP3b, the first conductive film FCL and the second conductive film SCL after the film formation is patterned by photolithography and etching. Through the above steps, the second portion CP1b, the second portion CP2b, the second portion CP3b, the first conductive film FCL and the second conductive film SCL are formed.

[0134] The effects of the semiconductor device according to the third embodiment will be described below. The effects of the semiconductor device according to the third embodiment will be mainly described below, and the differences from the effects of the semiconductor device according to the second embodiment will not be repeated.

[0135] In the semiconductor device of the third embodiment, the second conductive film SCL is formed integrally, so the field plate effect based on the second conductive film SCL can be further improved compared with the semiconductor device of the second embodiment in which the second conductive film SCL is divided into a plurality of parts. Therefore, according to the semiconductor device of the third embodiment, the off-state withstand voltage can be further improved.

[0136] The embodiments of the present invention are described above, but it should be understood that the embodiments disclosed this time are illustrative in all aspects and not limiting. The scope of the present invention is shown by the scope of the claims, and is intended to include the meaning equivalent to the scope of the claims and all changes within the scope.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A first wiring and a second wiring, which are arranged on the first surface; a first conductive film electrically connected to the first wiring; and Gate electrode, The semiconductor substrate comprises a source region of a first conductivity type located on the first surface, a drain region of the first conductivity type located on the second surface, a drift region of the first conductivity type located above the drain region, and a body region of a second conductivity type sandwiched between the source region and the drift region, wherein the second conductivity type is a conductivity type opposite to the first conductivity type. The drift region is configured to surround the body region when viewed from above, The first wiring is arranged to cross the boundary between the drift region and the body region in a plan view and has a first portion electrically connected to the drift region. The gate electrode is insulated from the body region sandwiched between the source region and the drift region and is opposite to the body region. The second wiring is electrically connected to the source region, The first conductive film is insulated from the second wiring and faces the second wiring, The first conductive film has one end portion terminated at a gate electrode, and the first wiring is connected to the one end portion of the first conductive film.

2. The semiconductor device according to claim 1, wherein: A second conductive film is further provided, the second conductive film being arranged so as to straddle the boundary and be electrically connected to the gate electrode.

3. The semiconductor device according to claim 2, characterized in that The second conductive film extends along the boundary.

4. The semiconductor device according to claim 2, characterized in that The second conductive film is arranged to overlap with the first portion in a plan view.

5. The semiconductor device according to claim 2, wherein: The second conductive film has a first end located above the drain region and a second end, wherein the second end is an end on the opposite side of the first end. The distance between the boundary and the first end is 3 μm or more, The distance between the boundary and the second end is 3 μm or more.

6. The semiconductor device according to claim 2, wherein: The first conductive film and the second conductive film are located in the same layer and are made of the same material.

7. The semiconductor device according to claim 2, characterized in that further comprising a third wiring, the third wiring being arranged on the first surface and being electrically connected to the gate electrode, The third wiring crosses the boundary and extends along the boundary, The third wiring has a third end and a fourth end disposed separately from the third end. The first portion passes between the third end and the fourth end in a plan view.

8. The semiconductor device according to claim 7, characterized in that The third wiring is electrically connected to the second conductive film at the third end and the fourth end.

9. The semiconductor device according to claim 2, characterized in that further comprising an interlayer insulating film, the interlayer insulating film being arranged on the first surface, At least one trench in which the second conductive film is buried is provided in the interlayer insulating film.

10. The semiconductor device according to claim 9, characterized in that The number of the grooves is multiple, A value obtained by dividing the width of the groove by the interval between the adjacent grooves is in a range of 0.5 to 1.

11. The semiconductor device according to claim 10, characterized in that The width of the groove is greater than or equal to 0.2 μm and less than or equal to 0.4 μm.

12. The semiconductor device according to claim 2, characterized in that The second conductive film is formed integrally.

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