Switch control circuit and method, switching power supply system

Abstract

The present invention discloses a switch control circuit and method, and a switch power supply system, wherein the switch control circuit includes an on-time control circuit, an off-time control circuit, and a logic circuit; the logic circuit is used to generate a switch control signal gate according to the output signals of the on-time control circuit and the off-time control circuit, and output it to the switch to control the on and off of the switch; the logic circuit can output the switch control signal gate for controlling the on-time of the switch only after the off-time of the current switch reaches a predetermined proportion of the off-time of the previous cycle. The switch control circuit and method, and the switch power supply system proposed in the present invention can make the blanking time no longer fixed, can adaptively adjust the time of the switch on point in different occasions or when the system is unstable, can control adjacent switch cycles to be more stable, effectively avoid sudden changes in the switch cycle and the inductor current entering the CCM mode at an earlier stage, and realize stable control of the output.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a switch control circuit and method, and a switch power supply system. Background Art

[0002] Figure 1 The figure is a schematic diagram of a low-level buck circuit topology. The low-level buck circuit includes a low-level switch Q. By controlling the on and off of the switch Q, the current flowing through the load LED is controlled to drive the LED. When the switch Q is turned on, the power supply, LED, inductor L and switch Q form a current path, and the current rises. When the switch Q is turned off, the LED, inductor L and diode D form a current path, and the current drops. Generally, the demagnetization detection circuit 10 detects the signal that the current of the inductor L drops to zero value, and obtains the ZCD (zero current detection) signal. When the ZCD signal comes, the switch Q is turned on. When the current flowing through the switch Q meets the conditions, that is, when the detection signal FB meets the predetermined conditions, the switch Q is turned off. This control method can be called critical current mode (BCM), or quasi-resonant control; similar control methods also exist in some other switch circuit topologies (such as isolated flyback power supply topology).

[0003] Figure 2 This is a control waveform diagram of a low-bit buck circuit; Figure 2 The waveform diagram corresponds to the above control method, and the waveforms correspond to the inductor current IL, the control signal gate of the switch Q, and the ZCD signal. However, sometimes due to the false triggering of the ZCD signal, it may cause the switch Q to turn on within a short time after it is turned off, so that it is turned on before the inductor current IL reaches zero value, instead of turning on when the inductor current IL becomes zero value (see Figure 2 The system enters continuous current mode (CCM) and the output is out of control.

[0004] Therefore, measures need to be taken to prevent such premature conduction. One control method is to set a blanking time of a fixed length (such as Figure 3 During this time, the switch will not be turned on by mistake. However, when there is interference in the system, especially for the isolated flyback power supply topology, or when there is mutual interference between multiple power supplies in parallel, or when the input voltage changes greatly, setting a fixed blanking time often does not play a good role in many cases (for example, when the frequency is too low).

[0005] It can be seen that the existing switch control circuit is not adaptable and cannot be applied to a variety of different occasions. For example, in the case of different input and output voltages, or in some occasions with interference, if the inductor current decline phase is long, the blanking time may be too short, and it is impossible to avoid entering the CCM mode when the current is large, causing the output to lose control. For occasions with a short inductor current decline phase, a short blanking time will prolong the triggering of the switch conduction point, causing the system performance to deteriorate.

[0006] In addition, the existing switch control circuit also has similar problems in situations where the system working environment is complex (such as when the system EMC interference is strong or multiple power supplies are connected in parallel). In many cases (such as when the frequency is too low), the blanking time set by a fixed time often fails to work at an early stage after shutdown, causing the circuit to enter the CCM mode at an early stage and lose output control.

[0007] In view of this, there is an urgent need to design a switch control method to overcome the above-mentioned defects of the existing control method. Summary of the invention

[0008] The present invention provides a switch control circuit and method, and a switch power supply system, which can realize stable control of output.

[0009] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0010] A switch control circuit, the switch control circuit comprising:

[0011] A conduction time control circuit, used to generate a first control signal for controlling the switch to be turned on;

[0012] A turn-off time control circuit, used to generate a second control signal for controlling the switch to turn off;

[0013] A logic circuit, whose input end is connected to the output end of the on-time control circuit and the off-time control circuit respectively, for generating a switch control signal gate according to the output signals of the on-time control circuit and the off-time control circuit, and outputting the signal to the switch to control the on and off of the switch;

[0014] The logic circuit can output a switch control signal gate for controlling the switch to turn on only after the current switch off time reaches a predetermined proportion of the previous cycle off time.

[0015] "Can" means being allowed, not whether the subsequent action will be executed immediately.

[0016] As an implementation mode of the present invention, the switch control circuit further includes a third control signal generating circuit;

[0017] The input end of the third control signal generating circuit receives the switch control signal gate to obtain the switch off time length of the previous cycle;

[0018] The output end of the third control signal generating circuit is connected to the logic circuit, and outputs the third control signal to the logic circuit to control the state of the switch control signal gate output by the logic circuit;

[0019] After the current switch off time reaches a predetermined proportion of the previous cycle off time, the third control signal generating circuit sends the third control signal to the logic circuit to allow the switch to be turned on, and the logic circuit can output the switch control signal gate to control the switch to be turned on.

[0020] As an implementation manner of the present invention, the off-time control circuit is further used to send a zero current detection signal ZCD to a logic circuit, and the zero current detection signal ZCD and the third control signal are connected to the logic circuit via an AND gate.

[0021] As an implementation mode of the present invention, the third control signal generating circuit includes a frequency locking circuit, which receives the switch control signal gate, thereby obtaining the switch-off time of the previous cycle, thereby obtaining the switch-off duration of the previous cycle;

[0022] The frequency locking circuit generates a third control signal based on the switch off time of the previous cycle, and sends a third control signal of the first state allowing the switch to be turned on to the logic circuit only after the switch off time of this cycle reaches a predetermined proportion of the switch off time of the previous cycle; when the switch is turned on, the frequency locking circuit controls the level of the third control signal to a second state different from the first state.

[0023] As an embodiment of the present invention, the on-time control circuit includes an error amplifier, a compensation network and an on-time modulation circuit; the error amplifier, the compensation network and the on-time modulation circuit are connected in sequence; the inverting input terminal of the error amplifier is connected to the current feedback signal, the non-inverting input terminal of the error amplifier is connected to the threshold signal Vth, and the error amplifier amplifies the error between the current feedback signal FB and the threshold signal Vth; the output terminal of the error amplifier is connected to the compensation network, and the amplified signal is output to the compensation network; the compensation network receives the signal amplified by the error amplifier, and generates a compensation signal, and sends the generated compensation signal to the on-time modulation circuit; the on-time modulation circuit is used to compare the compensation signal generated by the compensation circuit with the sawtooth wave signal, and output the comparison result to the logic circuit;

[0024] Alternatively, the on-time control circuit includes a comparison circuit, and when the output current feedback signal FB touches a threshold voltage, the trigger included in the logic circuit is set and the switch is turned off.

[0025] As an implementation mode of the present invention, the third control signal generating circuit is used as a part of the off time control circuit; the off time control circuit includes a second logic circuit, a frequency locking circuit and an AND gate;

[0026] The input end of the second logic circuit is connected to the output end of the demagnetization detection circuit, generates a zero current detection signal ZCD based on a signal output by the demagnetization detection circuit, and outputs the zero current detection signal ZCD to the input end of the AND gate;

[0027] The input end of the frequency locking circuit is connected to the switch control signal gate, the output end of the frequency locking circuit is connected to the input end of the AND gate; and the output end of the AND gate is connected to the logic circuit.

[0028] As an implementation mode of the present invention, the logic circuit includes a trigger, and the on-time control circuit includes an error amplifier, a compensation network and an on-time modulation circuit;

[0029] The output signal of the on-time modulation circuit is input to the reset terminal R of the trigger, and the output signal of the off-time control circuit is input to the set terminal S of the trigger.

[0030] As an implementation mode of the present invention, the frequency locking circuit is used to output the frequency locking signal A; the switch control signal gate can only be increased when the frequency locking signal A is in a valid value state, and is switched to a switch-on state;

[0031] The frequency locking circuit controls the frequency locking signal A to be in a valid value state after the current switch off time T1≥K*T0 is satisfied; wherein K is a set constant, and T0 is the switch off time of the previous cycle.

[0032] As an embodiment of the present invention, while the frequency locking signal A is in a high level state, if a high level pulse appears in the zero current detection signal ZCD, the logic circuit controls the switch control signal gate from low to high, which is used to turn on the switch, and the inductor current IL starts to rise; when the switch control signal gate changes from low to high, the frequency locking circuit controls the frequency locking signal A to become a low level.

[0033] A switching power supply system, comprising a switching circuit and the above-mentioned switching control circuit;

[0034] The switch circuit includes a switch and an inductor. The switch control circuit controls the current in the inductor by controlling the on and off of the switch, thereby controlling the current in the load.

[0035] As an implementation mode of the present invention, the switch circuit is any one of a low-level buck circuit, a low-level step-down boost circuit, a flyback voltage conversion circuit, and a boost circuit.

[0036] A switch control method, comprising:

[0037] Receive the switch control signal gate that controls the switch to turn on, and obtain the switch off time of the previous cycle;

[0038] It is determined whether the off-time of the current switch reaches a predetermined ratio of the off-time of the previous cycle. If so, the logic circuit can output a switch control signal gate to control the switch to turn on.

[0039] As an implementation mode of the present invention, a third control signal generating circuit is used to receive a switch control signal gate for controlling the switch to be turned on, thereby obtaining the switch off time length of the previous cycle;

[0040] Determine whether the current switch-off duration reaches a predetermined ratio of the switch-off duration of the previous cycle; if so, the third control signal generating circuit sends a third control signal to the logic circuit to allow the switch to be turned on;

[0041] The logic circuit combines the zero current detection signal ZCD and the state of the third control signal to output a corresponding switch control signal gate.

[0042] The beneficial effects of the present invention are as follows: the switch control circuit and method, and the switching power supply system proposed in the present invention can make the blanking time no longer fixed, and can adaptively adjust the time of the switch turn-on point in different occasions (for example, different input voltage Vin, or different output current requirements), or when the system is unstable, so that adjacent switching cycles can be controlled to be more stable, effectively avoiding sudden changes in the switching cycle and the inductor current entering the CCM mode at an earlier stage, thereby achieving stable control of the output. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. 4 is a topological diagram of an existing low-bit buck circuit. FIG.

[0044] Figure 2 It is a control waveform diagram of the existing low-level buck circuit.

[0045] Figure 3 Schematic diagram of the control waveform for setting the blanking time for the existing low-order buck circuit.

[0046] Figure 4 FIG. 4 is a circuit diagram of a switching circuit of a switching power supply system in an embodiment of the present invention.

[0047] Figure 5 FIG. 4 is a circuit diagram of a switch control circuit in an embodiment of the present invention.

[0048] Figure 6 FIG. 4 is a circuit diagram of a low-level buck circuit in which the switch circuit is a low-level buck circuit in an embodiment of the present invention.

[0049] Figure 7 FIG. 4 is a circuit diagram of a switch control circuit in an embodiment of the present invention.

[0050] Figure 8 FIG. 4 is a circuit diagram of a compensation network of a switch control circuit in an embodiment of the present invention.

[0051] Fig. 9 FIG. 1 is a schematic diagram of control waveforms of a switch control circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0054] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0055] The term "coupled" or "connected" in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrical conductive media. "Multiple" refers to two or more.

[0056] Figure 4 is a circuit diagram of a switch circuit in an embodiment of the present invention, Figure 5 FIG. 1 is a circuit diagram of a switch control circuit in an embodiment of the present invention. Figure 4 , Figure 5 As shown, the switch circuit 2 includes a switch tube; the switch control circuit 1 of the present invention includes: an on-time control circuit 11, an off-time control circuit 13, and a logic circuit 15.

[0057] The on-time control circuit 11 is used to generate a first control signal for controlling the switch to be turned on; the off-time control circuit 13 is used to generate a second control signal for controlling the switch to be turned off. The input end of the logic circuit 15 is connected to the output end of the on-time control circuit 11 and the off-time control circuit 13 respectively, and is used to generate a switch control signal gate according to the output signals of the on-time control circuit 11 and the off-time control circuit 13, and output it to the switch to control the switch to be turned on and off. The logic circuit 15 can only output the switch control signal gate for controlling the switch to be turned on after the off-time duration of the current switch reaches a predetermined proportion of the off-time duration of the previous cycle.

[0058] In one embodiment of the present invention, the switch control circuit further includes a third control signal generating circuit; the input end of the third control signal generating circuit receives the switch control signal gate to obtain the switch off duration of the previous cycle. The output end of the third control signal generating circuit is connected to the logic circuit 15, and outputs a third control signal to the logic circuit 15 to control the state of the switch control signal gate output by the logic circuit. After the switch off duration of this time reaches a predetermined proportion of the switch off duration of the previous cycle, the third control signal generating circuit sends a third control signal to the logic circuit 15 to allow the switch to be turned on, and the logic circuit 15 can output the switch control signal gate to control the switch to be turned on.

[0059] In one embodiment of the present invention, the off time control circuit is further used to send a zero current detection signal ZCD to the logic circuit 15, and the zero current detection signal ZCD and the third control signal are connected to the logic circuit 15 (which can be combined with the gate 135) through the AND gate 135. Figure 7 , Figure 7 In the embodiment, the third control signal generating circuit is a frequency locking circuit 133).

[0060] In one embodiment of the present invention, please continue to refer to Figure 5 , the third control signal generating circuit includes a frequency locking circuit 133, the frequency locking circuit 133 receives the switch control signal gate, thereby obtaining the switch-off time of the previous cycle, thereby obtaining the switch-off duration of the previous cycle. The frequency locking circuit 133 generates the third control signal based on the switch-off duration of the previous cycle, and sends the third control signal of the first state (such as a high level) that allows the switch to be turned on to the logic circuit 15 only after the switch-off duration of this cycle reaches a predetermined proportion of the switch-off duration of the previous cycle; when the switch is turned on, the frequency locking circuit 133 controls the level of the third control signal to a second state (such as a low level) different from the first state, and the second state is a state in which the switch is not allowed to be triggered to turn on after the switch is turned off.

[0061] Figure 6 is a circuit diagram of a low-bit buck circuit in one embodiment of the present invention; please refer to Figure 6 In one embodiment of the present invention, the switch circuit is a low-level buck circuit, and the low-level buck circuit includes a switch tube Q and an inductor L. Of course, the switch circuit can also be other topologies, such as a low-level buck-boost circuit (buck-boost), a flyback voltage conversion circuit (flyback), a boost circuit (boost), etc.

[0062] Figure 7 is a circuit diagram of a switch control circuit in one embodiment of the present invention; please refer to Figure 7In one embodiment of the present invention, the on-time control circuit 11 includes an error amplifier 111, a compensation network 113 and an on-time modulation circuit 115; the error amplifier 111, the compensation network 113 and the on-time modulation circuit 115 are connected in sequence. The inverting input terminal of the error amplifier 111 is connected to the current feedback signal, the non-inverting input terminal of the error amplifier 111 is connected to the threshold signal Vth, and the error amplifier 111 amplifies the error between the current feedback signal FB and the threshold signal Vth. The output terminal of the error amplifier 111 is connected to the compensation network 113, and the amplified signal is output to the compensation network 113. The compensation network 113 receives the signal amplified by the error amplifier 111, and generates a compensation signal Vc, and sends the generated compensation signal to the on-time modulation circuit 115. The on-time modulation circuit 115 is used to compare the compensation signal Vc generated by the compensation circuit 113 with the sawtooth wave signal M (such as Figure 8 As shown), the compared result is output to the logic circuit 15. Figure 8 FIG. 1 is a circuit diagram of a compensation network and an on-time modulation circuit 115 of a switch control circuit in an embodiment of the present invention; please refer to FIG. Figure 8 In one embodiment of the present invention, the compensation network 113 includes a capacitor C.

[0063] In another embodiment of the present invention, the on-time control circuit 11 includes a comparison circuit. When the output current feedback signal FB touches a threshold voltage, the trigger included in the logic circuit is set and the switch is turned off.

[0064] Please continue reading Figure 7In one embodiment of the present invention, the third control signal generating circuit is used as a part of the off-time control circuit 13 (the third control signal generating circuit can be a frequency locking circuit 133); the off-time control circuit 13 includes a second logic circuit 131, a frequency locking circuit 133 and an AND gate 135. The input end of the second logic circuit 131 is connected to the output end of the demagnetization detection circuit 137, generates a zero current detection signal ZCD based on the signal output by the demagnetization detection circuit 137, and outputs the zero current detection signal ZCD to the input end of the AND gate 135. The entire demagnetization detection circuit 137 or a part of the demagnetization detection circuit 137 can be located in the switch control circuit (the entire demagnetization detection circuit 137 or a part of the demagnetization detection circuit 137 can be used as a part of the switch control circuit); or, the demagnetization detection circuit can also be located outside the switch control circuit (the entire demagnetization detection circuit 137 can also be set independently without being a part of the switch control circuit). In one embodiment of the present invention, the demagnetization detection signal output by the demagnetization detection circuit 137 outputs a high level when the inductor current is zero and a low level when the inductor current is not zero. The logic circuit detects the rising edge of the demagnetization detection signal to generate a ZCD pulse signal. The input end of the frequency locking circuit 133 is connected to the switch control signal gate, and the output end of the frequency locking circuit 133 is connected to the input end of the AND gate 135; the output end of the AND gate 135 is connected to the logic circuit 15.

[0065] In one embodiment of the present invention, the logic circuit 15 includes a trigger 151; the output signal of the on-time modulation circuit 115 is input to the reset terminal R of the trigger 151, and the output signal of the off-time control circuit 13 is input to the set terminal S of the trigger 151. The trigger 151 is used to generate a switch control signal (PWM or gate).

[0066] In one embodiment of the present invention, the frequency locking circuit is used to output a frequency locking signal A; the switch control signal gate can only be increased when the frequency locking signal A is in a valid value state, and is switched to a switch-on state.

[0067] In one embodiment of the present invention, the frequency locking circuit controls the frequency locking signal A to be in a valid value state after satisfying the current switch off time T1≥K*T0; wherein K is a set constant (for example, a value between 80% and 95%, or other values), and T0 is the switch off time of the previous cycle.

[0068] In one embodiment of the present invention, when the frequency lock signal A is in a high level state, if a high level pulse appears in the zero current detection signal ZCD, the AND gate 135 outputs a high level pulse, the trigger 151 is set, and the logic circuit controls the switch control signal gate from low to high to turn on the switch, and the inductor current IL starts to rise; when the switch control signal gate changes from low to high, the frequency lock circuit controls the frequency lock signal A to become a low level.

[0069] Fig. 9 FIG. 1 is a schematic diagram of control waveforms of a switch control circuit according to an embodiment of the present invention; please refer to FIG. Fig. 9 In one embodiment of the present invention, the effective value of the frequency locking signal A appears in the second half of the switch control signal gate off period T0, T1, and T2. The switch control signal gate can only rise when the frequency locking signal A is in the effective value state and switch to the switch on state. The starting time t1 of the effective value of the frequency locking signal A is related to the time length of the previous cycle T0 of gate. Timing starts from the beginning of the T1 cycle, t1=K*T0, where K is a constant, for example, K can be selected as a value between 80% and 95%. The frequency locking signal A is the opposite signal of the switch control signal gate, and the "AND" signal of the signal generated by multiplying the off time length of the previous cycle by the ratio K.

[0070] When the frequency lock signal A is in the high level state, the zero current detection signal ZCD has a high level pulse, and the switch control signal gate changes from low to high, which is used to turn on the switch, and the inductor current IL starts to rise. When the switch control signal gate changes from low to high, the frequency lock signal A changes to a low level.

[0071] Due to the high switching frequency, the start time t1 of the frequency-locking signal can be adaptively adjusted in a very short time, effectively avoiding the switch tube Q from being turned on due to false triggering at an early stage, and effectively avoiding the switch from entering the CCM mode at an early stage when the inductor current drops, thereby making the output stable.

[0072] The present invention discloses a switching power supply system, the switching power supply system comprising a switching circuit and a switching control circuit; Figure 4 is a circuit diagram of a switch circuit in an embodiment of the present invention, Figure 5 FIG. 1 is a circuit diagram of a switch control circuit in an embodiment of the present invention. Figure 4 , Figure 5 and Figure 6 As shown, the switch circuit 2 includes a switch and an inductor. The switch control circuit 1 controls the current in the inductor by controlling the on and off of the switch Q, thereby controlling the current in the load.

[0073] Figure 6 is a circuit diagram of a low-bit buck circuit in one embodiment of the present invention; please refer to Figure 6In one embodiment of the present invention, the switch circuit is a low-level buck circuit, and the low-level buck circuit includes a switch Q and an inductor L. Of course, the switch circuit may also be other topologies, such as a low-level buck-boost circuit (buck-boost), a flyback voltage conversion circuit (flyback), a boost circuit (boost), and the like.

[0074] The specific composition of the switch control circuit 1 can be found in the above description of the switch control circuit, which will not be repeated here.

[0075] The present invention discloses a switch control method, comprising:

[0076] Receive the switch control signal gate that controls the switch to turn on, and obtain the switch off time of the previous cycle;

[0077] It is determined whether the off-time of the current switch reaches a predetermined ratio of the off-time of the previous cycle. If so, the logic circuit is allowed to output a switch control signal gate for controlling the switch to be turned on.

[0078] In one embodiment of the present invention, the switch control method includes:

[0079] Using the third control signal generating circuit to receive the switch control signal gate for controlling the switch to be turned on, thereby obtaining the switch off time of the previous cycle;

[0080] Determine whether the current switch-off duration reaches a predetermined ratio of the switch-off duration of the previous cycle; if so, the third control signal generating circuit sends a third control signal to the logic circuit to allow the switch to be turned on;

[0081] The logic circuit combines the zero current detection signal ZCD and the state of the third control signal to output a corresponding switch control signal gate.

[0082] For the specific process of each of the above steps, please refer to the above description of the components of the switch control circuit (especially the introduction of Figures 7 to 9 The specific control process has been introduced in detail when introducing the composition of the switch control circuit, so it will not be repeated here.

[0083] In summary, the switch control circuit and method, and the switching power supply system proposed in the present invention can make the blanking time no longer fixed, and can adaptively adjust the time of the switch turn-on point in different occasions (for example, different input voltage Vin, or different output current requirements), or when the system is unstable, so that adjacent switching cycles can be controlled to be more stable, effectively avoiding sudden changes in the switching cycle and the inductor current entering the CCM mode at an early stage, thereby achieving stable control of the output.

[0084] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various components equivalent to those of ordinary skill in the art are well known. It should be clear to those skilled in the art that the present invention can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A switch control circuit, characterized in that: The switch control circuit comprises: A conduction time control circuit, used to generate a first control signal for controlling the switch to be turned on; A turn-off time control circuit, used to generate a second control signal for controlling the switch to turn off; A logic circuit, whose input end is connected to the output end of the on-time control circuit and the off-time control circuit respectively, for generating a switch control signal gate according to the output signals of the on-time control circuit and the off-time control circuit, and outputting the signal to the switch to control the on and off of the switch; The logic circuit can output a switch control signal gate for controlling the switch to turn on only after the current switch off time reaches a predetermined proportion of the previous cycle off time; The on-time control circuit includes an error amplifier, a compensation network and an on-time modulation circuit; the error amplifier, the compensation network and the on-time modulation circuit are connected in sequence; the inverting input terminal of the error amplifier is connected to the current feedback signal, the non-inverting input terminal of the error amplifier is connected to the threshold signal Vth, and the error amplifier amplifies the error between the current feedback signal FB and the threshold signal Vth; the output terminal of the error amplifier is connected to the compensation network, and the amplified signal is output to the compensation network; the compensation network receives the signal amplified by the error amplifier, and generates a compensation signal, and sends the generated compensation signal to the on-time modulation circuit; the on-time modulation circuit is used to compare the compensation signal generated by the compensation circuit with the sawtooth wave signal, and output the comparison result to the logic circuit; Alternatively, the on-time control circuit includes a comparison circuit, and when the output current feedback signal FB touches a threshold voltage, the trigger included in the logic circuit is set and the switch is turned off; The switch control circuit further includes a third control signal generating circuit; The input end of the third control signal generating circuit receives the switch control signal gate to obtain the switch off time length of the previous cycle; The output end of the third control signal generating circuit is connected to the logic circuit, and outputs the third control signal to the logic circuit to control the state of the switch control signal gate output by the logic circuit; After the current switch off time reaches a predetermined proportion of the previous cycle off time, the third control signal generating circuit sends the third control signal to the logic circuit to allow the switch to be turned on, and the logic circuit can output the switch control signal gate to control the switch to be turned on; The third control signal generating circuit includes a frequency locking circuit, which receives the switch control signal gate, thereby obtaining the switch-off time of the previous cycle, thereby obtaining the switch-off duration of the previous cycle; The frequency locking circuit generates a third control signal based on the switch off time of the previous cycle, and sends a third control signal of the first state allowing the switch to be turned on to the logic circuit only after the switch off time of this cycle reaches a predetermined proportion of the switch off time of the previous cycle; when the switch is turned on, the frequency locking circuit controls the level of the third control signal to a second state different from the first state; The logic circuit includes a trigger, and the on-time control circuit includes an error amplifier, a compensation network and an on-time modulation circuit; The output signal of the on-time modulation circuit is input to the reset terminal R of the trigger, and the output signal of the off-time control circuit is input to the set terminal S of the trigger; The frequency locking circuit is used to output a frequency locking signal A; the switch control signal gate can only be increased when the frequency locking signal A is in a valid value state, and is switched to a switch-on state; The frequency locking circuit controls the frequency locking signal A to be in a valid value state after the switch off time T1≥K*T0 is satisfied; wherein K is a set constant, and T0 is the switch off time of the previous cycle; During the period when the frequency lock signal A is in a high level state, if a high level pulse appears in the zero current detection signal ZCD, the logic circuit controls the switch control signal gate from low to high to turn on the switch, and the inductor current IL starts to rise; when the switch control signal gate changes from low to high, the frequency lock circuit controls the frequency lock signal A to become a low level.

2. The switch control circuit according to claim 1, characterized in that: The off-time control circuit is further used to send a zero current detection signal ZCD to the logic circuit, and the zero current detection signal ZCD and the third control signal are connected to the logic circuit through an AND gate.

3. The switch control circuit according to claim 1, characterized in that: The third control signal generating circuit is used as a part of the off time control circuit; the off time control circuit includes a second logic circuit, a frequency locking circuit and an AND gate; The input end of the second logic circuit is connected to the output end of the demagnetization detection circuit, generates a zero current detection signal ZCD based on a signal output by the demagnetization detection circuit, and outputs the zero current detection signal ZCD to the input end of the AND gate; The input end of the frequency locking circuit is connected to the switch control signal gate, the output end of the frequency locking circuit is connected to the input end of the AND gate; and the output end of the AND gate is connected to the logic circuit.

4. A switching power supply system, characterized in that: The switching power supply system comprises a switching circuit and a switching control circuit as claimed in any one of claims 1 to 3; The switch circuit includes a switch and an inductor. The switch control circuit controls the current in the inductor by controlling the on and off of the switch, thereby controlling the current in the load.

5. The switching power supply system according to claim 4, characterized in that: The switch circuit is any one of a low-level buck circuit, a low-level step-down and step-up circuit, a flyback voltage conversion circuit, and a step-up circuit.

6. A switch control method for a switch control circuit according to any one of claims 1 to 3, characterized in that: include: Receive the switch control signal gate that controls the switch to turn on, and obtain the switch off time of the previous cycle; Determine whether the current switch-off duration reaches a predetermined ratio of the previous cycle's switch-off duration. If so, the logic circuit can output a switch control signal gate to control the switch to turn on. Generate a first control signal for controlling the switch to be turned on by a conduction time control circuit; The on-time control circuit includes an error amplifier, a compensation network and an on-time modulation circuit; The error amplifier, the compensation network, and the on-time modulation circuit are connected in sequence; the inverting input terminal of the error amplifier is connected to the current feedback signal, the non-inverting input terminal of the error amplifier is connected to the threshold signal Vth, and the error amplifier amplifies the error between the current feedback signal FB and the threshold signal Vth; the output terminal of the error amplifier is connected to the compensation network, and the amplified signal is output to the compensation network; the compensation network receives the signal amplified by the error amplifier, and generates a compensation signal, and sends the generated compensation signal to the on-time modulation circuit; The on-time modulation circuit is used to compare the compensation signal generated by the compensation circuit with the sawtooth wave signal, and output the comparison result to the logic circuit; Alternatively, the on-time control circuit includes a comparison circuit, and when the output current feedback signal FB touches a threshold voltage, the trigger included in the logic circuit is set and the switch is turned off.

7. The switch control method according to claim 6, characterized in that: Using the third control signal generating circuit to receive the switch control signal gate for controlling the switch to be turned on, thereby obtaining the switch off time of the previous cycle; Determine whether the current switch-off duration reaches a predetermined ratio of the switch-off duration of the previous cycle; if so, the third control signal generating circuit sends a third control signal to the logic circuit to allow the switch to be turned on; The logic circuit combines the zero current detection signal ZCD and the state of the third control signal to output a corresponding switch control signal gate.

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