A configuration protection circuit for satellite-borne equipment

Abstract

The present invention provides a configuration protection circuit for satellite-borne equipment, comprising an FPGA chip, a memory and a monitor electrically connected to the FPGA chip, the memory being used to store a loading program of the FPGA chip, the monitor monitoring the working state of the FPGA chip, and when the FPGA chip fails, the monitor controlling the memory to reload the program to the FPGA chip, the FPGA chip being a chip XC7A100T, the memory comprising a ROM chip XC17V16 and a RAM chip XCF32PV, and the monitor being a chip TPS3823. The circuit of the present invention can monitor the working state of the FPGA chip in real time, recover through program loading after a failure occurs, and has the characteristics of high reliability and strong versatility.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite-borne equipment circuits, and in particular to a configuration protection circuit used in satellite-borne equipment. Background Art

[0002] In satellite-borne electronic equipment, there are high requirements for the reliability of circuit operation, especially for programmable electronic components. When the internal circuit fails, it can be updated by reloading the program. However, the existing technology lacks effective monitoring and protection for the configuration circuits for program loading, which often results in the failure to detect faults in time and the failure to effectively load after a fault. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a configuration protection circuit for satellite-borne equipment to solve the problem of lack of safe and effective protection for fault monitoring and program loading of programmable electronic components in the prior art.

[0004] To solve the above problems, the solution provided by the present invention is to provide a configuration protection circuit for satellite-borne equipment, including an FPGA chip, and a memory and a monitor electrically connected to the FPGA chip, the memory is used to store the loading program of the FPGA chip, the monitor monitors the working status of the FPGA chip, and when the FPGA chip fails, the monitor controls the memory to reload the program to the FPGA chip, the FPGA chip is a chip XC7A100T, the memory includes a ROM chip XC17V16, and the monitor is a chip TPS3823.

[0005] In another embodiment of the configuration protection circuit used in satellite-borne equipment of the present invention, the chip XC7A100T includes a monitoring pin for monitoring the internal working state, and the monitoring pin is electrically connected to the WDI pin of the chip TPS3823. When the chip XC7A100T works normally, the monitoring pin outputs a pulse signal to the WDI pin at a regular interval. When the monitoring pin stops outputting the pulse signal, the chip TPS3823 determines that the chip XC7A100T has a fault.

[0006] In another embodiment of the configuration protection circuit used in the satellite-borne equipment of the present invention, the RESET pin of the chip TPS3823 is also electrically connected to the program loading monitoring pin of the chip XC7A100T. When the chip TPS3823 determines that the chip XC7A100T fails, the RESET pin outputs a start signal to the program loading monitoring pin, and then the chip XC7A100T reloads the program from the chip XC17V16.

[0007] In another embodiment of the configuration protection circuit used in satellite-borne equipment of the present invention, the MR pin of the chip TPS3823 is also externally connected to a reset signal. When the MR pin receives the reset signal, the RESET pin outputs a start signal to the program loading monitoring pin, and then the chip XC7A100T reloads the program from the chip XC17V16.

[0008] In another embodiment of the configuration protection circuit used in satellite-borne equipment of the present invention, the control interface electrically connecting the chip XC7A100T and the chip XC17V16 includes a clock pin for transmitting a clock signal, an enable pin for transmitting an enable signal, and an interrupt pin for transmitting an interrupt signal, and the data interface electrically connecting the chip XC7A100T and the chip XC17V16 includes an 8-bit data port.

[0009] In another embodiment of the configuration protection circuit used in satellite-borne equipment of the present invention, the memory also includes a RAM chip XCF32PV, and the RESET pin of the chip TPS3823 is also electrically connected to the chip select pin of the chip XCF32PV. When the chip TPS3823 determines that the chip XC7A100T has a fault, the RESET pin outputs a start signal to the program loading monitoring pin, and also outputs a chip select signal to the chip select pin of the chip XCF32PV, and then the chip XC7A100T reloads the program from the chip XCF32PV.

[0010] In another embodiment of the configuration protection circuit used in satellite-borne equipment of the present invention, the control interface electrically connecting the chip XC7A100T and the chip XCF32PV includes a clock pin for transmitting a clock signal, an enable pin for transmitting an enable signal, and an interrupt pin for transmitting an interrupt signal, and the data interface electrically connecting the chip XC7A100T and the chip XCF32PV includes an 8-bit data port.

[0011] The beneficial effects of the present invention are as follows: the present invention provides a configuration protection circuit for satellite-borne equipment, including an FPGA chip, and a memory and a monitor electrically connected to the FPGA chip, the memory is used to store the loading program of the FPGA chip, the monitor monitors the working state of the FPGA chip, when the FPGA chip fails, the monitor controls the memory to reload the program to the FPGA chip, the FPGA chip is a chip XC7A100T, the memory includes a ROM chip XC17V16 and a RAM chip XCF32PV, and the monitor is a chip TPS3823. The circuit of the present invention can monitor the working state of the FPGA chip in real time, recover through program loading after a failure occurs, and has the characteristics of high reliability and strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a composition principle diagram of a configuration protection circuit used in a satellite-borne device according to the present invention;

[0013] Figure 2 is a monitor circuit diagram in another embodiment of a configuration protection circuit used in a satellite-borne device according to the present invention;

[0014] Figure 3 It is a circuit diagram of a part of an interface of an FPGA chip in another embodiment of a configuration protection circuit used in a satellite-borne device according to the present invention;

[0015] Figure 4 is a ROM memory circuit diagram in another embodiment of a configuration protection circuit used in a satellite-borne device according to the present invention;

[0016] Figure 5 FIG. 4 is a circuit diagram of a RAM memory in another embodiment of a configuration protection circuit used in a satellite-borne device according to the present invention. DETAILED DESCRIPTION

[0017] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are provided in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0018] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0019] The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not used to limit the present invention. The term "and / or" used in this description includes any and all combinations of one or more related listed items.

[0020] Figure 1 The present invention shows an embodiment of a configuration protection circuit for satellite-borne equipment, which includes an FPGA chip, a memory and a monitor electrically connected to the FPGA chip, the memory is used to store the loading program of the FPGA chip, the monitor monitors the working state of the FPGA chip, and when the FPGA chip fails, the monitor controls the memory to reload the program to the FPGA chip. Preferably, the FPGA chip is a chip XC7A100T, the memory includes a ROM chip XC17V16, and the monitor is a chip TPS3823.

[0021] like Figure 2 As shown, the chip XC7A100T includes a monitoring pin for monitoring the internal working state, and the monitoring pin is electrically connected to the WDI pin of the chip TPS3823. When the chip XC7A100T works normally, the monitoring pin outputs a pulse signal WDI to the WDI pin at a regular time. When the monitoring pin stops outputting the pulse signal, the chip TPS3823 determines that the chip XC7A100T fails.

[0022] Furthermore, the / RESET pin of the chip TPS3823 is also electrically connected to the program loading monitoring pin of the chip XC7A100T. When the chip TPS3823 determines that the chip XC7A100T fails, the / RESET pin outputs a start signal PROG to the program loading monitoring pin, and then the chip XC7A100T reloads the program from the chip XC17V16. In addition, the / MR pin of the chip TPS3823 is also externally connected to a reset signal. When the / MR pin receives the reset signal, the / RESET pin outputs a start signal to the program loading monitoring pin of the chip XC7A100T, and then the chip XC7A100T reloads the program from the chip XC17V16.

[0023] like Figure 3 As shown, the chip XC7A100T includes a control interface with the chip XC17V16, mainly including a clock pin CCLK for transmitting a clock signal FPGA_CCLK, an enable pin DONE for transmitting an enable signal FPGA_DONE, and an interrupt pin INIT for transmitting an interrupt signal FPGA_INT, and these pins are electrically connected to corresponding pins of the chip XC17V16. Figure 4 As shown, the corresponding pins of the chip XC17V16 include a clock pin CLK for transmitting a clock signal FPGA_CCLK, an enable pin / CE for transmitting an enable signal FPGA_DONE, an interrupt pin OE / RESET for transmitting an interrupt signal FPGA_INT, and Figure 4 Also shown are 8-bit data ports, namely D0-D7, which are used to transmit data signals FPGA_DIN0 to FPGA_DIN7 respectively. These data interfaces are also connected to the corresponding data interfaces of chip XC7A100T.

[0024] Further preferably, the memory includes a RAM chip XCF32PV, which is mainly used for loading programs in the debugging stage of the FPGA chip. That is, in the debugging stage, when the power is always on, the program can be loaded and debugged through the chip XCF32PV, which has the characteristics of fast speed, but when the power is off, the program data in the chip XCF32PV will be lost. For the chip XC17V16, after the program is loaded, the loaded program data is retained regardless of whether the power is off or not.

[0025] like Figure 5 As shown, the RESET pin of the chip TPS3823 is also electrically connected to the chip select pin / CF of the chip XCF32PV. When the chip TPS3823 determines that the chip XC7A100T fails, the RESET pin outputs a start signal PROG to the program loading monitoring pin, and also outputs a chip select signal PROG to the chip select pin of the chip XCF32PV. Then the chip XC7A100T reloads the program from the chip XCF32PV. It can be seen that in the debugging stage, the program is preferentially loaded from the chip XCF32PV to the chip XC7A100T.

[0026] Furthermore, the interface between the chip XCF32PV and the chip XC7A100T also includes a clock pin CCLK for transmitting the clock signal FPGA_CCLK, an enable pin / CE for transmitting the enable signal FPGA_DONE, an interrupt pin OE / RESET for transmitting the interrupt signal FPGA_INT, and Figure 5 Also shown are 8-bit data ports, namely D0-D7, which are used to transmit data signals FPGA_DIN0 to FPGA_DIN7 respectively. These data interfaces are also connected to the corresponding data interfaces of chip XC7A100T.

[0027] The beneficial effects of the present invention are as follows: the present invention provides a configuration protection circuit for satellite-borne equipment, including an FPGA chip, and a memory and a monitor electrically connected to the FPGA chip, the memory is used to store the loading program of the FPGA chip, the monitor monitors the working state of the FPGA chip, when the FPGA chip fails, the monitor controls the memory to reload the program to the FPGA chip, the FPGA chip is a chip XC7A100T, the memory includes a ROM chip XC17V16 and a RAM chip XCF32PV, and the monitor is a chip TPS3823. The circuit of the present invention can monitor the working state of the FPGA chip in real time, recover through program loading after a failure occurs, and has the characteristics of high reliability and strong versatility.

[0028] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A configuration protection circuit for onboard equipment, It is characterized in that It includes an FPGA chip, and a memory and a monitor electrically connected to the FPGA chip, wherein the memory is used to store a loading program of the FPGA chip, and the monitor monitors the working state of the FPGA chip. When the FPGA chip fails, the monitor controls the memory to reload the program to the FPGA chip. The FPGA chip is a chip XC7A100T, the memory includes a ROM chip XC17V16, and the monitor is a chip TPS3823; The MR pin of the chip TPS3823 is also externally connected to a reset signal, and the RESET pin of the chip TPS3823 is electrically connected to the program loading monitoring pin of the chip XC7A100T. When the MR pin receives the reset signal, the RESET pin outputs a start signal to the program loading monitoring pin, and then the chip XC7A100T reloads the program from the chip XC17V16; The memory also includes a RAM chip XCF32PV, which is used for loading programs to the chip XC7A100T during the program debugging stage. The RESET pin of the chip TPS3823 is also electrically connected to the chip select pin of the chip XCF32PV. In the program debugging stage, the program is preferentially loaded from the chip XCF32PV to the chip XC7A100T. When the chip TPS3823 determines that the chip XC7A100T fails, the RESET pin outputs a start signal to the program loading monitoring pin, and also outputs a chip select signal to the chip select pin of the chip XCF32PV. When the power is on during the debugging stage, the chip XC7A100T reloads the program from the chip XCF32PV. The control interfaces electrically connecting the chip XC7A100T with the chip XC17V16 and the chip XCF32PV all include the same clock pin for transmitting a clock signal, the same enable pin for transmitting an enable signal, and the same interrupt pin for transmitting an interrupt signal. The data interfaces electrically connecting the chip XC7A100T with the chip XC17V16 and the chip XCF32PV all include the same 8-bit data port.

2. The configuration protection circuit for use in a satellite-borne device according to claim 1, It is characterized in that The chip XC7A100T includes a monitoring pin for monitoring the internal working status, and the monitoring pin is electrically connected to the WDI pin of the chip TPS3823. When the chip XC7A100T works normally, the monitoring pin outputs a pulse signal to the WDI pin at a regular interval. When the monitoring pin stops outputting the pulse signal, the chip TPS3823 determines that the chip XC7A100T fails.

3. The configuration protection circuit for use in a satellite-borne device according to claim 2, It is characterized in that When the chip TPS3823 determines that the chip XC7A100T fails, the RESET pin of the chip TPS3823 outputs a start signal to the program loading monitoring pin, and then the chip XC7A100T reloads the program from the chip XC17V16.

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