Reverse-conducting IGBT

Abstract

The present invention relates to a reverse-conducting IGBT. A power semiconductor device includes a semiconductor body, a first load terminal structure disposed on the front side of the semiconductor body, and a second load terminal structure disposed on the rear side of the semiconductor body, and is configured to control a load current between the first load terminal structure and the second load terminal structure by means of at least one transistor cell. The transistor cell is at least partially included in the semiconductor body and is electrically connected to the first load terminal structure on one side and to the drift region of the semiconductor body on the other side, the drift region having a first conductivity type. The semiconductor body further includes: a transistor short region having a first conductivity type, wherein a transition between the transistor short region and the first load terminal structure forms a Schottky contact; and a separation region that separates the transistor short region from the drift region and has a second conductivity type complementary to the first conductivity type.

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices and methods of processing power semiconductor devices. In particular, this specification relates to embodiments of power semiconductor devices having reverse current capability, such as reverse conducting IGBTs. Background Art

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving electric motors or machines, rely on power semiconductor devices. For example, by way of non-limiting examples only, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0003] Power semiconductor devices typically include a semiconductor body configured to conduct a load current between two load terminals of the device. Further, the load current is controlled by a transistor cell at least partially included in the semiconductor body. For example, the transistor cell includes an insulating electrode that can set the power semiconductor device in one of a forward conducting state and a blocking state when receiving a corresponding control signal from, for example, a driver unit.

[0004] Occasionally, such power semiconductor devices are further configured to conduct a reverse current between the two load terminals. For example, the reverse current can be conducted via a body diode of the device. In some cases, a dedicated diode region can be provided to enable such a reverse conducting state of the device. It is generally desirable to reduce the conduction losses in both the forward conducting state and the reverse conducting state of such a device. Summary of the Invention

[0005] According to an embodiment, a power semiconductor device includes a semiconductor body, a first load terminal structure disposed on a front side of the semiconductor body, and a second load terminal structure disposed on a rear side of the semiconductor body. The power semiconductor device is configured to control a load current between the first load terminal structure and the second load terminal structure by means of at least one transistor cell at least partially included in the semiconductor body and electrically connected to the first load terminal structure on one side and to a drift region of the semiconductor body on the other side, the drift region having a first conductivity type. The semiconductor body further includes: a transistor short region having a first conductivity type, wherein a transition between the transistor short region and the first load terminal structure forms a Schottky contact; and a separation region separating the transistor short region from the drift region and having a second conductivity type complementary to the first conductivity type.

[0006] According to a further embodiment, a reverse-conducting IGBT has a semiconductor body and a plurality of transistor cells implemented at least partially therein. The reverse-conducting IGBT further includes, within the semiconductor body and outside the transistor cells: a transistor short region having a first conductivity type and butt-jointed to the emitter terminal of the reverse-conducting IGBT, wherein a Schottky contact is formed at the transition between the transistor short region and the emitter terminal; and a separation region separating the transistor short region from the drift region of the reverse-conducting IGBT, the separation region having a second conductivity type complementary to the first conductivity type, and the drift region having the first conductivity type.

[0007] According to yet a further embodiment, a method of processing a power semiconductor device includes: providing a semiconductor body having a front side and a back side; providing a drift region having a first conductivity type within the semiconductor body; creating at least one transistor cell at the front side, wherein the transistor cell is at least partially included in the semiconductor body and electrically connected to the drift region; creating within the semiconductor body: a transistor short region disposed at the front side and having the first conductivity type, and a separation region separating the transistor short region from the drift region and having a second conductivity type complementary to the first conductivity type; and creating a first load terminal structure at the front side such that the first load terminal structure is electrically connected to the at least one transistor cell, and a Schottky contact is formed at the transition between the transistor short region and the first load terminal structure.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the drawings. Description of the Drawings

[0009] The parts in the various figures are not necessarily to scale; instead, emphasis is placed on illustrating the principles of the invention. Further, in the various figures, the same reference numerals denote corresponding parts. In the drawings:

[0010] Figure 1 A section of a vertical cross-section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated;

[0011] Figure 2 A section of a vertical cross-section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated;

[0012] Figure 3 A section of a vertical cross-section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated;

[0013] Figure 4Schematically and exemplarily illustrate a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; and

[0014] Figure 5 Schematically and exemplarily illustrate a section of a vertical cross-section of a power semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific embodiments in which the invention may be practiced are shown by way of illustration.

[0016] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "leading", "trailing", "beneath", "above", etc., may be used with reference to the orientation of the figure being described. Since the various parts of the embodiments may be positioned in many different orientations, the directional terms are for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0017] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not meant to be a limitation of the invention. For example, features illustrated or described as part of one embodiment may be used on or in combination with other embodiments to yield yet additional embodiments. It is intended that the invention include such modifications and variations. By using specific language to describe the examples, such specific language should not be construed as limiting the scope of the appended claims. The figures are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals in different figures where not otherwise stated.

[0018] As used in this specification, the term "horizontal" is intended to describe an orientation that is generally parallel to the horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, where the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0019] As used in this specification, the term "vertical" is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer. For example, the extension direction Z mentioned below can be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0020] In this specification, n-doping is referred to as "the first conduction type", and p-doping is referred to as "the second conduction type". Alternatively, the opposite doping relationship can be adopted, such that the first conduction type can be p-doping and the second conduction type can be n-doping.

[0021] Furthermore, in this specification, the expression "having the first (second) conduction type", which can be used to characterize a specific semiconductor region, is intended to describe that the corresponding semiconductor region has a net dopant concentration of the first (second) conduction type. This generally does not exclude the presence of dopants of complementary second (first) conductivity at a lower dopant concentration compared to the first (second) conduction type.

[0022] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection", and "electrically connected" are intended to describe the existence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, areas, parts, or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component. Further, in the context of this specification, the term "in contact" is intended to describe the existence of a direct physical connection between two elements of the corresponding semiconductor device; for example, the transition between two elements in contact may not include additional intermediate elements, etc.

[0023] In addition, in the context of this specification, if not otherwise stated, the term "electrically insulated" is used in its generally reasonable context and is thus intended to describe that two or more components are positioned separately from each other and there is no ohmic connection connecting those components. However, components that are electrically insulated from each other can nevertheless be coupled to each other, for example, mechanically and / or capacitively and / or inductively. By way of example, the two electrodes of a capacitor can be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, for example, by means of an insulating part, such as a dielectric.

[0024] The specific embodiments described in this specification relate to power semiconductor devices (such as power semiconductor transistors) having a strip cell configuration that can be used within a power converter or power supply, but are not limited thereto. Thus, in an embodiment, the semiconductor device is configured to carry a load current that will be fed to a load and / or provided by a power source accordingly. For example, the semiconductor device may include one or more active power semiconductor units, such as monolithically integrated diode units, and / or monolithically integrated transistor units, and / or monolithically integrated IGBT units, and / or monolithically integrated RC-IGBT units and / or their derivatives. Such diode units and / or such transistor units may be integrated in a power semiconductor module. A plurality of such units may constitute a cell field that is arranged together with the active pole region of the power semiconductor device.

[0025] As used in this specification, the term "power semiconductor device" is intended to describe a semiconductor device on a single chip having high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for use in high current and / or high voltage, where the high current is typically in the ampere range, for example up to tens or hundreds of amperes, and the high voltage is typically above 100V, more typically 600V and above, for example up to at least 6500V. For example, the processed semiconductor devices described below may be semiconductor devices having a strip cell configuration or a square or polygonal cell configuration, and may be configured to be employed as power components in low, medium, and / or high voltage applications.

[0026] For example, as used in this specification, the term "power semiconductor device" does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0027] Figures 1 to 5 Each of schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device 1 according to some embodiments. The following description generally refers to Figures 1 to 5 all of. Certain features of the exemplary embodiments will be explained in more detail with explicit reference to Figures 1 to 5 one or more of.

[0028] The illustrated cross-section is parallel to the plane defined by a first lateral direction X and a vertical direction Z. Each of the illustrated components of the power semiconductor device 1 may extend along a second lateral direction Y (not illustrated).

[0029] The power semiconductor device 1 includes a semiconductor body 10, for example based on silicon or silicon carbide. Other possible semiconductor materials are further mentioned below. The semiconductor body 10 is coupled to each of a first load terminal structure 11 and a second load terminal structure 12 of the power semiconductor device 1. For example, the power semiconductor device 1 is an IGBT, such as a reverse-conducting IGBT (RC-IGBT), and the first load terminal structure 11 is or includes the emitter terminal of the IGBT. The second load terminal structure 12 may constitute or include, for example, the collector terminal of the IGBT. For example, the first load terminal structure 11 includes at least one first metallization 110, 111, 112, and the second load terminal structure 12 may include at least one second metallization.

[0030] The power semiconductor device 1 may exhibit a vertical assembly, according to which the semiconductor body 10 is sandwiched between the first load terminal structure 11 and the second load terminal structure 12. The first load terminal structure 11 may be arranged on the front side 10-1 of the semiconductor body 10, and the second load terminal structure 12 may be arranged on the rear side 10-2 of the semiconductor body 10. Accordingly, the at least one first metallization 110, 111, 112 of the first load terminal structure 11 may be front-side metallizations, and the at least one second metallization of the second load terminal structure 12 may be rear-side metallizations. For example, by means of these terminal structures 11 and 12, the power semiconductor device 1 receives and outputs load current. Accordingly, at least one of these terminal structures 11 and 12, for example the first load terminal structure 11, may include one or more bonding pads (not shown) such that, for example, it docks with a plurality of bonding wires.

[0031] The semiconductor body 10 includes a drift region 100 having dopants of a first conductivity type. For example, the drift region 100 is an n - doped region. Further, the dopant concentration and the total extension of the drift region 100 along the vertical direction Z may substantially determine the blocking capability, i.e., the maximum blocking voltage of the power semiconductor device 1. For example, the blocking voltage is greater than 500 V, greater than 1 kV, or even greater than 3 kV.

[0032] Further, one or more transistor cells 130 are arranged on the front side 10-1. The at least one transistor cell 130 may be at least partially included in the semiconductor body 10 and may be electrically connected to the first load terminal structure 11 on one side and to the drift region 100 on the other side. The power semiconductor device 1 may be configured to control the current flow between the first load terminal structure 11 and the second load terminal structure 12 by means of the at least one transistor cell 130. For example, the first cell 130 may include a MOS control head for controlling the current flow.

[0033] As exemplarily depicted in Figures 2 to 5 each transistor cell 130 may include at least one source region 104, which is electrically connected to the first load terminal structure 11. The source region 104 may be included in the semiconductor body 10 and may have a net dopant concentration of a first conductivity type (e.g., n-type). For example, the source region 104 includes dopants of a first conductivity type (such as n-type) at a higher dopant concentration than the drift region 100. In other embodiments, the source region 104 may be formed, for example, by means of a metal in contact with the semiconductor body 10, such as by forming a metal-to-semiconductor transition at the transition from a part of the first load terminal structure 11 and the semiconductor body 10. The semiconductor body 10 may be configured to receive and / or output load current from and / or to the first load terminal structure 11 via the source region 104.

[0034] Furthermore, each transistor cell 130 may include a channel region 101 (also referred to as the body region 101), which is included in the semiconductor body 10. The channel region 101 may have a net dopant concentration of a second conductivity type complementary to the first conductivity type. For example, if the drift region 100 and the source region 104 each have n-type dopants, the channel region 101 has p-type dopants. The channel region 101 may be arranged to isolate the source region 104 from the drift region 100. The transistor cell 130 may be configured to induce a conduction channel for dopants of the first conductivity type within the channel region 101.

[0035] In an embodiment, the channel region 101 is electrically connected to the first load terminal structure 11 (see Figures 2 to 5 ). For example, the channel region 101 may include a first port region 1010 having a second conductivity type, which is at a higher dopant concentration than the rest of the channel region 101, wherein the first port region is in contact with a first part 110 of the first load terminal structure 11. For example, an ohmic contact is established between the first port region 1010 and the first part 110 of the first load terminal structure 11.

[0036] For example, a pn junction is formed at the transition between the channel region 101 and the drift region 100. The pn junction may be configured to block a blocking voltage in the blocking state of the power semiconductor device 1.

[0037] To control the flow of load current through the power semiconductor device 1 between the first load terminal structure 11 and the second load terminal structure 12, each transistor cell 130 may further include a control electrode 1310 (also referred to as a gate electrode), which is electrically connected to a control terminal (also referred to as a gate terminal; not shown) of the power semiconductor device 1. The control electrode 1310 may be arranged and configured to induce the transfer channel within the channel region 101 such that the transfer channel extends from the source region 104 to the drift region 100 within the channel region 101. For example, the control electrode 1310 is configured to induce the transfer channel depending on a control signal (such as a voltage signal) provided to the control electrode 1310 from outside the power semiconductor device 1. For example, the control signal may be provided via a gate terminal (not shown) of the power semiconductor device 1.

[0038] In an embodiment, the at least one control electrode 1310 extends at least partially within a trench 131 formed in the semiconductor body 10. For example, the trench 131 includes an insulating structure 1311 that insulates the control electrode 1310 from the channel region 101. The insulating structure 1311 may include a gate dielectric, such as an oxide, for example, silicon dioxide. For example, such a trench 131 extends substantially along the vertical direction Z from the front side 10-1 into the semiconductor body 10, as Figures 2 to 5 depicted.

[0039] Contrary to the at least one transistor cell 130 arranged on the front side 10-1, at least one first backside emitter region 105 is provided in the semiconductor body 10 on the back side 10-2. The first backside emitter region 105 is electrically connected to the second load terminal structure 12 (such as the backside metallization 12) and includes a dopant of a second conductivity type. For example, if the drift region 100 is n-doped, such as in the case of an n-channel IGBT 1, the first backside emitter region 105 may be implemented as a p + -doped semiconductor region. The first backside emitter region 105 may be configured to inject charge carriers of the second conductivity type into the drift region 100 in the forward conduction state of the power semiconductor device 1. Thus, a bipolar forward conduction mode can be achieved, as is well known from IGBTs.

[0040] In an embodiment, the lateral extent of the first backside emitter region 105 totals at least 20% of the vertical extent of the semiconductor body 10 (i.e., the total chip thickness measured along the vertical direction Z), such as at least 50%, or even 100%.

[0041] The first rear-side emitter region 105 and the at least one transistor cell 130 exhibit a first common lateral extension range LX1 along a first lateral direction X. In other words, there is a finite lateral overlap LX1 along the first lateral direction X between the transistor cell 130 disposed on the front side 10-1 of the semiconductor body 10 and the first rear-side emitter region 105 disposed on the rear side 10-2. For example, the first common lateral extension range LX1 amounts to at least 10%, at least 30%, at least 50%, or even 100% of the lateral extension of the transistor cell 130 along the first lateral direction X. For example, in the case where there are multiple transistor cells 130 (see Figures 2 - 5 ) and / or multiple first rear-side emitter regions 105 provided in the semiconductor device 1, the sum of the respective first common lateral extension ranges LX1 of each transistor cell 130 and the first rear-side emitter region 105 can amount to at least 10%, at least 30%, or even at least 50% of the total lateral extension of all the transistor cells 130 along the first lateral direction X.

[0042] Furthermore, in addition to the at least one first rear-side emitter region 105, at least one second rear-side emitter region 106 can be provided in the semiconductor body 10. The second rear-side emitter region 106 is electrically connected to the second load terminal structure 12 and has a net dopant concentration of a first conductivity type. For example, the second rear-side emitter region 106 can allow the reverse current capability of the power semiconductor device 1. In an embodiment, the power semiconductor device 1 is a reverse-conducting IGBT (RC-IGBT), where the at least one second rear-side emitter region 106 is a short region, such as an n short region, disposed on the rear side 10-2 to allow the reverse-conducting diode operation of the RC-IGBT 1.

[0043] For example, the rear side 10-2 of the semiconductor body 10 exhibits one or more first rear-side emitter regions 105 acting as an "IGBT region" and one or more second rear-side emitter regions 106 acting as a "diode region", such that both the IGBT operation of the power semiconductor device 1 in the forward conduction state and the diode operation in the reverse conduction state are allowed.

[0044] As Figures 1 to 5As illustrated in each of, the semiconductor body 10 further includes a transistor short region 107 of a first conductivity type, wherein a Schottky contact 108 is formed at the transition between the transistor short region 107 and the first load terminal structure 11. For example, the transistor short region 107 contacts a second part 112 of the first load terminal structure 11, which may include a metal, such as at least one of the following: aluminum (Al), silver (Ag), gold (Au), palladium (Pd), platinum (Pt), nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), or a silicide, such as platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), molybdenum silicide (MoSi), or manganese silicide (MnSi). In the vicinity of the second part 112 of the first load terminal structure 11, the transistor short region 107 may include, for example, an n-type dopant with a dopant concentration in the range from 10 13 cm -3 to 10 17 cm -3 . The Schottky contact 108 can thus be formed as a metal-to-semiconductor transition between the second part 112 and the transistor short region 107.

[0045] The Schottky contact 108 can be configured to reduce the emitter efficiency of the channel region 101 during the reverse conduction operation of the power semiconductor device 1, which is accomplished by providing the possibility that charge carriers of the first conductivity type flow to the first load terminal structure 11 without causing injection of charge carriers of the second conductivity type from the channel region 101 into the drift region 100.

[0046] In an embodiment according to Figures 2 to 5 , the power semiconductor device 1 includes at least two transistor cells 130, wherein the transistor short region 107 is arranged outside the at least two transistor cells 130 and laterally in the middle of the at least two transistor cells 130.

[0047] For example, the transistor short region 107 is arranged to be laterally adjacent to the trench 131 of the at least one transistor cell 130 and in contact with the trench 131. The transistor short region 107 can also be arranged to be laterally adjacent to one trench 131 of each of two adjacent transistor cells 130 and in contact with the one trench 131 (see Figures 2 to 5 ).

[0048] In an embodiment, the transistor short region 107 can be laterally defined by at least two trenches 131, wherein the lateral distance of the trenches 131 is less than the depth of at least one of the trenches 131.

[0049] The semiconductor body 10 further includes a separation region 109 that separates the transistor short region 107 from the drift region 100 and has a second conductivity type complementary to the first conductivity type. For example, the separation region 109 includes dopants of the second conductivity type having a dopant concentration in the range from 10 15 cm -3 to 10 18 cm -3 .

[0050] A transition between the separation region 109 and the drift region 100 can form a pn junction 103-1. For example, due to this pn junction 103-1, a relatively high blocking capability of the power semiconductor device 1 can be ensured.

[0051] In an embodiment, at least a portion of the separation region 109 is arranged to be laterally adjacent to and in contact with a trench 131, such as the gate trench 131 of the power semiconductor device 1. For example, the separation region 109 extends within the semiconductor body 10 (along the vertical direction Z) at least as deep as ½ of the depth of the trench 131, such as at least as deep as the depth of the trench 131, or even at least as deep as 4 / 3 times the depth of the trench 131.

[0052] The separation region 109 can also be arranged to be laterally adjacent to and in contact with one trench 131 of each of two adjacent transistor cells 130, as Figures 2 to 5 illustrated.

[0053] Within the transistor short region 107, the concentration of the dopants of the first conductivity type can be reduced by at least a factor of 10, such as at least a factor of 100, or even at least a factor of 1000, along the direction pointing from the separation region 109 to the first load terminal structure 11 (such as along the direction opposite to the vertical direction Z).

[0054] For example, the transistor short region 107 includes a first portion 107-1 that abuts the first load terminal structure 11 and a second portion 107-2 that abuts the separation region 109. The concentration of the dopants of the first conductivity type in the first portion 107-1 can be at most 1 / 10, such as at most 1 / 100, or even at most 1 / 1000, of the concentration of the dopants of the first conductivity type in the second portion 107-2.

[0055] As Figure 3 illustrated, the semiconductor body 10 can further include a contact region 1014 that has the second conductivity type and is arranged to be in contact with each of the first load terminal structure 11 and the transistor short region 107. The contact region 1014 can exhibit dopants of the second conductivity type in a range from 10 17cm -3 to 10 20 cm -3 in concentration. For example, the contact region 1014 may be a p + -doped semiconductor region.

[0056] In an embodiment, the contact region 1014 is arranged to contact the trench 131. Further, the contact region 1014 may be separated from the isolation region 109 by the transistor short region 107 (see Figure 3 ).

[0057] The transition between the contact region 1014 and the transistor short region 107 may form a pn junction. This pn junction may provide an additional path (in addition to the Schottky contact 108) for charge carriers of the second conductivity type to flow out of the semiconductor body 10 into the first load terminal structure 11, for example when the power semiconductor device 1 is switched.

[0058] Referring to Figures 2 to 5 , the power semiconductor device 1 may further include a diode emitter region 102, which is arranged within the semiconductor body 10, outside the at least one transistor cell 130 and has the second conductivity type. For example, the diode emitter region 102 takes the form of a p-well arranged on the front side 10-1. The diode emitter region 102 is electrically connected to the first load terminal structure 11. The transition between the diode emitter region 102 and the drift region 100 forms a pn junction 103.

[0059] For example, the diode emitter region 102 may be arranged separately from the channel region 101. In another embodiment, in which the power semiconductor device 1 may exhibit a strip cell configuration, the diode emitter region 102 may be arranged within the same mesa and in contact with the channel region 101.

[0060] In an embodiment, the diode emitter region 102 exhibits a second common lateral extent LX2 with the second backside emitter region 106. In other words, there is a finite lateral overlap LX2 along the first lateral direction X between the diode emitter region 102 disposed on the front side 10-1 and the second backside emitter region 106 disposed on the back side 10-2. For example, the second common lateral extent LX2 amounts to at least 10%, at least 30%, at least 50%, or even 100% of the lateral extent of the diode emitter region 102 along the first lateral direction X. For example, in the case (not shown) where there are multiple diode emitter regions 102 and / or multiple second backside emitter regions 106 provided in the semiconductor device 1, the sum of the respective second common lateral extents LX2 of each diode emitter region 102 with the second backside emitter region 106 can amount to at least 10%, at least 30%, or even at least 50% of the sum of the total lateral extents of all diode emitter regions 102 along the first lateral direction X.

[0061] The diode emitter region 102 can be arranged and configured to inject charge carriers of a second conductivity type into the drift region 100 during the reverse-conduction operation of the power semiconductor device 1. For example, the injection of the charge carriers of the second conductivity type can occur substantially independently of the switching state of the at least one transistor cell 130, i.e., independently of whether a conduction channel is induced in the channel region 101 by the control electrode 1310.

[0062] In an embodiment, as Figures 2 to 5 shown, at least a portion of the diode emitter region 102 is arranged to be laterally adjacent to and in contact with the trench 131. For example, as shown in the vertical cross-section in Figures 2 to 4 , the diode emitter region 102 can be laterally defined by at least two trenches 131, similar to the channel region 101 of the transistor cell 130. The one or more trenches 131 arranged adjacent to the diode emitter region 102 can include the electrode 1310. The electrode 1310 can be electrically connected to the gate terminal of the power semiconductor device 1 or to the first load terminal structure 11, as schematically illustrated in Figure 2 .

[0063] In Figure 5 the embodiment illustrated, the diode emitter region 102 has a greater lateral extent than each of the transistor cells 130. For example, the lateral extent W1 of the diode emitter region 102 amounts to at least 3 times, such as at least 5 times, or even at least 10 times the lateral extent W2 of the at least one transistor cell 130.

[0064] As Figure 2 and 3As depicted, in addition to the diode emitter region 102, a floating region 102-1 having a second conductivity type may be provided within the semiconductor body 10. For example, the floating region 102-1 may be separated from the diode emitter region 102 by a trench 131. Further, the floating region 102-1 may be insulated from the first load terminal structure 11 by an insulating region 1112 (such as an oxide layer).

[0065] In Figure 4 an embodiment, instead of the floating region 102-1, an additional diode emitter region 102 is provided, and the additional diode emitter region 102 is electrically connected to the first load terminal structure 11.

[0066] The diode emitter region 102 may include a second port region 1020 arranged to contact the first load terminal structure 11, wherein the concentration of the dopant of the second conductivity type within the second port region 1020 is at least 10 times, such as at least 100 times, or even at least 1000 times, the concentration of the dopant of the second conductivity type within the remainder of the diode emitter region 102. For example, the second port region 1020 contacts the third portion 111 of the first load terminal structure 11 (see Figures 2 to 5 ). For example, an ohmic contact is established at the transition between the second port region 1020 and the third portion 111 of the load terminal structure 11.

[0067] According to an embodiment, the power semiconductor device 1 is a reverse conducting IGBT (RC-IGBT) having a transistor cell field 13 that includes a plurality of transistor cells 130 and a plurality of transistor short regions 107 arranged within the transistor cell field 13 and outside the transistor cells 130 (see Figures 2 to 5 ). The first load terminal 11 may be the emitter terminal 11 of the RC-IGBT 1. The semiconductor body 10 of the reverse conducting IGBT 1 may further include a plurality of separation regions 109, each separation region 109 separating the transistor short region 107 from the drift region 100 of the reverse conducting IGBT 1, as described above. Further, one or more diode emitter regions 102 may be provided within the semiconductor body 10.

[0068] Refer to Figures 2 to 5, the semiconductor body 10 may further include a buffer layer 100-1 (commonly also referred to as a field stop layer), the buffer layer 100-1 having a first conductivity type, being at a higher concentration than the drift region 100 and separating the drift region 100 from at least the first backside emitter region 105. For example, the maximum doping concentration of the buffer region 100-1 is at least 10 times, such as at least 100 times, or even at least 1000 times, the doping concentration of the drift region 100. Further, the buffer layer 100-1 may be arranged and configured to also separate the drift region 100 from the second backside emitter region 106.

[0069] In a variant, the semiconductor body 10 may include an intermediate region (not shown), the intermediate region having a first conductivity type, being at a higher doping concentration than the drift region 100 and extending beneath at least one of the transistor cell 130, the diode emitter region 102, and the isolation region 109, such that at least a portion of the drift region 100 extends beneath the intermediate region. For example, the doping concentration of the intermediate region is at least 10 times, such as at least 100 times, or even at least 1000 times, the doping concentration of the drift region 100.

[0070] Further, referring to Figures 2 to 5 , one or more insulating blocks 1101, 1111, 1121 may be provided on the front side 10-1 of the semiconductor body 10, adjacent to the trench 131. For example, the insulating blocks 1101, 1111, 1121 may include a dielectric material, such as an oxide, for example silicon oxide. The insulating blocks 1101, 1111, 1121 may also extend above the trench 131 and cover the electrode 1310.

[0071] According to another embodiment, a method of processing a power semiconductor device 1 is presented. The method may include the following steps: providing a semiconductor body 10 having a front side 10-1 and a back side 10-2; providing a drift region 100 having a first conductivity type within the semiconductor body 10; creating at least one transistor cell 130 on the front side 10-1, wherein the transistor cell is at least partially included in the semiconductor body 10 and electrically connected to the drift region 100; creating within the semiconductor body 10: a transistor short region 107 disposed on the front side 10-1 and having a first conductivity type; and an isolation region 109 that separates the transistor short region 107 from the drift region 100 and has a second conductivity type complementary to the first conductivity type; and creating a first load terminal structure 11 on the front side 10-1 such that the first load terminal structure 11 is electrically connected to the at least one transistor cell 130, and forming a Schottky contact 108 at the transition between the transistor short region 107 and the first load terminal structure 11.

[0072] Exemplary ways of implementing the methods presented above may correspond to embodiments of the power semiconductor device 1 as described above and as elaborated in the dependent claims. In this context, reference is made to the foregoing.

[0073] The embodiments described above include the recognition that in power semiconductor devices with reverse-conducting capabilities, such as RC-IGBTs, the performance in the reverse-conducting mode may depend on the gate-emitter voltage provided to the gate electrode of the transistor cell. For example, if a conduction channel is provided through the gate electrode, the emitter efficiency of the body diode may be reduced, thereby reducing the charge carrier density and increasing the conduction losses in the reverse-conducting mode. It may thus be desirable to make the reverse-conducting behavior of the power semiconductor device independent of the gate-emitter voltage currently provided to the gate electrode.

[0074] According to one or more embodiments, a power semiconductor device, such as an RC-IGBT, has a plurality of transistor cells and one or more transistor short regions arranged outside the transistor cells. The at least one transistor short region has a net dopant concentration of a first conductivity type, which is the conductivity type that also predominates in the drift region of the device. A Schottky contact is formed at the transition between the transistor short region and a first load terminal structure, such as the emitter terminal in the case of an RC-IGBT. The Schottky contact can be configured to reduce the emitter efficiency of the channel region (or body region) during the reverse-conducting operation of the power semiconductor device, which is accomplished by providing the possibility that charge carriers flow to the load terminal structure without causing injection of charge carriers of a second conductivity type from the channel region into the drift region.

[0075] Furthermore, a separation region of a second conductivity type is provided, which separates the transistor short region from the drift region. The separation region can be configured to build a blocking pn structure into the drift region, thereby ensuring a relatively high blocking capability of the power semiconductor device.

[0076] According to one or more additional embodiments, the power semiconductor device may include a diode emitter region, which is arranged outside the at least one transistor cell and has a second conductivity type, wherein the diode emitter region is electrically connected to the first load terminal structure. The diode emitter region can be configured to inject charge carriers of a second conductivity type into the drift region during the reverse-conducting operation of the power semiconductor device. For example, the injection of charge carriers of a second conductivity type may occur substantially independently of the switching state of the at least one transistor cell, i.e., independently of whether the control electrode induces a conduction channel in the channel region.

[0077] In the foregoing, embodiments of a method for processing semiconductor devices were explained. For example, these semiconductor devices are based on silicon (Si). Accordingly, the single-crystal semiconductor region or layer, such as the semiconductor body 10, the drift region 100, the source region 104, and the channel region 101 of the exemplary embodiments, may be a single-crystal Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be employed.

[0078] However, it should be understood that the semiconductor body 10 and components, such as regions 100, 100-1, 102, 104, 107, and 109, may be made of any semiconductor material suitable for fabricating semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group-IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The previously mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-silicon germanium heterojunction semiconductor materials. For power semiconductor device applications, currently mainly Si, SiC, GaAs, and GaN materials are used.

[0079] Spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding device in addition to those depicted in the figures. Further, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout this description, like terms refer to like elements.

[0080] As used herein, the terms "having", "containing", "including", "comprising", "exhibiting", and the like are open-ended terms that indicate the presence of the stated element or feature, but do not preclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular unless the context clearly indicates otherwise.

[0081] Considering the above scope of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A power semiconductor device, which includes a semiconductor body, a first load terminal structure arranged on the front side of the semiconductor body, and a second load terminal structure arranged on the rear side of the semiconductor body, and is configured to control a load current between the first load terminal structure and the second load terminal structure by means of at least one transistor cell, the at least one transistor cell being at least partially included in the semiconductor body and being electrically connected to the first load terminal structure on one side and to the drift region of the semiconductor body on the other side, the drift region having a first conductivity type, wherein the semiconductor body further includes: a transistor short region of the first conductivity type arranged outside the at least one transistor cell, wherein a transition between the transistor short region and the first load terminal structure forms a Schottky contact outside the at least one transistor cell; a separation region that separates the transistor short region from the drift region outside the at least one transistor cell, the separation region having a second conductivity type complementary to the first conductivity type; and a diode emitter region of the second conductivity type, which is arranged outside the at least one transistor cell and is electrically connected to the first load terminal structure, wherein a transition between the diode emitter region and the drift region forms a pn junction, wherein the transistor short region is arranged to be laterally adjacent to and in contact with a trench of the at least one transistor cell, wherein the transistor short region is laterally defined by at least two trenches, wherein a lateral distance between the at least two trenches is less than a depth of at least one of the at least two trenches.

2. The power semiconductor device according to claim 1, wherein the transistor short region includes a first part docked to the first load terminal structure and a second part docked to the separation region, and wherein a concentration of a dopant of the first conductivity type in the first part is at most 1 / 10 of a concentration of the dopant of the first conductivity type in the second part.

3. The power semiconductor device according to claim 1, wherein, In the transistor short region, the concentration of the dopant of the first conductivity type decreases to at least 1 / 10 along a direction from the separation region towards the first load terminal structure.

4. The power semiconductor device according to claim 1, wherein the power semiconductor device includes at least two transistor cells, and wherein the transistor short region is arranged outside the at least two transistor cells and is laterally in the middle of the at least two transistor cells.

5. The power semiconductor device according to claim 1, wherein the semiconductor body includes a first rear-side emitter region of the second conductivity type, the first rear-side emitter region being arranged to be in electrical contact with the second load terminal structure.

6. The power semiconductor device according to claim 5, wherein the at least one transistor cell exhibits at least a common lateral extent with the first rear-side emitter region.

7. The power semiconductor device according to claim 1, wherein the semiconductor body includes a second rear-side emitter region of the first conductivity type, the second rear-side emitter region being arranged to be in electrical contact with the second load terminal structure.

8. The power semiconductor device according to claim 7, wherein the diode emitter region has at least a common lateral extent with the second backside emitter region.

9. The power semiconductor device according to claim 7, wherein the lateral extent of the diode emitter region is at least three times the lateral extent of the at least one transistor cell.

10. The power semiconductor device according to claim 7, wherein the diode emitter region includes a second port region arranged to contact the first load terminal structure, and wherein the concentration of the dopant of the second conductivity type within the second port region is at least ten times the concentration of the dopant of the second conductivity type within the remainder of the diode emitter region.

11. The power semiconductor device according to claim 1, wherein at least a portion of the isolation region is arranged to be laterally adjacent to and in contact with the at least two trenches.

12. The power semiconductor device according to claim 11, wherein the isolation region extends within the semiconductor body at least as deep as half the depth of the at least two trenches.

13. The power semiconductor device according to claim 1, wherein at least a portion of the diode emitter region is arranged to be laterally adjacent to and in contact with a trench, and wherein the trench includes an electrode.

14. The power semiconductor device according to claim 13, wherein the electrode is electrically connected to the first load terminal structure.

15. The power semiconductor device according to claim 1, wherein the semiconductor body further includes a contact region of the second conductivity type arranged to contact each of the first load terminal structure and the transistor short region.

16. The power semiconductor device according to claim 1, wherein the power semiconductor device has a reverse current capability.

17. A reverse-conducting IGBT comprising a semiconductor body and a plurality of transistor cells at least partially implemented within the semiconductor body, the reverse-conducting IGBT further including within the semiconductor body and external to the transistor cells: A transistor short region of a first conductivity type that abuts the emitter terminal of the reverse-conducting IGBT, wherein a transition between the transistor short region and the emitter terminal forms a Schottky contact outside the plurality of transistor cells; And An isolation region that separates the transistor short region outside the plurality of transistor cells from the drift region of the reverse-conducting IGBT, the isolation region having a second conductivity type complementary to the first conductivity type, and the drift region having the first conductivity type, Wherein the transistor short region is arranged to be laterally adjacent to and in contact with the trenches of the plurality of transistor cells, Wherein the transistor short region is laterally defined by at least two trenches, Wherein the lateral distance between the at least two trenches is less than the depth of at least one of the at least two trenches.

18. A method of processing a power semiconductor device, the method comprising: Providing a semiconductor body having a front side and a back side; Providing a drift region of a first conductivity type within the semiconductor body; At least one transistor cell is formed on the front side, wherein the at least one transistor cell is at least partially included in a semiconductor body and is electrically connected to a drift region; Formed within the semiconductor body are: A transistor short region of a first conductivity type, which is arranged on the front side and outside the at least one transistor cell; And A separation region, which separates the transistor short region from the drift region outside the at least one transistor cell, the separation region having a second conductivity type complementary to the first conductivity type; And A first load terminal structure is formed on the front side such that the first load terminal structure is electrically connected to the at least one transistor cell, and a Schottky contact is formed outside the at least one transistor cell at a transition between the transistor short region and the first load terminal structure, wherein the transistor short region is arranged to be laterally adjacent to and in contact with a trench of the at least one transistor cell, wherein the transistor short region is laterally defined by at least two trenches, wherein a lateral distance between the at least two trenches is less than a depth of at least one of the at least two trenches.

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