Drive interlock circuit of intelligent power module and intelligent power module

Abstract

The invention relates to power control technology, and proposes a driving interlocking circuit of an intelligent power module and an intelligent power module. The interlocking circuit is an interface circuit composed of multiple transistor switch circuits, and the interlocking circuit includes an input end, an output end, and an interlocking signal input end; the input end is used to connect to the first control end of a bridge arm; the output end is used to connect to the first power end; the interlocking signal input end is used to connect to the second control end of the above bridge arm; the potential signal of the input end is transmitted to the output end through the interlocking circuit; when the input end and the interlocking signal input end input a high level at the same time, the interlocking circuit outputs a low level through the output end. The driving interlocking circuit makes it impossible for the driving signal of the same bridge arm to be high at the same time, that is, the upper and lower IGBT tubes of the same bridge arm cannot be turned on at the same time, avoiding the short circuit fault caused by the upper and lower IGBT tubes of the same bridge arm being directly turned on.

Description

Technical Field

[0001] The present application relates to power control technology, and in particular to a drive interlocking circuit of an intelligent power module and an intelligent power module. Background Art

[0002] Intelligent power module (IPM Intelligent Power Module) is an advanced power switching device, which has the advantages of high current density, low saturation voltage and high voltage resistance of GTR (high power transistor), and the advantages of high input impedance, high switching frequency and low driving power of MOSFET (field effect transistor). In addition, the intelligent power module integrates logic, control, detection and protection circuits, which is easy to use. It not only reduces the volume and development time of the system, but also greatly enhances the reliability of the system. It adapts to the development direction of today's power devices - modularization, composite and power integrated circuit (PIC), and has been more and more widely used in the field of power electronics.

[0003] At present, there are mostly two driving methods for intelligent power modules. One is that the microcontroller unit (MCU) directly transmits the driving signal to the intelligent power module. Although this driving method is simple, it cannot achieve the driving signal interlocking function; the other is to use an isolated optical coupler to transmit the driving signal, which can achieve the driving signal interlocking function, but it is used under the condition that the signal does not need to be isolated, and the cost is high. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a driving interlocking circuit of an intelligent power module and an intelligent power module.

[0005] In the first aspect, the present application provides a driving interlock circuit of an intelligent power module, the interlock circuit comprising a plurality of transistor switching circuits, the interlock circuit comprising an input end, an output end and an interlock signal input end; the input end is used to connect to a first control end of a bridge arm; the output end is used to connect to a first power end; the interlock signal input end is used to connect to the second control end of the above-mentioned bridge arm; the potential signal of the input end is transmitted to the output end via the interlock circuit; when a high level is input at the input end and the interlock signal input end at the same time, the interlock circuit outputs a low level through the output end.

[0006] According to one embodiment of the present application, the interlock circuit includes a first switch circuit, a second switch circuit and a third switch circuit; the first control electrode of the first switch circuit is connected to the input end, and the first load electrode of the first switch circuit is used to be connected to the second switch circuit; the second control electrode of the second switch circuit is connected to the first load electrode, and the second load electrode of the second switch circuit is connected to the output end; the third control electrode of the third switch circuit is connected to the interlock signal input end, and the third load electrode of the third switch circuit is used to be connected to the second load electrode and the output end.

[0007] According to an embodiment of the present application, the third switch circuit has a polarity opposite to that of the first switch circuit and the second switch circuit.

[0008] According to an embodiment of the present application, the first switch circuit is turned on according to a high level signal input to the first control electrode, the first switch circuit is turned on to make the second control electrode low level, and the second switch circuit is turned off; or,

[0009] The first switch circuit is turned off according to the low level signal input by the first control electrode. When the first switch circuit is turned off, the second control electrode is connected to a high level through the first load electrode, and the second switch circuit is turned on.

[0010] According to an embodiment of the present application, the third switch circuit is turned on according to the low level signal input by the third control electrode, and when the second switch circuit is turned off, the third switch circuit outputs a high level signal to the output end, or when the second switch circuit is turned on, the third switch circuit outputs a low level signal to the output end; or,

[0011] The third switch circuit is disconnected according to the high level signal input to the third control electrode. When the second switch circuit is disconnected, the third switch circuit outputs a low level signal to the output end, or when the second switch circuit is turned on, the third switch circuit outputs a low level signal to the output end.

[0012] According to an embodiment of the present application, the first switch circuit and the second switch circuit are NPN type electronic switch circuits; and the third switch circuit is a PNP type electronic switch circuit.

[0013] According to an embodiment of the present application, the second switch circuit is connected in series with a load loop of the third switch circuit.

[0014] According to an embodiment of the present application, both the first switch circuit and the second switch circuit are provided with a voltage dividing resistor.

[0015] According to an embodiment of the present application, the first switch circuit, the second switch circuit and the third switch circuit are all provided with a current limiting resistor located at a control electrode.

[0016] According to an embodiment of the present application, both the first switch circuit and the third switch circuit are provided with a pull-up resistor.

[0017] According to an embodiment of the present application, the voltage of the switch power supply of the first switch circuit and the third switch circuit is higher than the voltage of the input terminal and the interlock signal input terminal.

[0018] According to an embodiment of the present application, a voltage dividing resistor is connected in parallel to the second switch circuit.

[0019] According to an embodiment of the present application, the third control electrode of the third switch circuit is connected to the switching power supply via a pull-up resistor, and the pull-up resistor is connected in series with the current limiting resistor on the third control electrode.

[0020] According to an embodiment of the present application, the switching power supply of the first switching circuit is grounded through a current limiting resistor and a voltage dividing resistor on a control electrode of the second switching circuit.

[0021] In a second aspect, the present application provides an intelligent power module, each bridge arm having a first control end and a second control end; wherein the first control end and the second control end of at least one bridge arm are both provided with a drive interlocking circuit of the intelligent power module as described above.

[0022] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0023] In the drive interlock circuit provided in the embodiment of the present application, the drive signal of the same bridge arm cannot be at a high level at the same time, that is, the upper and lower IGBT tubes of the same bridge arm cannot be turned on at the same time, thereby avoiding the short-circuit fault caused by the direct conduction of the upper and lower IGBT tubes of the same bridge arm, and improving the safety and reliability of the power circuit; and the circuit uses fewer electronic components and takes transistors as the core device, which is not only low in cost but also simple in structure and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 A schematic diagram of a drive interlock circuit provided in an embodiment of the present application.

[0027] Figure 2 A circuit diagram of an intelligent power module provided in an embodiment of the present application.

[0028] 1. interlock circuit; 11. input terminal; 12. output terminal; 13. interlock signal input terminal; 14. first switch circuit; 141. first control electrode; 142. first load electrode; 143. first emitter; Q1. first transistor; 15. second switch circuit; 151. second control electrode; 152. second load electrode; 153. second emitter; Q2. second transistor; 16. third switch circuit; 161. third control electrode; 162. third load electrode; 163. third emitter; Q3. third transistor;

[0029] 2. Micro control unit; 21. First control terminal; 22. Second control terminal;

[0030] 3. Intelligent power module; 31. First power terminal; 32. Second power terminal. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] Figure 1 A schematic diagram of a driving interlocking circuit provided in an embodiment of the present application. As shown in the figure, the embodiment of the present application first provides a driving interlocking circuit of an intelligent power module, the interlocking circuit 1 mainly includes a plurality of transistor switch circuits, and the interlocking circuit 1 mainly includes an input terminal 11, an output terminal 12 and an interlocking signal input terminal 13; the input terminal 11 is used to connect a first control terminal 21 of a bridge arm. The output terminal 12 is used to connect to the first power terminal 31. The interlocking signal input terminal 13 is used to connect the second control terminal 22 of the above-mentioned bridge arm; the control signal of the input terminal 11 is transmitted to the output terminal 12 via the interlocking circuit; when the input terminal 11 and the interlocking signal input terminal 13 are simultaneously input with a high level, the interlocking circuit outputs a low level through the output terminal 12.

[0033] The embodiment of the present invention proposes a drive interlock circuit, which uses fewer electronic components and takes transistors as core components. It can not only avoid short-circuit faults caused by simultaneous conduction of upper and lower IGBT tubes of the same bridge arm inside the intelligent power module 3, but also improve the safety and reliability of the power circuit, and has low cost, simple structure, and is easy to implement.

[0034] According to an embodiment of the present application, the interlock circuit includes a first switch circuit 14, a second switch circuit 15, and a third switch circuit 16; the first control electrode 141 of the first switch circuit 14 is connected to the input terminal 11, the first load electrode 142 of the first switch circuit 14 is used to connect to the second switch circuit 15, and the first emitter 143 is grounded. The second control electrode 151 of the second switch circuit 15 is connected to the first load electrode 142, the second load electrode 152 of the second switch circuit 15 is connected to the output terminal 12, and the second emitter 153 is grounded. The third control electrode 161 of the third switch circuit 16 is connected to the interlock signal input terminal 13, the third load electrode 162 of the third switch circuit 16 is used to connect to the second load electrode 152 and the output terminal 12, and the third emitter 163 is connected to the switch power supply through the pull-up resistor R8.

[0035] The third switch circuit 16 has opposite polarity to the first switch circuit 14 and the second switch circuit 15. In a specific exemplary embodiment, the first switch circuit 14 and the second switch circuit 15 are selected as NPN type electronic switch circuits; the third switch circuit 16 is selected as PNP type electronic switch circuit.

[0036] Among them, the first switch circuit 14 is turned on according to the high-level signal input by the first control electrode 141, and the first switch circuit 14 is turned on to make the second control electrode 151 at a low level, and the second switch circuit 15 is disconnected; or, the first switch circuit 14 is cut off according to the low-level signal input by the first control electrode 141, and the first switch circuit 14 is cut off, then the second control electrode 151 is connected to a high level through the first load electrode 142, and the second switch circuit 15 is turned on.

[0037] According to one embodiment of the present application, the third switch circuit 16 is turned on according to a low-level signal input by the third control electrode 161, and when the second switch circuit 15 is disconnected, the third switch circuit 16 outputs a high-level signal to the output terminal 12, or when the second switch circuit 15 is turned on, the third switch circuit 16 outputs a low-level signal to the output terminal 12; or, the third switch circuit 16 is turned off according to a high-level signal input by the third control electrode 161, and when the second switch circuit 15 is disconnected, the third switch circuit 16 outputs a low-level signal to the output terminal 12, or when the second switch circuit 15 is turned on, the third switch circuit 16 outputs a low-level signal to the output terminal 12.

[0038] According to an embodiment of the present application, the load loops of the second switch circuit 15 and the third switch circuit 16 are connected in series. That is, the second load electrode 152 of the second switch circuit 15 is directly connected to the third load electrode 162 of the third switch circuit 16, and the two can be used to connect to the output terminal 12.

[0039] According to an embodiment of the present application, the control transistor of the first switch circuit 14 is a first NPN-type triode Q1, and the first switch circuit 14 is provided with a current-limiting resistor R1 located at a first control electrode 141, and a voltage-dividing resistor R2, one end of the voltage-dividing resistor R2 is connected to the first control electrode 141, and the other end is grounded. The first load electrode 142 (or collector) of the first triode Q1 is connected to the switching power supply through a pull-up resistor R3.

[0040] According to one embodiment of the present application, the control transistor of the second switch circuit 15 is a second NPN-type triode Q2, and the second switch circuit 15 is provided with a current limiting resistor R4 located at the second control electrode 151, and a voltage dividing resistor R5, one end of the voltage dividing resistor R5 is connected to the second control electrode 151, and the other end is grounded. The second load electrode 152 (or collector) of the second triode Q2 is connected to the switching power supply through the third switch circuit 16. According to one embodiment of the present application, according to one embodiment of the present application, the switching power supply of the first switch circuit 14 can be grounded through the current limiting resistor and the voltage dividing resistor on the control electrode 151 of the second switch circuit 15.

[0041] According to an embodiment of the present application, the control transistor of the third switch circuit 16 is a third triode Q3 of the PNP type, and the third switch circuit 16 is provided with a current limiting resistor R6 located at the third control electrode 161, and a pull-up resistor R7. The third load electrode 162 (or collector) of the third triode Q3 is connected to the output terminal 12, and the third emitter 163 is connected to the switching power supply through the pull-up resistor R8. The third control electrode 161 of the third switch circuit 16 is connected to the switching power supply through the pull-up resistor, and the pull-up resistor is connected in series with the current limiting resistor on the third control electrode 161. The second switch circuit 15 is connected in parallel with a voltage divider resistor R9. The third load electrode 162 can be grounded through the voltage divider resistor R9.

[0042] In one embodiment, the voltage of the switch power supply of the first switch circuit 14 and the third switch circuit 16 is higher than the voltage of the input terminal 11 and the interlock signal input terminal 13 .

[0043] In the present application, this circuit uses fewer electronic components and takes triodes as core devices, which not only avoids short-circuit faults caused by simultaneous conduction of the upper and lower IGBT tubes of the same bridge arm inside the intelligent power module 3, but also improves the reliability of the power circuit, and has low cost and simple structure.

[0044] The following reference Figure 2An exemplary description of a specific embodiment of the present application is as follows:

[0045] As shown in the figure, the microcontroller unit 2 in the figure can be an intelligent controller (MCU). The figure shows the first control end 21 and the second control end 22 of a bridge arm. The corresponding intelligent power module 3 has corresponding first power end 31 and second power end 32. The first control end 21 is signal-connected to the first power end 31 through the interlock circuit 1, and the second control end 22 is signal-connected to the second power end 32 through another interlock circuit 1.

[0046] This circuit is composed of triodes and resistors. The first triode Q1 and the second triode Q2 are NPN-type triodes. The NPN-type triode is used as a switch. When Uc>Ub>Ue and Ube≥Uon (turn-on voltage), the NPN-type triode conducts, otherwise it turns off; the third triode Q3 is a PNP-type triode. The PNP-type triode is used as a switch. When Uc<Ub<Ue and Ueb≥Uon (turn-on voltage), the NPN-type triode conducts, otherwise it turns off. R1, R4, and R6 are the current-limiting resistors of the NPN-type first triode Q1, the NPN-type second triode Q2, and the PNP-type third triode Q3, respectively.

[0047] The input signals are UP_PWM and UN_PWM simultaneously sent by the microcontroller unit 2. Generally, the I / O supply voltage of the microcontroller unit 2 is 3.3V. Therefore, in this application, the 3.3V level is called the high level, and the 0V level is called the low level; the output signal is UP. UP_PWM is connected to the base terminal of the NPN-type first triode Q1 through the current-limiting resistor R1. The terminal voltage of the resistor R2 is equal to Ube1 of the NPN-type first triode Q1. The emitter of the first triode Q1 is grounded. The collector of the first triode Q1 is pulled up to the power supply +5V through the resistor R3. At the same time, the collector of the first triode Q1 is also connected to the base terminal of the NPN-type first triode Q1 through the current-limiting resistor R4. The terminal voltage of the resistor R5 is equal to Ube2 of the second triode Q2. The emitter of the second triode Q2 is grounded. The collector of the second triode Q2 and the collector of the PNP-type third triode Q3 are connected together as the output terminal UP. UN_PWM is connected to the base terminal of the third triode Q3 through the current-limiting resistor R6. The base of the third triode Q3 is pulled up to the power supply +5V through the resistor R7. The emitter of the third triode Q3 is pulled up to the power supply +5V through the resistor R8.

[0048] Figure 1 Function description: The functions that this circuit can achieve are shown in the truth table of Table 1.

[0049] (INPUT)UP_PWM (INPUT)UN_PWM (OUTPUT)UP H L H L H L H H L L L

[0050] Table 1

[0051] 1) When the microcontroller unit 2 simultaneously sends out a high-level UP_PWM and a low-level UN_PWM: Since UP_PWM is high-level, the Ube1 of the NPN-type first triode Q1 >= Uon, and the first triode Q1 conducts; after the first triode Q1 conducts, the Ube2 of the NPN-type second triode Q2 < Uon, and the second triode Q2 turns off; since UN_PWM is low-level, the Ueb of the PNP-type triode >= Uon, and the third triode Q3 conducts. Therefore, the voltage of the output signal UP is high level [UP = 5 * R9 / (R8 + R9)].

[0052] 2) When the microcontroller unit 2 simultaneously sends out a low-level UP_PWM and a high-level UN_PWM: Since UP_PWM is low-level, the Ube1 of the NPN-type first triode Q1 < Uon, and the first triode Q1 turns off; after the first triode Q1 turns off, the Ube2 of the NPN-type second triode Q2 >= Uon, where Ube2 = 5 * R5 / (R3 + R4 + R5), and the second triode Q2 conducts; since UN_PWM is high-level, the Ueb of the PNP-type third triode Q3 < Uon, and the third triode Q3 turns off. Therefore, the voltage of the output signal UP is low level (UP = the on-state voltage drop Vce2 of the NPN-type triode).

[0053] 3) When the microcontroller unit 2 simultaneously sends out a high-level UP_PWM and a high-level UN_PWM: Since UP_PWM is high-level, the Ube1 of the NPN-type first triode Q1 >= Uon, and the first triode Q1 conducts; after the first triode Q1 conducts, the Ube2 of the NPN-type second triode Q2 < Uon, and the second triode Q2 turns off; since UN_PWM is high-level, the Ueb of the PNP-type third triode Q3 < Uon, and the third triode Q3 turns off. Therefore, the voltage of UP is low level.

[0054] 4) When the microcontroller unit 2 simultaneously sends out a low-level UP_PWM and a low-level UN_PWM: Since UP_PWM is low-level, the Ube1 of the NPN-type first triode Q1 < Uon, and the first triode Q1 turns off; after the first triode Q1 turns off, the Ube2 of the NPN-type second triode Q2 >= Uon, where Ube2 = 5 * R5 / (R3 + R4 + R5), and the second triode Q2 conducts; since UN_PWM is low-level, the Ueb of the PNP-type triode >= Uon, and the third triode Q3 conducts. Therefore, the voltage of the output signal UP is low level (UP = the on-state voltage drop Vce2 of the NPN-type triode).

[0055] Figure 2 Yes Figure 1The application diagram specifically shows the driving interlocking circuit of the same bridge arm of the intelligent power module 3. The intelligent power module 3 in the figure integrates 6 IGBT tubes, UP and UN are the driving signals of the upper and lower IGBT tubes of the same upper bridge arm, and the corresponding driving signal can only turn on the corresponding IGBT tube when it is at a high level.

[0056] (INPUT)UP_PWM (INPUT)UN_PWM (OUTPUT)UP (OUTPUT)UN H L H L L H L H H H L L L L L L

[0057] Table 2 Figure 2 The truth table of

[0058] To sum up, the intelligent power module 3 drive interlocking circuit of the present application has the following technical effects: the drive signals (UP, UN) of the same bridge arm cannot be high level at the same time, that is, the upper and lower IGBT tubes of the same bridge arm cannot be turned on at the same time, avoiding the short circuit fault caused by the direct connection of the upper and lower IGBT tubes of the same bridge arm, and improving the safety and reliability of the power circuit; and the circuit uses fewer electronic components, with transistors as the core components, which is not only low in cost, but also simple in structure and easy to implement.

[0059] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0060] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A drive interlock circuit (1) of an intelligent power module, characterized in that: The interlock circuit (1) comprises a plurality of transistor switch circuits, and the interlock circuit (1) comprises an input terminal (11), an output terminal (12), and an interlock signal input terminal (13); The input end (11) is used to connect to a first control end (21) of a bridge arm; the output end (12) is used to connect to a first power end (31); the interlock signal input end (13) is used to connect to a second control end (22) of the bridge arm; the control signal of the input end (11) is transmitted to the output end (12) via the interlock circuit; when a high level is input to the input end (11) and the interlock signal input end (13) at the same time, the interlock circuit outputs a low level through the output end (12); The interlocking circuit comprises a first switch circuit (14), a second switch circuit (15) and a third switch circuit (16); a first control electrode (141) of the first switch circuit (14) is connected to the input terminal (11), and a first load electrode (142) of the first switch circuit (14) is used to be connected to the second switch circuit (15); a second control electrode (151) of the second switch circuit (15) is connected to the first load electrode (142), and a second load electrode (152) of the second switch circuit (15) is connected to the output terminal (12); a third control electrode (161) of the third switch circuit (16) is connected to the interlocking signal input terminal (13), and a third load electrode (162) of the third switch circuit (16) is used to be connected to the second load electrode (152) and the output terminal (12); The first switch circuit (14) is turned on according to a high-level signal input by the first control electrode (141), and the first switch circuit (14) is turned on so that the second control electrode (151) is at a low level, and the second switch circuit (15) is turned off; or the first switch circuit (14) is turned off according to a low-level signal input by the first control electrode (141), and the first switch circuit (14) is turned off, so that the second control electrode (151) is connected to a high level through the first load electrode (142), and the second switch circuit (15) is turned on; The third switch circuit (16) is turned on according to a low-level signal input by the third control electrode (161), and when the second switch circuit (15) is turned off, the third switch circuit (16) outputs a high-level signal to the output end (12), or when the second switch circuit (15) is turned on, the third switch circuit (16) outputs a low-level signal to the output end (12); or the third switch circuit (16) is turned off according to a high-level signal input by the third control electrode (161), and when the second switch circuit (15) is turned off, the third switch circuit (16) outputs a low-level signal to the output end (12), or when the second switch circuit (15) is turned on, the third switch circuit (16) outputs a low-level signal to the output end (12); The first switch circuit (14) and the second switch circuit (15) are NPN type electronic switch circuits; and the third switch circuit (16) is a PNP type electronic switch circuit.

2. The driving interlock circuit of the intelligent power module according to claim 1, characterized in that: The third switch circuit (16) has a polarity opposite to that of the first switch circuit (14) and the second switch circuit (15).

3. The driving interlock circuit of the intelligent power module according to claim 1, characterized in that: The second switch circuit (15) and the load circuit of the third switch circuit (16) are connected in series.

4. The driving interlock circuit of the intelligent power module according to claim 1, characterized in that: The first switch circuit (14) and the second switch circuit (15) are both provided with voltage dividing resistors.

5. The driving interlock circuit of the intelligent power module according to claim 1, characterized in that: The first switch circuit (14), the second switch circuit (15) and the third switch circuit (16) are all provided with a current limiting resistor located at a control electrode.

6. The driving interlock circuit of the intelligent power module according to claim 1, characterized in that: The first switch circuit (14) and the third switch circuit (16) are both provided with a pull-up resistor.

7. The driving interlocking circuit of the intelligent power module according to any one of claims 1 to 6, characterized in that: The voltage of the switch power supplies of the first switch circuit (14) and the third switch circuit (16) is higher than the voltage of the input terminal (11) and the interlock signal input terminal (13).

8. The driving interlocking circuit of the intelligent power module according to any one of claims 1 to 6, characterized in that: The second switch circuit (15) is connected in parallel with a voltage dividing resistor.

9. The driving interlocking circuit of the intelligent power module according to any one of claims 1 to 6, characterized in that: The third control electrode (161) of the third switch circuit (16) is connected to the switch power supply via a pull-up resistor, and the pull-up resistor is connected in series with the current limiting resistor on the third control electrode (161).

10. The driving interlocking circuit of the intelligent power module according to any one of claims 1 to 6, characterized in that: The switching power supply of the first switching circuit (14) is grounded via a current limiting resistor and a voltage dividing resistor on a control electrode (151) of the second switching circuit (15).

11. An intelligent power module, characterized in that: It comprises a plurality of bridge arms, each bridge arm having a first control end (21) and a second control end (22); The first control end (21) and the second control end (22) of at least one bridge arm are both provided with a driving interlocking circuit of the intelligent power module according to any one of claims 1 to 9.

Images