Method for manufacturing semiconductor package structure

Abstract

A method for manufacturing a semiconductor package structure includes the following steps: bonding a die to a wafer; forming a dielectric material layer on the wafer and the die; the dielectric material layer covers the top surface and sidewalls of the die; performing at least one planarization process to remove a portion of the dielectric material layer and a portion of the die to expose the top surface of the die and form a dielectric layer located on the side of the die; the dielectric layer surrounds and covers the sidewalls of the die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of U.S. Provisional Application No. 62 / 580,434 filed on November 1, 2017. The above patent application is hereby incorporated by reference in its entirety into this application and constitutes a part of this specification. Technical Field

[0003] The disclosed embodiment relates to a method for manufacturing a semiconductor package structure. Background Art

[0004] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density comes from the continued decrease in minimum feature size, which enables more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize smaller areas compared to previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated chips (3DIC), wafer level packages (WLP), and package on package (PoP) devices, among others.

[0005] Three-dimensional integrated chips offer increased integration density and other advantages, such as faster speed and higher bandwidth, due to the reduced length of interconnection lines between stacked chips. However, there are still many challenges to be addressed for three-dimensional integrated chip technology. Summary of the invention

[0006] The disclosed embodiment provides a method for manufacturing a semiconductor package structure, which includes the following steps: bonding a die to a wafer; forming a dielectric material layer on the wafer and the die; the dielectric material layer covers the top surface and sidewalls of the die; performing at least one planarization process to remove a portion of the dielectric material layer and a portion of the die to expose the top surface of the die and form a dielectric layer located on the side of the die; the dielectric layer surrounds and covers the sidewalls of the die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A to Figure 1Cis a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package structure according to a first embodiment of the present disclosure.

[0008] Figure 2A to Figure 2C is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package structure according to a second embodiment of the present disclosure.

[0009] Figure 3 According to some embodiments of the present disclosure Figure 2C A top view of a semiconductor package structure is shown.

[0010] FIG. 4A to FIG. 4D is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package structure according to a third embodiment of the present disclosure.

[0011] FIG. 5A to FIG. 5C is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package structure according to a fourth embodiment of the present disclosure.

[0012] FIG. 6A to FIG. 6D is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package structure according to a fifth embodiment of the present disclosure.

[0013] Figure 7 is a flow chart of a method of manufacturing a semiconductor package structure according to some embodiments of the present disclosure.

[0014] [Explanation of Symbols]

[0015] 10: Substrate

[0016] 11: Device layer

[0017] 12: Metallization structure

[0018] 13: Passivation layer

[0019] 14: Pad

[0020] 15: Cutting Road

[0021] 16a, 16b, 16c: Die

[0022] 18: Chip

[0023] 18a: First surface

[0024] 18b: Second surface

[0025] 19a, 19b, 19c: Die

[0026] 20: Substrate

[0027] 21: Device layer

[0028] 22: Metallization structure

[0029] 23: Passivation layer

[0030] 24: Pad

[0031] 25: Gap

[0032] 26a: First surface

[0033] 26b: Second surface

[0034] 27: Dielectric material layer

[0035] 27b: Dielectric layer

[0036] 28: Main body

[0037] 29: Protrusion

[0038] 30: Gap

[0039] 32: Mask layer

[0040] 33: Opening

[0041] 35: Hard mask layer

[0042] 35a, 35b: Hard mask

[0043] 100a, 100b, 100c, 100d, 100e: semiconductor packaging structure

[0044] 119c: Virtual Die

[0045] 126b: Top surface

[0046] 127, 127a: dielectric material layer

[0047] 127b: Dielectric layer

[0048] 128, 128a: Main body

[0049] 129, 129b: protrusion

[0050] 129a, 129c: Remaining part

[0051] 132, 132a: mask layer

[0052] H1, H2: Height

[0053] S1: Distance

[0054] S100, S102, S104: Steps

[0055] T0, T1, T2, T3, T4, T6, T10, T11: thickness

[0056] W1, W2, W3, W4, W5: Width DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which the second feature is formed "on" the first feature or "on" the second feature may include an embodiment in which the second feature and the first feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature, thereby making the second feature and the first feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed by itself.

[0058] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "on," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0059] Other features and processes may also be included. For example, a test structure may be included to facilitate verification testing of a three-dimensional package or a three-dimensional integrated chip device. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which enable testing of the three-dimensional package or the three-dimensional integrated chip, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0060] Figure 1A to Figure 1C is a schematic cross-sectional view showing a method for manufacturing a semiconductor package structure according to a first embodiment of the present disclosure. In some embodiments, the semiconductor package structure includes a three-dimensional integrated chip (3DIC) structure.

[0061] Reference Figure 1A, a wafer 18 including a plurality of dies 16a, 16b, and 16c is provided. For example, the dies 16a, 16b, and 16c may be application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless radio frequency chips, voltage regulator chips, or memory chips, respectively. The dies 16a, 16b, and 16c may be the same type of dies or different types of dies. Figure 1A The number of tube cores formed in the wafer 18 shown in is for illustration only, and the present disclosure is not limited thereto. In some embodiments, the wafer 18 includes a plurality of tube cores arranged in an array, and the number of the tube cores can be adjusted according to the design of the product. In some embodiments, the tube cores 16a, 16b and 16c can be separated along the cutting road 15 by a tube core cutting process. In some embodiments, the tube core 16c is close to the edge of the wafer 18, and the tube cores 16a and 16b are far away from the edge of the wafer 18. In some embodiments, the edge of the wafer 18 has a circular shape or an arc shape.

[0062] In some embodiments, the wafer 18 includes a substrate 10, a device layer 11, a metallization structure 12, a passivation layer 13, and a plurality of pads 14. The substrate 10 is a semiconductor substrate, such as a silicon substrate. For example, the substrate 10 is a bulk silicon substrate, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate. The dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination of an N-type dopant and a P-type dopant. The substrate 10 may also be formed of other semiconductor materials. The other semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, or the like. The substrate 10 includes an active region and an isolation structure (not shown in the figure).

[0063] The device layer 11 includes a variety of devices (not shown) formed on the active area of ​​the substrate 10. In some embodiments, the device includes active components, passive components, or a combination of active components and passive components. In some embodiments, for example, the device includes an integrated circuit device. In some embodiments, the device is, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. That is, the wafer 18 is a wafer in which a device is formed rather than a carrier. The metallization structure 12 is formed on the substrate 10 and the device layer 11. In some embodiments, the metallization structure 12 includes one or more dielectric layers and an interconnect structure (not shown) formed therein. The interconnect structure includes multilayer contacts, conductive lines, and plugs, and is electrically connected to the devices in the device layer 11.

[0064] Pads 14 are formed on metallization structure 12. Pads 14 are electrically connected to interconnect structures in metallization structure 12 to provide external connections for devices in device layer 11. The material of pads 14 may include metal or metal alloy, such as aluminum, copper, nickel or alloys thereof.

[0065] The passivation layer 13 is formed above the metallization structure 12 and on the side of the pad 14 to cover the sidewall of the pad 14. In some embodiments, the passivation layer 13 is also referred to as a dielectric layer. The passivation layer 13 may be a single-layer structure or a multi-layer structure. The passivation layer 13 includes an insulating material, such as silicon oxide, silicon nitride, a polymer, or a combination thereof. The polymer is, for example, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like. In some embodiments, the top surface of the passivation layer 13 is substantially flush with the top surface of the pad 14. The top surface of the passivation layer 13 and the top surface of the pad 14 form the active surface of the wafer 18. In some embodiments, the active surface is referred to as the first surface 18a (or the front surface) of the wafer 18, and the second surface 18b (or the back surface) (i.e., the bottom surface) of the wafer 18 is opposite to the first surface 18a.

[0066] In other words, the die 16a, 16b or 16c includes the substrate 10, the device layer 11, the metallization structure 12, the passivation layer 13 and the pad 14. The pad 14 is electrically connected to the device in the device layer 11 through the interconnection structure of the metallization structure 12.

[0067] Still refer to Figure 1A , for example, multiple dies 19a, 19b, and 19c are bonded to wafer 18 by a chip on wafer (CoW) bonding process. In some embodiments, die 19a is bonded to die 16a, die 19b is bonded to die 16b, and die 19c is bonded to die 16c. In some embodiments, die 19c is adjacent to the edge of wafer 18 and is referred to as an edge die. Dies 19a and 19b are away from the edge of wafer 18. In some embodiments, dies 19a, 19b, and 19c include active components or passive components, respectively. For example, dies 19a, 19b, and 19c may be application specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless radio frequency chips, voltage regulator chips, or memory chips, respectively. Dies 19a, 19b, and 19c may be dies of the same type or dies of different types.

[0068] In some embodiments, the dies 19a, 19b, and 19c are dies cut from one or more wafers by a die sawing process. That is, the dies 19a, 19b, and 19c may be cut from the same wafer or different wafers. Before singulating the dies 19a, 19b, and 19c, a grinding process may be performed to thin the wafer. Thereafter, the dies 19a, 19b, and 19c are bonded to the wafer 18. In some embodiments, a grinding process is then performed to further thin the dies 19a, 19b, and 19c.

[0069] In some embodiments, the dies 19a, 19b, and 19c include a substrate 20, a device layer 21, a metallization structure 22, a passivation layer 23, and a plurality of pads 24, respectively. In some embodiments, the material and structural characteristics of the substrate 20, the device layer 21, the metallization structure 22, the passivation layer 23, and the pads 24 are similar to or different from the material and structural characteristics of the substrate 10, the device layer 11, the metallization structure 12, the passivation layer 13, and the pads 14.

[0070] The dies 19a, 19b, and 19c may have the same size or different sizes. In some embodiments where the dies 19a, 19b, and 19c have the same size, the dies 19a, 19b, and 19c have substantially the same height H1 and the same width W1. That is, the top surfaces of the dies 19a, 19b, and 19c are substantially flush with each other. The height H1 of the dies 19a, 19b, and 19c ranges from 5 μm to 775 μm. In one embodiment, the height H1 is, for example, 20 μm. The width W1 of the dies 19a, 19b, and 19c ranges from 1 mm to 30 mm. In one embodiment, the width W1 of the die 19a is, for example, 5 mm, 10 mm, or 20 mm. In some embodiments, there are multiple gaps 25 between the dies 19a, 19b, and 19c. That is, the dies 19a, 19b, and 19c are dispersedly located on the wafer 18. The width W2 of the gap 25 (ie, the distance between adjacent dies 19a and 19b or 19b and 19c) ranges from 30 μm to 1 mm.

[0071] The dies 19a, 19b, and 19c respectively have a first surface 26a (i.e., bottom surface) and a second surface 26b (i.e., top surface) opposite to each other. In some embodiments, the first surface 26a (or referred to as the front surface) is the active surface of the die 19a, 19b, or 19c, including the surface of the passivation layer 23 and the surface of the pad 24. The second surface 26b (or referred to as the back surface) is the top surface of the substrate 20 of the die 19a, 19b, or 19c. In some embodiments, the first surface 26a of the die 19a, 19b, and 19c is bonded to the first surface 18a of the wafer 18. That is, the die 19a / 19b / 19c and the wafer 18 are respectively configured to face each other.

[0072] In some embodiments, the dies 19a, 19b, and 19c are aligned with the dies 16a, 16b, and 16c, respectively. The pads 24 are aligned with the pads 14, and the passivation layer 23 is aligned with the passivation layer 13, but the present disclosure is not limited thereto. In some embodiments, the dies 19a, 19b, and 19c are bonded to the wafer 18 by a suitable bonding method. The suitable bonding method is, for example, hybrid bonding, fusion bonding, or a combination thereof. In some embodiments, as Figure 1A As shown, one die 19a, 19b or 19c is respectively bonded to one die 16a, 16b or 16c of wafer 18, but the present disclosure is not limited thereto. In some other embodiments, two or more dies may be bonded to one die 16a, 16b or 16c of wafer 18 (not shown).

[0073] In some embodiments where the bonding method includes hybrid bonding, the hybrid bonding includes at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding (e.g., dielectric-to-dielectric bonding). That is, the pad 24 is bonded to the pad 14 by metal-to-metal bonding, and the passivation layer 23 is bonded to the passivation layer 13 by dielectric-to-dielectric bonding.

[0074] In some embodiments where the bonding method includes melt bonding, the bonding operation of melt bonding can be performed as follows. First, in order to avoid the generation of unbonded areas (i.e., interface bubbles), the surfaces to be bonded of the dies 19a, 19b, and 19c and the surfaces to be bonded of the wafer 18 (i.e., the first surfaces 26a of the dies 19a, 19b, and 19c and the first surface 18a of the wafer 18) are treated to make them sufficiently clean and smooth. Then, the dies 19a, 19b, and 19c are aligned and placed in physical contact with the dies 16a, 16b, and 16c of the wafer 18 at room temperature with slight pressure to start the bonding operation. Thereafter, an annealing process is performed at an elevated temperature to strengthen the chemical bonds between the surfaces to be bonded of the dies 19a, 19b, and 19c and the surfaces to be bonded of the wafer 18 and to convert the chemical bonds into covalent bonds.

[0075] In some other embodiments, the dies 19a, 19b, and 19c may be bonded to the wafer 18 through a plurality of connectors (not shown), and an underfill layer may be formed to fill the spaces between the dies 19a, 19b, and 19c and the wafer 18 and surround the connectors. The connectors are located between the pads 14 and 24 so that the dies 19a, 19b, and 19c are electrically connected to the wafer 18, respectively. The connectors may be conductive bumps, such as solder bumps, silver balls, copper balls, gold bumps, copper bumps, copper pillars, or any other suitable metal bumps or the like.

[0076] Reference Figure 1B After the dies 19a, 19b and 19c are bonded to the wafer 18, a dielectric material layer 27 is formed over the wafer 18 and the dies 19a, 19b and 19c. The dielectric material layer 27 covers the top surface of the wafer 18 and the top surfaces and sidewalls of the dies 19a, 19b and 19c. That is, the gap 25 between the dies 19a, 19b and 19c is filled with the dielectric material layer 27, and the dielectric material layer 27 is also referred to as a gap filling dielectric layer. In some embodiments, the gap 25 is filled with the dielectric material layer 27. In some embodiments, the material of the dielectric material layer 27 includes a molding compound, a molding underfill, a resin (e.g., an epoxy resin), or a combination thereof, or the like. The method of forming the dielectric material layer 27 includes a molding process, a molding underfilling (MUF) process, or a combination thereof.

[0077] In some embodiments, dielectric material layer 27 has a substantially flat top surface. In some embodiments, the sidewalls of dielectric material layer 27 located on the edge of wafer 18 are substantially vertical. The thickness T0 of dielectric material layer 27 is greater than the height H1 of die 19a, 19b, or 19c. In some embodiments, the thickness T0 of dielectric material layer 27 is greater than 5 μm and less than or equal to 800 μm. Here, thickness T0 refers to the thickness of dielectric material layer 27 from the top surface of wafer 18 to the top surface of dielectric material layer 27. In some embodiments where the edge of wafer 18 is rounded or arc-shaped, dielectric material layer 27 may extend to a portion of the sidewall covering the edge of wafer 18. Therefore, the thickness of a portion of dielectric material layer 27 located on the edge of wafer 18 is greater than thickness T0.

[0078] In some embodiments, dielectric material layer 27 includes body portion 28 and protrusion 29. Body portion 28 is located on wafer 18 and on the sides of die 19a, 19b, and 19c, surrounding and covering the sidewalls of die 19a, 19b, and 19c. In some embodiments, the top surface of body portion 28 is substantially flush with the second surface of die 19a, 19b, and 19c. Protrusion 29 is located on body portion 28 and on die 19a, 19b, and 19c, covering the second surface 26b of die 19a, 19b, and 19c and the top surface of body portion 28. In some embodiments, protrusion 29 is a continuous layer located above wafer 18, and the width of protrusion 29 is substantially the same as the width of wafer 18.

[0079] Reference Figure 1C , thereafter a planarization process is performed to remove a portion of the dielectric material layer 27 located on the second surface 26b of the tube cores 19a, 19b and 19c, so that the second surface 26b (i.e., the top surface) of the tube cores 19a, 19b and 19c is exposed, and a dielectric layer 27b is formed. In some embodiments, some portions of the substrate 20 of the tube cores 19a, 19b and 19c are also removed during the planarization process, and the height of the tube cores 19a, 19b and 19c is reduced from H1 to H2. In some embodiments, the height H2 is greater than 1μm and less than or equal to 100μm. In an embodiment where the height H1 is 20μm, the height H2 is 10μm. However, the present disclosure is not limited thereto, and in some other embodiments, the substrate 20 is not removed during the planarization process. In some embodiments, the planarization process, for example, includes a chemical mechanical polishing (CMP) process.

[0080] Still refer to Figure 1C In some embodiments, the top surface of the dielectric layer 27b is substantially flush with the second surface 26b of the tube core 19a, 19b and 19c. In other words, the protrusion 29 is removed during the planarization process. In some embodiments where some portions of the tube core 19a, 19b and 19c are removed, the protrusion 29 of the dielectric material layer 27 and a portion of the main body 28 are removed, and the dielectric layer 27b has a thickness T2. The value of the thickness T2 of the dielectric layer 27b is substantially the same as the value of the height H2 of the tube core 19a, 19b or 19c. In other words, the dielectric layer 27b has the same plane as the scattered tube core 19a, 19b and 19c.

[0081] Still refer to Figure 1C, the semiconductor package structure 100a is now completed, and the semiconductor package structure 100a includes a wafer 18, a plurality of tube cores 19a, 19b and 19c, and a dielectric layer 27b. The tube cores 19a, 19b and 19c are bonded to the wafer 18. The dielectric layer 27b is formed on the wafer 18 and is located on the sides of the tube cores 19a, 19b and 19c. The dielectric layer 27b fills the gap 25 between the tube cores 19a, 19b and 19c to cover a portion of the first surface 18a of the wafer 18 and cover the sidewalls of the tube cores 19a, 19b and 19c. In other words, the tube core 19a, 19b or 19c is surrounded and protected by the dielectric layer 27b. The second surface 26b of the tube cores 19a, 19b and 19c is exposed, and subsequent processes can be performed to stack more components or devices on the semiconductor package structure 100a.

[0082] Figure 2A to Figure 2C 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor package structure according to a second embodiment of the present disclosure. The second embodiment differs from the first embodiment in that a dielectric material layer 127 is formed on the wafer 18 and the dies 19a, 19b and 119c, and the material and the forming method of the dielectric material layer 127 are different from the material and the forming method of the dielectric material layer 27.

[0083] Reference Figure 1A and Figure 2A , execute and Figure 1A The process similar to the process shown in the figure is used to bond the dies 19a, 19b and 119c to the wafer 18. The die 119c is located on the side of the die 19a and 19b and on the edge of the wafer 18, that is, the die 119c is closer to the edge or end of the wafer 18. A dielectric material layer 127 is formed over the wafer 18 to cover a portion of the first surface 18a of the wafer 18 and to cover the second surface 26b and sidewalls of the dies 19a, 19b and 119c. In some embodiments, the material of the dielectric material layer 127 includes an inorganic dielectric material, an organic dielectric material, or a combination of an inorganic dielectric material and an organic dielectric material. The inorganic dielectric material includes an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), or a combination thereof. The organic dielectric material includes a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), epoxy resin, or a combination thereof or the like. The dielectric material layer 127 is formed by a deposition process, such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) or the like.

[0084] Still refer to Figure 2A , the surface or topography of the dielectric material layer 127 is undulating. In some embodiments, the topography of the dielectric material layer 127 is similar to the tube cores 19a, 19b and 119c on the wafer 18. In some embodiments, the dielectric material layer 127 includes a main body 128 and a plurality of protrusions 129. The main body 128 is located on the wafer 18 and is located on the side of the tube cores 19a, 19b and 119c, covering a portion of the first surface 18a of the wafer 18 and the sidewalls of the tube cores 19a, 19b and 119c. That is, the gap 25 located between the tube cores 19a, 19b and 119c is filled by the dielectric material layer 127. In some embodiments, the gap 25 is filled by the dielectric material layer 127. The edge of the main body 128 covers the edge of the wafer 18 and has a shape similar to the shape of the edge of the wafer 18. The protrusions 129 are located above the main body 128 and respectively on the tube cores 19a, 19b and 119c to cover the second surface 26b of the tube cores 19a, 19b and 119c and a portion of the top surface of the main body 128. In other words, the top corners of the tube cores 19a, 19b and 119c are covered by the dielectric material layer 127. In some embodiments, the number of protrusions 129 is the same as the number of tube cores 19a, 19b and 119c on the wafer 18. The cross-sectional shape of the protrusion 129 can be, for example, a square, a rectangle, a rectangle with an arc-shaped sidewall, a square with an arc-shaped sidewall, or a trapezoid. However, the present disclosure is not limited thereto, and the cross-sectional shape of the protrusion 129 can be any other shape as long as the second surface 26b, the top corners and the sidewalls of the tube cores 19a, 19b and 119c are covered. In some embodiments, the thickness T1 of the main body 128 is substantially the same as the height H1 of the tube core 19a or 19b. The thickness T10 of the protrusion 129 may be the same as or different from the thickness T1 of the body portion 128 .

[0085] In some embodiments, the sidewall of the protrusion 129 is arc-shaped, and the width of the protrusion 129 gradually increases and then gradually decreases from top to bottom. That is, the protrusion 129 has a maximum width at the middle area from top to bottom. In some embodiments, the bottom width W3 of the protrusion 129 is greater than the width W1 of the tube core 19a, 19b or 119c. That is, the protrusion 129 covers the top surface of the tube core 19a, 19b or 119c and a portion of the top surface of the main body 128 surrounding the tube core 19a, 19b or 119c. In some embodiments, the top surface of the tube core 19a, 19b and 119c is completely covered by the protrusion 129. In some embodiments, the ratio of the bottom width W3 to the width W1 ranges from 1 to 1.5.

[0086] Still refer to Figure 2AIn some embodiments, there are a plurality of gaps 30 between adjacent protrusions 129. The gaps 30 are located above the gaps 25, and a portion of the top surface of the main body 128 is exposed by the gaps 30. In some embodiments, the width of the gaps 30 decreases from top to bottom and then increases. The bottom width W4 of the gaps 30 is less than the width W2 of the gaps 25. For example, the cross-sectional shape of the gaps 30 may be rectangular, trapezoidal, or narrow vase-shaped.

[0087] Reference Figure 2B , the protrusion 129 of the dielectric material layer 127 is removed to expose the second surface 26b of the tube cores 19a, 19b and 119c, and the dielectric material layer 127a including the main body 128a remains. The protrusion 129 is removed by a first planarization process (for example, a chemical mechanical polishing process). In some embodiments, a portion of the main body 128 is also removed during the planarization process, and a slight recess may be generated in the main body 128a. In some embodiments, a large amount of the main body 128 of the dielectric material layer 127 located on the edge of the wafer 18 is removed, and the sidewall of the tube core 119c (edge ​​tube core) close to the edge of the wafer 18 is partially exposed or damaged. The sidewalls of the tube cores 19a and 19b and the sidewalls of the tube core 119c away from the edge of the wafer 18 are still covered and protected by the dielectric material layer 127a.

[0088] Reference Figure 2C, remove some portions of the tube cores 19a, 19b and 119c and a portion of the main body 128a of the dielectric material layer 127a, and form a dielectric layer 127b. The removal method includes a second planarization process, such as a chemical mechanical polishing process. In some embodiments, the top surface of the dielectric layer 127b located between the tube cores 19a, 19b and 119c is substantially flush with the second surface 26b of the tube cores 19a and 19b. In some embodiments, a portion of the top surface of the dielectric layer 127b located on the edge of the wafer 18 is inclined and lower than the second surface 26b of the tube cores 19a and 19b. Since a large amount of the dielectric material layer 127 located on the edge of the wafer 18 is removed during the first planarization process, and a portion of the sidewall of the tube core 119c (i.e., the edge tube core) close to the edge of the wafer 18 is not covered and protected by the dielectric material layer 127a, the tube core 119c may be further damaged during the second planarization process and suffer from morphological degradation. That is, a portion of die 119c not covered by dielectric material layer 127a is removed, and die 119c having top surface 126b is formed. A portion of top surface 126b of die 119c near die 19b is flush with second surface 26b of die 19a and 19b, and another portion of top surface 126b near edge of wafer 18 is inclined and lower than second surface 26b. In some embodiments, die 119c is a dummy die formed on the edge of wafer 18, so that during the first planarization process and the second planarization process, die 19a and 19b are protected from damage in the lateral direction. In some embodiments, dummy die 119c does not include a device or metallization structure. In this document, when an element is described as "dummy", the element is electrically floating or electrically isolated from other elements.

[0089] Figure 3 According to some embodiments of the present disclosure Figure 2C It is worth noting that for the sake of simplicity, Figure 2C Only one edge of the wafer 18 and three dies 19a, 19b and 119c are shown. Figure 3 , the wafer 18 includes a plurality of dies 19a / 19b and a plurality of dummy dies 119c formed therein. The dummy dies 119c are formed on the edge of the wafer 18 to surround the dies 19a and 19b. In some embodiments, the dies 19a and 19b are effective dies and are protected by the dummy dies 119c during the planarization process. In some embodiments, the size of the dummy dies 119c is less than or equal to the size of the dies 19a or 19b. The dummy dies 119c may have the same size or different sizes.

[0090] Reference Figure 2C and Figure 3, the semiconductor package structure 100b is now completed. The difference between the semiconductor package structure 100b and the semiconductor package structure 100a is that a plurality of dummy dies 119c are formed on the edge of the wafer 18 to protect the effective dies 19a and 19b. The other structural features of the semiconductor package structure 100b are substantially the same as those of the semiconductor package structure 100a, and will not be described in detail.

[0091] FIG. 4A to FIG. 4D is a schematic cross-sectional view of a method for manufacturing a semiconductor package structure according to a third embodiment of the present disclosure. The third embodiment is different from the second embodiment in that a mask layer 32 is formed after forming the dielectric material layer 127. The details are as follows.

[0092] Reference Figure 4A , in the first embodiment Figure 1A After the process shown in the figure has bonded the dies 19a, 19b and 19c to the wafer 18, a process similar to Figure 2A The dielectric material layer 127 is formed on the wafer 18 by a process. The dielectric material layer 127 includes a main body 128 and a plurality of protrusions 129, and a plurality of gaps 30 are located between the protrusions 129. The material, formation method and structural characteristics of the dielectric material layer 127 are similar to those described in the second embodiment.

[0093] Reference Figure 4B , a mask layer 32 is formed over the wafer 18. The mask layer 32 is disposed on the main body 128 of the dielectric material layer 127 and is located on the side of the protrusion 129. The mask layer 32 fills the gap 30 between the protrusions 129 of the dielectric material layer 127 and protrudes from the top surface of the protrusion 129. In some embodiments, the mask layer 32 covers a portion of the top surface of the main body 128 and some portions of the sidewall and top surface of the protrusion 129. The main body 128 located on the edge of the wafer 18 is also covered by the mask layer 32.

[0094] The mask layer 32 has a plurality of openings 33 that expose portions of the top surface of the protrusion 129. The openings 33 are located at corresponding positions above the tube cores 19a, 19b, and 19c. In some embodiments, the width W5 of the opening 33 is equal to or less than the width W1 of the tube core 19a, 19b, or 19c. The width W5 depends on the width W1 of the tube core 19a, 19b, or 19c. In some embodiments, the distance S1 between the sidewall of the opening 33 and the sidewall of the tube core 19a, 19b, or 19c adjacent thereto ranges from 1 μm to 100 μm. In one embodiment, the distance S1 is 20 μm.

[0095] In some embodiments, the mask layer 32 is, for example, a patterned photoresist. The mask layer 32 is formed, for example, by the following method: first, a photoresist layer is formed on the dielectric material layer 127, the photoresist layer filling the gap 30 and covering the top surface of the protrusion 129. Thereafter, an exposure and development process is performed on the photoresist layer.

[0096] Reference Figure 4B and Figure 4C , a removal process is performed using the mask layer 32 as a mask to remove some portions of the protrusion 129 exposed by the opening 33, and to form a dielectric material layer 127a. In some embodiments, after performing the removal process, some portions of the second surface 26b of the tube cores 19a, 19b, and 19c are exposed. However, the present disclosure is not limited thereto, and in some other embodiments, after performing the removal process, the second surface 26b of the tube cores 19a, 19b, and 19c is not exposed. The removal method includes an etching process. The etching process may be an anisotropic etching process, an isotropic etching process, or a combination of an anisotropic etching process and an isotropic etching process. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination of a wet etching process and a dry etching process. Thereafter, for example, the mask layer 32 is stripped by an ashing process.

[0097] Reference Figure 4C After removing some portions of the protrusion 129, a plurality of remaining portions 129a remain on the main body 128 and on the tube cores 19a, 19b and 19c. The remaining portions 129a cover some portions of the second surface 26b of the tube cores 19a, 19b and 19c and a portion of the top surface of the main body 128. In other words, the top corners of the tube cores 19a, 19b and 19c are covered by the dielectric material layer 127a. Specifically, the remaining portions 129a cover the top surfaces of the edges of the tube cores 19a, 19b and 19c and the top surface of a portion of the main body 128 adjacent to the edges of the tube cores 19a, 19b and 19c. In other words, the dielectric material layer 127a covers the side walls of the tube cores 19a, 19b and 19c and the top surfaces of the edges of the tube cores 19a, 19b and 19c. In some embodiments, the cross-sectional shape of the remaining portions 129a is, for example, a tooth shape, a triangle shape, or an arc shape. In some embodiments, as Figure 4C As shown, the remaining portion 129a has a vertical sidewall and an arc-shaped sidewall. The vertical sidewall is the inner sidewall of the remaining portion 129a located on the tube cores 19a, 19b and 19c, and the arc-shaped sidewall is the outer sidewall of the remaining portion 129a located on the main body 128. However, the present disclosure is not limited thereto, and in some other embodiments, the inner sidewall of the remaining portion 129a is not vertical but inclined.

[0098] Reference Figure 4C and Figure 4D, remove the remaining portion 129a of the dielectric material layer 127a and a portion of the main body 128 and some portions of the tube cores 19a, 19b and 19c to form a dielectric layer 127b and expose the second surface 26b of the tube cores 19a, 19b and 19c. The tube cores 19a, 19b and 19c are thinned, and the height of the tube cores 19a, 19 or 19c is reduced from H1 to H2. In some embodiments, the removal process is also referred to as a thinning process. The thinning process includes a planarization process, such as a chemical mechanical polishing process. In some embodiments, the chemical mechanical polishing process has a high selectivity of the substrate 20 to the dielectric material layer 127a.

[0099] Reference Figure 4D In some embodiments, the top surface of the dielectric layer 127b is substantially flush with the second surface 26b of the tube core 19a, 19b and 19c. The thickness T2 of the dielectric layer 127b is substantially the same as the height H2 of the tube core 19a, 19b or 19c. The range of the thickness T2 and the height H2 is substantially the same as that described in the first embodiment. The sidewalls of the tube core 19a, 19b and 19c are surrounded and covered by the dielectric layer 127b, and the second surface 26b of the tube core 19a, 19b and 19c is exposed. In some embodiments, the sidewalls of the dielectric layer 127b located on the edge of the wafer 18 are not vertical but are curved, rounded or inclined.

[0100] Still refer to Figure 4D , the semiconductor package structure 100c is completed. The semiconductor package structure 100c is similar to the semiconductor package structure 100a ( Figure 1C ) is that the material of the dielectric layer 127b and the shape of the sidewall of the dielectric layer 127b located on the edge of the wafer 18 are different from the material and the shape of the dielectric layer 27. Other structural characteristics of the semiconductor package structure 100c are substantially the same as those of the semiconductor package structure 100a.

[0101] FIG. 5A to FIG. 5C 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor package structure according to a fourth embodiment of the present disclosure. The fourth embodiment differs from the third embodiment in that a mask layer 132 is formed in the gap 30 between the protrusions 129, and the mask layer 132 does not cover the top surface of the protrusion 129. In other words, the mask layer 132 is formed on the main body 128, covering the top surface of the main body 128 and the sidewalls of the protrusion 129.

[0102] Reference Figure 4A and Figure 5A After forming the dielectric material layer 127 on the wafer 18 and the dies 19a, 19b and 19c, a mask layer 132 is formed on the main body 128 of the dielectric material layer 127 and the side of the protrusion 129. The structural characteristics and thickness range of the dielectric material layer 127 are similar to Figure 4A The third embodiment is shown in the figure and is substantially the same as that described in the third embodiment. The mask layer 132 is filled in the gap 30 between the protrusions 129 of the dielectric material layer 127. In some embodiments, the top surface of the mask layer 132 is slightly lower than the top surface of the protrusion 129. The material of the mask layer 132 is, for example, photoresist. The mask layer 132 is, for example, formed in the following manner: first, a photoresist material layer is formed above the dielectric material layer 127 by spin coating. The photoresist material layer covers the sidewalls and the top surface of the dielectric material layer 127. Thereafter, a portion of the photoresist material layer located on the top surface of the dielectric material layer 127 is removed so that the top surface of the protrusion 129 is exposed. The removal method of the photoresist material layer includes an etching process, such as an etch-back process.

[0103] Reference Figure 5A and Figure 5B , remove some portions of the protrusion 129 and a portion of the mask layer 132 to form a dielectric material layer 127a and a mask layer 132a. The dielectric material layer 127a includes a main body 128 and a plurality of protrusions 129b. In some embodiments, the removal method includes an etching process, such as a blanket etching process. That is, the removal process is performed to reduce the thickness of the protrusion 129 and the mask layer 132. In some embodiments, the thickness of the protrusion 129b is reduced from T10 to T11. In some embodiments, the thickness of the mask layer 132a is reduced from T3 to T4. The top surfaces of the dies 19a, 19b, and 19c are covered by the protrusion 129b, and the top surface of the main body 128 of the dielectric material layer 127a is covered by the mask layer 132a and the protrusion 129b.

[0104] Reference Figure 5B and Figure 5C , remove the mask layer 132a. Remove the protrusion 129b of the dielectric material layer 127a and a portion of the main body 128 and some portions of the tube cores 19a, 19b and 19c to form a dielectric layer 127b, and the top surface of the dielectric layer 127b is substantially flush with the second surface 26b of the tube cores 19a, 19b and 19c. The removal method includes a planarization process, such as a chemical mechanical polishing process. At this point, the semiconductor package structure 100d is completed. The structural characteristics of the semiconductor package structure 100d are substantially the same as the structural characteristics of the semiconductor package structure 100c, and will not be repeated here.

[0105] FIG. 6A to FIG. 6D 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor package structure according to a fifth embodiment of the present disclosure. The fifth embodiment differs from the third embodiment in that a hard mask 35 a is formed on the sidewalls of the protrusion 129 of the dielectric material layer 127 and on the top surface of the body 128 .

[0106] Reference Figure 4A and Fig. 6A After forming a dielectric material layer 127 over the wafer 18 and the dies 19a, 19b, and 19c, a hard mask layer 35 is formed on the dielectric material layer 127. In some embodiments, the hard mask layer 35 is a conformal hard mask layer. That is, the hard mask layer 35 has a substantially equal thickness extending along the area on which the hard mask layer 35 is formed. In some embodiments, the thickness T6 of the hard mask layer 35 ranges from 100 angstroms to 3000 angstroms. The material of the hard mask layer 35 is different from the material of the dielectric material layer 127. In some embodiments, the material of the hard mask layer 35 includes silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In an alternative embodiment, the hard mask layer 35 includes a conductive material. The conductive material includes a metal, a metal nitride, or a combination of a metal and a metal nitride. In some embodiments, the hard mask layer 35 includes titanium nitride, tantalum nitride, titanium, tantalum, boron nitride, or a combination thereof. The hard mask layer 35 is formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD) or the like.

[0107] Reference Fig. 6A and Figure 6B , a portion of the top surface of the hard mask layer 35 covering the protrusion 129 of the dielectric material layer 127 is removed to expose the top surface of the protrusion 129 and form a hard mask 35a. In some embodiments, the hard mask 35a is also referred to as a mask layer. The removal method includes a planarization process, such as a chemical mechanical polishing process.

[0108] Reference Figure 6B , the hard mask 35a covers the top surface of the main body 128 of the dielectric material layer 127 and the sidewalls of the protrusion 129. In some embodiments, the top surface of the hard mask 35a is substantially flush with the top surface of the protrusion 129. In some embodiments, the hard mask 35a located on the sidewall of the protrusion 129 is arc-shaped, and a portion of the protrusion 129 is covered by the hard mask 35a.

[0109] Reference Figure 6B and Figure 6C , using the hard mask 35a as a mask to remove some parts of the protrusion 129, and forming a dielectric material layer 127a including a main body 128 and a plurality of remaining parts 129c. In some embodiments, the second surfaces 26b of the tube cores 19a, 19b and 19c are exposed, but the present disclosure is not limited to this. The removal method includes, for example, an etching process. The etching process can be an anisotropic etching process or an isotropic etching process. In some embodiments, the etching process includes a wet etching process, a dry etching process or a combination thereof.

[0110] Reference Figure 6C In some embodiments, the second surfaces 26b of the dies 19a, 19b, and 19c are completely exposed. The remaining portion 129c is located on the main body 128 and is surrounded and covered by the hard mask 35a. In some embodiments, the remaining portion 129c is arc-shaped and has vertical sidewalls and arc-shaped sidewalls. The arc-shaped sidewalls are in contact with the hard mask 35a and are covered by the hard mask 35a, but the present disclosure is not limited to this. In some other embodiments, both sidewalls of the remaining portion 129c are not vertical. The top surface of the main body 128 is covered by the hard mask 35a and the remaining portion 129c.

[0111] Reference Figure 6C and Fig.6D , remove the hard mask 35a, the remaining portion 129c of the dielectric material layer 127, a portion of the main body 128, and some portions of the tube cores 19a, 19b, and 19c to form a dielectric layer 127b, and the top surface of the dielectric layer 127b is substantially flush with the second surface 26b of the tube cores 19a, 19b, and 19c. In some embodiments, the hard mask 35b remains on the edge of the dielectric layer 127b. The removal method includes a planarization process, such as a chemical mechanical polishing process. At this point, the semiconductor package structure 100e is completed. Except that the hard mask 35b may remain on the edge of the dielectric layer 127b, other structural characteristics of the semiconductor package structure 100e are similar to those of the semiconductor package structures 100c / 100d.

[0112] Figure 7 is a flow chart of a method for forming a semiconductor package structure according to some embodiments of the present disclosure. Figure 7 In step S100, the die is bonded to the wafer. In step S102, a dielectric material layer is formed on the wafer and the die, wherein the dielectric material layer covers the top surface and sidewalls of the die. In step S104, at least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die to expose the top surface of the die and form a dielectric layer located on the side of the die, wherein the dielectric layer surrounds and covers the sidewalls of the die.

[0113] In the third to fifth embodiments of the present disclosure, when some parts of the protrusion 129 are removed, the main body 128 of the dielectric material layer 127 is covered and protected by the mask layer 32 / 132 or the hard mask 35a, and the remaining part 129a / 129b / 129c remains. Therefore, the problem of damage or depression of the main body 128 of the dielectric material layer 127 is avoided or reduced, especially the damage to the main body 128 on the edge of the wafer 18 is avoided or reduced. In the first embodiment of the present disclosure, since the protrusion 29 is a continuous layer covering the main body 28, the main body 28 is not damaged when the protrusion 29 is removed or during the planarization process. Therefore, the sidewalls of the tube core 19a, 19b and 19c are always covered and protected by the dielectric material layer 127a / 27 during the planarization process. Thereby, damage to the tube core 19a, 19b and 19c is avoided or reduced, that is, the morphology degradation of the edge tube core is avoided or reduced. In these embodiments, all of the dies 19a, 19b, and 19c located on the wafer 18 are active dies. Therefore, all of the active dies are achieved without chip area penalty loss.

[0114] On the other hand, in the embodiment of the present disclosure, the top corners of the tube cores 19a, 19b and 19c are covered and protected by the dielectric material layer 27 / 127 / 127a, avoiding or reducing the top corner rounding problem that may occur during the removal or planarization or thinning process.

[0115] In some embodiments of the present disclosure, after forming the semiconductor package structure 100a / 100b / 100c / 100d / 100e, subsequent processes may be performed to stack more layers of dies or devices on the semiconductor package structure 100a / 100b / 100c / 100d / 100e to form a multi-layer stacked chip-on-wafer structure. Through vias (e.g., through silicon vias (TSV), through insulator vias (TIV), through dielectric vias (TDV), the like, or a combination thereof) may be formed to electrically connect the dies or devices on the semiconductor package structure 100a / 100b / 100c / 100d / 100e to the dies 19a / 19b / 19c of the wafer 18. In some embodiments, after forming the multi-layer stacked chip-on-wafer structure, a die sawing process is performed to singulate the stacked structure.

[0116] In an embodiment of the present disclosure, the top surface of the dielectric layer around the tube core is coplanar with the top surface of the tube core. In other words, the dielectric layer and the dispersed tube core have the same plane. Therefore, more layers of tube cores or devices can be further stacked on the semiconductor package structure formed above. In some embodiments, two or more layers of tube cores are allowed to be stacked on a wafer.

[0117] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package structure includes the following steps: bonding a tube die to a wafer; forming a dielectric material layer on the wafer and the tube die; the dielectric material layer covers the top surface and sidewalls of the tube die; performing at least one planarization process to remove a portion of the dielectric material layer and a portion of the tube die to expose the top surface of the tube die and form a dielectric layer located on the side of the tube die; the dielectric layer surrounds and covers the sidewalls of the tube die.

[0118] In the above method of manufacturing a semiconductor package structure, the die and the wafer are arranged face to face.

[0119] In the above method for manufacturing a semiconductor package structure, the die and the wafer are bonded by hybrid bonding, fusion bonding or a combination thereof or connected by a plurality of connectors.

[0120] In the above method for manufacturing a semiconductor package structure, the dielectric material layer is formed by a molding compound, a molding underfill, a resin or a combination thereof through a molding process, a molded underfill (MUF) process or a combination thereof.

[0121] In the above method for manufacturing a semiconductor package structure, the dielectric material layer is formed by a deposition process using an inorganic material, an organic material or a combination thereof.

[0122] In the above method for manufacturing a semiconductor package structure, the at least one planarization process includes a first planarization process and a second planarization process. The first planarization process is performed to remove the dielectric material layer on the top surface of the tube core. And the second planarization process is performed to remove a portion of the dielectric material layer located on the side of the tube core and some portions of the tube core.

[0123] According to an alternative embodiment of the present disclosure, a method for manufacturing a semiconductor package structure includes the following steps. A plurality of tube cores are bonded to a wafer. A dielectric material layer is formed on the wafer and on the plurality of tube cores to cover the side walls and top surfaces of the plurality of tube cores. The dielectric material layer includes a main body portion located at the side of the tube core and a plurality of protrusions located on the plurality of tube cores. A mask layer is formed to cover at least the side walls of the plurality of protrusions and the top surface of the main body portion. A removal process is performed using the mask layer as a mask to partially remove the plurality of protrusions of the dielectric material layer, and the remaining plurality of protrusions form a plurality of residual portions. The mask layer and the plurality of residual portions are removed. A portion of the main body portion of the dielectric material layer and some portions of the plurality of tube cores are removed to form a dielectric layer, the top surface of which is flush with the top surfaces of the plurality of tube cores.

[0124] In the above-mentioned method for manufacturing a semiconductor packaging structure, the bottom width of one of the multiple protrusions is greater than the width of one of the multiple tube cores, and the one of the multiple protrusions covers the top surface of the one of the multiple tube cores and a portion of the top surface of the main body.

[0125] In the above method for manufacturing a semiconductor package structure, a plurality of gaps are formed between the plurality of protrusions of the dielectric material layer, and the mask layer is filled in the plurality of gaps.

[0126] In the above method for manufacturing a semiconductor package structure, the mask layer further extends to cover some portions of the top surfaces of the plurality of protrusions.

[0127] In the above method for manufacturing a semiconductor package structure, the plurality of remaining portions cover edges of the plurality of dies and a portion of the top surface of the main body portion.

[0128] In the above method for manufacturing a semiconductor package structure, the plurality of remaining portions, a portion of the main portion of the dielectric material layer, and some portions of the plurality of dies are removed by a planarization process.

[0129] In the above method for manufacturing a semiconductor package structure, the removal process removes some portions of the protrusions and a portion of the mask layer through a blanket etching process, so that the thickness of the plurality of protrusions and the thickness of the mask layer are reduced.

[0130] In the above method for manufacturing a semiconductor package structure, after performing the blanket etching process, the remaining mask layer is stripped off, and the remaining portion, a portion of the main body portion, and some portions of the plurality of dies are removed by a planarization process.

[0131] In the above method for manufacturing a semiconductor package structure, the mask layer is a hard mask, and the hard mask is conformally formed on the sidewalls of the plurality of protrusions and on the top surface of the main body.

[0132] In the above method for manufacturing a semiconductor package structure, after the removal process, the hard mask, the remaining portion, a portion of the main portion, and some portions of the die are removed through a planarization process.

[0133] According to an alternative embodiment of the present disclosure, a method for manufacturing a semiconductor package structure includes the following steps. A die and a dummy die are bonded to a wafer. A dielectric material layer is formed on the wafer to cover the top surface and sidewalls of the die and the top surface and sidewalls of the dummy die. A portion of the dielectric material layer and a portion of the die are removed by performing at least one planarization process. During the at least one planarization process, the sidewalls of the die are protected laterally by the dielectric material layer and the dummy die.

[0134] In the above method for manufacturing a semiconductor package structure, the dummy die is bonded to the side of the die and is closer to the edge of the wafer than the die.

[0135] In the above method for manufacturing a semiconductor package structure, the at least one planarization process includes: performing a first planarization process until the top surface of the die is exposed; and performing a second planarization process to reduce the thickness of the die.

[0136] In the above method for manufacturing a semiconductor package structure, after performing the second planarization process, a portion of the top surface of the dummy die is inclined.

[0137] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Electrically bonding a plurality of first dies to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, wherein the plurality of first dies are discrete dies separated from each other, and the plurality of second dies are connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer and the plurality of first dies, wherein the dielectric material layer covers top surfaces and sidewalls of the plurality of first dies; as well as performing at least one planarization process to remove a portion of the dielectric material layer and some portions of the plurality of first dies so that the top surfaces of the plurality of first dies are exposed and a dielectric layer is formed on the sides of the plurality of first dies, The dielectric layer surrounds and covers the sidewalls of the plurality of first dies. 2 . The method for manufacturing a semiconductor package structure according to claim 1 , wherein the plurality of first dies and the wafer are arranged face to face. 3 . The method for manufacturing a semiconductor package structure according to claim 1 , wherein the plurality of first dies are bonded to the wafer by hybrid bonding, fusion bonding, or a combination of the hybrid bonding and the fusion bonding.

4. The method for manufacturing a semiconductor package structure according to claim 1, wherein the dielectric material layer is formed by a molding compound, a molding underfill, a resin, or a combination of the molding compound, the molding underfill, and the resin through a molding process, a molding underfill process, or a combination of the molding process and the molding underfill process. 5 . The method for manufacturing a semiconductor package structure according to claim 1 , wherein the dielectric material layer is formed of an inorganic material, an organic material, or a combination of the inorganic material and the organic material through a deposition process.

6. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The at least one planarization process includes a first planarization process and a second planarization process; performing the first planarization process to remove the dielectric material layer on the top surfaces of the plurality of first dies; as well as The second planarization process is performed to remove a portion of the dielectric material layer located at the sides of the plurality of first dies and some portions of the plurality of first dies. 7 . The method for manufacturing a semiconductor package structure according to claim 1 , wherein the wafer is not a carrier.

8. The method for manufacturing a semiconductor package structure according to claim 1, wherein a first portion of the dielectric layer located on the edge of the wafer has a first thickness, a second portion of the dielectric layer located between the plurality of first dies has a second thickness, and the first thickness is greater than the second thickness.

9. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Bonding a plurality of first dies to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, wherein the plurality of first dies are discrete dies separated from each other, and the plurality of second dies are connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer and on the plurality of first tube cores to cover the sidewalls and top surfaces of the plurality of first tube cores, wherein the dielectric material layer comprises a main body portion located at the sides of the plurality of first tube cores and a plurality of protrusions located on the plurality of first tube cores; forming a mask layer, wherein the mask layer at least covers the side walls of the plurality of protrusions and the top surface of the main body; performing a removal process using the mask layer as a mask to partially remove the plurality of protrusions of the dielectric material layer, and the remaining plurality of protrusions form a plurality of remaining portions; removing the mask layer and the plurality of remaining portions; as well as A portion of the main body of the dielectric material layer and some portions of the multiple first tube cores are removed to form a dielectric layer, wherein the dielectric layer has a top surface flush with the top surfaces of the multiple first tube cores so that the top surfaces of the multiple first tube cores are exposed, and the dielectric layer is located on the sides of the multiple first tube cores, wherein the dielectric layer surrounds and covers the side walls of the multiple first tube cores.

10. The method for manufacturing a semiconductor package structure according to claim 9, wherein a bottom width of one of the plurality of protrusions is greater than a width of one of the plurality of first tube cores, and the one of the plurality of protrusions covers the top surface of the one of the plurality of first tube cores and a portion of the top surface of the main body.

11. The method for manufacturing a semiconductor package structure according to claim 10, wherein The plurality of protrusions of the dielectric material layer have a plurality of gaps between them; and The mask layer fills in the plurality of gaps. 12 . The method for manufacturing a semiconductor package structure according to claim 11 , wherein the mask layer further extends to cover portions of the top surfaces of the plurality of protrusions. 13 . The method according to claim 12 , wherein the plurality of remaining portions cover edges of the plurality of first dies and a portion of the top surface of the body portion. 14 . The method for manufacturing a semiconductor package structure according to claim 13 , wherein the plurality of remaining portions, a portion of the main portion of the dielectric material layer, and some portions of the plurality of first dies are removed by a planarization process. 15 . The method for manufacturing a semiconductor package structure according to claim 11 , wherein the removing process removes some portions of the protrusions and a portion of the mask layer by a blanket etching process, so that the thickness of the plurality of protrusions and the thickness of the mask layer are reduced. 16 . The method for manufacturing a semiconductor package structure according to claim 15 , wherein after performing the blanket etching process, the remaining mask layer is stripped off, and the remaining portion, a portion of the main body portion and some portions of the plurality of first dies are removed by a planarization process. 17 . The method for manufacturing a semiconductor package structure according to claim 11 , wherein the mask layer is a hard mask, and the hard mask is conformally formed on sidewalls of the plurality of protrusions and on the top surface of the body portion. 18 . The method for manufacturing a semiconductor package structure according to claim 17 , wherein after the removing process, the hard mask, the remaining portion, a portion of the body portion, and some portions of the plurality of first dies are removed by a planarization process.

19. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Bonding a plurality of first dies and a dummy die to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, the plurality of second dies being connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer to cover the top surfaces and sidewalls of the plurality of first dies and the top surface and sidewalls of the dummy die; as well as removing a portion of the dielectric material layer and a portion of the plurality of first dies by performing at least one planarization process, wherein during the at least one planarization process, the sidewalls of the plurality of first dies are laterally protected by the dielectric material layer and the dummy dies, Wherein the at least one planarization process comprises: performing a first planarization process until the top surfaces of the plurality of first dies are exposed; as well as performing a second planarization process to reduce the thickness of the plurality of first dies, After performing the second planarization process, the dielectric material layer forms a dielectric layer, a portion of the top surface of the virtual tube core is inclined, the top surfaces of the multiple first tube cores and the virtual tube core are exposed, and the dielectric layer is located on the sides of the multiple first tube cores and the virtual tube core, wherein the dielectric layer surrounds and covers the side walls of the multiple first tube cores and the virtual tube core. 20 . The method for manufacturing a semiconductor package structure according to claim 19 , wherein the dummy die is bonded on a side of the plurality of first dies and closer to an edge of the wafer than the plurality of first dies.

21. A method for manufacturing a semiconductor package structure, comprising: Bonding a plurality of first dies to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, wherein the plurality of first dies are discrete dies separated from each other, and the plurality of second dies are connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer and the plurality of first tube cores to cover the sidewalls and top surfaces of the plurality of first tube cores, wherein the dielectric material layer comprises a main body portion located at the sides of the plurality of first tube cores and a plurality of protrusions located on the plurality of first tube cores, the plurality of protrusions being spaced apart from each other; selectively removing a first portion of the plurality of protrusions while protecting the main body of the dielectric material layer; as well as The second portion of the plurality of protrusions is removed to form a dielectric layer so that the top surfaces of the plurality of first tube cores are exposed, and the dielectric layer is located on the sides of the plurality of first tube cores, wherein the dielectric layer surrounds and covers the side walls of the plurality of first tube cores. 22 . The method for manufacturing a semiconductor package structure according to claim 21 , wherein when the first portion of the plurality of protrusions is selectively removed, the main portion of the dielectric material layer is protected by the second portion of the plurality of protrusions and a mask layer. 23 . The method for manufacturing a semiconductor package structure according to claim 22 , wherein the mask layer is formed after forming the dielectric material layer to cover a top surface of the body portion. 24 . The method for manufacturing a semiconductor package structure according to claim 22 , further comprising removing the mask layer after selectively removing the first portion of the plurality of protrusions. 25 . The method for manufacturing a semiconductor package structure according to claim 21 , wherein selectively removing the first portion of the plurality of protrusions comprises performing an etching process, and removing the second portion of the plurality of protrusions comprises performing a chemical mechanical polishing process. 26 . The method for manufacturing a semiconductor package structure according to claim 21 , wherein after selectively removing the first portion of the plurality of protrusions and before removing the second portion of the plurality of protrusions, top surfaces of the plurality of first dies are partially exposed. 27 . The method for manufacturing a semiconductor package structure according to claim 21 , wherein after selectively removing the first portion of the plurality of protrusions, at least top corners of the plurality of first dies are covered by the second portion of the plurality of protrusions.

28. The method for manufacturing a semiconductor package structure according to claim 21, further comprising: After removing the second portion of the plurality of protrusions, portions of the body portion of the dielectric material layer and portions of the plurality of first dies are removed.

29. A method for manufacturing a semiconductor package structure, comprising: bonding a plurality of first dies to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, wherein the plurality of second dies are connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer to cover top surfaces and sidewalls of the plurality of first dies; performing a removal process to remove a portion of the dielectric material layer to expose at least a portion of the top surfaces of the plurality of first dies, wherein after performing the removal process, the dielectric material layer includes a protrusion located above the top surfaces of the plurality of first dies; as well as A planarization process is performed to make the top surfaces of the multiple first tube cores and the top surface of the dielectric material layer planar, thereby forming a dielectric layer located on the sides of the multiple first tube cores, so that the top surfaces of the multiple first tube cores are exposed, and the dielectric layer is located on the sides of the multiple first tube cores, wherein the dielectric layer surrounds and covers the side walls of the multiple first tube cores. 30 . The method for manufacturing a semiconductor package structure according to claim 29 , wherein the protrusion covers top corners of the plurality of first dies. 31 . The method for manufacturing a semiconductor package structure according to claim 29 , wherein after performing the removal process, the top surfaces of the plurality of first dies are completely exposed, and the protrusions are adjacent to top corners of the plurality of first dies.

32. The method for manufacturing a semiconductor package structure according to claim 29, wherein The dielectric material layer includes a main body portion located at sides of the plurality of first tube cores and a protrusion located above the plurality of first tube cores and the main body portion; and The protrusion covers the top surfaces of the plurality of first dies and a portion of the body portion.

33. The method for manufacturing a semiconductor package structure according to claim 32, wherein performing the removing process comprises: forming a mask to cover the top surface of the main body and the sidewalls of the protrusion; as well as performing an etching process using the mask as an etching mask to remove the portion of the dielectric material layer while the main body portion is protected by the mask, wherein the portion of the dielectric material layer is a first portion of the protrusion and a second portion of the protrusion remains to form the protrusion, the mask covering the protrusion; and The planarization process removes a portion of the protrusion and the body of the dielectric material layer and a portion of the substrate of the plurality of first dies. 34 . The method for manufacturing a semiconductor package structure according to claim 33 , wherein the planarization process further removes a portion of the mask covering the protrusion and the portion of the main body, and other portions of the mask remain on an edge of the dielectric layer. 35 . The method for manufacturing a semiconductor package structure according to claim 33 , wherein the mask is formed to also cover a portion of a top surface of the protrusion, and the method further comprises removing the mask before performing the planarization process. 36 . The method for manufacturing a semiconductor package structure according to claim 33 , wherein during the planarization process, a removal rate of the substrate is greater than a removal rate of the dielectric material layer.

37. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Bonding a plurality of first dies to a wafer, wherein the wafer is a semiconductor wafer having a plurality of devices formed therein, the wafer comprising a continuous semiconductor substrate having a plurality of die regions, and the wafer comprising a plurality of second dies embedded in the plurality of die regions of the wafer, the plurality of second dies being electrically connected to the plurality of first dies, wherein the plurality of first dies are discrete dies separated from each other, and the plurality of second dies are connected to each other and embedded in the wafer; forming a dielectric material layer on the wafer to cover the plurality of first tube cores, wherein the dielectric material layer comprises a main body portion located at the sides of the plurality of first tube cores and a plurality of protrusions located on the plurality of first tube cores; forming a mask layer on the main body and sides of the plurality of protrusions; performing a removal process to reduce the thickness of the plurality of protrusions and the thickness of the mask layer, thereby forming a plurality of remaining protrusions and a remaining mask layer covering the plurality of first dies and the body portion; removing the remaining mask; as well as The remaining protrusions of the dielectric material layer and a portion of the main body are removed to form a dielectric layer so that the top surfaces of the first tube cores are exposed, and the dielectric layer is located on the sides of the first tube cores, wherein the dielectric layer surrounds and covers the side walls of the first tube cores. 38 . The method for manufacturing a semiconductor package structure according to claim 37 , wherein during the removal process, a reduced thickness of the protrusion is greater than a reduced thickness of the mask layer. 39 . The method for manufacturing a semiconductor package structure according to claim 37 , wherein the mask layer is formed to have a top surface lower than top surfaces of the plurality of protrusions. 40 . The method for manufacturing a semiconductor package structure according to claim 37 , wherein the remaining mask layer is formed to have a top surface higher than top surfaces of the plurality of remaining protrusions. 41 . The method for manufacturing a semiconductor package structure according to claim 37 , wherein during the removal process, the main body portion is protected by the mask layer and edges of the plurality of protrusions. 42 . The method for manufacturing a semiconductor package structure according to claim 37 , wherein the removing process removes a portion of the plurality of protrusions and a portion of the mask layer simultaneously. 43 . The method for manufacturing a semiconductor package structure according to claim 42 , wherein the remaining mask layer is removed before removing the plurality of remaining protrusions.

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