Switched capacitor DC-DC converter including external flying capacitor and internal flying capacitor

Abstract

The present invention relates to an integrated circuit switched capacitor DC-DC converter, comprising a first switched capacitor converter based on at least one external flying capacitor and a second switched capacitor converter comprising a plurality of internal flying capacitors. A controller is configured to select a converter topology of the first switched capacitor converter and to select a converter topology of the second switched capacitor converter.

Description

Technical Field

[0001] The present invention relates to an integrated circuit switched capacitor DC-DC converter, comprising a first switched capacitor converter based on at least one external flying capacitor and a second switched capacitor converter comprising a plurality of internal flying capacitors. A controller is configured to select a converter topology of the first switched capacitor converter and a converter topology of the second switched capacitor converter. Background Art

[0002] Switched capacitor DC-DC power converters are known in the art and have been used in various types of portable communication devices, such as head-mounted hearing devices. Switched capacitor DC-DC power converters are used to convert a DC input voltage from an energy source or power supply (e.g., a rechargeable battery) of a portable communication device to a higher or lower DC output voltage suitable for powering various types of integrated circuits and other active components. Compared to inductor-based counterparts, switched capacitor DC-DC power converters have certain attractive characteristics - such as relatively low EMI levels, because there is no energy stored in the magnetic field of the inductor. Switched capacitor DC-DC power converters can have small size and high energy conversion efficiency. Different topologies of switched capacitor DC-DC power converters can provide DC voltage increase (i.e., boost) and DC voltage reduction (i.e., buck) with topology-dependent optimal voltage conversion ratios (e.g., 1:2 or 1:3 boost conversion, and 2:1 and 3:1 buck conversion).

[0003] Switched capacitor DC-DC converters are ideal for powering head-worn hearing devices, where the compact size of the housing or custom casing and small battery capacity often severely limit the size of the power circuit, power conversion efficiency, and electromagnetic radiation.

[0004] However, maintaining the high energy conversion efficiency of existing switched capacitor DC-DC converters remains a challenge in applications where the DC input voltage varies over a large voltage range and similarly in applications where the load power or load current exhibits large variations. With respect to the varying levels of the DC input voltage of the SC DC-DC converter, many types of rechargeable battery power supplies (e.g., lithium-ion battery cells) exhibit large voltage variations, such as from about 4.2V in a fully charged state to about 3.0V in a discharged state. With respect to the varying load power, this may be caused by fluctuations in power consumption of various types of consumers (e.g., circuit blocks or modules, such as flash memory, RF transceivers, etc.) powered by the switched capacitor DC-DC converter. Some of these consumers may inherently exhibit highly variable power consumption (e.g., audio power amplifiers of hearing devices) or exhibit highly variable power consumption because they are only temporarily activated. The latter type of consumer may be in sleep mode / power-off state for long periods of time, which are interrupted by relatively short bursts of activity, resulting in corresponding bursts of power consumption.

[0005] A fully integrated switched capacitor DC-DC converter is generally capable of achieving high energy conversion efficiency at a small output power level, because a large number of flying capacitors and a correspondingly large number of converter topologies can be easily designed in an integrated format, wherein the flying capacitor is integrally formed on a semiconductor die or circuit, i.e., on-chip. A large number of converter topologies means that the inherent energy efficiency of the switched capacitor DC-DC converter can be kept high despite large variations in the DC input voltage. However, a fully integrated switched capacitor DC-DC converter is generally unable to support large load power levels, because the capacitance of the integrated flying capacitor is limited and there are practical limitations on the switching frequency. On the other hand, it is generally impractical to achieve high inherent energy efficiency in a switched capacitor DC-DC converter based on an external flying capacitor (i.e., an off-chip flying capacitor). It is impractical to provide a large number of separate flying capacitors and associated wire routing and interconnect pins on a carrier board, particularly for compact portable communication devices such as mobile phones, head-mounted hearing devices, and the like.

[0006] Therefore, there remains a need in the art for a switched capacitor DC-DC converter having improved performance characteristics, such as smaller size and better adaptability to varying load conditions and varying DC input voltages, and in particular, an improved switched capacitor DC-DC converter that is capable of providing large load power bursts at normal or ordinary and typically much smaller load power levels without compromising energy conversion efficiency. Summary of the invention

[0007] A first aspect of the invention relates to an integrated circuit switched capacitor DC-DC converter, comprising a first switched capacitor converter, comprising: a DC input for receiving a battery supply voltage; a first switch array, comprising a plurality of individually controllable semiconductor switches, which can be connected to at least one external flying capacitor to form one or more individual converter topologies of the first switched capacitor converter for converting the battery supply voltage to an intermediate voltage. The integrated circuit switched capacitor DC-DC converter also includes a second switched capacitor converter, comprising: an input connected to an intermediate voltage; a second switch array, comprising a plurality of individually controllable semiconductor switches and a plurality of internal flying capacitors (e.g., two, three or four), which can be configured to form a plurality of individual converter topologies for converting the intermediate voltage to a DC output voltage. The integrated circuit switched capacitor DC-DC converter also includes a controller, which is connected to the respective control terminals of the individually controllable semiconductor switches of the first and second switch arrays to select the converter topology of the first switched capacitor converter and select the converter topology of the second switched capacitor converter.

[0008] The battery supply voltage may be supplied by a rechargeable battery cell or (one or more) disposable battery cells providing the battery supply voltage to the DC input of the integrated circuit switched capacitor DC-DC converter. The one or more battery cells may, for example, include disposable zinc-air (Zn-Air) batteries or may include at least one rechargeable lithium-ion (Li-Ion) battery cell. Lithium-ion battery cells provide a nominal battery voltage of around 4.0V, but the battery voltage varies significantly from about 4.2V in a fully charged state to about 3.0V in a discharged state. Other types of rechargeable battery cells often exhibit similar battery voltage variations depending on the state of charge of the battery.

[0009] The integrated circuit switched capacitor DC-DC converter can be configured as a buck converter. The first switched capacitor converter can be configured to reduce the battery voltage in a 2:1, 3:2 or 3:1 manner by appropriately selecting the topology of the first switched capacitor converter by the controller. The second switched capacitor converter can include a large number of selectable converter topologies, such as those specified under n=3 in Table 1. The controller can be configured to determine and select a specific converter topology among a plurality of selectable converter topologies, which exhibits the highest inherent energy efficiency at the intermediate voltage provided by the first converter and the desired DC output voltage, as discussed in detail below with further reference to the accompanying drawings. Therefore, the controller can be configured to dynamically switch between different topologies of the second switched capacitor DC-DC converter in response to changes in the battery supply voltage and / or changes in the DC output voltage to repeatedly maximize the inherent energy efficiency of the second switched capacitor DC-DC converter. Certain embodiments of the controller may be further configured to switch between different topologies of the second switched capacitor DC-DC converter in response to changes in the intermediate voltage. This can be achieved by comparing the intermediate voltage with a specific threshold voltage and switching the topology in which the intermediate voltage exceeds the threshold voltage.

[0010] Those skilled in the art will appreciate that the first and second switched capacitor converters of the integrated circuit switched capacitor DC-DC converter are connected in series from a DC input receiving a battery supply voltage to a DC output voltage because the intermediate voltage output by the first switched capacitor converter is connected to the input of the second switched capacitor converter. Such a series connection means that the first switched capacitor converter shields the second switched capacitor converter from receiving the full battery voltage level. This means that the plurality of controllable semiconductor switches of the second converter can be implemented as standard low voltage semiconductor transistors rather than high voltage devices, the advantages of which are discussed in further detail below with reference to the accompanying drawings.

[0011] The intermediate voltage at the input of the second switched capacitor DC-DC converter may not be connected to any pad or terminal of the integrated circuit or semiconductor die or chip, i.e. not accessible from the outside. Thus, this embodiment operates without any off-chip smoothing capacitor coupled to the intermediate voltage, resulting in a beneficial reduction in external components and chip area.

[0012] At least one external flying capacitor of the first switched capacitor converter is external, i.e., off-chip, relative to the integrated circuit that maintains the remaining circuits of the switched capacitor DC-DC converter. Therefore, at least one external flying capacitor can be arranged on a carrier, such as a single layer of a multilayer printed circuit board (PCB) that maintains the integrated circuit. Multiple internal flying capacitors of the second switched capacitor converter are integrated on the integrated circuit, i.e., integrated on a semiconductor die or chip. The second switched capacitor converter may, for example, include more than two, three, four, or five internal flying capacitors. The integrated characteristics of multiple internal flying capacitors often limit the maximum capacitance of the flying capacitor, due to the relatively low capacitance per area or capacitance density available on the integrated circuit, as discussed in further detail below with reference to the accompanying drawings. However, due to the reasons discussed above, a large number of flying capacitors means that the inherent energy efficiency of the second switched capacitor DC-DC converter can be maintained high under large changes in the DC input voltage and / or changes in the DC output voltage.

[0013] According to one embodiment of an integrated circuit switched capacitor DC-DC converter, a controller is configured to: directly or indirectly determine a state of charge of at least one external flying capacitor; compare the state of charge to a predetermined charge criterion; and in response to meeting the predetermined charge criterion, recharge the at least one external flying capacitor via a first switch array. The controller may be configured to: recharge the at least one external flying capacitor by connecting the at least one external flying capacitor between a DC input providing a battery supply voltage and an input of a second switched capacitor converter by switching respective states of a first pair and a second pair of individually controllable semiconductor switches of the first switch array, as discussed in further detail below with reference to the accompanying drawings.

[0014] According to one embodiment of the integrated circuit switched capacitor DC-DC converter, the controller is configured to recharge at least one external flying capacitor at a default or minimum switching frequency, for example, above 16 kHz, regardless of a predetermined state of charge, to set a lower limit on the switching frequency of the first switched capacitor converter. By selecting a minimum switching frequency above the audio frequency band, for example, above 16 kHz or above 20 kHz, the controller prevents switching frequency noise on the DC output voltage and other power rails from leaking into audio signals of various types of audio processing circuits that may be powered by the integrated circuit switched capacitor DC-DC converter.

[0015] The integrated circuit switched capacitor DC-DC converter preferably includes a clock generator that generates a clock signal and derives at least a pair of non-overlapping clock phases therefrom for controlling the state switching of a plurality of individually controllable semiconductor switches of each of the first and second switch arrays. In some embodiments, even though the frequency of the non-overlapping clock phases of the first switch array may be significantly lower than the frequency of the non-overlapping clock phases of the second switch array, the individually controllable semiconductor switches of the first converter portion and the individually controllable semiconductor switches of each of the first and second switch arrays may be driven by synchronized non-overlapping clock phases, as discussed in further detail below with reference to the accompanying drawings.

[0016] An integrated circuit switched capacitor DC-DC converter may include: a first controllable bypass switch (SWBP1) and a second controllable bypass switch (SWBP2), configured to: in a first state, connect at least one external flying capacitor in series between a DC input and a DC output voltage; in a second state, connect at least one external flying capacitor between a negative supply rail and the DC output voltage, thereby bypassing the second switched capacitor converter.

[0017] The first and second controllable bypass switches, i.e., bypass circuits, allow the controller to switch the switched capacitor DC-DC converter between two different operating modes. The first operating mode can be considered a normal operating mode, wherein the output of the first switched capacitor converter essentially charges the input of the second switched capacitor converter, and the second operating mode can be considered a "high power" mode, wherein the output of the first switched capacitor converter essentially charges the DC output voltage directly. The high power mode enables this embodiment of the switched capacitor DC-DC converter to provide large load power bursts without compromising energy conversion efficiency at normal or ordinary load power levels, as discussed in further detail below with reference to the accompanying drawings.

[0018] The first controllable bypass switch can be configured to selectively connect and disconnect a first terminal of at least one external flying capacitor to and from the DC output voltage according to a first switch control signal provided by the controller, and the second controllable bypass switch (SWBP2) is configured to selectively connect and disconnect a second terminal of at least one external flying capacitor to and from the DC output voltage according to a second switch control signal provided by the controller.

[0019] According to another embodiment, the controller is configured to: generate a first switch control signal for a first pair of individually controllable semiconductor switches synchronously with a first clock phase (p1) of a clock signal; and generate a second switch control signal for a second pair of individually controllable semiconductor switches synchronously with a second clock phase (p2) of the clock signal.

[0020] The second switched capacitor converter preferably includes an output voltage regulator, for example, based on a feedback mechanism. The output voltage regulator may include: a reference voltage input for receiving a first DC reference voltage and a feedback voltage input for receiving a feedback voltage representing a DC output voltage; an error signal generator configured to combine the first DC reference voltage and the feedback voltage to determine a control signal. The controller is configured to generate respective clock phases for a plurality of individually controllable semiconductor switches of the second switch array to regulate the DC output voltage. Various exemplary control schemes that may be used by the output voltage regulator to control the DC output voltage are discussed in further detail below with reference to the accompanying drawings.

[0021] The controller may be configured to select a topology of the second switched capacitor converter such that an inherent energy efficiency of the second switched capacitor converter is maximized;

[0022] The inherent energy efficiency is η1=VCR / iVCR=Vo1 / (Vint*iVCR);

[0023] η1 = intrinsic energy efficiency of the second switched capacitor converter at the set point voltage of the DC output voltage;

[0024] VCR = voltage conversion ratio of the selected converter topology;

[0025] iVCR = ideal voltage conversion ratio;

[0026] Vint = intermediate voltage.

[0027] The total capacitance of the at least one external flying capacitor may be greater than 500 nF or greater than 2 μF; and / or the total capacitance of the plurality of internal flying capacitors (ie, on-chip capacitors) may be less than 100 nF or 22 nF—eg, less than 5 nF.

[0028] A second aspect of the invention relates to a head mounted hearing device comprising an integrated circuit switched capacitor DC-DC converter according to any of the above embodiments and at least one rechargeable battery cell, such as one or more lithium ion battery cells, connectable to a DC input to provide a battery supply voltage.

[0029] The head-mounted hearing device may include a hearing instrument or a hearing aid, such as a BTE, RIE, ITE, ITC or CIC. The hearing aid may include one or more microphones for picking up sound from the external environment of the hearing instrument and, in response, generating a first audio signal. The head-mounted hearing device may alternatively be an earphone, a receiver, a receiver, an earpiece, an earmuff or an earmuff, such as an earhook earphone, an in-ear earphone, an earmuff earphone, an earmuff earphone, a behind-the-neck earphone, a helmet earphone, a headset, etc.

[0030] Head-mounted hearing devices may include various active components and audio transducers for receiving input speech and other sound signals, processing the received sound signals, and converting the processed sound signals into corresponding output sound signals for application to the user's ears and / or transmission to a remote listener. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which:

[0032] Figure 1 a simplified schematic block diagram showing a head mounted hearing device according to any of the following embodiments of the present invention, the hearing device comprising an exemplary integrated circuit switched capacitor DC-DC converter;

[0033] Figure 2 A first simplified schematic block diagram of a first switched capacitor DC-DC converter topology and a second simplified schematic block diagram of a second switched capacitor DC-DC converter topology are shown to illustrate the background of the present invention;

[0034] Figure 3 A general electrical model of a switched capacitor DC-DC converter is shown for explaining the background of the present invention;

[0035] Figure 4 is a simplified schematic block diagram of an exemplary integrated circuit switched capacitor DC-DC converter according to an embodiment of the present invention; and

[0036] Figure 5 Various voltage waveforms at internal circuit nodes of an exemplary integrated circuit switched capacitor DC-DC converter during operation are shown. DETAILED DESCRIPTION

[0037] In the following, various exemplary embodiments of the present switched capacitor DC-DC converter are described with reference to the accompanying drawings. Those skilled in the art will appreciate that, for the sake of clarity, the drawings are schematic and simplified, and therefore only the details essential to understanding the present invention are shown, while other details are omitted. The same reference numerals represent the same elements or components throughout. Therefore, it is not necessary to describe the same elements or components in detail with respect to each of the accompanying drawings. Those skilled in the art will further appreciate that certain actions and / or steps may be described or depicted in a particular order of occurrence, and those skilled in the art will appreciate that such specificity regarding the order is not actually required.

[0038] Figure 1 A simplified schematic block diagram of an exemplary head mounted hearing device 10 according to any of the following embodiments of the present invention is shown, the hearing device 10 comprising an integrated circuit switched capacitor DC-DC converter 100. The DC input voltage input terminal of the switched capacitor DC-DC converter 100 is connected to a rechargeable battery power source V DD. The rechargeable battery power supply is connected to the hearing device circuit via the positive supply voltage terminal 19, including an integrally formed switched capacitor DC-DC converter 100. The skilled person will appreciate that the battery power supply in other embodiments of the present invention may include: a non-rechargeable battery power supply, wherein it is desired to step up or down the nominal DC voltage level provided by such a non-rechargeable battery power supply to a different DC voltage level that is more optimal (e.g., lower power consumption) for the active circuit or circuit block. The head-mounted hearing device 10 may include a hearing instrument or a hearing aid, including various types of hearing aid housing styles, such as behind-the-ear (BTE), in-the-canal (ITC), deep-in-the-canal (CIC), RIC, etc. The rechargeable battery power supply V DD At least one lithium-ion battery cell may be included, so a nominal DC input voltage Vbat of around 4.0V may be supplied to the switched capacitor DC-DC converter 100. However, the battery discharge curve of the lithium-ion battery cell results in a large variation in the DC input voltage Vbat from approximately 4.2V in a fully charged state to approximately 3.0V in a discharged state, which has several effects on the design of the switched capacitor DC-DC converter 100, as described below. The head-mounted hearing device 10 includes at least one microphone M1 that generates an audio signal in response to input sound at the device. The audio signal is amplified / buffered and digitized in an input channel that includes an optional microphone preamplifier (not shown) and an analog-to-digital converter 120 to provide a digital microphone signal to an appropriate input port or channel of a control and processing circuit 109 or processor. The head-mounted hearing device 10 may include a wireless transceiver 104 coupled to an antenna 105.

[0039] The processor 109 may include a software programmable DSP core and may apply one or more signal processing functions to the digital microphone signal under the control of a set of executable program instructions or codes. The one or more signal processing functions may be adapted to process the digital microphone signal as required (e.g., according to the hearing loss of the user), wherein the head mounted hearing device 10 includes a hearing aid or hearing loss compensation function, so that a properly compensated microphone signal is provided to the user via the micro speaker 119. These signal processing functions may include different processing parameters for functions such as non-linear amplification, noise reduction, frequency response shaping, etc. The processor 109 is clocked by a master clock signal provided by a master / system clock generator 115, and the clock frequency may be above 2 MHz, for example, between 2 MHz and 40 MHz. The master clock generator 115 may additionally provide a synchronous clock signal to the analog-to-digital converter 120 and the class D output amplifier 113. As described above, the class D output amplifier 113 may convert the compensated microphone signal into a corresponding modulated output signal of a predetermined modulation frequency, which is applied to the micro receiver or speaker 119 for generating sound pressure in the ear canal of the hearing instrument user. The modulation frequency of the class D output amplifier may vary depending on the type of modulation scheme and the performance requirements of the amplifier in a particular application.The class D output amplifier 113 may be configured to PWM or PDM modulate the output signal to the speaker 119 at a modulation frequency between 250 kHz and 2 MHz.

[0040] The present embodiment of the switched capacitor DC-DC converter 100 is configured to reduce the applied DC input voltage in two separate steps by utilizing first and second switched capacitor DC-DC converters (not shown) connected in series to generate a DC output voltage Vout, as discussed in more detail below. The output / smoothing capacitor Co1 is connected to the DC output voltage Vout of the switched capacitor DC-DC converter 100. The first switched capacitor DC-DC converter includes an external flying capacitor C fly , where the term "external" means external to the integrated circuit or semiconductor die or chip into which the rest of the switched capacitor DC-DC converter 100 is integrated (possibly together with other active circuit blocks of the head mounted hearing device 10). These other active circuits may include the analog to digital converter ΣΔ1 120 discussed above, the clock generator 115, the processor 109, the RF wireless transceiver 104, the class D audio output amplifier 113, etc.

[0041] The capacitance of the output / smoothing capacitor Co1 may be greater than 500 nF, for example between 1 μF and 10 μF, whereas in a typical head-mounted hearing device 10, the flying capacitor C fly The capacitance can be between 500nF and 10μF.

[0042] If the rechargeable battery power source VDD If a Li-ion battery cell is included, the switched capacitor DC-DC converter 100 may be designed to provide a nominal DC output voltage Vo1 between 1.5 V and 1.0 V, for example approximately 1.2 V. The 1.2 V DC output voltage typically provides optimal or near-optimal power supply conditions for certain individual circuits or circuit blocks of the head mounted hearing device 10 (e.g., the class D audio output amplifier 113 or certain supporting circuits within the signal processor or DSP 109). Those skilled in the art will appreciate that many circuit blocks of the device 10 powered by the DC output voltage Vo1, such as the class D audio output amplifier 113 and flash or EEPROM memory (not shown) or sensor interface circuits (not shown), may exhibit current or power consumption that is highly variable over time, such as having relatively small power consumption for long periods of time, punctuated by occasional bursts of relatively high power consumption. This time-varying power consumption causes certain challenges for conventional switched capacitor DC-DC converters, as described below, while the hybrid characteristics of the present switched capacitor DC-DC converter 100 are able to adapt to the varying power consumption requirements of a load circuit or consumer without sacrificing high conversion efficiency during normal or average power consumption, as discussed in further detail below.

[0043] Figure 2 The upper part of FIG. 2 shows a simplified schematic block diagram of a charge pump stage of a first switched capacitor DC-DC converter for illustrating the background of the present invention. The switched capacitor DC-DC converter is a step-down 2:1 topology configured to convert a DC input voltage Vbat into a DC output voltage of approximately half the DC input voltage. The charge pump circuit 200 includes a flying capacitor C fly , output / smoothing capacitor C out and a switch array including a first controllable semiconductor switch SW1, a second controllable semiconductor switch SW2, a third controllable semiconductor switch SW3, and a fourth controllable semiconductor switch SW4. The switches SW1 and SW2 are driven by a first clock phase Φ1 of a clock signal, and the switches SW3 and SW4 are driven by a second clock phase Φ2 of the clock signal, as schematically shown in the figure. The first clock phase Φ1 and the second clock phase Φ2 of the clock signal (alternatively represented as p1, p2 in the figure) are complementary and non-overlapping. The DC input voltage Vbat to the charge pump circuit 200 is applied to the switch SW1, and the output / smoothing capacitor C out Provides a DC output voltage V out The load of the charge pump circuit 200 is connected to the output / smoothing capacitor C out The flying capacitor C fly When charging, the output / smoothing capacitor C outProvide energy power to the load. Those skilled in the art will appreciate that each of the controllable semiconductor switches SW1, SW2, SW3, and SW4 may include a MOSFET (e.g., an NMOS transistor) or a combination of MOSFETs, because the small size, large off resistance, and low on resistance of the MOSFET switch are advantageous characteristics in many applications of the charge pump circuit 200. In the current buck topology of the charge pump circuit 200, SW1 is connected between the DC input voltage Vbat and the positive terminal of the flying capacitor SW4; SW2 is connected between the negative terminal of the flying capacitor SW4 and the DC output voltage. In the alternative 1:2 boost embodiment, SW2 is connected between the negative terminal of the flying capacitor and the negative DC power rail (e.g., GND). SW3 is connected between the negative terminal of the flying capacitor and the negative DC power rail (e.g., GND). In the alternative 1:2 boost embodiment, SW3 is connected between the negative terminal of the flying capacitor and the DC input voltage. SW4 is connected between the positive terminal of the flying capacitor and the DC output voltage. During operation of the charge pump circuit 200, the first switch SW1 and the second switch SW2 are switched between respective on and off states according to the first clock phase Φ1, and the third switch SW3 and the fourth switch SW4 are switched between respective on and off states according to the second clock phase Φ2. Thus, the switch array is configured to, in or during the first clock phase, conduct the conduction resistance of SW1 and SW2 from the DC input voltage Vbat to the flying capacitor C fly The combined on-resistance of SW1 and SW2 is given by resistor 2*R SW Schematically indicated.

[0044] In addition, during the first clock phase, switches SW3 and SW4 are open or non-conductive, which results in an equivalent schematic circuit diagram 200a. As shown, the flying capacitor C fly and output capacitor C out Equivalently connected in series with the DC input voltage V in and GND, so that when no load current is drawn from the output voltage of the charge pump circuit 200, in steady-state operation, the output voltage is charged to about half of the DC input voltage by periodically switching between the first clock phase and the second clock phase. The switch array is configured such that: in or during the second clock phase Φ2, since the flying capacitor and the output capacitor are connected in parallel by the on-state of the switches SW3 and SW4, the flying capacitor C is charged to the output capacitor C by a charge sharing mechanism. fly Discharge to the output capacitor C out During the second clock phase, switches SW1 and SW2 are disconnected, i.e., non-conductive, which results in an equivalent schematic circuit diagram 200b. As shown in the figure, the flying capacitor C fly and output capacitor C outEquivalently connected in parallel and disconnected from the DC input voltage Vbat. Those skilled in the art will appreciate that each of the controllable semiconductor switches SW1, SW2, SW3 and SW4 may include a control terminal (not shown), such as a gate terminal of a MOSFET, to which the first clock phase Φ1 or the second clock phase Φ2 is applied to selectively switch the considered controllable semiconductor switch between its on state and its off state.

[0045] Figure 2 The lower half of the figure shows a simplified schematic block diagram of a charge pump stage 200-1 of a second switched capacitor DC-DC converter supporting multiple converter topologies for illustrating the background of the present invention. This embodiment of the switched capacitor DC-DC converter can be configured to generate step-down conversion ratios of 1 / 3, 1 / 2, and 2 / 3 by appropriately adjusting the converter topology. Compared with the pump circuit 200 discussed above, the charge pump circuit 200-1 includes two separate flying capacitors - the first flying capacitor C fly1 and the second flying capacitor C fly2 The charge pump circuit 200-1 further includes an output / smoothing capacitor C out and a switch array including a total of seven controllable semiconductor switches controlled by respective clock phases of a non-overlapping first clock phase Φ1 and a second clock phase Φ2, as shown. During operation of the charge pump circuit 200, the switch array is configured to: in or during the first clock phase, the on-resistance of the active switch is controlled from the DC input voltage V in At the same time, the first flying capacitor C fly1 and the second flying capacitor C fly2 In addition, during the first clock phase, the switch operated by the second clock phase Φ2 is open or non-conductive, which results in an equivalent schematic circuit diagram 200-1a. As shown in the figure, the first flying capacitor, the second flying capacitor and the output capacitor C out The first flying capacitor and the second flying capacitor are equivalently connected in series between the DC input voltage Vbat and GND or another negative supply rail, so that for the reasons discussed above in conjunction with the first charge pump circuit 200, in steady-state operation of the pump circuit, the output voltage is charged to approximately one-third of the DC input voltage. During the second clock phase Φ2, the switch array is configured to discharge the first flying capacitor and the second flying capacitor to the output capacitor C through a charge sharing mechanism caused by the parallel connection of the first flying capacitor, the second flying capacitor and the output capacitor via the respective on-resistances of the active / conducting switches. outDuring the second clock phase, the switch operated by the first clock phase Φ1 is turned off or non-conducting, while the switch operated by the second clock phase Φ2 is turned on or conducting, which results in an equivalent schematic circuit diagram 200-1b of the charge pump circuit 200-1. As shown in the figure, the first flying capacitor C fly1 , the second flying capacitor C fly2 And the output capacitor C out Equivalently connected in parallel and disconnected from the DC input voltage Vbat.

[0046] Figure 3 is a general model 300 of a switched capacitor DC-DC converter, which is discussed below to highlight the background of some advantageous characteristics of an integrated circuit switched capacitor DC-DC converter according to the present invention. in The input power or energy is fed to the switched capacitor DC-DC converter and during operation the latter generates a DC output voltage Vout which, depending on the topology of the switched capacitor DC-DC converter, can be higher or lower than the DC input voltage, as described above. In general, the switched capacitor DC-DC converter efficiency is affected by both intrinsic energy losses due to linear losses when the SCDC-DC converter is operated with a voltage conversion ratio (VCR) that deviates from the so-called ideal voltage conversion ratio (iVCR) and some "extrinsic losses" due to, for example, parasitic capacitances at the output stage nodes, gate capacitances of semiconductor switches, etc. The on-resistances of the switches cause intrinsic power losses in the switched capacitor DC-DC converter, since the additional power required to regulate the DC output voltage to a level below Vbat*iVCR is dissipated in these on-resistances.

[0047] Experience has shown that intrinsic energy losses usually dominate in switched capacitor DC-DC converter designs using external flying capacitors, because the ratio of useful capacitance to parasitic capacitance is very large for such external flying capacitors. The intrinsic and extrinsic loss mechanisms of switched capacitor DC-DC converters are given by Figure 3 The model 300 includes an ideal transformer 302 having a voltage proportional to the actual VCR (i.e., V out / V in ) and the equivalent loss resistor R connected in series with the secondary winding of the transformer 302. eq . Loss resistance R eq There are two separate resistance components:

[0048] 1) a first resistance component representing an equivalent output resistance associated with switching one or more flying capacitors at a clock frequency of a clock signal driving a first clock phase and a second clock phase. Those skilled in the art will appreciate that the equivalent output resistance is inversely proportional to the clock frequency, such that an increase in the clock frequency results in a decrease in the equivalent output resistance; and

[0049] 2) A second resistance component representing the combined on-resistance of the active semiconductor switches in any particular clock phase, for example, the on-resistance of switches SW1 and SW2 in the first clock phase Φ1 of the exemplary 2:1 buck charge pump circuit 200 discussed previously.

[0050] The switched capacitor DC-DC converter is particularly energy efficient or power efficient when the relationship between the DC input voltage and the DC output voltage is one of the ideal voltage conversion ratios iVCR (e.g., 1 / 3 or 1 / 2 or 2 / 3 or 2, or 3 or 5, etc.) associated with the selected topology of the SC DC-DC converter. By increasing the number of flying capacitors, a greater number of possible converter topologies and associated iVCRs can be selected, as shown in Table 1 below, which illustrates the rapid growth of iVCR with n for a step-down switched capacitor DC-DC converter:

[0051] Table 1

[0052]

[0053] As described above, when the converter is operated with one of the iVCRs, the so-called inherent energy loss of the switched capacitor DC-DC converter is minimized, or equivalently, the inherent energy efficiency is maximized. Therefore, it seems desirable to include a large number of flying capacitors in the switched capacitor DC-DC converter design to enable multiple converter topologies or gears when the DC input voltage varies greatly and / or the target DC output voltage varies greatly. A large number of converter topologies enable the selection of a specific converter topology with an iVCR close to any desired operating point (in terms of DC input voltage and DC output voltage) of the SC converter, such as 1 / 5 or 2 / 3. This ensures the high inherent energy efficiency of the switched capacitor DC-DC converter. However, a large number of external capacitors are generally undesirable because the carrier of the switched capacitor DC-DC converter occupies an increased area, increases manufacturing costs, etc. These disadvantages are particularly evident for compact wearable devices (e.g., hearing instruments and headphones that are subject to severe space constraints).

[0054] Figure 4A simplified schematic block diagram of the previously discussed exemplary integrated circuit switched capacitor DC-DC converter 100 according to an embodiment of the present invention is shown. The integrated circuit switched capacitor DC-DC converter 100 includes a first switched capacitor converter 402 and a second switched capacitor converter 404. The first switched capacitor converter 402 includes a DC input 401 for receiving a battery supply voltage Vbat. The battery supply voltage Vbat is provided to the DC input 401 by maintaining an externally accessible pad or terminal of a semiconductor die or chip of the integrated circuit 100. The first switched capacitor converter 402 includes a first switch array including a first switching array that can be connected to an external flying capacitor C fly A plurality of individually controllable semiconductor switches SW0, SW1, SW2 and SW3. An external flying capacitor C fly A pair of externally accessible pads or terminals 405, 407 of the integrated circuit 100 are coupled to the first switch array. Those skilled in the art will appreciate that the illustrated switched capacitor DC-DC converter including only a single flying capacitor can be configured as a 1:1 converter topology, a 2:1 converter topology, or a 1:2 converter topology by appropriate switch array control. However, other embodiments of the first switched capacitor converter 402 may include one or more additional external flying capacitors and be configured to provide additional converter topologies, such as 1 / 3 and 2 / 3 step-down conversion ratios, by appropriately adjusting the converter topology. During operation, the first switched capacitor converter 402 generates an output voltage Vsc, int using the previously discussed operating mechanism. The output voltage Vsc, int can be regarded as an intermediate voltage of the switched capacitor DC-DC converter 100, because in some embodiments the intermediate voltage may not be connected to any pad or terminal of the semiconductor die or chip, i.e., it cannot be contacted from the outside. Therefore, the latter embodiment of the switched capacitor DC-DC converter 100 operates without any off-chip smoothing capacitor coupled to the intermediate voltage Vsc, int, so that the external components and chip area are beneficially reduced.

[0055] However, the output voltage Vsc,int is coupled to the input V of the second switched capacitor converter 404 via a conductor or trace 408. in The second switched capacitor converter 404 thus converts the output voltage Vsc,int provided by the first switched capacitor converter 402 into a DC output voltage Vout of the switched capacitor DC-DC converter 100. The smoothing capacitor C out4 is connected to the output voltage Vout of the switched capacitor DC-DC converter 100. This is preferably an external capacitor connected to the output of the second switched capacitor converter 404 via a terminal or pad 423 of the semiconductor die as shown. Those skilled in the art will appreciate that the first switched capacitor converter 402 and the second switched capacitor converter 404 are connected in series between the DC input 401 and the DC output voltage Vout. The second switched capacitor converter 404 includes a second switch array, which may include a plurality of individually controllable semiconductor switches, such as an output stage (not shown) of the converter 404 and a plurality of internal flying capacitors (not shown), such as three, four, five or even more internal flying capacitors (using the previous combination Figure 2 1 and 2). Therefore, multiple internal flying capacitors are integrated on the semiconductor die, i.e., chip, which greatly limits the maximum capacitance of each flying capacitor because the available capacitance per area or capacitance density on the semiconductor die is relatively low and the cost of die area is generally high. Multiple internal flying capacitors, the output stage, and a portion of the controller of the second converter 404 are arranged within a schematically shown circuit block 420, which interfaces with the rest of the integrated circuit switched capacitor DC-DC converter 100 via terminals Vin, Vfb, Vset, Vout, requestQ, and Vss.

[0056] The switched capacitor DC-DC converter 100 further includes a controller (not shown) discussed previously. The controller may be distributed over several control portions or circuits, such as a first control portion 411 and a second control portion arranged in a circuit block 420 of the second switched capacitor converter 404. The controller may include a digital state machine or a software programmable microprocessor of a suitable configuration. The controller is connected to the corresponding controllable semiconductor switches of the first switch array and the second switch array, and is capable of changing the corresponding topology of the first switched capacitor converter and the second switched capacitor converter. In some embodiments, the controller may be configured or programmed to: select the topology of the second switched capacitor converter 404 to maximize its inherent energy efficiency at the set point of the DC output voltage Vout.

[0057] Intrinsic energy efficiency η1=VCR / iVCR=Vo1 / (Vint*iVCR);

[0058] η1 = intrinsic energy efficiency of the second switched capacitor converter at the set point voltage of the DC output voltage;

[0059] VCR = Voltage conversion ratio of the selected converter topology:

[0060] iVCR = ideal voltage conversion ratio of the second switched capacitor converter;

[0061] Vsc,int=intermediate voltage at the input of the second switched capacitor converter.

[0062] The integrated circuit switched capacitor DC-DC converter 100 preferably includes a clock generator (not shown) that generates a clock signal and derives a pair of non-overlapping clock phases therefrom for controlling the state switching of four individually controllable semiconductor switches of the first switch array of the first switched capacitor converter 402. The same pair of non-overlapping clock phases can control the state switching of multiple individually controllable semiconductor switches of the second switch array of the second switched capacitor converter 404. The first control part 411 is configured to apply a pair of clock phases p1 and p2 to the individually controllable semiconductor switches of the first switch array, allowing the first control part 411 to control the timing of the non-overlapping clock phases p1 and p2. In this way, the first switched capacitor converter 402 can operate as a passive slave of the first control part 411, and control the flying capacitor C according to the request from the first control part 411. fly More specifically, during the discharge state or discharge phase of the first switch array of the first switched capacitor converter 402, the semiconductor switches SW1 and SW3 are switched to an on or conducting state by the first control portion 411 via non-overlapping clock phases p1, p2, while the semiconductor switches SW0 and SW2 are switched to an off or non-conducting state. This discharge state will charge the flying capacitor C fly connected in parallel to the DC input Vin of the second switched capacitor converter 404 and thus transferring energy or charge from C fly is passed to the second switched capacitor converter 404, so that C fly Gradually deplete or discharge.

[0063] In contrast, during the charging state or charging phase of the first switch array of the first switched capacitor converter 402, the states of the individually controllable semiconductor switches of the first switch array have been switched via the control portion 411 in accordance with a request of the controller, such that the semiconductor switches SW0 and SW2 are conducting and the semiconductor switches SW1 and SW3 are off or non-conducting. In this way, the flying capacitor C fly Now connected between the DC input voltage 401 and the DC input Vin of the second switched capacitor converter 404 via semiconductor switches SW0 and SW2. fly The DC input Vin of the second switched capacitor converter 404 is recharged and charged. This charging state of the first switch array of the first switched capacitor converter 402 can continue until the intermediate voltage to the second switched capacitor converter 404 is discharged again and the first switch array switches or switches back to the discharging state in response thereto, wherein the now recharged flying capacitor C flyProvides energy to the second switched capacitor converter 404. Those skilled in the art will appreciate that fly During charging, the intermediate voltage Vsc,int is decreasing. Therefore, in response to Vsc,int meeting a predetermined charge criterion, such as being below a certain threshold voltage, the controller may convert or switch the first switch array between a charging state and a discharging state. The predetermined charge criterion, such as a threshold voltage, may, for example, indicate that the integrated circuit switched capacitor DC-DC converter 100 cannot maintain the DC output voltage at a charge level at a target or desired output voltage. Therefore, the first switched capacitor converter 402 may operate with very high energy efficiency because the converter 402 may be configured to operate only at the flying capacitor C fly The flying capacitor C fly The state of charge of the flying capacitor C may be determined by the controller in a direct or indirect manner. The controller may be configured to indirectly determine the state of charge of the flying capacitor C by monitoring the switching frequency, or equivalently, monitoring the output resistance of the second switched capacitor converter 404. fly When the switching frequency of the second switched capacitor converter 404 reaches its maximum switching frequency, this condition may indicate that the flying capacitor C fly The charge on the capacitor is depleted. Therefore, in response, the controller issues a recharge command to the first switched capacitor converter 402 via the output port "requestQ" of the second switched capacitor converter 404. The recharge command is transmitted to the individually controllable semiconductor switches SW0, SW1, SW2 and SW3 of the first switch array through the first control part 411, resulting in the state switching of the first switch array discussed previously. Those skilled in the art will understand that this embodiment is particularly suitable for the case where the second switched capacitor converter 404 includes an output voltage regulator controlled by the switching frequency of the DC output voltage Vout.

[0064] An alternative embodiment of the controller may be configured to indirectly determine the flying capacitor C by monitoring the voltage difference between the DC output voltage Vout and a set point or target voltage Vset of the DC output voltage. fly state of charge.

[0065] The second switched capacitor converter 404 preferably includes an output voltage regulator configured to maintain the DC output voltage at a DC reference voltage or set point voltage, such as a DC output voltage between 0.6V and 1.4V. The reference voltage generator 413 is configured to provide the set point voltage to a reference voltage input Vset of the controller. The voltage regulator further includes a feedback voltage input Vfb, which is connected to the DC output voltage Vout. The voltage regulator further includes an error signal generator (not shown) configured to subtract the DC reference voltage Vset and the feedback voltage at the Vfb input to determine a control signal, such as an error signal, so that the controller represents the difference between the current DC output voltage and the set point voltage. According to this embodiment, the controller can be configured to control the requestQ signal via a second error signal representing Vout-Vset-Vdelta, where Vdelta is a voltage significantly less than Vset, such as less than one tenth, such as less than 20mV. When the second error signal becomes negative, it indicates that Vout has dropped below Vset-Vdelta, which may be due to the second switched capacitor converter 404 being unable to provide sufficient current to the load at the existing voltage level Vsc,int. Therefore, the controller may issue a requestQ signal in response to Vout-Vset-Vdelta becoming greater than (>) 0.

[0066] The controller may use various well-known control mechanisms to regulate the DC output voltage, such as pulse width control, single boundary control, pulse frequency control, pulse skipping control, etc. This may be achieved by appropriately controlling the timing of the respective clock phases of the plurality of individually controllable semiconductor switches of each of the first switch array and the second switch array.

[0067] In the case of pulse skipping control, the switching of the charging state of the first switched capacitor power converter 402 may be performed in response to the "shooting frequency" or the time interval between individual pulses generated by the controller exceeding a certain threshold. The detection of a high shooting frequency condition may be achieved by detecting whether the controller issues more than a certain number of pulses within a certain time frame. The detection may be achieved by a digital counter in combination with a divided clock signal derived from the master clock signal to define a pulse counting time frame.

[0068] When a single boundary switching controller (which can be considered a type of frequency modulation control) is used, when the DC output voltage Vout drops below the set point voltage, a phase transition of the output stage of the first switched capacitor power converter 402 is issued, for example, p1 to p2 or p2 to p1. The comparison can be performed by a dynamically clocked comparator so that a switching signal is issued as long as the output voltage is below the set point voltage. If the number of switches in a particular time frame exceeds a predetermined number, the controller issues a requestQ signal to cause a charge state transition or switch in the first switched capacitor converter 402.

[0069] The integrated circuit switched capacitor DC-DC converter 100 includes an optional bypass circuit that allows the controller to bypass the second switched capacitor converter 404 under certain operating conditions. The bypass circuit includes a first controllable bypass switch SW BP1 and a second controllable bypass switch SW BP2 . The bypass circuit allows the integrated circuit switched capacitor DC-DC converter 100 to switch from a normal operating mode as described above (wherein the output of the first switched capacitor converter 402 essentially charges the input of the second switched capacitor converter 404) to a "high power" mode (wherein the output of the first switched capacitor converter 402 essentially charges the DC output voltage and the output capacitor). The high power mode enables the switched capacitor DC-DC converter 100 to provide large load power bursts without compromising energy conversion efficiency at normal or ordinary load power levels. This is achieved by switching the first switch array SW0, SW1, SW2 and SW3 via a first controllable bypass switch SW BP1 and a second controllable bypass switch SW BP2 Connect directly to the output voltage Vout and the output capacitor C out To achieve.

[0070] The controller of the switched capacitor DC-DC converter 100 can be configured to select a normal operating mode when the load current provided at Vout is less than a specific current or power threshold or limit (e.g., 1 mW, 5.0 mA, or 1.0 mA, etc.). Due to the reasons discussed above, the second switched capacitor converter 404 is able to provide this small load power level with high efficiency. However, if the load power level jumps to a level above the power threshold or limit, the second switched capacitor converter 404 may not be able to provide the required power and accommodate the power burst due to the reasons discussed above. The controller detects that the power burst exceeds the power threshold, and in response, activates the bypass circuit to switch the switched capacitor DC-DC converter 100 to a high power mode. The output resistance or impedance of the first switched capacitor converter 402 is less than the output resistance of the second switched capacitor converter 404, especially because the external flying capacitor C flyThe capacitance of the external flying capacitor C is much larger than the combined capacitance of multiple internal or integrated flying capacitors of the second switched capacitor converter 404. fly The capacitance of may be greater than 500 nF or greater than 1 μF, while the combined capacitance of multiple internal or integrated flying capacitors is less than 50 nF. The controller may control the first controllable bypass switch SW BP1 and a second controllable bypass switch SW BP2 The first controllable bypass switch SW is controlled by connecting the corresponding control terminals 417, 418 to the appropriate ports or connections 417, 418 of the control terminals. BP1 and a second controllable bypass switch SW BP2 The first bypass switch SW BP1 The control or drive signal of is preferably synchronized with the first clock phase p1, and the second bypass switch SW BP2 The control or drive signal is preferably synchronized with the second clock phase p2.

[0071] Therefore, the first bypass switch SW BP1 and the second bypass switch SW BP2 During the first clock phase p1, the first semiconductor switch SW0 and the third semiconductor switch SW2 of the first switch array and the first bypass switch SW BP1 As a result, the external flying capacitor C fly connected between the DC input 401 and the DC output voltage Vout, so that C fly and C out Coupled in series to the DC input 401 and the battery voltage Vbat. External flying capacitor C fly The first terminal Vct is connected to the DC input 401 through SW0, and C fly The second terminal Vcb is connected through SW BP1 Connect to Vout.

[0072] During the second clock phase p2, the second semiconductor switch SW1 and the fourth semiconductor switch SW4 of the first switch array and the second bypass switch SW BP2 are all turned on / on, while SW0, SW2 and SW BP1 As a result, the external flying capacitor C fly is connected between a negative supply rail (eg, ground or a negative DC supply voltage relative to Vbat) and the DC output voltage, so that the second switched capacitor converter 404 is effectively bypassed because C fly coupled in parallel to the output capacitor C out The charge is discharged directly to the output capacitor C out .

[0073] The first controllable bypass switch SW BP1 and a second controllable bypass switch SW BP2 Each of the first controllable bypass switch SW may include one or more semiconductor switches, such as MOSFET devices. BP1 and a second controllable bypass switch SW BP2 Each of may include multiple switch segments coupled in parallel and individually controllable by a controller. The controller may be configured to turn on only the number of switch segments necessary to support the current load on Vout.

[0074] Those skilled in the art will appreciate that due to the limited number of available converter topologies, such as only 1:1 and 2:1 step-down based on a single flying capacitor, the inherent energy efficiency of the first switched capacitor converter 402 may be lower than ideal during the high power mode. However, if the duration of the power consumption burst is small compared to the time period of normal or ordinary load power level, this lower inherent energy efficiency may have only a marginal impact on the overall energy consumption. During the latter time period, the second switched capacitor converter 404 provides load power with a very high inherent energy efficiency.

[0075] Figure 5 Various graphs showing voltage waveforms at internal circuit nodes of an exemplary integrated circuit switched capacitor DC-DC converter 100 during operation. The DC output voltage Vout is set to 1.2 V. Curve 500 shows the voltage waveform of the external flying capacitor C at a battery voltage Vbat of 4.2 V (dashed line) and 3.0 V (solid line). fly As expected, Vct alternates between the battery voltage Vbat and Vout according to non-overlapping clock phases p1, p2. Curve 510 shows the external flying capacitor C at a battery voltage Vbat of 4.2V (dashed line) and 3.0V (solid line). flyThe corresponding voltage at the second terminal Vcb of . Vcb alternates between (Vbat minus Vout) and gnd (zero volts) according to non-overlapping clock phases p1, p2. Those skilled in the art will understand that at least some of the controllable semiconductor switches SW1, SW2, SW3 and SW4 of the first switch array of the first converter 402 are subjected to a voltage level corresponding to Vbat. This means that at least some of these controllable semiconductor switches must be so-called high-voltage devices in the prior art CMOS semiconductor process to be able to withstand the highest battery voltage level, such as 4.2V, without breakdown or other damage. On the other hand, curve 520 shows the corresponding intermediate voltage Vsc,int under the battery voltage Vbat of 4.2V (dashed line) and 3.0V (solid line), which is the input voltage Vin of the second switched capacitor converter 404. As shown in the figure, the intermediate voltage Vsc,int alternates between (Vbat minus Vout) and Vout according to non-overlapping clock phases p1, p2. As a result, the controllable semiconductor switches of the second switch array of the second converter 404 are subjected to a voltage level far below Vbat. The first converter 402 shields the second converter 404 to prevent it from withstanding the full Vbat voltage level. This means that the controllable semiconductor switch of the second converter 404 can be implemented as a standard low-voltage semiconductor transistor, which has a smaller parasitic capacitance and a smaller area than a high-voltage semiconductor transistor, thereby improving the energy efficiency of the second converter 404.

Claims

1. An integrated circuit switched capacitor DC-DC converter, comprising: A first switched capacitor converter comprising: A DC input for receiving a battery supply voltage; a first switch array comprising a plurality of individually controllable semiconductor switches connectable to at least one external flying capacitor to form one or more individual converter topologies of said first switched capacitor converter for converting a battery supply voltage to an intermediate voltage; A second switched capacitor converter comprising: an input connected to said intermediate voltage; a second switch array comprising a plurality of individually controllable semiconductor switches and a plurality of internal flying capacitors configurable to form a plurality of individual converter topologies for converting the intermediate voltage into a DC output voltage; a controller connected to respective control terminals of the respective individually controllable semiconductor switches of the first switch array and the second switch array to select a converter topology of the first switched capacitor converter and to select a converter topology of the second switched capacitor converter; and The first controllable bypass switch (SWBP1) and the second controllable bypass switch (SWBP2) are configured as follows: In a first state, connecting the at least one external flying capacitor between a DC input and a DC output voltage; In a second state, the at least one external flying capacitor is connected between the negative supply rail and the DC output voltage, thereby bypassing the second switched capacitor converter.

2. The integrated circuit switched capacitor DC-DC converter according to claim 1, wherein: The controller is configured to: directly or indirectly determining a state of charge of the at least one external flying capacitor; comparing the state of charge with a predetermined charge standard; In response to meeting a predetermined charging criterion, the at least one external flying capacitor is recharged via the first switch array.

3. The integrated circuit switched capacitor DC-DC converter according to claim 2, wherein: The controller is configured to: The at least one external flying capacitor is recharged by connecting the at least one external flying capacitor between the DC input and the input of the second switched capacitor converter by switching respective states of first and second pairs of individually controllable semiconductor switches of the first switch array.

4. The integrated circuit switched capacitor DC-DC converter according to claim 2 or 3, wherein: The predetermined charging criteria of the at least one external flying capacitor include one or more of the following: a switching frequency of the second switched capacitor converter; a voltage difference between the DC output voltage and a set point or target voltage of the DC output voltage; A voltage drop across the at least one external flying capacitor.

5. The integrated circuit switched capacitor DC-DC converter according to any one of claims 2 to 4, wherein: The controller is configured to: Regardless of the predetermined state of charge, the at least one external flying capacitor is recharged at a default or minimum switching frequency to set a lower limit on the switching frequency of the first switched capacitor converter.

6. The integrated circuit switched capacitor DC-DC converter according to claim 5, wherein: The minimum switching frequency is higher than 16 kHz.

7. The integrated circuit switched capacitor DC-DC converter according to any one of claims 1 to 6, wherein: The minimum switching frequency of the second switched capacitor converter is higher than 1 MHz, and / or The maximum switching frequency of the first switched capacitor converter is lower than 250 kHz.

8. The integrated circuit switched capacitor DC-DC converter according to claim 7, wherein: The lowest switching frequency of the second switched capacitor converter is higher than 5 MHz.

9. The integrated circuit switched capacitor DC-DC converter according to claim 7, wherein: The lowest switching frequency of the second switched capacitor converter is higher than 10 MHz.

10. The integrated circuit switched capacitor DC-DC converter according to claim 7, wherein: The maximum switching frequency of the first switched capacitor converter is lower than 100 kHz.

11. An integrated circuit switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The first switch array comprises: a first pair of individually controllable semiconductor switches driven by a first clock phase (p1) of the clock signal; a second pair of individually controllable semiconductor switches driven by a second non-overlapping clock phase (p2) of said clock signal, The first pair of individually controllable semiconductor switches is configured to charge the at least one external flying capacitor from a battery supply voltage during the first clock phase, and the second pair of individually controllable semiconductor switches is configured to discharge the at least one external flying capacitor to an input of the second switched capacitor converter during the second clock phase.

12. The integrated circuit switched capacitor DC-DC converter according to claim 11, wherein: The first controllable bypass switch (SWBP1) is configured to: selectively connect and disconnect a first terminal of the at least one external flying capacitor to and from the DC output voltage according to a first switch control signal provided by the controller; and The second controllable bypass switch (SWBP2) is configured to selectively connect and disconnect a second terminal of the at least one external flying capacitor from the DC output voltage according to a second switch control signal provided by the controller.

13. The integrated circuit switched capacitor DC-DC converter according to claim 12, wherein: The controller is configured to: generating the first switch control signal in synchronization with a first clock phase (p1) of the clock signal; as well as The second switch control signal is generated in synchronization with a second clock phase (p2) of the clock signal.

14. An integrated circuit switched capacitor DC-DC converter according to any preceding claim, wherein: The second switched capacitor converter comprises an output voltage regulator, wherein the output voltage regulator comprises: a reference voltage input for receiving a first DC reference voltage and a feedback voltage input for receiving a feedback voltage representative of the DC output voltage; an error signal generator configured to combine the first DC reference voltage and the feedback voltage to determine a control signal, The controller is configured to generate: Respective clock phases for a plurality of individually controllable semiconductor switches of the second switch array to regulate a DC output voltage.

15. An integrated circuit switched capacitor DC-DC converter according to any preceding claim, wherein: The controller is configured to: select a topology of the second switched capacitor converter so that an inherent energy efficiency of the second switched capacitor converter is maximized; The inherent energy efficiency is η1=VCR / iVCR=Vo1 / (Vint*iVCR); η1=the intrinsic energy efficiency of the second switched capacitor converter at the set point voltage of the DC output voltage; VCR = voltage conversion ratio of the selected converter topology; iVCR = ideal voltage conversion ratio; Vint = intermediate voltage.

16. An integrated circuit switched capacitor DC-DC converter according to any preceding claim, wherein: The total capacitance of the at least one external flying capacitor is greater than 500 nF; and / or The total capacitance of the plurality of internal flying capacitors is less than 22 nF.

17. The integrated circuit switched capacitor DC-DC converter of claim 16, wherein: The total capacitance of the plurality of internal flying capacitors is less than 5 nF.

18. A head-mounted hearing device, comprising: An integrated circuit switched capacitor DC-DC converter according to any one of the preceding claims; At least one rechargeable battery cell connectable to the DC input for providing a battery supply voltage.

19. The head mounted hearing device according to claim 18, wherein: The at least one rechargeable battery cell is one or more lithium-ion battery cells.

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