Semiconductor device and method for providing a semiconductor device

Abstract

A semiconductor device and method of providing a semiconductor device are described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed through the mask. The method also performs annealing in a volume increasing environment (e.g., hydrogen) at an annealing temperature greater than one hundred degrees Celsius and not greater than six hundred degrees Celsius. The second portion of each of the fins is exposed during the annealing so that the second portion of each of the fins undergoes volume expansion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Provisional Patent Application No. 62 / 587,333, filed on November 16, 2017, entitled “METHOD TO SELECTIVELY INCREASE SILICON FIN AREA FOR A VERTICALFIELD EFFECT TRANSISTOR,” which is assigned to the assignee of the present application and is incorporated herein by reference. Technical Field

[0003] The present application relates to a semiconductor device and a method for providing a semiconductor device. Background Art

[0004] The trend in CMOS devices is to reduce size. However, size reduction generally reduces device performance. To address the problems in planar CMOS devices, vertical devices have been developed. Vertical architectures can increase device density and improve performance. For example, fin field effect transistors (finFETs) have been developed. FinFETs can have better electrostatic or short channel effect (SCE) control than planar CMOS devices. Density and effective emitter width (W efff ) efficiency and gate length (L g ) is irrelevant, which allows for a more relaxed L g For vertical devices. Thus, FinFET devices replace planar CMOS devices at a smaller scale.

[0005] There is still a need to improve the performance of vertical devices. Mechanical means for improving performance other than changing Lg are limited due to the tight density within the specific layout of such devices. Therefore, research on vertical device architectures continues. Summary of the invention

[0006] A method of providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed through the mask. The method further performs an anneal in a volume-increasing ambient (e.g., hydrogen). The annealing is performed at an annealing temperature greater than one hundred degrees Celsius and not greater than six hundred degrees Celsius. The second portion of each of the fins is exposed during the annealing such that the second portion of each of the fins undergoes volume expansion.

[0007] A method of providing a semiconductor device is described. The method includes: providing a plurality of fins such that a first portion of each of the plurality of fins is covered by a mask and a second portion of each of the plurality of fins is exposed through the mask, each of the plurality of fins being formed of silicon; and performing annealing in a hydrogen environment at at least one annealing temperature for an annealing time, the at least one annealing temperature being at least two hundred degrees Celsius and not more than five hundred degrees Celsius, the annealing time being at least twenty seconds and not more than four hundred seconds, the second portion of each of the plurality of fins being exposed during the annealing such that the second portion of each of the plurality of fins undergoes volume expansion, the second portion being at least one of a channel region and a top source / drain region.

[0008] A semiconductor device is described. The semiconductor device includes: a plurality of fins, each of the plurality of fins having a channel region and a top source / drain region, at least one of the plurality of fins and the top source / drain region having an extended area; a plurality of gates covering a portion of the plurality of fins; a plurality of oxide layers existing between the plurality of fins and the plurality of gates; and a plurality of source / drain regions.

[0009] The method processes the fin so that the fin swells, wherein the fin is exposed to hydrogen annealing. In other words, the exposed portion undergoes volume expansion. If the channel area is exposed and annealed, the effective channel width increases through the bulging / volume expansion. If the top of the fin is exposed, the bulging / volume increase can provide more volume for the top source / drain processing. This can reduce the parasitic resistance at the top source / drain side. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart depicting an exemplary embodiment of a method for selectively increasing the volume of a portion of a fin structure in a semiconductor device.

[0011] Figure 2A to Figure 2B Portions of an exemplary embodiment of a fin structure during fabrication are depicted.

[0012] FIG. 3A to FIG. 3B Portions of another exemplary embodiment of a fin structure during fabrication are depicted.

[0013] Figure 4 is a flow chart depicting an exemplary embodiment of a method for providing a finFET with an extended channel volume in a semiconductor device.

[0014] Figures 5A to 7 Portions of an exemplary embodiment of a semiconductor device including a finFET during fabrication are depicted.

[0015] Figure 8is a flow chart depicting an exemplary embodiment of a method for providing a finFET with extended top source / drain volumes in a semiconductor device.

[0016] Figures 9 to 12 Portions of an exemplary embodiment of a semiconductor device including a finFET during fabrication are depicted.

[0017] Description of Figure Numbers

[0018] 100, 120, 150: methods;

[0019] 102, 104, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180: steps;

[0020] 200, 200A, 250, 250A: semiconductor devices;

[0021] 201: semiconductor layer;

[0022] 210, 210′, 210A, 210A′, 260, 260′, 260A, 260A′: fins;

[0023] 220, 220A: mask;

[0024] 251: Silicon layer;

[0025] 252: Hard mask;

[0026] 262: source / drain region;

[0027] 264, 264A, 264A′: bottom spacer;

[0028] 264A: Dielectric layer

[0029] 266, 266A: interface oxide;

[0030] 270, 270A: gate oxide;

[0031] 272, 272A: metal gate;

[0032] 274, 274A: top spacer;

[0033] 276, 276A: Top source / drain

[0034] 280, 280A: Fin field effect transistor. DETAILED DESCRIPTION

[0035] The exemplary embodiments are directed to forming finFETs. The following description is presented to enable one of ordinary skill in the art to make and use the invention, and is provided in the context of a patent application and its requirements. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. The exemplary embodiments are described primarily with respect to specific methods and systems provided in specific embodiments. However, the methods and systems will also operate effectively in other embodiments.

[0036] Phrases such as "exemplary embodiment," "one embodiment," and "another embodiment" may refer to the same or different embodiments, as well as multiple embodiments. The embodiments will be described with respect to a system and / or device having certain components. However, the system and / or device may include more or fewer components than shown, and the arrangement and type of components may be changed without departing from the scope of the invention. The exemplary embodiments will also be described in the context of a specific method having certain steps. However, the methods and systems operate effectively for other methods having different and / or additional steps and steps in different orders that are compatible with the exemplary embodiments. Therefore, the present invention is not intended to be limited to the embodiments shown, but should be consistent with the broadest scope consistent with the principles and features described herein.

[0037] Unless otherwise indicated herein or clearly contradictory to the context, the use of the terms "a / an" and "the" and similar indicators in describing the present invention (especially in the context of the following claims) should be understood to cover the singular as well as the plural. Unless otherwise indicated, the terms "include", "have", "include" and "contain" should be understood as open-ended terms (i.e., meaning "including (but not limited to)").

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those of ordinary skill in the art of the present invention. It should be noted that, unless otherwise specified, the use of any and all examples or exemplary terms provided herein is intended only to better illustrate the present invention, rather than to limit the scope of the present invention. In addition, unless otherwise defined, all terms defined in commonly used dictionaries should not be overly interpreted.

[0039] A method of providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed through the mask. The method also performs annealing in a volume increasing environment (e.g., hydrogen). The annealing is performed at an annealing temperature greater than one hundred degrees Celsius and not greater than six hundred degrees Celsius. The second portion of each of the fins is exposed during the annealing such that the second portion of each of the fins undergoes volume expansion.

[0040] Figure 1is a flow chart depicting an exemplary embodiment of a method 100 for providing a fin structure with a selectively extended volume for a component, i.e., a fin field effect transistor (finFET), in a semiconductor device. For simplicity, some steps may be omitted, performed in another order and / or in combination. Some steps may also include sub-steps. Additionally, the method 100 may begin after other steps of forming a semiconductor device have been performed. For example, the method may begin after semiconductor for a fin has been provided. Figure 2A to Figure 2B as well as FIG. 3A to FIG. 3B The exemplary embodiments of the semiconductor device 200 and the semiconductor device 200A are respectively depicted during the fabrication of the fin structure using the method 100. For simplicity, not all components are shown. Figures 2A to 3B Zhongqie Figures 2A to 3B Not drawn to scale. Additionally, the thickness or shape of specific layers may be exaggerated for illustrative purposes. The method 100 is described in the context of the semiconductor device 200 and the semiconductor device 200A. However, nothing prevents the method 100 from being used with a different semiconductor device.

[0041] Fins for semiconductor devices are manufactured and prepared for volume-enhancing annealing by step 102. The formation of the fins in step 102 includes providing a thinner hard mask on a semiconductor layer, such as Si. The hard mask covers the portion of the Si layer where the fin is to be formed and exposes the portion of the Si layer to be removed. Etching can then be performed to define the fin from the Si layer. In addition, step 102 ensures that the required portion of the fin is exposed for volume enhancement annealing. Therefore, an annealing mask is also provided, which exposes the portion of the fin that will have an increased volume. The annealing mask covers the portion of the fin that does not need to undergo volume expansion. In some embodiments, the annealing mask includes a portion of the hard mask for forming the fin. In such embodiments, it is necessary to protect the top of the fin from volume-increasing annealing. In other embodiments, the hard mask is removed and the hard mask is not part of the annealing mask. In some such embodiments, the top of the fin needs to have an increased volume. Other structures, such as spacers or other mask layers, may form all or part of the mask annealing.

[0042] Figure 2A and Figure 3A The semiconductor device 200 and the semiconductor device 200A are respectively depicted after step 102. Figure 2A, fins 210 have been formed from semiconductor layer 201. As discussed above, semiconductor layer 201 may be Si. It is desired that the channel volume of semiconductor device 200 be increased. Therefore, the sidewalls of the fins need to bend outward, providing a convex cross-section for each of fins 210. However, the top surface of each fin needs to remain substantially unchanged. Therefore, mask 220 exposes the sidewalls of fins 210. In some embodiments, mask 220 is used to define fins 210 from the underlying semiconductor layer 201. Similarly, Figure 3A Depicts fin 210A that has been formed from semiconductor layer 201. However, it is desirable for semiconductor device 200A to have an increased fin volume near the top source and / or drain (source / drain). It is desirable for the channel width to remain substantially unchanged. Therefore, mask 220A covers a majority of the sidewalls of fin 210A, but exposes the top of fin 210A.

[0043] When the mask 220 and the mask 220A are present, the semiconductor device 200 and the semiconductor device 200A are annealed in a volume increase environment by step 104. The volume increase environment for the Si fin 210 and the Si fin 210A is hydrogen. Annealing is performed so that the desired portion of the fin 210 and the fin 210A undergoes volume expansion. For example, except in hydrogen, the annealing may be performed at a temperature higher than one hundred degrees Celsius and not more than six hundred degrees Celsius. In some embodiments, the annealing temperature is at least two hundred degrees Celsius and not more than five hundred degrees Celsius. Annealing may be performed for an annealing time of at least ten seconds and not more than five hundred seconds. In some embodiments, the annealing time is at least twenty seconds and not more than four hundred seconds. Therefore, the exposed portions of the fin 210 and the fin 210A swell.

[0044] Figure 2B and Figure 3B The semiconductor device 200 and the semiconductor device 200A are respectively depicted after executing step 104. Figure 2B , the side edges of the fin 210' are exposed to annealing. The dotted lines indicate the original position of the side walls. Therefore, the side walls of the fin 210' have protruded outward. Therefore, the fin 210' has a protruding cross-section in the channel region. As the volume of the fin 210' increases, the channel width increases. See Figure 3B , the top of fin 210A′ is exposed to annealing. The original position of the top of fin 210A′ is also depicted by the dashed line. Therefore, the top of fin 210A′ has undergone volume expansion. Therefore, fin 210A′ has a larger top source / drain volume. Although hydrogen anneals are known, such anneals are only used to reduce the surface roughness of Si devices. Compared to the annealing performed in step 104, such anneals may not increase the volume of the structure (e.g., fin 210 / 210A) undergoing the annealing. In other words, the annealing performed in step 104 is performed so that the size of the desired portion of fin 210 / 210A is expanded.

[0045] Using method 100, the geometry of fin 210 and fin 210A can be adapted. By selectively exposing portions of fin 210 and fin 210A to hydrogen annealing, the volume of these portions of fin 210 and fin 210A can be selectively increased. In the illustrated embodiment, the width of the channel of fin 210′ ​​can be increased. Similarly, the size of the top of fin 210A′ can be increased. Therefore, fin 210A′ has a larger top source / drain volume. In other embodiments, other and / or additional regions of the fin can be exposed to annealing. These other and / or additional regions can thereby increase in volume. Therefore, the geometry of fin 210 / 210A can be adapted without significantly changing the manufacturing or lithography of semiconductor device 200 / 200A.

[0046] Figure 4 1 is a flow chart depicting an exemplary embodiment of a method 120 for providing a finFET with an extended channel volume in a semiconductor device. For simplicity, some steps may include sub-steps, may be omitted, may be performed in another order, and / or may be combined. Additionally, method 120 may begin after other steps of forming a semiconductor device have been performed. Figures 5A to 7 A portion of an exemplary embodiment of a semiconductor device 250 is depicted during fabrication of a finFET using method 120. For simplicity, not all components are shown. Figures 5A to 7 Zhongqie Figures 5A to 7 Not drawn to scale. For example, various structures that may be formed before the fins are not shown. Additionally, the thickness of the layers may be exaggerated for illustrative purposes. For clarity, only structures formed in the region of the transistor are shown. The method 120 is described in the context of the semiconductor device 250. However, nothing prevents the method 120 from being used with a different semiconductor device.

[0047] Fins are provided from the silicon layer, via step 122. For example, a dielectric hard mask may be fabricated on the underlying Si layer. The openings in the hard mask correspond to the Si regions to be removed. The Si layer is then etched, leaving the fins. Bottom source / drain regions are formed, via step 124. In some embodiments, step 124 includes growing an epitaxial layer, such as SiGe, for use in the source / drain. A bottom spacer layer is also provided, via step 126. Step 126 includes forming a dielectric layer having a desired height over the fin.

[0048] Figure 5A and Figure 5B Depicted are cross-sectional and perspective views of semiconductor device 250 after step 126 has been performed. Fins 260 have been formed from underlying silicon layer 251. Hard mask 252 is used to define fins 260 from silicon layer 251. Source / drain regions 262 and bottom spacers 264 have also been fabricated.

[0049] Through step 128, the semiconductor device 250 is annealed in a hydrogen environment so that the volume of the channel region increases. In some embodiments, step 128 includes annealing the semiconductor device 250 at an annealing temperature of at least two hundred degrees Celsius and no more than five hundred degrees Celsius for at least twenty seconds and no more than four hundred seconds. In some embodiments, the annealing may be performed at an annealing temperature of at least two hundred and fifty degrees Celsius. In some embodiments, the annealing time may be at least thirty seconds and no more than three hundred seconds. In the illustrated embodiment, step 128 is performed after step 124 and step 126. In other embodiments, step 128 may be performed before step 126 or before step 124 and step 126.

[0050] Fig. 6A and Figure 6B 1 and 2 depict cross-sectional and perspective views of semiconductor device 250 after performing step 128. Fig. 6A , the original position of the sidewall above the bottom spacer 264 is indicated by the dotted line. The volume of the portion of the fin 260′ covered by the hard mask 252, the source / drain region 262, and the bottom spacer 264 is not significantly changed. Due to the hydrogen annealing, the volume of the exposed portion of the silicon fin 260′ expands, bending outward. This increases the volume of the channel region of the fin 260′. In addition, as Figure 6B As can be seen in FIG. 2 , the outer regions of the fin 260 ′ tend to expand in volume beyond the central region.

[0051] The fabrication of the finFET then continues. An oxide layer and a conductive gate layer are provided via step 130. For example, an interface oxide layer and a gate oxide layer may be provided in step 130. In addition, a metal gate may be deposited. The oxide layer and the gate layer are patterned into a desired shape via step 132. A top spacer layer for the fin 260' is provided via step 134. A top source and / or drain region is also provided via step 136. In some embodiments, step 136 includes forming an epitaxial source / drain layer. An insulator may be deposited on the semiconductor device 250 via step 138. Contacts to the top source / drain and the bottom source / drain are formed via step 140. Additional dielectric may be deposited via step 142. The fabrication of the semiconductor device 250 may be completed via step 144.

[0052] Figure 7 A portion of the semiconductor device 250 is depicted after fabrication is complete. Thus, three fin FETs 280 are depicted. Each fin FET 280 includes a fin 260' having an extended channel region, a source / drain region 262, a bottom spacer 264, an interface oxide 266, a gate oxide 270, a metal gate 272, a top spacer 274, and a top source / drain 276.

[0053] Method 120 and semiconductor device 250 may share the benefits of method 100 and semiconductor device 200. Using method 120, the volume of a portion of fin 260' has been selectively increased. More specifically, the channel region of fin 260' in fin field effect transistor 280 has been expanded. Therefore, the geometry of fin field effect transistor 280 may be adapted without significantly changing the spacing between fins 260' or without method 120 of manufacturing fin field effect transistor 280.

[0054] Figure 8 1 is a flow chart depicting an exemplary embodiment of a method 150 for providing a finFET with an extended channel volume in a semiconductor device. For simplicity, some steps may be omitted, may include sub-steps, may be performed in another order, and / or may be combined. Additionally, method 150 may begin after other steps of forming a semiconductor device have been performed. Figures 9 to 12 A portion of an exemplary embodiment of a semiconductor device 250A is depicted during fabrication of a finFET using method 150. For simplicity, not all components are shown. Figures 9 to 12 Zhongqie Figures 9 to 12 Not drawn to scale. For example, various structures that may be formed before the fins are not shown. Additionally, the thickness of the layers may be exaggerated for illustrative purposes. For clarity, only structures formed in the region of the transistor are shown. Method 150 is described in the context of semiconductor device 250A. However, nothing prevents method 150 from being used with different semiconductor devices.

[0055] Fins are provided from the silicon layer, via step 152. For example, a dielectric hard mask may be fabricated on the underlying Si layer. The openings in the hard mask correspond to the Si regions to be removed. The Si layer is then etched, leaving the fins. Bottom source / drain regions are formed, via step 154. In some embodiments, step 154 ​​includes growing an epitaxial layer, such as SiGe, for use in the source / drain regions. Steps 152 and 154 are similar to steps 122 and 124 of method 120.

[0056] Fig. 9 The semiconductor device 250A is depicted after step 154 ​​has been performed. Thus, fins 260A have been formed from the underlying silicon layer 251. A hard mask 252 is used to define the fins 260A from the silicon layer 251. Source / drain regions 262 and bottom spacers 264 have also been fabricated.

[0057] The hard mask 252 used to form the fin 260A is removed, via step 156 . This step is performed so that the top surface of the fin 260A can be exposed during annealing, discussed below. A bottom spacer layer is deposited, via step 158 .

[0058] The bottom spacer 264A is then recessed via step 160 to expose the top of the fin 260A. Fig.10The semiconductor device 250A is depicted after performing step 160. Thus, the bottom spacers 264A have been deposited and their height has been reduced to allow the desired amount of the fins 260A to protrude above the top surface of the bottom spacers 264A.

[0059] Through step 162, the semiconductor device 250A is annealed in a hydrogen environment so that the volume of the top of the fin 260A increases. In some embodiments, step 162 includes annealing the semiconductor device 250A at an annealing temperature of at least two hundred degrees Celsius and no more than five hundred degrees Celsius for at least twenty seconds and no more than four hundred seconds. In some embodiments, the annealing may be performed at an annealing temperature of at least two hundred and fifty degrees Celsius. In some embodiments, the annealing time may be at least thirty seconds and no more than three hundred seconds.

[0060] Fig.11 A cross-sectional view of the semiconductor device 250A after performing step 162 is depicted. The original position of the sidewalls and top of the fin 260A′ above the bottom spacer 264A is indicated by the dotted lines. The volume of the portion of the fin 260A′ covered by the source / drain region 262 and the bottom spacer 264A is not significantly changed. Due to the hydrogen annealing, the volume of the exposed portion of the silicon fin 260A′ expands, bending outward. This convex shape increases the volume of the top region of the fin 260A′.

[0061] The fabrication of the finFET then continues. The bottom spacer 264A is thicker than required for the final device. Therefore, the bottom spacer 264A is further recessed by step 164. An oxide layer and a conductive gate are provided by step 166. For example, an interface oxide layer and a gate oxide layer may be provided in step 166. In addition, a metal gate may be deposited. The oxide layer and the gate layer are patterned into the desired shape in a similar manner to that used for the semiconductor device 250. However, to achieve the target length, the oxide layer and the gate layer also need to be removed from the top of the fin 260A′. Therefore, these layers are recessed by step 168. A top spacer layer for the fin 260A′ is provided by step 170. A top source and / or drain region is also provided by step 172. In some embodiments, step 172 includes forming an epitaxial source / drain layer. An insulator may be deposited on the semiconductor device 250A by step 174. Contacts to the top source / drain and the bottom source / drain are formed by step 176. Additional dielectric may be deposited via step 178. Fabrication of semiconductor device 250A may be completed via step 180.

[0062] Fig.12A portion of semiconductor device 250A is depicted after fabrication is complete. Thus, three fin field effect transistors 280A are depicted. Each fin field effect transistor 280A includes a fin 260A′ with an extended source / drain region, a source / drain region 262, a bottom spacer 264A′, an interface oxide 266A, a gate oxide 270A, a metal gate 272A, a top spacer 274A, and a top source / drain 276A. Bottom spacer 264A′ has been reduced in thickness in step 164. In addition, interface oxide 266A and gate oxide 270A and metal gate 272A expose the top of fin 260A′.

[0063] Method 150 and semiconductor device 250A can share the benefits of method 100 and semiconductor device 200. Using method 150, the volume of a portion of fin 260A' has been selectively increased. More specifically, the top source / drain region of fin 260A' in fin field effect transistor 280A has been expanded. This provides a larger volume for the top source drain processing of step 172. Therefore, parasitic resistance can be reduced. Therefore, the performance of fin field effect transistor 280A can be improved.

[0064] Methods and systems for selectively expanding the volume of fins in semiconductor devices have been described. The methods and systems have been described according to the illustrated exemplary embodiments, and one of ordinary skill in the art will readily recognize that the embodiments may vary, and any variations will be within the spirit and scope of the methods and systems. Therefore, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

1. A method for providing a semiconductor device, include: providing a plurality of fins such that a first portion of each of the plurality of fins is covered by a mask and a second portion of each of the plurality of fins is exposed through the mask, the plurality of fins being Si fins; as well as performing an anneal in a volume increasing environment at at least one annealing temperature greater than one hundred degrees Celsius and not greater than six hundred degrees Celsius, the second portion of each of the plurality of fins being exposed during the annealing such that the second portion of each of the plurality of fins undergoes a volume expansion, Wherein the second portion of each of the plurality of fins includes at least one of a source region and a drain region such that at least one of the source region and the drain region undergoes expansion during the annealing. 2 . The method for providing a semiconductor device according to claim 1 , wherein the volume enlargement environment is hydrogen gas.

3. The method for providing a semiconductor device according to claim 2, wherein the step of performing the annealing further comprises: The annealing is performed for an annealing time of at least ten seconds and no more than five hundred seconds. 4 . The method for providing a semiconductor device according to claim 3 , wherein the annealing time is at least twenty seconds and no more than four hundred seconds.

5. The method of providing a semiconductor device according to claim 2, wherein the at least one annealing temperature is at least two hundred degrees Celsius and no more than five hundred degrees Celsius.

6. The method for providing a semiconductor device according to claim 2, wherein the step of providing the plurality of fins further comprises: providing a hard mask on the semiconductor layer, the hard mask exposing a portion of the semiconductor layer; removing exposed portions of the semiconductor layer to form the plurality of fins, each of the plurality of fins having a top surface, the hard mask being present on the top surface; providing a bottom source / drain epitaxial layer on the removed portion of the semiconductor layer; as well as A bottom spacer is provided on the bottom source / drain epitaxial layer, the bottom spacer and the hard mask forming the mask.

7. A method of providing a semiconductor device, include: providing a plurality of fins such that a first portion of each of the plurality of fins is covered by a mask and a second portion of each of the plurality of fins is exposed through the mask, the plurality of fins being Si fins; as well as An anneal is performed in a volume increasing environment at at least one annealing temperature greater than one hundred degrees Celsius and not more than six hundred degrees Celsius, the second portion of each of the plurality of fins being exposed during the annealing such that the second portion of each of the plurality of fins undergoes volume expansion, wherein the second portion of each of the plurality of fins includes a channel region such that the channel region undergoes expansion during the annealing.

8. A method of providing a semiconductor device, include: Providing a plurality of fins such that a first portion of each of the plurality of fins is covered by a mask and a second portion of each of the plurality of fins is exposed through the mask, wherein the step of providing the plurality of fins further comprises: providing a hard mask on the semiconductor layer, the hard mask exposing a portion of the semiconductor layer; removing exposed portions of the semiconductor layer to form the plurality of fins, each of the plurality of fins having a top surface, the hard mask being present on the top surface; removing the hard mask; providing a bottom source / drain epitaxial layer on the removed portion of the semiconductor layer; as well as providing a recessed bottom spacer on the bottom source / drain epitaxial layer, the recessed bottom spacer forming the mask; as well as The annealing is performed in a volume increasing ambient at at least one annealing temperature greater than one hundred degrees Celsius and not greater than six hundred degrees Celsius, the second portion of each of the plurality of fins being exposed during the annealing such that the second portion of each of the plurality of fins undergoes volume expansion.

9. A method of providing a semiconductor device, include: providing a plurality of fins such that a first portion of each of the plurality of fins is covered by a mask and a second portion of each of the plurality of fins is exposed through the mask, each of the plurality of fins being composed of silicon; as well as In the presence of the mask, annealing is performed in a hydrogen environment at at least one annealing temperature for an annealing time, the at least one annealing temperature being at least two hundred degrees Celsius and not more than five hundred degrees Celsius, the annealing time being at least twenty seconds and not more than four hundred seconds, the second portion of each of the plurality of fins being exposed during the annealing such that the second portion of each of the plurality of fins undergoes volume expansion, the second portion including at least one of a channel region and a top source / drain region.

10. The method for providing a semiconductor device according to claim 9, wherein the step of providing the plurality of fins further comprises: providing a hard mask on the semiconductor layer, the hard mask exposing a portion of the semiconductor layer; removing exposed portions of the semiconductor layer to form the plurality of fins, each of the plurality of fins having a top surface, the hard mask being present on the top surface; removing the hard mask; providing a bottom source / drain epitaxial layer; as well as A recessed bottom spacer is provided, the recessed bottom spacer forming the mask.

11. A semiconductor device, include: a plurality of fins, each of the plurality of fins having a channel region and a top source / drain region, at least one of the plurality of fins and the top source / drain region having an expanded area, wherein the expanded area includes the top source / drain region such that the top source / drain region undergoes expansion during annealing; a plurality of gates covering a portion of the plurality of fins; A plurality of oxide layers existing between the plurality of fins and the plurality of gates; as well as Multiple source / drain regions.

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