Crystal oscillator circuit

Abstract

A method and a crystal oscillator circuit are disclosed for matching a supply voltage with a drive level of a crystal. The crystal oscillator circuit is based on a crystal oscillator circuit further comprising a capacitor C d The Pierce oscillator circuit. The capacitor C d Together with the load capacitor it acts as a capacitive voltage divider and the capacitance of this capacitor can be chosen to drop the supply voltage to match the drive level of the crystal oscillator without affecting the oscillation headroom of the crystal.

Description

Technical Field

[0001] Embodiments herein relate to crystal oscillator circuits. In particular, embodiments herein relate to matching a supply voltage for an amplifier to a drive level of a quartz crystal in the crystal oscillator circuit, and electronic devices including the crystal oscillator circuit. Background Art

[0002] A crystal oscillator circuit consists of a feedback network with an amplifier or gain element and a crystal. Historically both of these components were designed and manufactured by companies specializing in frequency control products. However, this paradigm has changed with independent companies designing and manufacturing crystals and amplifiers. This creates problems in matching the amplifier or gain element to the crystal.

[0003] An important factor for a well-functioning crystal oscillator is that the supply voltage of the amplifier should at least approximately match the drive level of the quartz crystal, otherwise the crystal will have problems reaching the target frequency and experience accelerated aging. Different solutions are explained in the prior art to match the supply voltage to the drive level of the crystal, and a solution often recommended by suppliers is to use a so-called Pierce oscillator circuit, in which a damping resistor is added. The damping resistor does damp the supply voltage of the crystal. However, it also affects the oscillation ability of the crystal. That is, the oscillation margin will be reduced and in some cases means that the crystal will not start to oscillate at all. Summary of the invention

[0004] In view of the foregoing, it is an object of embodiments herein to provide a technique for matching a supply voltage to a drive level of a crystal in a crystal oscillator circuit.

[0005] According to one aspect of the embodiments of this document, the object is achieved by a crystal oscillator circuit comprising: an inverting amplifier having an input and an output; and a feedback resistor having a first end connected to the input of the inverting amplifier and a second end connected to the output of the inverting amplifier.

[0006] The crystal oscillator circuit also includes: a quartz crystal having a first end and a second end; a first load capacitor connected between the first end of the quartz crystal and a signal ground; and a second load capacitor connected between the second end of the quartz crystal and the signal ground.

[0007] The crystal oscillator circuit also includes a third capacitor connected between the second end of the feedback resistor and the second end of the quartz crystal. Select the capacitance C of the third capacitor d , where C Lis the equivalent capacitance of the first and second load capacitors, and k is the damping factor. In this way, the supply voltage to the inverting amplifier is attenuated by the damping factor k at the second terminal of the quartz crystal and thus matches the drive level of the quartz crystal.

[0008] According to one aspect of the embodiments herein, this object is achieved by using the above-mentioned crystal oscillator circuit for matching the supply voltage of the inverting amplifier with the driving level of the quartz crystal.

[0009] According to one aspect of the embodiments of the present invention, the purpose is achieved by a method for matching the supply voltage of an inverting amplifier with the drive level of a quartz crystal in a crystal oscillator circuit. The crystal oscillator circuit includes: an inverting amplifier having an input and an output; and a feedback resistor having a first end connected to the input of the inverting amplifier and a second end connected to the output of the inverting amplifier. The crystal oscillator circuit also includes: a quartz crystal having a first end and a second end; a first load capacitor connected between the first end of the quartz crystal and a signal ground; and a second load capacitor connected between the second end of the quartz crystal and the signal ground. The method includes connecting a third capacitor between the second end of the feedback resistor and the second end of the quartz crystal, and according to the equation Select the capacitance C of the third capacitor d , where C L is the equivalent capacitance of the first and second load capacitors, and k is the damping factor. In this way, the supply voltage of the inverting amplifier is attenuated by the damping factor k at the second terminal of the quartz crystal to match the drive level of the quartz crystal.

[0010] The technique for matching the supply voltage to the drive level of a crystal in a crystal oscillator circuit is based on further including a capacitor C d The Pierce oscillator circuit. Capacitor C d Together with the load capacitor it acts as a capacitive voltage divider and the capacitance of this capacitor can be chosen to drop the supply voltage to match the drive level of the crystal oscillator without affecting the oscillation headroom of the crystal.

[0011] Crystal oscillator circuits according to embodiments herein are particularly useful when it is necessary to reduce the drive level of the crystal by a factor of 2 or more. That is, the mismatch is very large and means that using the alternative approach described in the prior art would require very large resistors.

[0012] The matching method according to the embodiment of this article is particularly suitable for but not limited to the following situations:

[0013] Oscillator circuits using physically small quartz crystals where low drive levels are required, typically <400uW;

[0014] Oscillator circuit with high supply voltage (e.g. greater than 1.5V);

[0015] Oscillator circuits using an inverting amplifier with high voltage gain, such as a buffered inverter with a square wave output voltage that swings rail-to-rail;

[0016] Oscillator circuit, which reduces the quartz crystal load capacitance C L Can lead to unacceptable frequency pulling sensitivity;

[0017] Oscillator circuits where adding a damping resistor results in severely reduced oscillation margin, e.g. when the parallel capacitance of the quartz crystal is high, typically greater than 1 pF;

[0018] Oscillator circuits where the transconductance of the inverting amplifier is unknown and it is therefore undesirable to introduce additional resistive damping that would reduce the oscillation margin;

[0019] Oscillator circuits where adding a damping resistor has only a slight effect on reducing the drive level, i.e. the required damping resistance is too high.

[0020] Thus, embodiments herein provide a technique for matching a supply voltage to the drive level of a crystal in a crystal oscillator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Examples of embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0022] Figure 1 is a schematic block diagram showing a Pierce oscillator circuit according to the prior art;

[0023] Figure 2 is a schematic diagram showing an equivalent circuit of a crystal;

[0024] Figure 3 is a schematic block diagram showing a negative resistance model of a crystal oscillator circuit;

[0025] Figure 4 is a schematic block diagram showing an oscillator circuit according to an embodiment of the present invention;

[0026] Figure 5 is a flow chart of a method for matching the drive level of a crystal; and

[0027] Figure 6 is a block diagram illustrating an electronic device in which an oscillator circuit according to embodiments herein may be implemented. DETAILED DESCRIPTION

[0028] As part of the embodiments developed herein, the function, principle and some problems of a Pierce oscillator circuit with a damping resistor according to the prior art will first be discussed and identified.

[0029] Figure 1 A simplified schematic diagram of a Pierce oscillator circuit 100 is shown. The Pierce oscillator circuit 100 includes a crystal Q, a feedback resistor R f , an inverter or inverting amplifier Inv, first and second load capacitors C1 and C2, and a damping resistor R d , where V DD is the supply voltage of the inverting amplifier Inv, g m is the transconductance gain of the inverting amplifier Inv, expressed in mA / V.

[0030] Feedback resistor R f Provides a bias point in the linear region of the transistor in the inverting amplifier Inv, which is close to V DD / 2. R f The typical value is about 1MΩ. f Can be embedded in the oscillator circuit. The feedback resistor R f The inverter Inv having a logic gate is converted into an analog amplifier.

[0031] Choose the values ​​of the load capacitors, C1 and C2, so that their series combination equals C L Typically, C1 and C2 are chosen to be slightly less than 2·C L Taking into account the stray capacitance C S The capacitor type should have a low temperature coefficient and a low tolerance, such as 5%.

[0032]

[0033] in

[0034] C S is the total stray capacitance, mainly from the input and output pad capacitance of the inverter.

[0035] The ideal characteristic of the Pierce oscillator circuit 100 is that the stray capacitance C s1 and C s2 The influence appears on C1 and C2 respectively, rather than on the crystal capacitor C0.

[0036] Figure 2 The equivalent circuit of the crystal is shown. Component L m , C m and R m They are called kinematic arms and represent the mechanical behavior of the crystal.

[0037] If R is ignored m , the impedance of the crystal is

[0038]

[0039] Figure 3 shows a negative resistance model for a crystal oscillator circuit that can be used with respect to C L and C0 optimized g m , in order to achieve the maximum oscillation margin. The oscillation condition in the negative resistance model is:

[0040] -R NEG =R M , that is, the absolute value of the negative resistance is equal to the resistance of the moving arm;

[0041] -X oSC =X M , i.e. the reactive part, i.e. the capacitive part of the active oscillator network and the reactive part of the moving arm must cancel out.

[0042] Given g m The oscillation margin can be expressed as the resistance R S , and expressed as

[0043] R s =|R NEG |-(R d +5R e ) Equation (2)

[0044] Where R e is any load capacitance C L The effective resistance of the crystal under

[0045]

[0046] Movement resistance R m Can reach 5R at startup m , so the effective resistance R e You can also achieve 5R e When checking the oscillation margin of a crystal oscillator circuit, you can add a resistor in series with the crystal and check whether the oscillation stops. Therefore, R S Corresponds to the maximum resistance that can be added in series with the crystal before oscillations cease.

[0047] The negative resistance, or gain around the loop, is g m , C1, C2 and C0. For g m_min or m_max , R will appear NEG_min . C1, C2 and C0 are part of the active network.

[0048] As C0 increases, the maximum achievable absolute value of the negative resistance decreases, as can be seen from the following equation:

[0049]

[0050] The drive level of the crystal can be determined using the following equation:

[0051] P x =R e I 2

[0052] The effective resistance of the crystal for any load capacitance is

[0053]

[0054] Where R m is the resistance of the crystal, and I is the current through the crystal, which can be defined as

[0055]

[0056] but

[0057] P x =R e ·(Vω·C1) 2

[0058] where V is the root mean square (RMS) value of the AC component of the voltage across C1.

[0059] At resonance, the reactance of the moving arm becomes inductive and reacts with C L +C0 parallel resonance. Then, the current I through the crystal can also be expressed as

[0060]

[0061] Where Vp is the peak voltage across the crystal, which gives

[0062]

[0063] The voltage gain of an unbuffered inverter can be in the hundreds. The voltage gain of a buffered inverter is in the range of thousands.

[0064] For a rough approximation of the power dissipated in the crystal, estimate that when the voltage at the output of the inverting amplifier is OUT When it is a square wave, the output voltage of the buffer inverter swings rail to rail, with a value close to V DD The peak-to-peak voltage swing is approximately a sine wave across the crystal, with a peak voltage V p =V DD .

[0065] For oscillators with unbuffered inverters or with amplitude-limited control, or when it can be measured, the maximum voltage amplitude obtained across the crystal should be used in calculating the drive level. OUT A rough approximation of the power dissipated by the crystal for a sine wave is given by assuming that there is a peak voltage across the crystal. of a sine wave.

[0066] From equation (4), we can see that in order to reduce the drive level, we can reduce R e , C L and / or V p . R m is given by the size of the crystal. Larger crystals will have lower R m But also has a higher C0. Lower C L will reduce the drive level, but it will also result in higher pulling sensitivity, i.e. the frequency change for each load capacitance change. C should be chosen L In order to maximize the negative resistance R that the active network of the crystal oscillator circuit can provide NEG .

[0067] Therefore, it may be necessary to reduce V p To reduce the drive level. p One way is to reduce V DD One method often proposed in the prior art is to add a series damping resistor R d , whose value is:

[0068]

[0069] In X OUT At a point with a value equal to V DD The peak-to-peak voltage swing of a square wave will be across the damping resistor R d The other side appears as a sine wave with a peak-to-peak voltage swing equal to V DD 90% of

[0070] However, the damping resistor R d This will directly reduce the oscillation margin, as shown in formula (2).

[0071] In order to solve the above problem, a capacitor C d In this way, C2 and the damping capacitor form a capacitive voltage divider, which directly reduces V p , expressed as

[0072] V p = k·V dd

[0073] in is the damping factor.

[0074] Assume that the undamped drive level is P1 and the target drive level is P t ,So

[0075] P t =k 2 P1

[0076] The capacitance of the damping capacitor is given by

[0077]

[0078] Figure 4 A crystal oscillator circuit 400 according to an embodiment of the present invention is shown. The crystal oscillator circuit 400 includes: an inverting amplifier 410 having an input 411 and an output 412; a feedback resistor 420 having a first end 421 connected to the input of the inverting amplifier 410 and a second end 422 connected to the output of the inverting amplifier 410; a quartz crystal 430 having a first end 431 and a second end 432; a first load capacitor C1 connected between the first end 431 of the quartz crystal 430 and a signal ground Gnd; a second load capacitor C2 connected between the second end 432 of the quartz crystal 430 and the signal ground Gnd; and a third capacitor 440 connected between the second end 422 of the feedback resistor 420 and the second end 432 of the quartz crystal 430.

[0079] According to the equation The capacitance C of the third capacitor 440 is selected d , where C L is the equivalent capacitance of the first and second load capacitors, and k is the damping factor, so that the supply voltage of the inverting amplifier 410 is attenuated by the damping factor k at the second terminal 432 of the quartz crystal 430 to match the drive level of the quartz crystal 430. The drive level is usually given in the product specification, which indicates the power consumption of the crystal when the oscillation circuit is operating. It is important for the crystal to stay within the drive level specification. Therefore, the supply voltage at the crystal should be at an appropriate level so that the power consumption of the crystal should not exceed the drive level specified in the crystal specification.

[0080] Figure 5 A flow chart is shown of a method for matching a supply voltage of an inverting amplifier to a drive level of a quartz crystal in a crystal oscillator circuit 400. The method comprises connecting 501 a third capacitor between a second end of a feedback resistor and a second end of the quartz crystal.

[0081] The method also includes the following steps: Select 502 the capacitance C of the third capacitor d, where is the equivalent capacitance of the first and second load capacitors, and k is the damping factor, so that the supply voltage of the inverting amplifier is attenuated by the damping factor k at the second end of the quartz crystal to match the drive level of the quartz crystal.

[0082] To illustrate the advantages of adding a damping capacitor according to the embodiments herein, a number of different crystals were investigated. Typically, the maximum drive level for these crystals is specified as 200-300uW, depending on the manufacturer. According to the datasheet, the maximum shunt capacitance C of the different crystals is 0_max The typical shunt capacitance C is specified in the range of 1-3pF. 0_ t yp In the range of 0.5-1pF. An example is given below.

[0083] Example 1: V DD =3.3V,f=24MHz,C L =10pF,C 0_ t yp =0.57pF,C 0_max =1.0pF,R m_max =80Ω

[0084] The effective resistance of the crystal can be calculated according to equation (3):

[0085] R e_max =R e (R m_max ,C L ,C 0_typ )=89.4Ω

[0086] According to the driving level of equation (4):

[0087] P1=P X (R e_max ,f,C L ,C 0_typ ,V DD )=1.2mW>300uW

[0088] It can be seen that the drive level to this crystal is too high and must be reduced. The problem is mainly caused by the high supply voltage.

[0089] If the load capacitance is reduced, that is, C L =8pF, then the drive level is:

[0090] P1=P X (R e_max ,f,C L ,C 0_typ ,V DD )=835uW

[0091] The crystal drive level is now lower because C L It has been reduced, but it is still too high and must be reduced further.

[0092] Assume the target drive level is P t =280uW,P t =k 2 ·P1 where k is the desired voltage damping factor.

[0093] The damping capacitor is

[0094] Example 2: V DD =1.8V,f=50MHz,C L =8pF,C 0_typ =1pF,C 0_max =3pF,R m_max =50Ω

[0095] The effective resistance of the crystal can be calculated according to equation (3):

[0096] R e_max =R e (R m_max ,C L ,C 0_typ )=63Ω

[0097] And the drive level is calculated according to equation (4):

[0098] P1=P X (R e_max ,f,C L ,C 0_typ ,V DD )=1.2mW>200uW

[0099] It can be seen that the drive level to this crystal is too high and must be reduced. The problem is mainly caused by the high supply voltage.

[0100] Assume the target drive level is P t =180uW,P t =k 2 ·P1, where k is the desired voltage damping factor.

[0101] The damping capacitor is

[0102] Some measurements have been made on the crystal oscillator circuit of the example above, and the measured drive levels are close to the estimated drive levels while maintaining the negative resistance.

[0103] The method for matching the supply voltage of the inverting amplifier to the drive level of the quartz crystal according to the embodiments of the present invention is particularly useful when the mismatch is very large. A large mismatch between the supply voltage of the inverting amplifier and the drive level of the quartz crystal means that the solution according to the prior art will require a large resistor, which will also severely reduce the oscillation margin. For example, when it is necessary to reduce the drive level by a factor of 2 or more, i.e., P1>2·Pt, where the drive level without damping is P1 and the target drive level is P t .

[0104] To avoid frequency accuracy issues and accelerated aging of the quartz crystal, the estimated power consumption P X Should be less than the maximum drive level (DL) specified in the quartz crystal data sheet.

[0105] So the goal is

[0106]

[0107] This makes

[0108]

[0109] For inverters with square wave output, i.e. buffer inverters with high voltage gain, e.g. 1000x, this method is particularly useful in the following cases:

[0110]

[0111] For inverters with sine wave output, i.e. unbuffered inverters with low voltage gain, e.g. 100x, this method is particularly useful in the following cases:

[0112]

[0113] Therefore, according to some embodiments herein, when the inverting amplifier is a buffered inverter and the output voltage from the inverting amplifier is a square wave, a typical damping factor may be Or even k < 1 / 2.

[0114] When the output voltage from the inverting amplifier is a sine wave, a typical damping factor may be

[0115] Although in some prior arts, in the case of a damping capacitor C d A capacitor is connected at the same position, but it has different functions. For example, in CN104052465, Figure 5In the CMOS Crystal Oscillators, capacitor CS is used for phase compensation to achieve zero phase shift. In "HCMOS Crystal Oscillators", Fairchild Semiconductor Application Note 340, May 1983, it is recommended that when the oscillator is operated at high frequencies, such as above 4 MHz, the damping resistor R2 should be changed to a small capacitor to avoid the additional phase shift of R2. The value of this capacitor is about 1 / ωC ​​but not less than about 20 pF.

[0116] Therefore, compared with the prior art, the function and purpose of the damping capacitor according to the embodiments herein are significantly different.

[0117] In summary, the technique for matching the supply voltage to the drive level of a crystal in a crystal oscillator circuit according to embodiments herein is based on also including a damping capacitor C d The Pierce oscillator circuit. Capacitor C d Together with the load capacitor it acts as a capacitive voltage divider and the capacitance of this capacitor can be chosen to drop the supply voltage to match the drive level of the crystal oscillator without affecting the oscillation headroom of the crystal oscillator circuit.

[0118] Crystal oscillator circuits according to embodiments herein are particularly useful when it is necessary to reduce the drive level of the crystal by a factor of 2 or more. That is, the mismatch is very large and means that by using damping resistors as described in the prior art a large resistance would be required, which may result in large phase shifts, lower oscillation margins, or even possible failure to initiate oscillation.

[0119] The matching method according to the embodiment of this article is particularly suitable for the following situations but is not limited to the following situations:

[0120] Oscillator circuits using physically small quartz crystals where low drive levels are required, typically <400uW;

[0121] Oscillator circuit with high supply voltage (e.g. greater than 1.5V);

[0122] Oscillator circuits using an inverting amplifier with high voltage gain, such as a buffered inverter with a square wave output voltage that swings rail-to-rail;

[0123] Oscillator circuit, which reduces the quartz crystal load capacitance C L Can lead to unacceptable frequency pulling sensitivity;

[0124] Oscillator circuits where adding a damping resistor results in severely reduced oscillation margins, for example when the parallel capacitance of a quartz crystal is high, typically greater than 1pF. This is because the oscillation margin is small and adding a resistor divider will affect the oscillation of the crystal;

[0125] Oscillator circuits where the transconductance of the inverting amplifier is unknown and it is therefore undesirable to introduce additional resistive damping that would reduce the oscillation margin;

[0126] Oscillator circuits where adding a damping resistor has only a slight effect on reducing the drive level, i.e. the required damping resistance is too high.

[0127] The crystal oscillator circuit 400 and method according to the embodiments of this document are used to match the supply voltage of an inverting amplifier with the driving level of a quartz crystal, and are applicable to any electronic device requiring a clock signal. Figure 6 An electronic device 600 is shown in which a crystal oscillator circuit 400 according to embodiments herein may be implemented. The electronic device 600 may also include a processing unit 620 for information storage and signal processing, a memory 640 for storing data, configurations, program codes, etc. The electronic device 600 may be any of a transmitter, a receiver, a transceiver, a frequency synthesizer, a wireless communication device, a wireless data acquisition device, a camera such as a surveillance camera or a network video recorder, a home automation device, a data recorder, a video encoder, a physical access controller, or a door station.

[0128] When the word "comprising" or "including" is used, it should be interpreted as non-limiting, ie meaning "including at least".

[0129] The embodiments herein are not limited to the preferred embodiments described above. Various substitutions, modifications and equivalents may be used. Therefore, the above embodiments should not be considered to limit the scope of the present invention, which is defined by the appended claims.

Claims

1. A crystal oscillator circuit (400), comprising: an inverting amplifier (410) having an input (411) and an output (412); a feedback resistor (420) having a first end (421) connected to the input of the inverting amplifier (410) and a second end (422) connected to the output of the inverting amplifier (410); a quartz crystal (430) having a first end (431) and a second end (432); a first load capacitor (C1) connected between the first end (431) of the quartz crystal (430) and a signal ground (Gnd); a second load capacitor (C2) connected between the second end (432) of the quartz crystal (430) and the signal ground (Gnd); a third capacitor (440) connected between the second end (422) of the feedback resistor and the second end (432) of the quartz crystal (430); Features: According to the equation The capacitance C of the third capacitor (440) is selected d , where C L is the equivalent capacitance of the first and second load capacitors, and k is a damping factor, such that the supply voltage to the inverting amplifier (410) is attenuated by the damping factor k at the second end (432) of the quartz crystal (430) to match the drive level of the quartz crystal (430); Wherein when the inverting amplifier is a buffered inverter and the output voltage from the inverting amplifier is a square wave, the required damping factor is or Where when the output voltage from the inverting amplifier is a sine wave, the required damping factor is 2. The crystal oscillator circuit (400) of claim 1, wherein the drive level is reduced by a factor of 2 or greater.

3. The crystal oscillator circuit (400) of claim 1, wherein the shunt capacitance of the quartz crystal (430) is greater than 1 pF.

4. The crystal oscillator circuit (400) of claim 1, wherein a driving level of the quartz crystal (430) is lower than 400uW.

5. The crystal oscillator circuit (400) according to any one of claims 1 to 4, wherein a supply voltage of the inverting amplifier (410) is greater than 1.5V.

6. An electronic device comprising the crystal oscillator circuit (400) according to any one of claims 1 to 5.

7. The electronic device of claim 6, comprising any one of a transmitter, a receiver, a transceiver, a frequency synthesizer, a wireless communication device, a wireless data acquisition device, a camera such as a surveillance camera or a network video recorder, a home automation device, a data recorder, a video encoder, a physical access controller, or a door station.

8. A method for matching a supply voltage of an inverting amplifier to a drive level of a quartz crystal in a crystal oscillator circuit, wherein the crystal oscillator circuit comprises: an inverting amplifier having an input and an output; a feedback resistor having a first end connected to the input of the inverting amplifier and a second end connected to the output of the inverting amplifier; a quartz crystal having a first end and a second end; a first load capacitor (C1) connected between the first end of the quartz crystal and a signal ground; a second load capacitor (C2) connected between the second terminal of the quartz crystal and the signal ground; and the method comprising: connecting a third capacitor between the second end of the feedback resistor and the second end of the quartz crystal; as well as According to the equation The capacitance C of the third capacitor is selected d , where C L is the equivalent capacitance of the first and second load capacitors, and k is a damping factor, such that the supply voltage of the inverting amplifier is attenuated by the damping factor k at the second end of the quartz crystal to match the drive level of the quartz crystal; Wherein when the inverting amplifier is a buffered inverter and the output voltage from the inverting amplifier is a square wave, the required damping factor is or k<1 / 2; Where when the output voltage from the inverting amplifier is a sine wave, the required damping factor is 9. A method of using the crystal oscillator circuit (400) according to any one of claims 1 to 5, for matching the supply voltage of the inverting amplifier (410) to the drive level of the quartz crystal (430).

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