Fin Field-Effect Transistor Device Structure

Abstract

Embodiments of the present disclosure provide a fin field-effect transistor device structure, which includes a fin structure formed on a substrate and a first gate structure formed on the fin structure. The fin field-effect transistor device structure further includes a first capping layer formed on the first gate structure and a first etch stop layer located on the first capping layer and the first gate structure. The fin field-effect transistor device structure further includes a first source / drain contact structure formed on the fin structure and adjacent to the first gate structure. A portion of the first etch stop layer directly above the first capping layer is higher than another portion of the first etch stop layer directly above the first gate spacer layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit manufacturing, and particularly to a fin field effect transistor device structure with a capping layer and a method for forming the same. Background Art

[0002] Semiconductor devices are used in applications of various electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing materials of insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using lithography techniques to pattern the various material layers to form circuit components and elements on the semiconductor substrate. Many integrated circuits are usually fabricated on a single semiconductor wafer, and the individual dies on the wafer are separated by dicing along the scribe lines. For example, in a multi-chip module, or in other types of packages, these individual dies are usually separately packaged.

[0003] As the semiconductor industry has advanced to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have given rise to the development of three-dimensional designs, such as fin field effect transistors (FinFETs). FinFETs are fabricated using thin and vertical fins (or fin structures) extending from a substrate, with the channels of the FinFETs formed in the vertical fins and gates provided on the fins. The advantages of FinFETs may include reducing short-channel effects and providing higher current.

[0004] Although existing FinFET device structures and methods for fabricating FinFET device structures are generally sufficient for their intended purposes, they are still not entirely satisfactory in all aspects. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed on a substrate, and a first gate structure formed on the fin structure. The fin field effect transistor (FinFET) device structure further includes a first gate spacer adjacent to the first gate structure, a first capping layer formed on the first gate structure, and a first etch stop layer formed on the first capping layer and the first gate structure. The fin field effect transistor (FinFET) device structure further includes a first source / drain (S / D) contact structure formed on the fin structure and adjacent to the first gate structure, wherein a portion of the first etch stop layer directly above the first capping layer is higher than another portion of the first etch stop layer directly above the first gate spacer.

[0006] According to some other embodiments of the present disclosure, a fin field-effect transistor (FinFET) device structure is provided. The fin field-effect transistor (FinFET) device structure includes a fin structure formed on a substrate, and a first gate structure formed on the fin structure, the first gate structure having a first width. The fin field-effect transistor (FinFET) device structure also includes a second gate structure formed on the fin structure, the second gate structure having a second width, and the first width is greater than the second width. The fin field-effect transistor (FinFET) device structure further includes a first capping layer formed on the first gate structure, and the first capping layer directly contacts the top surface of the first gate structure. The fin field-effect transistor (FinFET) device structure further includes a second capping layer formed on the second gate structure, and the second capping layer directly contacts the top surface of the second gate structure. The top surface of the first capping layer is higher than the top surface of the second capping layer.

[0007] According to some embodiments of the present disclosure, a method for forming a fin field-effect transistor (FinFET) device structure is provided. The method includes forming a fin structure on a substrate, and the substrate includes a first region and a second region. The method also includes forming a first gate structure on the fin structure in the first region, the first gate structure having a first width. The method also includes forming a second gate structure on the fin structure in the second region, the second gate structure having a second width, and the first width is greater than the second width. The method further includes forming a first capping layer and a second capping layer on the first gate structure and the second gate structure respectively. The first capping layer directly contacts the top surface of the first gate structure, and the second capping layer directly contacts the top surface of the second gate structure, and the top surface of the first capping layer is higher than the top surface of the second capping layer. The method further includes forming a first etch stop layer and a second etch stop layer on the first capping layer and the second capping layer respectively. Description of the Drawings

[0008] To make the embodiments of the present disclosure easier to understand, the following provides a detailed description in conjunction with the accompanying drawings. It should be noted that according to industrial standard examples, each component (feature) is not necessarily drawn to scale. In fact, for the sake of clear discussion, the dimensions of each component can be arbitrarily enlarged or reduced.

[0009] Figures 1A to 1K A three-dimensional schematic diagram showing each stage of forming a fin field-effect transistor device structure according to some embodiments of the present disclosure.

[0010] Figures 2A to 2E Shown according to some embodiments of the present disclosure, forming Figures 1G to 1K A cross-sectional schematic diagram showing each stage of the fin field-effect transistor device structure shown, Figure 2A Shown along Figure 1G A cross-sectional schematic diagram of line I-I'.

[0011] Figure 3AShows a perspective schematic view of a fin field-effect transistor device structure according to some embodiments of the present disclosure.

[0012] Figure 3B Shows a cross-sectional schematic view along Figure 3A line I-I' of.

[0013] Figure 4A Shows a perspective schematic view of a fin field-effect transistor device structure according to some embodiments of the present disclosure.

[0014] Figure 4B Shows a cross-sectional schematic view along Figure 4A line I-I' of.

[0015] Description of reference numerals:

[0016] 11 ~ First region;

[0017] 12 ~ Second region;

[0018] 100, 200, 300 ~ Fin field-effect transistor (FinFET) device structures;

[0019] 102 ~ Substrate;

[0020] 104 ~ Dielectric layer;

[0021] 106 ~ Mask layer;

[0022] 108 ~ Photoresist layer;

[0023] 110 ~ Fin structure;

[0024] 112 ~ Insulating layer;

[0025] 114 ~ Isolation structure;

[0026] 116a ~ First dummy gate dielectric layer;

[0027] 116b ~ Second dummy gate dielectric layer;

[0028] 118a ~ First dummy gate electrode layer;

[0029] 118b ~ Second dummy gate electrode layer;

[0030] 120a ~ First dummy gate structure;

[0031] 120b ~ Second dummy gate structure;

[0032] 122a ~ First gate spacer layer;

[0033] 122b ~ Second gate spacer layer;

[0034] 124 - Source / Drain (S / D) structure;

[0035] 124a - First Source / Drain (S / D) structure;

[0036] 124b - Second Source / Drain (S / D) structure;

[0037] 128 - Interlayer dielectric layer;

[0038] 128a - First part;

[0039] 128b - Second part;

[0040] 130a - First trench;

[0041] 130b - Second trench;

[0042] 134a - First gate dielectric layer;

[0043] 134b - Second gate dielectric layer;

[0044] 136a - First work function layer;

[0045] 136b - Second work function layer;

[0046] 138a - First gate electrode layer;

[0047] 138b - Second gate electrode layer;

[0048] 139 - Conductive layer;

[0049] 140a - First gate structure;

[0050] 140b - Second gate structure;

[0051] 142a - First capping layer;

[0052] 142b - Second capping layer;

[0053] 144a - First etch stop layer;

[0054] 144b - Second etch stop layer;

[0055] 150 - Dielectric layer;

[0056] 162 - Barrier layer;

[0057] 164 - Conductive layer;

[0058] 166a - First Source / Drain (S / D) contact structure;

[0059] 166b - Second Source / Drain (S / D) contact structure;

[0060] W1 ~ The first width;

[0061] W2 ~ The second width;

[0062] H1 ~ The height difference. Detailed implementation manners

[0063] The following provides many different embodiments or examples to implement different components (features) of the subject matter of the embodiments of the present disclosure. The following describes specific examples of component and configuration manners to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that a first component is formed above or on a second component, which may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which additional components are formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in each example. This repetition is for the purpose of simplification and clarity, and is not itself used to specify the relationship between the various embodiments and / or configurations discussed.

[0064] Some variations of the embodiments are described below. In the various figures and the described embodiments, similar reference numerals are used to label similar elements. It can be understood that additional operations may be provided before, during, and after the described methods, and some of the operations described herein may be replaced or eliminated for other embodiments of the methods.

[0065] Any suitable method can be used to pattern the fin structure. For example, one or more lithography processes are used to pattern the fin structure, which includes double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes. For example, it enables the resulting pattern to have a smaller pitch than that achievable using other single direct lithography processes. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed on the sides of the patterned sacrificial layer using a self-alignment process, and then the sacrificial layer is removed, and the fin structure can be patterned using the remaining spacer pattern.

[0066] Embodiments for forming a fin field-effect transistor device structure are provided herein, Figures 1A to 1K showing a three-dimensional schematic diagram of each stage of forming a fin field-effect transistor device structure 100 according to some embodiments of the present disclosure.

[0067] Refer to Figure 1A, a substrate 102 is provided. The substrate 102 includes a first region 11 and a second region 12. The first region 11 is used to form a first gate structure (to be formed later) with a long channel, and the second region 12 is used to form a second gate structure (to be formed later) with a short channel.

[0068] The substrate 102 can be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 can include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 is made of compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 has an epitaxial layer on a bulk semiconductor.

[0069] After that, a dielectric layer 104 and a mask layer 106 are formed on the substrate 102, and a photoresist layer 108 is formed on the mask layer 106. The photoresist layer 108 is patterned through a patterning process, which includes a lithography process and an etching process. The lithography process includes photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process can include a dry etching process or a wet etching process.

[0070] The dielectric layer 104 is a buffer layer between the substrate 102 and the mask layer 106. In addition, when removing the mask layer 106, the dielectric layer 104 is used as a stop layer. The dielectric layer 104 can be made of silicon oxide, and the mask layer 106 can be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some other embodiments, more than one mask layer 106 is formed on the dielectric layer 104.

[0071] The dielectric layer 104 and the mask layer 106 are formed through a deposition process, such as a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process, or other suitable processes.

[0072] As Figure 1B shown, after the photoresist layer 108 is patterned, the dielectric layer 104 and the mask layer 106 are patterned by using the patterned photoresist layer 108 as a mask. According to some embodiments, a patterned dielectric layer 104 and a patterned mask layer 106 are obtained. After that, the patterned photoresist layer 108 is removed.

[0073] Next, an etching process is performed on the substrate 102 by using the patterned dielectric layer 104 and the patterned mask layer 106 as masks to form the fin structure 110. The etching process can be a dry etching process or a wet etching process.

[0074] In some embodiments, the substrate 102 is etched by a dry etching process. The dry etching process includes using a fluorine-based etching gas, such as SF6, C x F y , NF3, or a combination of the foregoing. The etching process can be a time-controlled process and is continuously performed until the fin structure 110 reaches a predetermined height. In some other embodiments, the width of the fin structure 110 gradually increases from the top to the lower part.

[0075] As Figure 1C shown, after the fin structure 110 is formed, according to some embodiments, an insulating layer 112 is formed to cover the fin structure 110 on the substrate 102.

[0076] In some embodiments, the insulating layer 112 is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low dielectric constant dielectric materials. The insulating layer 112 can be deposited by a chemical vapor deposition (CVD) process, a spin-on glass process, or other suitable processes.

[0077] Next, the insulating layer 112 is thinned or planarized to expose the top surface of the patterned mask layer 106. In some embodiments, the insulating layer 112 is thinned by a chemical mechanical polishing (CMP) process. After that, the patterned dielectric layer 104 and the patterned mask layer 106 are removed.

[0078] Next, as Figure 1D shown, according to some embodiments, a portion of the insulating layer 112 is removed to form the isolation structure 114. The isolation structure 114 can be a shallow trench isolation (STI) structure that surrounds the fin structure 110. The lower part of the fin structure 110 is surrounded by the isolation structure 114, and the higher part of the fin structure 110 protrudes from the isolation structure 114. In other words, a portion of the fin structure 110 is buried in the isolation structure 114. The isolation structure 114 prevents electrical interference or crosstalk.

[0079] After that, as Figure 1E shown, according to some embodiments, a first dummy gate structure 120a and a second dummy gate structure 120b are formed, which span the fin structure 110 and extend over the isolation structure 114.

[0080] In some embodiments, the first dummy gate structure 120a includes a first dummy gate dielectric layer 116a, and a first dummy gate electrode layer 118a is located on the first dummy gate dielectric layer 116a. The second dummy gate structure 120b includes a second dummy gate dielectric layer 116b, and a second dummy gate electrode layer 118b is located on the second dummy gate dielectric layer 116b. After the first dummy gate structure 120a is formed, a first gate spacer layer 122a is formed on the sidewall surfaces on both sides of the first dummy gate structure 120a, and the first gate spacer layer 122a can be a single layer or multiple layers. In addition, a second gate spacer layer 122b is formed on the sidewall surfaces on both sides of the second dummy gate structure 120b.

[0081] After that, a source / drain (S / D) structure 124 is formed on the fin structure 110. In some embodiments, some portions of the fin structure 110 adjacent to the first dummy gate structure 120a and the second dummy gate structure 120b are recessed to form notches on both sides of the fin structure 110, and strained material is grown in the notches by an epitaxial process to form the source / drain (S / D) structure 124. Furthermore, the source / drain (S / D) structure 124 is formed above the isolation structure 114.

[0082] In addition, the lattice constant of the strained material can be different from the lattice constant of the substrate 102. In some embodiments, the source / drain (S / D) structure 124 includes Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or similar materials. The source / drain (S / D) structure 124 includes a first source / drain (S / D) structure 124a (shown in Figure 2A ), which is adjacent to the first gate structure 140a (shown in Figure 1G ), and a second source / drain (S / D) structure 124b (shown in Figure 2A ), which is adjacent to the second gate structure 140b (shown in Figure 1G ).

[0083] After the source / drain (S / D) structure 124 is formed, a contact etch stop layer (CESL) (not shown) is selectively formed on the substrate 102, and an inter-layer dielectric (ILD) layer 128 is formed on the contact etch stop layer. In some other embodiments, the contact etch stop layer (CESL) is made of silicon nitride, silicon oxynitride, and / or other suitable materials. The contact etch stop layer can be formed by plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or other suitable processes.

[0084] The inter-layer dielectric layer 128 can include a multi-layer structure made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The inter-layer dielectric layer 128 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0085] After that, a polishing process is performed on the inter-layer dielectric layer 128 until the top surfaces of the first dummy gate structure 120a and the second dummy gate structure 120b are exposed. In some embodiments, the inter-layer dielectric layer 128 is planarized by a chemical mechanical polishing (CMP) process. The inter-layer dielectric layer 128 includes a first portion 128a in the first region 11 and a second portion 128b in the second region 12.

[0086] The first dummy gate structure 120a has a first width W1 along a first direction, and the second dummy gate structure 120b has a second width W2 along the first direction. The first direction is the growth direction of the fin structure 110, and the first width W1 is greater than the second width W2. In some embodiments, the first width W1 ranges from about 20 nm to about 100 nm. In some embodiments, the second width W2 ranges from about 2 nm to about 10 nm.

[0087] For regions with different exposed areas (or etched areas), it is difficult to control the etching uniformity due to the loading effect. Depending on the etching method, the loading effect may be that the etching rate of a larger area is faster or slower than that of a smaller area. In other words, the loading effect is that the etching rate in a larger area does not match the etching rate in a smaller area. This indicates that the loading effect is affected by the pattern density. It should be noted that the first width W1 of the first dummy gate structure 120a is greater than the second width W2 of the second dummy gate structure 120b. Due to the loading effect, the first portion 128a of the interlayer dielectric layer 128 in the first region 11 is higher than the second portion 128b of the interlayer dielectric layer 128 in the second region 12. Therefore, due to the loading effect, there is a height difference H1 between the first portion 128a and the second portion 128b of the interlayer dielectric layer 128. In some embodiments, the height difference H1 ranges from about 15 nm to about 20 nm.

[0088] After that, as Figure 1F shown, according to some embodiments, the first dummy gate structure 120a and the second dummy gate structure 120b are removed to form a first trench 130a and a second trench 130b in the interlayer dielectric layer 128. The first trench 130a is formed in the first region 11, and the second trench 130b is formed in the second region 12. The dummy gate dielectric layers 116a, 116b and the dummy gate electrode layers 118a, 118b are removed by an etching process, such as a dry etching process or a wet etching process.

[0089] Then, as Figure 1G shown, according to some embodiments, a first gate structure 140a is formed in one of the first trenches 130a, and a second gate structure 140b is formed in one of the second trenches 130b. In addition, the first gate structure 140a and the second gate structure 140b are formed on the isolation structure 114.

[0090] In the first region 11, the first gate structure 140a includes a first gate dielectric layer 134a, a first gate electrode layer 138a located on the first gate dielectric layer 134a, and a conductive layer 139 located on the first gate electrode layer 138a. In the second region 12, the second gate structure 140b includes a second gate dielectric layer 134b and a second gate electrode layer 138b located on the second gate dielectric layer 134b.

[0091] The conductive layer 139 is configured to reduce the impedance between a contact structure (subsequently formed on the conductive layer) and the first gate structure 140a. In some embodiments, the conductive layer 139 is made of a low-impedance conductive material, such as tungsten (W) or molybdenum (Mo). It is noted that no conductive layer is formed above the second gate dielectric layer 134b and the second gate electrode layer 138b because each second trench 130b has a smaller width, and the width of the second trench 130b is too small to be filled with other materials.

[0092] The first gate dielectric layer 134a and the second gate dielectric layer 134b can be single-layer or multi-layer structures. The first gate dielectric layer 134a and the second gate dielectric layer 134b are each independently made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), a high-k dielectric material, or a combination of the foregoing. In some embodiments, the first gate dielectric layer 134a and the second gate dielectric layer 134b are deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or a spin coating process.

[0093] The first gate electrode layer 138a and the second gate electrode layer 138b are each independently made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. The first gate electrode layer 138a and the second gate electrode layer 138b are formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0094] The first gate structure 140a has a first width W1 along a first direction, and the second gate structure 140b has a second width W2 along the first direction. The first direction is the growth direction of the fin structure 110, and the first width W1 is greater than the second width W2. In some embodiments, the first width W1 ranges from about 20 nm to about 100 nm. In some embodiments, the second width W2 ranges from about 2 nm to about 10 nm.

[0095] Next, as Figure 1H shown, according to some embodiments, a first capping layer 142a is formed on the first gate structure 140a, and a second capping layer 142b is formed on the second gate structure 140b. The first capping layer 142a and the second capping layer 142b are configured to prevent the underlying layers from being damaged by subsequent processes. More particularly, the first capping layer 142a and the second capping layer 142b are used as a barrier layer to protect the underlying layers. In some embodiments, the bottom surface of the first capping layer 142a is generally flush with the top surface of the conductive layer 139, and the term "generally" means reasonable variations due to the manufacturing process.

[0096] More particularly, the first capping layer 142a and the second capping layer 142b are selectively formed in some regions. The first capping layer 142a directly contacts the top surface of the first gate structure 140a. More particularly, the first capping layer 142a directly contacts the top surface of the conductive layer 139.

[0097] In some embodiments, the first capping layer 142a is not formed on the first gate spacer 122a. In some embodiments, the first capping layer 142a is not formed on the first portion 128a of the interlayer dielectric layer 128. The second capping layer 142b directly contacts the second gate electrode layer 138b. In some embodiments, the second capping layer 142b is not formed on the second gate spacer 122b. In some other embodiments, the second capping layer 142b is not formed on the second portion 128b of the interlayer dielectric layer 128.

[0098] In some embodiments, the first capping layer 142a and the second capping layer 142b are made of silicon nitride (SixNy). In some embodiments, the first capping layer 142a and the second capping layer 142b are formed simultaneously by an atomic layer deposition (ALD) process. Precursors gases and an inhibitor gas are used in the atomic layer deposition (ALD) process. The precursors gases may include hexachlorodisilane (HCD), bis tertbutylamino silane (BTBAS), dichlorosilane (DCS, SiH2Cl2), disilane (DS), SiH4, NH3, N2, or other suitable materials. The inhibitor gas may include N-trimethylsilylpyrrole, octadecyltrichlorosilane (ODTS), or trimethylchrolosilane (TMCS). The inhibitor gas is used to react with the material of the interlayer dielectric layer 128 to form an inhibition layer on the interlayer dielectric layer 128. The precursors gases used to form the first capping layer 142a and the second capping layer 142b do not react with the inhibition layer, which prevents the first capping layer 142a and the second capping layer 142b from being formed on the interlayer dielectric layer 128. Thus, the first capping layer 142a and the second capping layer 142b are selectively formed on specific regions, such as on the conductive layer 139, the second gate electrode layer 138b, or the second gate dielectric layer 134b.

[0099] In some embodiments, before forming the first capping layer 142a and the second capping layer 142b, a cleaning process is performed on the exposed top surfaces of the first gate structure 140a, the second gate structure 140b, the interlayer dielectric layer 128, the first gate spacer layer 122a, and the second gate spacer layer 122b. In some embodiments, the cleaning process includes using hydrogen (H2) and / or argon (Ar). In some embodiments, the cleaning process is performed for about 5 minutes to about 15 minutes.

[0100] Since the top surface of the first gate structure 140a is higher than the top surface of the second gate structure 140b, the top surface of the first capping layer 142a is higher than the top surface of the second capping layer 142b. In addition, because the first gate structure 140a is wider than the second gate structure 140b, the first capping layer 142a is wider than the second capping layer 142b. In some embodiments, the first capping layer 142a has a first thickness T1 in the range from about 3 nm to about 5 nm. When the first thickness T1 of the first capping layer 142a is within the above range, the first capping layer 142a can provide sufficient protection to the underlying layer.

[0101] After that, as Figure 1I shown, according to some embodiments, a first etch stop layer 144a is formed on the first capping layer 142a and the first gate structure 140a, and a second etch stop layer 144b is formed on the second capping layer 142b and the second gate structure 140b. Then, a dielectric layer 150 is formed on the first etch stop layer 144a and the second etch stop layer 144b.

[0102] Since the first capping layer 142a is higher than the second capping layer 142b, and the first portion 128a of the interlayer dielectric layer 128 is higher than the second portion 128b of the interlayer dielectric layer 128, the first etch stop layer 144a in the first region 11 is higher than the second etch stop layer 144b in the second region 12. In addition, a portion of the first etch stop layer 144a directly above the first capping layer 142a is higher than another portion of the first etch stop layer 144a, and this other portion is directly above the first gate spacer 122a.

[0103] The first etch stop layer 144a is conformally formed on the first capping layer 142a, the first gate spacer 122a, and the first portion 128a of the interlayer dielectric layer 128. Since the first capping layer 142a protrudes from the top surface of the first gate structure 140a, a portion of the first etch stop layer 144a directly above the first capping layer 142a is higher than another portion of the first etch stop layer 144a. Similarly, the second etch stop layer 144b is conformally formed on the second capping layer 142a, the second gate spacer 122b, and the second portion 128b of the interlayer dielectric layer 128. Since the second capping layer 142b protrudes from the top surface of the second gate structure 140b, a portion of the second etch stop layer 144b directly above the second capping layer 142b is higher than another portion of the second etch stop layer 144b. In other words, a portion of the first etch stop layer 144a is higher than another portion of the first etch stop layer 144a, and a portion of the second etch stop layer 144b is higher than another portion of the second etch stop layer 144b.

[0104] In some embodiments, the first capping layer 142a and the first etch stop layer 144a are made of the same material, such as silicon nitride (SixNy). In some embodiments, the second capping layer 142b and the second etch stop layer 144b are made of the same material, such as silicon nitride (SixNy). In some embodiments, the first etch stop layer 144a and the second etch stop layer 144b are formed simultaneously by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes. The dielectric layer 150 can be made of a multi-layer structure including various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials.

[0105] After that, as Figure 1J shown, according to some embodiments, a plurality of trenches (not shown) are formed through the dielectric layer 150, the first etch stop layer 144a, the second etch stop layer 144b, and the interlayer dielectric layer 128, and a barrier layer 162 is formed on the sidewall surfaces of each trench. Then, a conductive layer 164 is formed on the barrier layer 162 and the dielectric layer 150.

[0106] The barrier layer 162 is used to separate the conductive layer 164 from the interlayer dielectric layer 128. In some embodiments, the barrier layer 162 is made of Ti / TiN. In some embodiments, the barrier layer 162 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or other suitable processes.

[0107] The conductive layer 164 is used to electrically connect to the source / drain (S / D) structure 124 (as Figure 2D shown). In some embodiments, the conductive layer 164 is made of a low-impedance material, such as tungsten (W), cobalt (Co), titanium (Ti), nickel (Ni), tantalum (Ta), hafnium (Hf), zirconium (Zr), platinum (Pt), or molybdenum (Mo). In some embodiments, the conductive layer 164 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an electroplating process.

[0108] Then, as Figure 1KAs shown, according to some embodiments, the portions of the conductive layer 164 outside the trenches are removed, and portions of the dielectric layer 150 are removed. In some embodiments, the above-mentioned portions of the conductive layer 164 are removed by a grinding process, such as a chemical mechanical polishing (CMP) process. As a result, a first source / drain (S / D) contact structure 166a is formed in the first region 11, and a second source / drain (S / D) contact structure 166b is formed in the second region 12. The top surface of the first source / drain (S / D) contact structure 166a is generally flush with the top surface of the second source / drain (S / D) contact structure 166b. In addition, the first source / drain (S / D) contact structure 166a and the second source / drain (S / D) contact structure 166b are buried in the dielectric layer 150.

[0109] As described above, there is a height difference between the first etch stop layer 144a in the first region 11 and the second etch stop layer 144b in the second region 12. In other words, the first etch stop layer 144a in the first region 11 is higher than the second etch stop layer 144b in the second region 12. The first portion of the dielectric layer 150 in the first region 11 is also higher than the second portion of the dielectric layer 150 in the second region 12. In addition, the removal of the first portion of the dielectric layer 150 in the first region 11 is earlier than the removal of the second portion of the dielectric layer 150 in the second region 12.

[0110] When the chemical mechanical polishing (CMP) process is performed on the dielectric layer 150, the chemical mechanical polishing (CMP) process stops until the first etch stop layer 144a is exposed. However, although the first etch stop layer 144a is exposed, the first portion of the dielectric layer 150 is not flush with the second portion of the dielectric layer 150. The chemical mechanical polishing (CMP) process is continuously performed until the first portion of the dielectric layer 150 is flush with the second portion of the dielectric layer 150. As a result, the first etch stop layer 144a can be removed, and the underlying layer can also be removed. In some other embodiments, if no capping layer is formed on the conductive layer 139 to provide additional protection for the underlying layers (such as the conductive layer 139, the first gate dielectric layer 134a, and the first gate electrode layer 138a), these underlying layers are easily removed by the chemical mechanical polishing (CMP) process. When the chemical mechanical polishing (CMP) process is performed to planarize the dielectric layer 150, the first capping layer 142a of the embodiments of the present disclosure is configured to protect the conductive layer 139 and the first gate structure 140a.

[0111] It should be noted that the portion of the first etch stop layer 144a directly above the first capping layer 142a is generally flush with the top surface of the first source / drain (S / D) contact structure 166a, and another portion of the first etch stop layer 144a directly above the first portion 128a of the interlayer dielectric layer 128 is lower than the top surface of the first source / drain (S / D) contact structure 166a. When performing a chemical mechanical polishing (CMP) process to planarize the dielectric layer 150 in the first region 11 and the second region 12, the first capping layer 142a is selectively formed on the conductive layer 139 to protect the underlying layers from being damaged. In addition, since the first capping layer 142a and the second capping layer 142b are selectively formed in some regions, there is no need to use a removal process or a lithography process to pattern the first capping layer 142a and the second capping layer 142b. Therefore, the manufacturing time and cost can be reduced.

[0112] Figures 2A to 2E showing, in accordance with some embodiments of the present disclosure, the formation Figures 1G to 1K of a cross-sectional schematic view of various stages of the fin field-effect transistor (FinFET) device structure shown, wherein Figure 2A showing a cross-sectional schematic view along Figure 1G line I-I' of.

[0113] As Figure 2A shown, source / drain (S / D) structures 124 are formed on the fin structure 110, and the source / drain (S / D) structures 124 include a first source / drain (S / D) structure 124a in the first region 11 and a second source / drain (S / D) structure 124b in the second region 12.

[0114] After that, as Figure 2B shown, in accordance with some embodiments of the present disclosure, a first capping layer 142a is selectively formed on the top surface of the conductive layer 139 in the first region 11, and a second capping layer 142b is selectively formed on the top surface of the second gate electrode layer 138b. Since the top surface of the conductive layer 139 is higher than the top surface of the second gate electrode layer 138b, the first capping layer 142a is higher than the second capping layer 142b.

[0115] Next, as Figure 2CAs shown, according to some embodiments of the present disclosure, a first etch stop layer 144a is formed on a first capping layer 142a, and the first etch stop layer 144a is formed on a first portion 128a of the interlayer dielectric layer 128. A second etch stop layer 144b is formed on a second capping layer 142b, and the second etch stop layer 144b is formed on a second portion 128b of the interlayer dielectric layer 128. Then, a dielectric layer 150 is formed on the first etch stop layer 144a and the second etch stop layer 144b. Since the first capping layer 142a is higher than the second capping layer 142b, a first portion of the dielectric layer 150 is higher than a second portion of the dielectric layer 150.

[0116] After that, as Figure 2D shown, according to some embodiments, a plurality of trenches (not shown) are formed through the dielectric layer 150, the first etch stop layer 144a, the second etch stop layer 144b, and the interlayer dielectric layer 128, and a barrier layer 162 is formed on the sidewalls of each trench. Then, a conductive layer 164 is formed on the barrier layer 162 and the dielectric layer 150.

[0117] Next, as Figure 2E shown, the portion of the conductive layer 164 outside the trenches is removed, and a portion of the dielectric layer 150 is removed to form a first source / drain (S / D) contact structure 166a in a first region 11 and a second source / drain (S / D) contact structure 166b in a second region 12. The first source / drain (S / D) contact structure 166a is electrically connected to the first source / drain (S / D) structure 124a, and the second source / drain (S / D) contact structure 166b is electrically connected to the second source / drain (S / D) structure 124b.

[0118] It should be noted that when a polishing process (as Figure 2D shown) is performed on the dielectric layer 150 in the first region 11 and the second region 12, when the second portion of the dielectric layer 150 does not reach a predetermined depth, a portion of the first gate structure 140a may be removed and exposed. Thus, the function of the first gate structure 140a may deteriorate and reduce the performance of the fin field-effect transistor (FinFET) device structure. Therefore, the first capping layer 142a is configured to protect the first gate structure 140a.

[0119] Figure 3A shows a perspective schematic view of a fin field-effect transistor device structure 200 according to some embodiments of the present disclosure. Some of the processes and materials used to form the fin field-effect transistor device structure 200 are similar or the same as those used to form the fin field-effect transistor device structure 100, and are not repeated herein. Figure 3B is a cross-sectional schematic view taken along line I-I’ of Figure 3A .

[0120] As Figure 3A and Figure 3B shown, the first gate structure 140a further includes a first work function layer 136a located between the first gate dielectric layer 134a and the first gate electrode layer 138a, and the second gate structure 140b further includes a second work function layer 136b located between the second gate dielectric layer 134b and the second gate electrode layer 138b. It should be noted that the second capping layer 142a is formed not only on the second gate electrode layer 138b but also on the second work function layer 136b.

[0121] The first work function layer 136a and the second work function layer 136b are each independently made of a metal material, and the metal material may include an N-type work function metal or a P-type work function metal. The N-type work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium-aluminum alloy (TiAl), titanium-aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum-carbonitride (TaCN), tantalum-silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination of the foregoing. The P-type work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination of the foregoing.

[0122] Figure 4A A perspective schematic diagram showing a fin field-effect transistor device structure 300 according to some embodiments of the present disclosure. Some of the processes and materials used to form the fin field-effect transistor device structure 300 are similar or the same as those used to form the fin field-effect transistor device structure 100, and are not repeated herein. Figure 4B is a cross-sectional schematic diagram taken along line I-I’ of Figure 4A .

[0123] As Figure 4A and Figure 4B shown, the second capping layer 142b is formed not only on the second gate electrode layer 138b but also on the second gate dielectric layer 134b. It should be noted that the second capping layer 142b is not formed on the second gate spacer layer 122b and the second part 128b of the interlayer dielectric layer 128.

[0124] Embodiments of forming a fin field-effect transistor (FinFET) device structure and a method of forming the same are provided herein. The fin field-effect transistor (FinFET) device structure includes a substrate having a first region and a second region. A first gate structure having a first width is formed on the first region, and a second gate structure having a second width is formed on the second region, the first width being greater than the second width. A first capping layer is selectively formed on the top surface of the first gate structure to protect the underlying layers from being removed or damaged. Accordingly, the performance of the fin field-effect transistor (FinFET) device structure can be improved.

[0125] In some embodiments, a fin field-effect transistor (FinFET) device structure is provided. The fin field-effect transistor device structure includes a fin structure formed on a substrate, and a first gate structure formed on the fin structure. The fin field-effect transistor device structure also includes a first capping layer formed on the first gate structure, and a first etch stop layer formed on the first capping layer and the first gate structure. The fin field-effect transistor device structure further includes a first source / drain (S / D) contact structure formed on the fin structure and adjacent to the first gate structure. Additionally, a portion of the first etch stop layer directly above the first capping layer is higher than another portion of the first etch stop layer directly above the first gate spacer layer.

[0126] In some embodiments, the first capping layer of the fin field-effect transistor device structure is not formed on the first gate spacer layer.

[0127] In some embodiments, the fin field-effect transistor device structure further includes a first source / drain (S / D) structure formed on the fin structure and located below the first source / drain (S / D) contact structure, wherein the first source / drain (S / D) contact structure is electrically connected to the first source / drain (S / D) structure.

[0128] In some embodiments, the fin field-effect transistor device structure further includes a dielectric layer formed on the first capping layer and the first etch stop layer, wherein the first source / drain (S / D) contact structure is buried in the dielectric layer.

[0129] In some embodiments, the fin field-effect transistor device structure further includes a second gate structure formed on the fin structure; a second capping layer formed on the second gate structure, wherein the first capping layer is higher than the second capping layer; and a second gate spacer layer formed adjacent to the second gate structure, wherein the second capping layer is not formed on the second gate spacer layer.

[0130] In some embodiments, the second gate structure of the fin field-effect transistor device structure includes a second gate dielectric layer formed on the fin structure; a second work function layer formed on the second gate dielectric layer; and a second gate electrode layer formed on the second work function layer, wherein the second capping layer directly contacts the second work function layer.

[0131] In some embodiments, the fin field-effect transistor device structure further includes an isolation structure formed on the substrate, wherein the first gate structure and the first source / drain (S / D) contact structure are formed on the isolation structure.

[0132] In some embodiments, the first gate structure of the fin field-effect transistor device structure includes a first gate dielectric layer formed on the fin structure; a first gate electrode layer formed on the first gate dielectric layer; and a conductive layer formed on the first gate dielectric layer and the first gate electrode layer, wherein the first capping layer directly contacts the conductive layer.

[0133] In some embodiments, a first capping layer of a fin field-effect transistor device structure directly contacts a top surface of a first gate structure.

[0134] In some embodiments, a fin field-effect transistor (FinFET) device structure is provided. The fin field-effect transistor device structure includes a fin structure formed on a substrate, and a first gate structure formed on the fin structure, the first gate structure having a first width. The fin field-effect transistor device structure also includes a second gate structure formed on the fin structure, the second gate structure having a second width, and the first width being greater than the second width. The fin field-effect transistor device structure further includes a first capping layer formed on the first gate structure, and the first capping layer directly contacts the top surface of the first gate structure. The fin field-effect transistor device structure still further includes a second capping layer formed on the second gate structure, and the second capping layer directly contacts the top surface of the second gate structure, wherein a top surface of the first capping layer is higher than a top surface of the second capping layer.

[0135] In some embodiments, the fin field-effect transistor device structure further includes a first source / drain (S / D) contact structure formed on the fin structure and adjacent to the first gate structure, wherein a portion of a first etch stop layer directly above the first gate structure is flush with a top surface of the first source / drain (S / D) contact structure.

[0136] In some embodiments, the fin field-effect transistor device structure further includes a first gate spacer layer formed adjacent to the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer.

[0137] In some embodiments, the first gate structure of the fin field-effect transistor device structure includes a first gate dielectric layer formed on the fin structure; a first gate electrode layer formed on the first gate dielectric layer; and a conductive layer formed on the first gate dielectric layer and the first gate electrode layer, wherein the first capping layer directly contacts the conductive layer.

[0138] In some embodiments, the fin field-effect transistor device structure further includes a first etch stop layer formed on the first capping layer and the first gate structure; and a second etch stop layer formed on the second capping layer and the second gate structure, wherein the first etch stop layer is higher than the second etch stop layer.

[0139] In some embodiments, the second gate structure of the fin field-effect transistor device structure includes a second gate dielectric layer formed on the fin structure; and a second gate electrode layer formed on the second gate dielectric layer, wherein the second capping layer directly contacts a top surface of the second gate electrode layer.

[0140] In some embodiments, the second gate structure of the fin field-effect transistor device structure further includes a second work function layer located between the second gate dielectric layer and the second gate electrode layer, wherein the second capping layer is in direct contact with the second work function layer.

[0141] In some embodiments, a method of forming a fin field-effect transistor (FinFET) device structure is provided. The method includes forming a fin structure on a substrate, and the substrate includes a first region and a second region. The method also includes forming a first gate structure on the fin structure in the first region, and the first gate structure has a first width. The method also includes forming a second gate structure on the fin structure in the second region, the second gate structure has a second width, and the first width is greater than the second width. The method further includes forming a first capping layer and a second capping layer on the first gate structure and the second gate structure, respectively. The first capping layer is in direct contact with the top surface of the first gate structure, the second capping layer is in direct contact with the top surface of the second gate structure, and the top surface of the first capping layer is higher than the top surface of the second capping layer. The method further includes forming a first etch stop layer and a second etch stop layer on the first capping layer and the second capping layer, respectively.

[0142] In some embodiments, the method of forming a fin field-effect transistor device structure further includes forming a dielectric layer on the fin structure, wherein the dielectric layer is adjacent to the first gate structure and the second gate structure, and the first capping layer is not formed on the dielectric layer. In addition, a first portion of the dielectric layer directly above the first gate structure is higher than a second portion of the dielectric layer directly above the second gate structure.

[0143] In some embodiments, the method of forming a fin field-effect transistor device structure further includes forming a first trench and a second trench in the dielectric layer, wherein the first trench is in the first region and the second trench is in the second region; forming a conductive layer in the first trench and the second trench and on the dielectric layer; removing a portion of the conductive layer to form a first source / drain (S / D) contact structure in the first region and a second source / drain (S / D) contact structure in the second region, wherein a portion of the first etch stop layer directly above the first gate structure is flush with the top surface of the first source / drain (S / D) contact structure.

[0144] In some embodiments, the method of forming a fin field-effect transistor device structure further includes performing a cleaning process on the top surfaces of the first gate structure and the second gate structure before forming the first capping layer and the second capping layer on the first gate structure and the second gate structure, respectively.

[0145] The components of several embodiments are outlined above so that those of ordinary skill in the art can better understand the concepts of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that the embodiments of the present disclosure can be used as a basis to design or modify other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and other options can be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined by the appended claims.

Claims

1. A fin field-effect transistor device structure, comprising: A fin structure formed on a substrate; A first gate structure formed on the fin structure; A first gate spacer layer formed adjacent to the first gate structure; A first capping layer formed on the first gate structure; A first etch stop layer formed on the first capping layer and the first gate structure, wherein a top surface and a sidewall surface of the first capping layer directly contact the etch stop layer; And A first source / drain contact structure formed on the fin structure and adjacent to the first gate structure, wherein the entirety of the first capping layer is higher than a topmost surface of the first gate spacer layer.

2. The fin field-effect transistor device structure according to claim 1, wherein the first capping layer is not formed on the first gate spacer layer.

3. The fin field-effect transistor device structure according to claim 1, further comprising: A first source / drain structure formed on the fin structure and located below the first source / drain contact structure, wherein the first source / drain contact structure is electrically connected to the first source / drain structure.

4. The fin field-effect transistor device structure according to claim 1, further comprising: A dielectric layer formed on the first capping layer and the first etch stop layer, wherein the first source / drain contact structure is buried in the dielectric layer.

5. The fin field-effect transistor device structure according to claim 1, further comprising: A second gate structure formed on the fin structure; A second capping layer formed on the second gate structure, wherein the first capping layer is higher than the second capping layer; and A second gate spacer layer formed adjacent to the second gate structure, wherein the second capping layer is not formed on the second gate spacer layer.

6. The fin field-effect transistor device structure according to claim 5, wherein the second gate structure comprises: A second gate dielectric layer formed on the fin structure; A second work function layer formed on the second gate dielectric layer; And A second gate electrode layer formed on the second work function layer, wherein the second capping layer directly contacts the second work function layer.

7. The fin field-effect transistor device structure according to claim 1, further comprising: An isolation structure formed on the substrate, wherein the first gate structure and the first source / drain contact structure are formed on the isolation structure.

8. The fin field-effect transistor device structure according to claim 1, wherein the first gate structure comprises: A first gate dielectric layer formed on the fin structure; A first gate electrode layer formed on the first gate dielectric layer; and A conductive layer formed on the first gate dielectric layer and the first gate electrode layer, wherein a bottommost surface of the first capping layer directly contacts a topmost surface of the conductive layer.

9. The fin field-effect transistor device structure according to claim 7, wherein the first capping layer directly contacts a top surface of the first gate structure.

10. A fin field-effect transistor device structure, comprising: A fin structure formed on a substrate; A first gate structure formed on the fin structure, wherein the first gate structure has a first width; A second gate structure is formed on the fin structure, wherein the second gate structure has a second width, and the first width is greater than the second width; An interlayer dielectric layer is formed adjacent to the first gate structure and the second gate structure, wherein the interlayer dielectric layer includes: a first portion located in a first region of the substrate; and a second portion located in a second region of the substrate; A first capping layer is formed on the first gate structure, wherein the first capping layer directly contacts a top surface of the first gate structure; and A second capping layer is formed on the second gate structure, wherein the second capping layer directly contacts a top surface of the second gate structure, wherein a first top surface of the first capping layer is higher than a second top surface of the second capping layer, and the second top surface of the second capping layer is higher than a third top surface of the second portion of the interlayer dielectric layer.

11. The fin field effect transistor device structure as claimed in claim 10, further comprising: A first etch stop layer is formed on the first capping layer and the first gate structure; And A first source / drain contact structure is formed on the fin structure and adjacent to the first gate structure, wherein a portion of the first etch stop layer directly above the first gate structure is flush with a top surface of the first source / drain contact structure.

12. The fin field effect transistor device structure as claimed in claim 10, further comprising: A first gate spacer layer is formed adjacent to the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer, and the entirety of the first capping layer is on the first gate structure.

13. The fin field effect transistor device structure as claimed in claim 10, wherein the first gate structure includes: A first gate dielectric layer is formed on the fin structure; A first gate electrode layer is formed on the first gate dielectric layer; and A conductive layer is formed on the first gate dielectric layer and the first gate electrode layer, wherein a bottommost surface of the first capping layer directly contacts a topmost surface of the conductive layer.

14. The fin field effect transistor device structure as claimed in claim 10, further comprising: A first etch stop layer is formed on the first capping layer and the first gate structure; And A second etch stop layer is formed on the second capping layer and the second gate structure, wherein the first etch stop layer is higher than the second etch stop layer.

15. The fin field effect transistor device structure as claimed in claim 10, wherein the second gate structure includes: A second gate dielectric layer is formed on the fin structure; And A second gate electrode layer is formed on the second gate dielectric layer, wherein the second capping layer directly contacts a top surface of the second gate electrode layer.

16. The fin field effect transistor device structure as claimed in claim 15, wherein the second gate structure includes: A second work function layer is located between the second gate dielectric layer and the second gate electrode layer, wherein the second capping layer directly contacts the second work function layer.

17. A method of forming a fin field effect transistor device structure, comprising: Forming a fin structure on a substrate, wherein the substrate includes a first region and a second region; Form a first gate structure on the fin structure in the first region, wherein the first gate structure has a first width; Form a second gate structure on the fin structure in the second region, wherein the second gate structure has a second width, and the first width is greater than the second width; Form a first capping layer and a second capping layer on the first gate structure and the second gate structure respectively, wherein a top surface of the first capping layer is higher than a top surface of the second capping layer; And Form a first etch stop layer and a second etch stop layer on the first capping layer and the second capping layer respectively, wherein a sidewall surface of the first capping layer directly contacts the first etch stop layer.

18. The method of forming a fin field effect transistor device structure according to claim 17, further comprising: Form a dielectric layer on the fin structure, wherein the dielectric layer is adjacent to the first gate structure and the second gate structure, and the first capping layer is not formed on the dielectric layer, and the first capping layer is on the first gate structure, and the second capping layer is on the second gate structure.

19. The method of forming a fin field effect transistor device structure according to claim 18, further comprising: Form a first trench and a second trench in the dielectric layer, wherein the first trench is in the first region, and the second trench is in the second region; Form a conductive layer in the first trench and the second trench and on the dielectric layer; And Remove a part of the conductive layer to form a first source / drain contact structure in the first region, and form a second source / drain contact structure in the second region, wherein a part of the first etch stop layer directly above the first gate structure is flush with a top surface of the first source / drain contact structure.

20. The method of forming a fin field effect transistor device structure according to claim 17, further comprising: Before forming the first capping layer and the second capping layer on the first gate structure and the second gate structure respectively, perform a cleaning process on the top surface of the first gate structure and the top surface of the second gate structure.

21. A fin field effect transistor device structure, comprising: A first gate structure formed on a fin structure located on a substrate; A first capping layer formed on the first gate structure; A first etch stop layer formed on the first capping layer and the first gate structure, wherein a top surface of the first capping layer and a sidewall surface directly contact the etch stop layer; A dielectric layer formed on the substrate, wherein the dielectric layer has a first part and a second part, the first part and the second part have a step height, and the first gate structure is formed in the first part of the dielectric layer; A second gate structure formed on the fin structure and in the second part of the dielectric layer; And A second capping layer formed on the second gate structure, wherein a first top surface of the first capping layer is higher than a second top surface of the second capping layer.

22. The fin field effect transistor device structure according to claim 21, further comprising: A first source / drain structure formed on the fin structure; And A first source / drain contact structure is formed on the first source / drain structure, wherein a top surface of the first source / drain contact structure is higher than a top surface of the first capping layer.

23. The fin field-effect transistor device structure according to claim 21, wherein the first gate structure comprises: A first gate dielectric layer formed on the fin structure; A first gate electrode layer formed on the first gate dielectric layer; And A conductive layer formed on the first gate electrode layer, wherein a bottommost surface of the first capping layer directly contacts the conductive layer.

24. The fin field-effect transistor device structure according to claim 21, further comprising: A first gate spacer layer formed adjacent to the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer.

25. The fin field-effect transistor device structure according to claim 22, further comprising: An isolation structure formed on the substrate, wherein the first gate structure and the first source / drain contact structure are formed on the isolation structure.

26. The fin field-effect transistor device structure according to claim 21, further comprising: A second etch stop layer formed on the second capping layer, wherein a top surface and a sidewall surface of the second capping layer directly contact the second etch stop layer.

27. The fin field-effect transistor device structure according to claim 21, wherein the second gate structure comprises: A second gate dielectric layer formed on the fin structure; and A second gate electrode layer formed on the second gate dielectric layer, wherein the second capping layer directly contacts the second gate electrode layer.

28. The fin field-effect transistor device structure according to claim 21, wherein the first capping layer has a band width from a bottom surface to a top surface.

29. A fin field-effect transistor device structure, comprising: A first gate structure formed on a fin structure located on a substrate; A second gate structure formed on the fin structure; An interlayer dielectric layer formed adjacent to the first gate structure and the second gate structure, wherein the interlayer dielectric layer comprises: a first portion located in a first region of the substrate; and a second portion located in a second region of the substrate; A first capping layer formed on the first gate structure; A second capping layer formed on the second gate structure, wherein a first top surface of the first capping layer and a second top surface of the second capping layer are both higher than a third top surface of the second portion of the interlayer dielectric layer; A first etch stop layer formed on the first capping layer; and A second etch stop layer formed on the second capping layer, wherein the first etch stop layer is higher than the second etch stop layer.

30. The fin field-effect transistor device structure according to claim 29, wherein the first gate structure is formed in the first portion, the second gate structure is formed in the second portion, and there is a spacer height between the first portion and the second portion.

31. The fin field-effect transistor device structure according to claim 29, wherein the first gate structure has a first width, the second gate structure has a second width, and the first width is greater than the second width.

32. The fin field effect transistor device structure according to claim 29, wherein the first gate structure comprises: a first gate dielectric layer formed on the fin structure; a first gate electrode layer formed on the first gate dielectric layer; and a conductive layer formed on the first gate electrode layer, wherein a bottom surface of the first capping layer directly contacts the conductive layer.

33. The fin field effect transistor device structure according to claim 29, further comprising: a first source / drain structure formed on the fin structure; and a first source / drain contact structure formed on the first source / drain structure, wherein a part of the first etch stop layer is lower than a top surface of the first source / drain contact structure.

34. The fin field effect transistor device structure according to claim 29, further comprising: a first gate spacer layer formed adjacent to the first gate structure; and a second gate spacer layer formed adjacent to the second gate structure, wherein a top surface of the first gate spacer layer is higher than a top surface of the second gate spacer layer.

35. The fin field effect transistor device structure according to claim 29, wherein the first capping layer has a band width from a bottom surface to a top surface.

36. The fin field effect transistor device structure according to claim 29, further comprising: a first gate spacer layer formed adjacent to the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer.

37. A method of forming a fin field effect transistor device structure, comprising: forming a fin structure on a substrate, wherein the substrate comprises a first region and a second region; forming a first gate structure on the fin structure in the first region; forming a second gate structure on the fin structure in the second region; forming a first capping layer on the first gate structure; forming a first etch stop layer on the first capping layer, wherein a side surface of the first capping layer directly contacts the first etch stop layer; forming a first trench and a second trench in a dielectric layer, wherein the first trench is in the first region and the second trench is in the second region; forming a conductive layer in the first trench and the second trench and on the dielectric layer; and removing a part of the conductive layer to form a first source / drain contact structure in the first region and a second source / drain contact structure in the second region, wherein a part of the first etch stop layer is lower than a top surface of the first source / drain contact structure.

38. The method of forming a fin field effect transistor device structure according to claim 37, further comprising: forming a second capping layer on the second gate structure; and forming a dielectric layer adjacent to the first gate structure and the second gate structure, wherein the first capping layer and the second capping layer are both higher than the dielectric layer.

39. The method of forming a fin field effect transistor device structure according to claim 37, wherein the dielectric layer has a first part and a second part, the first gate structure is formed in the first part, the second gate structure is formed in the second part, and there is a spacer height between the first part and the second part.

40. A fin field-effect transistor device structure, comprising: A first gate structure formed on a fin structure; A conductive layer formed on the first gate structure; A first capping layer formed on the conductive layer, wherein a top surface of the conductive layer directly contacts a bottom surface of the first capping layer; A second gate structure formed on the fin structure; A second capping layer formed on the second gate structure, wherein the top surface of the conductive layer is higher than a top surface of the second capping layer, and a top surface of the first capping layer is higher than the top surface of the second capping layer; And An etch stop layer formed on the first capping layer and the second capping layer.

41. The fin field-effect transistor device structure according to claim 40, further comprising: A first gate spacer formed on a sidewall of the first gate structure, wherein the first capping layer is not formed on the first gate spacer.

42. The fin field-effect transistor device structure according to claim 40, wherein the first capping layer has a width from the bottom surface to the top surface.

43. The fin field-effect transistor device structure according to claim 40, wherein a sidewall of the conductive layer is aligned with a sidewall of the first capping layer.

44. The fin field-effect transistor device structure according to claim 40, wherein the etch stop layer has a step height.

45. The fin field-effect transistor device structure according to claim 40, wherein the first gate structure has a first width, the second gate structure has a second width, and the first width is greater than the second width.

46. The fin field-effect transistor device structure according to claim 40, further comprising: A first source / drain structure formed on the fin structure; And A first source / drain contact structure formed on the first source / drain structure, wherein a top surface of the first source / drain contact structure is higher than the top surface of the first capping layer.

47. The fin field-effect transistor device structure according to claim 40, wherein the first gate structure comprises: A first gate dielectric layer formed on the fin structure; and A first gate electrode layer formed on the first gate dielectric layer, wherein a sidewall of the conductive layer is aligned with a sidewall of the first gate dielectric layer.

48. A fin field-effect transistor device structure, comprising: A first gate structure formed on a fin structure; A second gate structure formed on the fin structure; A first capping layer formed on the first gate structure; A second capping layer formed on the second gate structure, wherein a top surface of the first gate structure is higher than a top surface of the second gate structure, such that a top surface of the first capping layer is higher than the top surface of the second capping layer; And An etch stop layer formed on the first capping layer and the second capping layer.

49. The fin field-effect transistor device structure according to claim 48, further comprising: An interlayer dielectric layer formed adjacent to the first gate structure and the second gate structure, wherein the interlayer dielectric layer has a step height.

50. The fin field-effect transistor device structure according to claim 48, further comprising: A conductive layer is located between the first gate structure and the first capping layer, wherein one sidewall of the conductive layer is aligned with one sidewall of the first capping layer.

51. The fin field-effect transistor device structure as claimed in claim 48, further comprising: A first gate spacer layer is formed on one sidewall of the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer.

52. The fin field-effect transistor device structure as claimed in claim 51, further comprising: A second gate spacer layer is formed on one sidewall of the second gate structure, wherein a top surface of the first gate spacer layer is higher than a top surface of the second gate spacer layer.

53. The fin field-effect transistor device structure as claimed in claim 48, wherein the first capping layer has a top width and a bottom width, and the bottom width is greater than the top width.

54. The fin field-effect transistor device structure as claimed in claim 48, wherein the first gate structure comprises: A first gate dielectric layer is formed on the fin structure; and A first gate electrode layer is formed on the first gate dielectric layer, wherein one sidewall of the first gate dielectric layer is aligned with one sidewall of the first capping layer.

55. A fin field-effect transistor device structure, comprising: A first gate structure is formed on a fin structure; A first capping layer is formed on the first gate structure; A first gate spacer layer is formed on one sidewall of the first gate structure, wherein the first capping layer is not formed on the first gate spacer layer; A second gate structure is formed on the fin structure; A second gate spacer layer is formed on one sidewall of the second gate structure; A second capping layer is formed on the second gate structure, wherein the second capping layer is not formed on the second gate spacer layer; And An etch stop layer is formed on the first capping layer and the second capping layer, wherein a top surface of the first capping layer is higher than a top surface of the second capping layer.

56. The fin field-effect transistor device structure as claimed in claim 55, further comprising: A first source / drain structure is formed on the fin structure; And A first source / drain contact structure is formed on the first source / drain structure, wherein a top surface of the first source / drain contact structure is higher than the top surface of the first capping layer.

57. The fin field-effect transistor device structure as claimed in claim 55, wherein a top width of the first capping layer is greater than a top width of the second capping layer.

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