Vertical semiconductor device and method for manufacturing the same

Abstract

A vertical semiconductor device includes: insulating patterns located on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate; a channel structure located on the substrate and penetrating the insulating patterns; a first conductive pattern partially filling a gap between the insulating pattern and the channel structure adjacent to each other in the first direction and having a slit in a surface thereof, the slit extending in a direction parallel to the top surface of the substrate; and a second conductive pattern located on the first conductive pattern in the gap and filling the slit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0159648 filed on November 27, 2017 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to a semiconductor device and a method for manufacturing the same. More particularly, example embodiments relate to a vertical type semiconductor device and a method for manufacturing the same. Background Art

[0004] In a vertical type semiconductor device, a channel layer of a channel structure may be electrically connected to a substrate.

[0005] However, as the aspect ratio of the channel structure increases, electrical connection between the channel layer and the substrate may be difficult. Summary of the invention

[0006] Example embodiments provide a vertical type semiconductor device including a gate structure.

[0007] According to an example embodiment, a vertical semiconductor device is provided. The vertical semiconductor device includes: insulating patterns located on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate; a channel structure located on the substrate and penetrating the insulating patterns; a first conductive pattern partially filling a gap between the insulating patterns and the channel structure adjacent to each other in the first direction and having a slit in its surface, the slit extending in a direction parallel to the top surface of the substrate; and a second conductive pattern located on the first conductive pattern in the gap and filling the slit.

[0008] According to an example embodiment, a vertical semiconductor device is provided. The vertical semiconductor device includes: insulating patterns located on a substrate and spaced apart from each other in a first direction perpendicular to the top surface of the substrate, the insulating patterns extending in a second direction parallel to the top surface of the substrate; channel structures located on the substrate, each channel structure penetrating the insulating patterns; and gate structures located in a gap between the insulating patterns and the channel structures adjacent to each other in the first direction, the gate structures extending in the second direction. The gate structure includes: a first conductive pattern along the top and bottom surfaces of the insulating pattern and the channel structure, and having a slit in its surface; and a second conductive pattern located on the first conductive pattern, used to fill the slit and including a material different from the first conductive pattern.

[0009] According to an example embodiment, a vertical semiconductor device is provided. The vertical semiconductor device includes: a pattern structure including a gate structure and an insulating pattern alternately and repeatedly stacked on a substrate in a first direction perpendicular to a top surface of the substrate; a channel structure penetrating the insulating pattern; and a common source line located between the pattern structures, the common source line extending in a second direction parallel to the top surface of the substrate and contacting the substrate. The gate structure includes: a first conductive pattern having a slit extending in a direction parallel to the top surface of the substrate; and a second conductive pattern located on the first conductive pattern for filling the slit.

[0010] According to example embodiments, the gate structure in each level may include a first conductive pattern having a slit and a second conductive pattern filling the slit. Accordingly, an empty space may not be formed in the gate structure. Therefore, the inclination or bending of the insulating pattern due to the empty space can be reduced or prevented. In addition, since the insulating pattern is formed to be structurally stable, a short circuit failure between the gate structures arranged above and below the insulating pattern can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 23 Representative are non-limiting example embodiments as described herein.

[0012] Figure 1 , Figure 2A , Figure 2B and Figure 3 are a plan view and a cross-sectional view illustrating a vertical type semiconductor device according to example embodiments.

[0013] Figures 4 to 20 are cross-sectional views and plan views illustrating a method of manufacturing a vertical type semiconductor device according to example embodiments.

[0014] Fig.21 and Fig. 22 is a cross-sectional view illustrating a vertical type semiconductor device according to example embodiments.

[0015] Fig.23 is a cross-sectional view illustrating a method of manufacturing a vertical type semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0016] Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings.

[0017] Figure 1 , Figure 2A , Figure 2B and Figure 3 are a plan view and a cross-sectional view illustrating a vertical type semiconductor device according to example embodiments.

[0018] Figure 1 is along Figure 2A A cross-sectional view taken along the line A-A' in FIG. Figure 3 yes Figure 1 An enlarged view of portion “A” in FIG. Figure 2A is a plan view showing a vertical type semiconductor device when viewed from the top. Figure 2B is along Figure 1 The plane diagram intercepted by the line I-I' in FIG. That is, Figure 2B is a plan view taken along a direction parallel to the top surface of the semiconductor substrate, which shows a slit portion.

[0019] In all the drawings of this specification, a direction substantially perpendicular to the top surface of the semiconductor substrate is referred to as a first direction, and two directions substantially parallel to the top surface of the semiconductor substrate and intersecting each other are referred to as a second direction and a third direction, respectively. The first direction and the second direction are substantially perpendicular to each other.

[0020] refer to Figure 1 , Figure 2A , Figure 2B and Figure 3 , the vertical semiconductor device may include: a pattern structure including a gate structure 156 and insulating patterns 102a, 106a, 110a alternately and repeatedly stacked on a semiconductor substrate 100; a channel structure 134 penetrating the pattern structure; and a common source line 162 located between the pattern structures and in contact with the semiconductor substrate 100. The semiconductor pattern 114 may be disposed between the semiconductor substrate 100 and the channel structure 134.

[0021] The semiconductor substrate 100 may include a semiconductor material such as silicon, germanium, silicon germanium, etc., or may include a III-V type compound such as GaP, GaAs, GaSb, etc. The semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0022] The pattern structure may extend in the second direction, and a plurality of pattern structures may be arranged along the third direction. Accordingly, a trench 140 may be provided between the pattern structures to extend along the second direction. The trench 140 may expose the semiconductor substrate 100.

[0023] The channel structure 134 may penetrate the pattern structure and extend along the first direction.

[0024] In example embodiments, the channel structure 134 may be disposed on the semiconductor pattern 114 protruding from the semiconductor substrate 100 in the first direction. In some example embodiments, although not shown in the drawings, the channel structure 134 may contact the semiconductor substrate 100 .

[0025] The channel structure 134 may be formed in the channel hole 112 penetrating the pattern structure. The channel structure 134 may include a first barrier pattern 120 a , a charge storing pattern 122 a , a tunnel insulating pattern 124 a , a channel pattern 128 , a buried insulating pattern 130 , and a pad pattern 132 .

[0026] The first barrier pattern 120a, the charge storage pattern 122a, and the tunnel insulation pattern 124a may be sequentially stacked on the sidewalls of the channel hole 112. The channel pattern 128 may be formed along the surfaces of the tunnel insulation pattern 124a and the semiconductor pattern 114. Accordingly, the channel pattern 128 may have a cylindrical shape. The channel pattern 128 may be electrically connected to the semiconductor substrate 100 through the semiconductor pattern 114. The buried insulation pattern 130 may be disposed on the channel pattern 128 and may completely fill the channel hole 112.

[0027] The tunnel insulating pattern 124a, the first barrier pattern 120a, and the buried insulating pattern 130 may include an oxide such as silicon oxide, and the charge storing pattern 122a may include a nitride such as silicon nitride. The channel pattern 128 may include, for example, polysilicon.

[0028] The pad pattern 132 may be disposed on the first barrier pattern 120a, the charge storage pattern 122a, the tunnel insulation pattern 124a, the channel pattern 128, and the buried insulation pattern 130 in the upper portion of the channel hole 112. The pad pattern 132 may include, for example, polysilicon. Although not shown in the figure, a contact plug and a bit line may also be disposed on the pad pattern 132.

[0029] In the pattern structure, the insulating patterns 102 a , 106 a , 110 a may be disposed on the semiconductor substrate 100 , and may be arranged to be spaced apart from each other in the first direction.

[0030] The insulating patterns 102a, 106a, 110a may include a pad insulating pattern 102a, a first insulating pattern 106a, and a second insulating pattern 110a. The pad insulating pattern 102a, the first insulating pattern 106a, and the second insulating pattern 110a may be arranged to be spaced apart from each other in the first direction. The insulating patterns 102a, 106a, 110a may extend in the second direction. The insulating patterns 102a, 106a, and 110a may include silicon oxide.

[0031] The gate structure 156 may be disposed between the insulating patterns 102a, 106a, 110a adjacent to each other in the first direction. The gate structure 156 may be formed on a sidewall of the channel structure 134. The gate structure 156 may extend in the second direction.

[0032] In example embodiments, the lowermost gate structure 156 may function as a ground selection line GSL, and one or two uppermost gate structures 156 may function as a string selection line SSL. The gate structures 156 interposed between the ground selection line and the string selection line may function as word lines.

[0033] The gate structure 156 may be formed in the first gap 142a between the second insulating patterns 110a and between the first insulating pattern 106a and the second insulating pattern 110a, and in the second gap 142b between the pad insulating pattern 102a and the first insulating pattern 106a, respectively. The gate structures 156 formed in the first gap 142a and the second gap 142b may have substantially the same shape.

[0034] Hereinafter, in the first gap 142a and the second gap 142b, a portion in the upper portion of each gap corresponding to the insulating pattern may be referred to as a first portion, a portion corresponding to the side wall of the channel structure 134 or the semiconductor pattern 114 may be referred to as a second portion, and a portion in the lower portion of each gap corresponding to the insulating pattern may be referred to as a third portion.

[0035] The gate structure 156 may include a first conductive pattern 150a and a second conductive pattern 154a. In example embodiments, the gate structure 156 may further include a barrier pattern 146a surrounding a top surface, a sidewall, and a bottom surface of the first conductive pattern 150a.

[0036] The barrier pattern 146a may be conformally disposed along the first portion, the second portion, and the third portion of each of the first gap 142a and the second gap 142b. The barrier pattern 146a may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0037] The first conductive pattern 150a may be disposed on the barrier pattern 146a to partially fill the first gap 142a and the second gap 142b. The first conductive pattern 150a may be formed along a first portion, a second portion, and a third portion of each of the first gap 142a and the second gap 142b, and may have a long and narrow slit 152 between the first portion and the third portion in a direction parallel to the top surface of the semiconductor substrate 100. The slit 152 may be formed in a surface of the first conductive pattern 150a.

[0038] The slit 152 may be formed in a middle region of each of the first gap 142 a and the second gap 142 b in the first direction.

[0039] In the first conductive pattern 150a, an entrance of the slit 152 adjacent to the trench 140 may be open toward the trench 140. In example embodiments, a width of the entrance of the slit 152 in the first direction may be smaller than other portions of the slit 152.

[0040] The first conductive pattern 150a may include a metal material having low resistance. For example, the first conductive pattern 150a may include tungsten.

[0041] The second conductive pattern 154a may be disposed on the first conductive pattern 150a and the barrier pattern 146a to cover the surfaces of the first conductive pattern 150a and the barrier pattern 146a. The second conductive pattern 154a may fill the slit 152 of the first conductive pattern 150a. The second conductive pattern 154a may be disposed in the first gap 142a and the second gap 142b.

[0042] The second conductive pattern 154a may include a metal or a metal nitride that can easily fill the slit 152. For example, the second conductive pattern 154a may include titanium, titanium nitride, tantalum, tantalum nitride, etc. As an example, the second conductive pattern 154a may include titanium nitride.

[0043] In example embodiments, a second barrier layer 144 may be further disposed along the sidewalls of the second insulating pattern 110a and the surfaces of the first gap 142a and the second gap 142b. The second barrier layer 144 may contact the first barrier pattern 120a of the channel structure 134. Accordingly, the first barrier pattern 120a and the second barrier layer 144 may be disposed as one barrier structure. Accordingly, the second barrier layer 144 may contact the semiconductor pattern 114.

[0044] In example embodiments, the second barrier layer 144 may include a metal oxide, such as aluminum oxide, zirconium oxide, hafnium oxide, or the like.

[0045] like Figure 2B As shown, in a plan view showing a slit portion of the gate structure 156 taken in a direction parallel to the top surface of the semiconductor substrate, the second barrier layer 144 and the barrier pattern 146a may be disposed on the sidewalls of the channel structure 134, and the first conductive pattern 150a may be disposed on the barrier pattern 146a to surround the channel structure 134. The second conductive pattern 154a may be disposed on the first conductive pattern 150a.

[0046] Since the second conductive pattern 154 a fills the slit portion, an empty space may be removed from the gate structure 156 .

[0047] In example embodiments, the gate structure 156 including the barrier pattern 146a, the first conductive pattern 150a, and the second conductive pattern 154a stacked on each other may not completely fill the first gap 142a and the second gap 142b. That is, in the first gap 142a and the second gap 142b, a space between the sidewall of the gate structure 156 and the sidewall of the insulating patterns 102a, 106a, 110a may be provided.

[0048] Sidewalls of the gate structure 156 , sidewalls of the insulation patterns 102 a , 106 a , 110 a , and a surface of the semiconductor substrate 100 may be exposed through the trench 140 .

[0049] An insulating spacer 160 may be disposed on a sidewall of the trench 140. The insulating spacer 160 may cover a sidewall of the gate structure 156 and sidewalls of the insulating patterns 102a, 106a, 110a.

[0050] A common source line 162 may be disposed on the insulating spacer 160 to fill the trench 140 .

[0051] The common source line 162 may include a metal material. As an example, the common source line 162 may include tungsten.

[0052] Although not shown in the drawings, a third insulating layer may be disposed on the second insulating pattern 110a, the common source line 162, and the insulating spacer 160, and a contact plug penetrating the third insulating layer to contact the pad pattern may be disposed. A bit line contacting the contact plug may be disposed.

[0053] Figures 4 to 20 are cross-sectional views and plan views illustrating a method of manufacturing a vertical type semiconductor device according to example embodiments.

[0054] Figure 4 , Figure 5 , Figures 7 to 9 as well as Figures 11 to 19 is a cross-sectional view, Figure 6 and Fig.10 It is a floor plan. Fig.14 , Fig.16 and Fig.19 They are Fig.13 , Fig.15 and Fig.18 An enlarged cross-sectional view of portion “A” in FIG.

[0055] refer to Figure 4 , a pad insulating layer 102 may be formed on a semiconductor substrate 100. A lower sacrificial layer 104 may be formed on the pad insulating layer 102. A first insulating layer 106 may be formed on the lower sacrificial layer 104. Sacrificial layers 108 and second insulating layers 110 may be alternately and repeatedly formed on the first insulating layer 106.

[0056] In example embodiments, the lower sacrificial layer 104 may be provided as a mold layer for forming a ground selection line. The sacrificial layer 108 may be provided as a mold layer for forming a word line and a string selection line.

[0057] In example embodiments, the pad insulating layer 102 may have a thickness in the first direction that is smaller than the first insulating layer 106 and the second insulating layer 110. The first insulating layer 106 may have a thickness in the first direction that is larger than the second insulating layer 110.

[0058] The pad insulating layer 102, the first insulating layer 106, and the second insulating layer 110 may include silicon oxide. The lower sacrificial layer 104 and the sacrificial layer 108 may include silicon nitride.

[0059] For example, pad insulating layer 102, first insulating layer 106, second insulating layer 110, lower sacrificial layer 104 and sacrificial layer 108 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. As an example, pad insulating layer 102 may be formed by a thermal oxidation process.

[0060] refer to Figure 5 and Figure 6 , an etching mask pattern (not shown) may be formed on the uppermost second insulating layer 110, and the second insulating layer 110, the sacrificial layer 108, the first insulating layer 106, the lower sacrificial layer 104, and the pad insulating layer 102 may be etched using the etching mask pattern to form a plurality of channel holes 112 exposing the top surface of the semiconductor substrate 100. In example embodiments, the top surface of the semiconductor substrate 100 may be partially etched. The channel holes 112 may be arranged in each unit block. A plurality of channel holes 112 may be arranged in the second direction and the third direction in one unit block.

[0061] refer to Figure 7 , the semiconductor pattern 114 may be formed to partially fill the lower portion of each channel hole 112. The semiconductor pattern 114 may be formed on the semiconductor substrate 100 exposed by each channel hole 112. The first blocking layer 120, the charge storage layer 122, and the tunnel insulating layer 124 may be conformally sequentially formed on the sidewalls of the channel holes 112, the top surface of the semiconductor pattern 114, and the uppermost second insulating layer 110.

[0062] For example, a selective epitaxial growth (SEC) process may be performed using the top surface of the semiconductor substrate 100 exposed by the channel hole 112 as a seed to form a semiconductor pattern 114 partially filling the channel hole 112. The semiconductor pattern 114 may be formed to include single crystal silicon or single crystal germanium, and in some cases, n-type impurities or p-type impurities may be doped therein.

[0063] In example embodiments, the semiconductor pattern 114 may provide a channel pattern as a lowermost ground selection transistor. Therefore, a top surface of the semiconductor pattern 114 may be formed to be located between a top surface and a bottom surface of the first insulating layer 106. Since the first insulating layer 106 has a thickness greater than that of the second insulating layer 110 formed thereon, the semiconductor pattern 114 may be formed by an epitaxial growth process so that a top surface of the semiconductor pattern 114 may be located between a top surface and a bottom surface of the first insulating layer 106.

[0064] In example embodiments, the first blocking layer 120 may be formed to include silicon oxide, the charge storage layer 122 may be formed to include silicon nitride, and the tunnel insulating layer 124 may be formed to include silicon oxide. The first blocking layer 120, the charge storage layer 122, and the tunnel insulating layer 124 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0065] refer to Figure 8 A channel structure 134 may be formed on the semiconductor pattern 114 to fill the channel hole 112. The channel structure 134 may include a first barrier pattern 120a, a charge storing pattern 122a, a tunnel insulating pattern 124a, a channel pattern 128, a buried insulating pattern 130, and a pad pattern 132.

[0066] For example, the tunnel insulating layer 124 , the charge storage layer 122 , and the first barrier layer 120 may be anisotropically etched in sequence to form a first tunnel insulating pattern 124 a , a charge storage pattern 122 a , and a first barrier pattern 120 a on the sidewalls of the channel holes 112 .

[0067] During the etching process, portions of the tunnel insulating layer 124, the charge storage layer 122, and the first barrier layer 120 formed on the semiconductor pattern 114 and the second insulating layer 110 may be removed. Accordingly, a top surface of the semiconductor pattern 114 may be exposed within the channel hole 112.

[0068] In example embodiments, before performing the anisotropic etching process, a process of forming a protection spacer (not shown) on the tunnel insulating layer 124 formed on the sidewall of the channel hole 112 may be further performed. During the etching process, the protection spacer may protect the tunnel insulating layer 124, the charge storage layer 122, and the first blocking layer 120 on the sidewall of the channel hole 112. After the anisotropic etching process is performed, the protection spacer may be removed.

[0069] In example embodiments, a channel layer may be conformally formed on the semiconductor pattern 114, the tunnel insulating pattern 124a, and the second insulating layer 110, and a buried insulating layer may be formed on the channel layer to completely fill the channel hole 112. The buried insulating layer and the channel layer may be planarized until the top surface of the second insulating layer 110 is exposed. Accordingly, a channel pattern 128 and a buried insulating pattern 130 may be formed. The channel pattern 128 may have a cylindrical shape in contact with the semiconductor pattern 114. The buried insulating pattern 130 may have a columnar shape.

[0070] In some example embodiments, a channel layer may be formed on the semiconductor pattern 114, the tunnel insulating pattern 124a, and the second insulating layer 110 to completely fill the channel hole 112, and the channel layer may be planarized until the top surface of the second insulating layer 110 is exposed to form a channel pattern. In example embodiments, the channel pattern may have a columnar shape, and a buried insulating pattern may not be formed.

[0071] Then, upper portions of the channel pattern 128, buried insulating pattern 130, tunnel insulating pattern 124a, charge storing pattern 122a, and first barrier pattern 120a may be removed to form openings, and a conductive material may be formed in the openings to form pad patterns 132. The pad pattern 132 may include polysilicon.

[0072] refer to Fig. 9 and Fig.10 , the second insulating layer 110 , the sacrificial layer 108 , the first insulating layer 106 , the lower sacrificial layer 104 , and the pad insulating layer 102 may be partially removed to form a trench 140 , which exposes a top surface of the semiconductor substrate 100 .

[0073] In example embodiments, the trench 140 may be formed to extend in the second direction, and a plurality of trenches 140 may be arranged along the third direction. The cell block regions may be separated by the trenches 140.

[0074] When the trench 140 is formed, a mold structure including the pad insulating pattern 102a, the lower sacrificial pattern 104a, the first insulating pattern 106a, the sacrificial pattern 108a, and the second insulating pattern 110a may be formed. The mold structure may extend in the second direction.

[0075] The second insulating pattern 110 a , the sacrificial pattern 108 a , the first insulating pattern 106 a , the lower sacrificial pattern 104 a , and the pad insulating pattern 102 a may be exposed through the sidewalls of the trenches 140 .

[0076] refer to Fig.11, the lower sacrificial pattern 104a and the sacrificial pattern 108a exposed by the groove 140 may be selectively removed. Accordingly, first gaps 142a may be formed between the second insulating patterns 110a and between the first insulating pattern 106a and the second insulating pattern 110a, respectively, and second gaps 142b may be formed between the pad insulating pattern 102a and the first insulating pattern 106a.

[0077] The process of selectively removing the lower sacrificial pattern 104a and the sacrificial pattern 108a may include an isotropic etching process. In example embodiments, the sacrificial pattern 108a and the lower sacrificial pattern 104a exposed through the trench 140 may be removed by a wet etching process using an etching solution including phosphoric acid or sulfuric acid.

[0078] A ground selection line may be formed in the bottom second gap 142b by the following process. A portion of the sidewall of the semiconductor pattern 114 may be exposed through the second gap 142b. A word line and a string selection line may be formed in the first gap 142a by the following process. The first barrier pattern 120a of the channel structure 134 may be exposed through the first gap 142a.

[0079] refer to Fig.12 The second barrier layer 144 may be conformally formed on the pad insulating pattern 102a, the semiconductor pattern 114, the first insulating pattern 106a, the second insulating pattern 110a, and the first barrier pattern 120a exposed by the trench 140 and the first and second gaps 142a and 142b. The barrier layer 146 may be formed on the second barrier layer 144.

[0080] In example embodiments, the second barrier layer 144 may be formed to include metal oxides such as aluminum oxide, hafnium oxide, zirconium oxide, etc. The barrier layer 146 may be formed to include titanium nitride, tantalum nitride, titanium, tantalum, or the like.

[0081] When the second barrier layer 144 and the barrier layer 146 are formed, the inner width in the first direction of each of the first gap 142 a and the second gap 142 b may be reduced.

[0082] refer to Fig.13 and Fig.14 , a first conductive layer 150 may be formed on the barrier layer 146 to fill the first gap 142a and the second gap 142b. The first conductive layer 150 may include a metal material. For example, the first conductive layer 150 may be formed to include tungsten.

[0083] For example, the first conductive layer 150 may be formed by a chemical vapor deposition process or an atomic layer deposition process. The first conductive layer 150 may be deposited along the contour of the underlying layer to have a uniform thickness. Accordingly, the first conductive layer 150 may be formed on the sidewalls and bottom surfaces of the trench 140 and the first, second, and third portions of each of the first and second gaps 142a, 142b. Thus, when the first conductive layer 150 may be formed on the barrier layer 146 to have a thickness of at least about half of the inner width of the first and second gaps 142a, 142b in the first direction, the first and second gaps 142a, 142b may be filled with the first conductive layer 150.

[0084] However, since the inner widths of the first gap 142a and the second gap 142b are relatively small, the deposition source gas for forming the first conductive layer 150 may not easily flow into the first gap 142a and the second gap 142b. Before the first conductive layer 150 is formed to have a sufficient thickness to completely fill the first gap 142a and the second gap 142b, a portion of the first conductive layer 150 formed on the entrance of the first gap 142a and the second gap 142b communicating with the groove 140 may be formed relatively thick. In example embodiments, the entrances of the first gap 142a and the second gap 142b may be closed by the first conductive layer 150. When the entrances of the first gap 142a and the second gap 142b are closed, the deposition source gas may no longer flow into the first gap 142a and the second gap 142b, so that the inner spaces of the first gap 142a and the second gap 142b may not be completely filled by the first conductive layer 150. Accordingly, a slit 152 may be formed in the first gap 142a and the second gap 142b, which is a long and thin gap in a direction parallel to the top surface of the semiconductor substrate 100. The slit 152 may be formed in the middle region of each of the first gap 142a and the second gap 142b in the first direction. In example embodiments, at the entrance of the first gap 142a and the second gap 142b adjacent to the trench 140, the width of the slit 152 in the first direction may be relatively narrow.

[0085] refer to Fig.15 and Fig.16 , the first conductive layer 150 and the barrier layer 146 may be partially etched to form a first conductive pattern 150a and a barrier pattern 146a in the first gap 142a and the second gap 142b.

[0086] For example, in the etching process, portions of the first conductive layer 150 and the barrier layer 146 formed on the second insulating pattern 110a, the first insulating pattern 106a, the pad insulating pattern 102a, and the semiconductor substrate 100 may be removed. Accordingly, the second barrier layer 144 on the second insulating pattern 110a, the first insulating pattern 106a, the pad insulating pattern 102a, and the semiconductor substrate 100 may be exposed. In addition, portions of the first conductive layer 150 and the barrier layer 146 formed on the entrances of the first gap 142a and the second gap 142b may be removed. Accordingly, the first conductive pattern 150a and the barrier pattern 146a may be formed. The etching process may include an isotropic etching process.

[0087] During the etching process, portions of the first conductive layer 150 having a relatively large thickness at the entrances of the first and second gaps 142a and 142b may be removed to open the inner space of the slit 152. Accordingly, the slit 152 may communicate with the trench 140.

[0088] In example embodiments, the first conductive pattern 150a may be formed along the first portion, the second portion, and the third portion of each of the first gap 142a and the second gap 142b, and may include a slit 152 between the first portion and the third portion. That is, the first conductive pattern 150a may remain on the sidewall of the semiconductor pattern 114 exposed by the second gap 142b and the channel structure 134 exposed by the first gap 142a.

[0089] refer to Fig.17 , a second conductive layer 154 may be formed on the exposed second barrier layer 144, the barrier pattern 146a, and the first conductive pattern 150a. The second conductive layer 154 may completely fill the slit 152 of the first conductive pattern 150a. The second conductive layer 154 may be formed along the sidewall and bottom surface of the trench 140 to partially fill the trench 140.

[0090] The second conductive layer 154 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0091] The second conductive layer 154 may include a material capable of filling the narrow slit 152. The second conductive layer 154 may include a material different from the first conductive pattern 150a. In example embodiments, the second conductive layer 154 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. For example, the second conductive layer 154 may include titanium nitride.

[0092] refer to Fig.18 and Fig.19The second conductive layer 154 may be partially etched to form a second conductive pattern 154a on the first conductive pattern 150a and the barrier pattern 146a. The second conductive pattern 154a may be formed in the first gap 142a and the second gap 142b.

[0093] For example, during the etching process, portions of the second conductive layer 154 formed on the second insulating pattern 110a, the first insulating pattern 106a, the pad insulating pattern 102a, and the semiconductor substrate 100 may be removed, thereby exposing the second barrier layer 144. In addition, portions of the second conductive layer 154 formed on the entrances of the first gap 142a and the second gap 142b may be removed. The etching process may include an isotropic etching process.

[0094] By performing the isotropic etching process, a gate structure 156 including a barrier pattern 146 a , a first conductive pattern 150 a , and a second conductive pattern 154 a may be formed in the first gap 142 a and the second gap 142 b .

[0095] The second conductive pattern 154a may cover the upper surface of the first conductive pattern 150a and may fill the slit. As the second conductive pattern 154a is formed, the slit may be removed from the gate structure 156.

[0096] In the case where the gate structure includes a slit, the deposition gas and / or hydrogen does not escape from the slit to remain in the slit. The upper and lower insulating patterns may be partially etched by the retained gas, resulting in cracks in the insulating pattern and tilting of the insulating pattern. In addition, in the case where the gate structure includes a slit, the upper and lower insulating patterns may become structurally unstable, so that the insulating pattern may tilt downward or break. In this way, when the upper and lower insulating patterns are not formed to be stable, the gate structures formed above and below the insulating patterns may be electrically connected to each other, resulting in a short circuit failure between the two gate structures. However, according to example embodiments, because the slit is removed by the second conductive pattern 154a, the upper and lower insulating patterns may have a stable structure, thereby reducing or preventing failures.

[0097] refer to Fig. 20 , an insulating spacer layer may be formed on the second barrier layer 144 and the second conductive pattern 154 a . The insulating spacer layer may be anisotropically etched to form insulating spacers 160 on the sidewalls of the trench 140 .

[0098] Subsequently, the insulating spacers 160 may be used as an etching mask to etch the second barrier layer 144 not covered by the insulating spacers 160. Accordingly, portions of the second barrier layer 144 on the second insulating pattern 110a and the semiconductor substrate 100 may be removed.

[0099] A conductive layer may be formed on the insulating spacer 160, the semiconductor substrate 100, and the second insulating pattern 110a to fill the trench. The conductive layer may be planarized until the top surface of the second insulating pattern 110a is exposed to form a common source line 162 in the trench. The common source line 162 may include tungsten. The common source line 162 may extend in the second direction.

[0100] Then, although not shown in the drawings, an upper insulating layer may be formed on the common source line 162 and the insulating spacer 160, and then, a contact plug penetrating the upper insulating layer to contact the pad pattern may be formed. A bit line contacting the contact plug may be formed.

[0101] The above-described processes may be performed to manufacture a vertical type semiconductor device.

[0102] Fig.21 and Fig. 22 is a cross-sectional view illustrating a vertical type semiconductor device according to example embodiments.

[0103] Fig. 22 It is shown Fig.21 An enlarged cross-sectional view of portion "B" in FIG.

[0104] In addition to the shape of the gate structure, Fig.21 and Fig. 22 The vertical semiconductor device shown can be compared with the reference Figure 1 , Figure 2A , Figure 2B and Figure 3 The vertical semiconductor devices described are substantially the same.

[0105] refer to Fig.21 and Fig. 22 , the gate structure 156a may include a barrier pattern 146a, a first conductive pattern 150b, and a second conductive pattern 154a.

[0106] The blocking pattern 146 a may be disposed along the first portion, the second portion, and the third portion of each of the first gap 142 a and the second gap 142 b .

[0107] The first conductive pattern 150b may be disposed only on the first portion and the third portion of the first gap 142a and the second gap 142b. The slit 152a may be disposed between the first portion and the third portion. That is, the first conductive pattern 150b may not be formed on the portion of the sidewall of the semiconductor pattern 114 exposed by the second gap 142b and the channel structure 134 exposed by the first gap 142a. Accordingly, the portion of the barrier pattern 146a on the second portion of each of the first gap 142a and the second gap 142b may be exposed by the first conductive pattern 150b.

[0108] The second conductive pattern 154a may be disposed on the barrier pattern 146a and the first conductive pattern 150b. The second conductive pattern 154a may fill the slit 152a.

[0109] Can be referenced by Figures 4 to 20 The process described is substantially the same as the process for manufacturing the vertical semiconductor device.

[0110] But when referring to Fig.15 and Fig.16 When describing a process, Fig.23 As shown, portions of the first conductive layer on the sidewalls of the semiconductor pattern 114 exposed by the second gaps 142 b and the channel structures 134 exposed by the first gaps 142 a may be removed.

[0111] According to the vertical type semiconductor device of example embodiments, malfunction due to a gate structure may be reduced or prevented. The vertical type semiconductor device may be applied to various electronic products.

[0112] While example embodiments have been particularly shown and described, a person skilled in the art will understand that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A vertical semiconductor device, include: insulating patterns located on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate; a channel structure located on the substrate and penetrating the insulating pattern; a first conductive pattern partially filling a gap between the insulating pattern and the channel structure adjacent to each other in the first direction and having a slit in a surface of the first conductive pattern, the slit extending in a direction parallel to the top surface of the substrate; as well as A second conductive pattern is located on the first conductive pattern in the gap and fills the slit, the width of the entrance of the slit in the first direction is smaller than the width of other parts of the slit in the first direction, and the second conductive pattern includes a material different from that of the first conductive pattern.

2. The vertical semiconductor device according to claim 1, in, The first conductive pattern includes a metal material.

3. The vertical semiconductor device according to claim 1, in, The first conductive pattern includes tungsten.

4. The vertical semiconductor device according to claim 1, in, The second conductive pattern includes titanium, titanium nitride, tantalum, or tantalum nitride. 5 . The vertical type semiconductor device according to claim 1 , further comprising a barrier pattern surrounding a top surface, a sidewall, and a bottom surface of the first conductive pattern.

6. The vertical semiconductor device according to claim 1, in, The gap is defined as a space between surfaces of an upper insulating pattern and a lower insulating pattern adjacent to each other in the first direction and the channel structure, the first conductive pattern is along a top surface of the lower insulating pattern, the channel structure and a bottom surface of the upper insulating pattern, and the slit is located between the first conductive pattern on the top surface of the lower insulating pattern and the first conductive pattern on the bottom surface of the upper insulating pattern.

7. The vertical semiconductor device according to claim 1, in, The slit is located in a middle region of the gap in the first direction.

8. The vertical semiconductor device according to claim 1, in, A gate structure including the first and second conductive patterns extends in a second direction parallel to the top surface of the substrate.

9. The vertical semiconductor device according to claim 8, in, The plurality of gate structures are arranged in a third direction perpendicular to the second direction and parallel to a top surface of the substrate, and trenches extend along the second direction between the gate structures and expose the substrate.

10. The vertical semiconductor device according to claim 9, in, An entrance of the slit adjacent to the groove is open toward the groove.

11. The vertical semiconductor device according to claim 9, further comprising: include: an insulating spacer, located on a sidewall of the trench and used to cover the first conductive pattern; as well as A common source line is located on the insulating spacer and is used to fill the trench.

12. The vertical semiconductor device according to claim 8, in, When a middle region of the gate structure in the first direction is viewed in a plan view taken along a direction parallel to the top surface of the substrate, the first conductive pattern has a shape surrounding the channel structure. 13 . The vertical type semiconductor device according to claim 1 , further comprising a semiconductor pattern between the substrate and the channel structure.

14. A vertical semiconductor device, include: Insulation patterns, which are located on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate, the insulation patterns extending in a second direction parallel to the top surface of the substrate; A channel structure, which is located on the substrate, each channel structure penetrates the insulating pattern; as well as a gate structure located in a gap between the insulating pattern and the channel structure adjacent to each other in the first direction, the gate structure extending in the second direction, The gate structure comprises: a first conductive pattern along top and bottom surfaces of the insulating pattern and the channel structure and having a slit in a surface of the first conductive pattern; as well as The second conductive pattern is located on the first conductive pattern, is used to fill the slit and includes a material different from that of the first conductive pattern, and the width of the entrance of the slit in the first direction is smaller than the width of other parts of the slit in the first direction.

15. The vertical semiconductor device according to claim 14, in, The plurality of gate structures are arranged in a third direction perpendicular to the second direction and parallel to a top surface of the substrate, and trenches extend along the second direction between the gate structures and expose the substrate.

16. The vertical semiconductor device according to claim 15, in, The inlet of the slit adjacent to the groove is open toward the groove.

17. A vertical semiconductor device, include: a pattern structure including gate structures and insulating patterns alternately and repeatedly stacked on the substrate in a first direction perpendicular to a top surface of the substrate; a channel structure penetrating the pattern structure; as well as a common source line located between the pattern structures, the common source line extending in a second direction parallel to the top surface of the substrate and contacting the substrate, The gate structure comprises: a first conductive pattern having slits extending in a direction parallel to a top surface of the substrate; as well as The second conductive pattern is located on the first conductive pattern and is used to fill the slit. The width of the entrance of the slit in the first direction is smaller than the width of other parts of the slit in the first direction. The second conductive pattern includes a material different from that of the first conductive pattern.

18. The vertical semiconductor device according to claim 17, in, The first conductive pattern includes tungsten, and the second conductive pattern includes titanium, titanium nitride, tantalum, or tantalum nitride.

19. The vertical semiconductor device according to claim 17, in, The entrance of the slit is open toward the common source line.

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