Semiconductor Devices

Abstract

A semiconductor device comprises: a substrate including a groove, the groove being located below an isolation region and having a side portion including a plurality of stepped portions; a plurality of gate electrodes spaced apart from each other on the substrate and stacked in a direction perpendicular to an upper surface of the substrate; a channel structure passing between a first plurality of gate electrodes; and an isolation region passing between a second plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2017-0165077 filed on December 4, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Some example embodiments relate to semiconductor devices. Background Art

[0004] Electronic devices have become progressively smaller while still processing large amounts of data. Therefore, it is desirable to increase the integration of semiconductor memory devices used in such electronic products. In order to improve the integration of semiconductor memory devices, flat memory devices including memory cells having a flat transistor structure have been continuously scaled down. In recent years, vertical memory devices have been proposed in which memory cells having a vertical transistor structure rather than a planar transistor structure are stacked. Summary of the invention

[0005] Some example embodiments provide a semiconductor device in which occurrence of bridging defects between gate electrodes and between a gate electrode and a common source line may be reduced, and slits (or gaps) may be reduced or prevented from being formed in a common source line.

[0006] Some example embodiments provide a semiconductor device having improved reliability.

[0007] Some example embodiments provide a method of manufacturing a semiconductor device, in which the occurrence of bridging defects between gate electrodes and between a gate electrode and a common source line can be reduced, and slits (or gaps) can be reduced or prevented from being formed in a common source line.

[0008] Some example embodiments provide a method of manufacturing a semiconductor device having improved reliability.

[0009] According to some example embodiments, a semiconductor device includes a substrate including a groove located below an isolation region and having a side portion including a plurality of stepped portions. The semiconductor device also includes a plurality of gate electrodes spaced apart from each other on the substrate and stacked in a direction perpendicular to an upper surface of the substrate. The semiconductor device also includes a channel structure passing between a first plurality of gate electrodes. The semiconductor device also includes an isolation region passing between a second plurality of gate electrodes, the isolation region extending from an upper surface of the substrate and having an inclined lateral surface.

[0010] According to some example embodiments, a semiconductor device includes a substrate having a groove, the groove including a first region, a second region, and a third region having different widths. The semiconductor device also includes a stacked structure, the stacked structure including a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the substrate. The semiconductor device also includes a common source line passing through the stacked structure to at least contact the first region of the groove, the common source line extending on the substrate in one direction.

[0011] According to some example embodiments, a semiconductor device includes: a substrate, the substrate includes a groove, the groove includes a first region having a first width, a second region having a second width greater than the first width, and a third region having a third width greater than the second width. The semiconductor device also includes a plurality of stacked structures, each of the stacked structures includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the substrate; a plurality of channel structures, passing through the plurality of stacked structures to extend in a direction perpendicular to an upper surface of the substrate. The semiconductor device also includes a plurality of partition walls between the stacked structures, the plurality of partition walls are on the groove of the substrate and extend on the substrate in one direction, and the partition walls at least contact the lateral surface of the third region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a plan view illustrating a portion of a cell region of a semiconductor device according to some example embodiments;

[0014] Figure 2 is a cross-sectional view of a semiconductor device including a common source line having an upper region and a lower region according to some example embodiments;

[0015] Figure 3 is a cross-sectional view of a semiconductor device including a common source line having a single region according to some example embodiments;

[0016] Figure 4 is a cross-sectional view of a semiconductor device including a groove having four regions of different widths according to some example embodiments;

[0017] FIG. 5A to FIG. 5I is a cross-sectional view of a method of manufacturing a semiconductor device according to some example embodiments;

[0018] Figure 6 According to some example embodiments, Figure 2 a cross-sectional view of a semiconductor device having a semiconductor pattern;

[0019] Figure 7is a cross-sectional view of a semiconductor device including a memory cell array region and a peripheral circuit region according to some example embodiments;

[0020] Figure 8 is a cross-sectional view of a semiconductor device according to some example embodiments, wherein the thickness of the insulating partition wall varies such that the thickness close to the substrate is greater than the thickness far from the substrate; and

[0021] Fig. 9 is a cross-sectional view of a semiconductor device according to some example embodiments, wherein the thickness of the insulating partition wall varies such that the thickness close to the substrate is smaller than the thickness far from the substrate. DETAILED DESCRIPTION

[0022] Hereinafter, some example embodiments will be described with reference to the accompanying drawings.

[0023] Figure 1 is a plan view illustrating a portion of a cell region of a semiconductor device according to some example embodiments; and Figure 2 is along Figure 1 A cross-sectional view taken along line II′ of a semiconductor device including a common source line having an upper region and a lower region.

[0024] refer to Figure 1 and Figure 2 According to some example embodiments, the semiconductor device may include a substrate 3, a stacked structure ST, a channel structure 42, a common source line 78, and an insulating partition wall 72. The stacked structure ST may include a molded insulating layer 8 and a conductive layer 57. The channel structure 42 may include a dielectric structure 30, a semiconductor layer 33, a filling insulating layer 36, a conductive pad 39, and a semiconductor pattern 38. The semiconductor device may further include a contact plug 84 connected to the conductive pad 39, and a bit line 87 connected to the contact plug 84.

[0025] The substrate 3 may include a semiconductor material such as a Group IV semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI compound semiconductor material. For example, the substrate 3 may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate.

[0026] The stacked structure ST may be disposed on the substrate 3. The stacked structure ST may include molded insulating layers 8 and conductive layers 57. The conductive layers 57 may be disposed between the molded insulating layers 8. The molded insulating layers 8 and the conductive layers 57 may be alternately and repeatedly stacked on the substrate 3. The conductive layers 57 may be spaced apart from each other on the substrate 3 and may be stacked in a second direction perpendicular to the upper surface of the substrate 3. The molded insulating layers 8 may be spaced apart from each other on the substrate 3 and may be stacked in a second direction perpendicular to the upper surface of the substrate 3. Each of the conductive layers 57 may include a first conductive layer 55 and a second conductive layer 56.

[0027] In an example, the conductive layer 57 may include select gate electrodes 57s and 57g and a cell gate electrode 57w. The conductive layer 57 may be a gate electrode.

[0028] The lowermost selection gate electrode 57g of the selection gate electrodes 57s and 57g may be a ground selection line (GSL), and the uppermost selection gate electrode 57s thereof may be a string selection line (SSL).

[0029] The cell gate electrode 57w may be disposed between the uppermost selection gate electrode 57s and the lowermost selection gate electrode 57g. The cell gate electrode 57w may be a word line of a memory cell. The cell gate electrodes 57w may be spaced apart from each other in a second direction perpendicular to the upper surface of the substrate 3.

[0030] The mold insulating layer 8 may include: a first lower mold insulating layer 5L disposed between the lowermost selection gate electrode 57g and the substrate 3; a second lower mold insulating layer 5U disposed between the lowermost selection gate electrode 57g and the lowermost cell gate electrode among the cell gate electrodes 57w; an intermediate mold insulating layer 6 disposed between the cell gate electrodes 57w and between the uppermost cell gate electrode among the cell gate electrodes 57w and the uppermost selection gate electrode 57s; and an upper mold insulating layer 7 disposed on the uppermost selection gate electrode 57s. The first lower mold insulating layer 5L contacting the upper surface of the substrate 3 may be thinner than each of the intermediate mold insulating layers 6. The second lower mold insulating layer 5U and the upper mold insulating layer 7 may be thicker than each of the intermediate mold insulating layers 6.

[0031] The channel structure 42 may be disposed in a channel hole CH passing through the stack structure ST. For example, the channel structure 42 may pass through the stack structure ST. The channel hole CH may have a width that becomes narrower toward a lower region thereof.

[0032] The channel structure 42 may include: a semiconductor layer 33 extending in a second direction perpendicular to the upper surface of the substrate 3; and a dielectric structure 30 disposed between the semiconductor layer 33 and the stacked structure ST. The semiconductor layer 33 may be a channel layer.

[0033] The dielectric structure 30 may include a first dielectric layer 21, a second dielectric layer 24, and a third dielectric layer 27 sequentially formed in the channel hole CH. The second dielectric layer 24 may be inserted between the first dielectric layer 21 and the third dielectric layer 27. The second dielectric layer 24 may contact the first dielectric layer 21 and the third dielectric layer 27. The third dielectric layer 27 may contact the semiconductor layer 33. The first dielectric layer 21 may be a blocking layer. The first dielectric layer 21 may include, for example, silicon oxide. The second dielectric layer 24 may be a charge storage layer. The second dielectric layer 24 may be a charge trapping layer. The second dielectric layer 24 may include silicon nitride, silicon oxynitride, and silicon-rich silicon oxide. The third dielectric layer 27 may be a tunnel layer. The third dielectric layer 27 may be formed of silicon oxide or a silicon oxide-based dielectric.

[0034] The channel structure 42 may further include: a filling insulating layer 36 filling the space within the semiconductor layer 33; and a conductive pad 39 disposed on the filling insulating layer 36. The filling insulating layer 36 may contact the semiconductor layer 33. The filling insulating layer 36 may be formed of an insulating material, such as silicon oxide. The conductive pad 39 may be formed of a conductive material, such as polysilicon having n-type conductivity.

[0035] The semiconductor pattern 38 may be disposed in the channel hole CH. The semiconductor pattern 38 may be disposed under the semiconductor layer 33. The semiconductor pattern 38 may be an epitaxial layer grown from the substrate 3 using a selective epitaxial growth (SEG) process. The semiconductor pattern 38 may contact the semiconductor layer 33. An insulating layer 63 may be disposed between the semiconductor pattern 38 and the lowermost selection gate electrode 57g. The insulating layer 63 may contact the semiconductor pattern 38. The insulating layer 63 may be formed of silicon oxide.

[0036] The fourth dielectric layer 54 may be interposed between the conductive layer 57 and the mold insulating layer 8, and may extend between the conductive layer 57 and the dielectric structure 30. The fourth dielectric layer 54 and the first dielectric layer 21 may constitute a barrier layer.

[0037] The fourth dielectric layer 54 may be formed of a high-k dielectric material. The high-k dielectric material may be at least one of the following: aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSix O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAI x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O v ) and praseodymium oxide (Pr 2 O 3 ). The fourth dielectric layer 54 may be formed of crystalline aluminum oxide.

[0038] The first upper insulating layer 45 may be disposed on the stacked structure ST and the channel structure 42. The first upper insulating layer 45 may be formed of an insulating material such as silicon oxide.

[0039] The common source line 78 may be disposed in the isolation region OP, which passes through the first upper insulating layer 45 and the stacked structure ST and extends into the substrate 3. The isolation region OP may extend in a first direction parallel to the upper surface of the substrate 3. The lateral surface of the isolation region OP may be flat and may not have an uneven pattern, and the width of the isolation region OP may narrow as the isolation region OP approaches the substrate 3. The lateral surface of the conductive layer 57 may be coplanar with the lateral surface of the mold insulating layer 8. The common source line 78 may pass through the first upper insulating layer 45 and the stacked structure ST. The common source line 78 may extend in a first direction parallel to the upper surface of the substrate 3, and may cut the first upper insulating layer 45 and the stacked structure ST in a second direction perpendicular to the upper surface of the substrate 3.

[0040] The groove RCS may be formed in the upper surface of the substrate 3 below the isolation region OP. The common source line 78 may be disposed in the groove RCS. The groove RCS may have a side including a plurality of step portions SP. The width of the upper portion of the groove RCS may be similar to or the same as the width of the lower portion of the isolation region OP. The lateral surface of the upper portion of the groove RCS may be coplanar with the lateral surface of the isolation region OP. The width of the upper portion of the groove RCS may be greater than the width of the lower portion of the groove RCS. The groove RCS may include a first region R1, a second region R2, and a third region R3 having different widths. The second region R2 may be disposed on the first region R1, and the third region R3 may be disposed on the second region R2. The first width W1 of the first region R1 may be narrower than the second width W2 of the second region R2, and the second width W2 of the second region R2 may be narrower than the third width W3 of the third region R3. The third width W3 of the third region R3 may be similar to or the same as the width of the lower portion of the isolation region OP. Each of the lateral surfaces of the third region R3 may be coplanar with a lateral surface of a lowermost mold insulating layer (eg, a first lower mold insulating layer 5L of the mold insulating layer 8 contacting the upper surface of the substrate 3 ).

[0041] The common source line 78 may be connected to the lowermost portion of the groove RCS. The common source line 78 may contact the lowermost portion of the groove RCS (e.g., the first region R1 of the groove RCS). The common source line 78 may include the lowermost portion of the groove RCS, for example, a lower region contacting the first region R1 and an upper region disposed on the lower region, and the width of the upper region may be greater than the width of the lower region. The width of the upper region may narrow as the upper region approaches the substrate 3.

[0042] In an example, the common source line 78 may be formed of a conductive material. The conductive material may include at least one of a metal such as Ti, Ta, Cu, Al, or W and a metal nitride such as TiN, TaN, or TiAlN.

[0043] The insulating partition wall 72 may be disposed between the stacked structure ST and the common source line 78. The insulating partition wall 72 may be disposed between the common source line 78 and the conductive layer 57, and may contact the conductive layer 57 disposed on the isolation region OP. The insulating partition wall 72 may extend in a first direction parallel to the upper surface of the substrate 3 (e.g., in a direction similar to or the same direction as the direction in which the common source line 78 may extend). The insulating partition wall 72 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0044] The lower portion of the insulating partition wall 72 may contact at least a portion of the stepped portion SP of the recess RCS. The lower portion of the insulating partition wall 72 may contact the second region R2 and the third region R3 of the recess RCS. As described above, the common source line 78 may contact the first region R1 of the recess RCS.

[0045] The insulating partition wall 72 may have a first thickness T1 at a portion on the lateral surface of the lowermost gate electrode (e.g., the lateral surface of the lowermost selection gate electrode 57g), and may have a second thickness T2 at a portion on the lateral surface of the uppermost gate electrode (e.g., the lateral surface of the uppermost selection gate electrode 57s), and the second thickness T2 may be similar to or the same as the first thickness T1. The first distance between the lowermost selection gate electrode 57g and the common source line 78 may be similar to or the same as the second distance between the uppermost selection gate electrode 57s and the common source line 78.

[0046] The impurity region 75 may be disposed within the substrate 3 below the common source line 78. The impurity region 75 may be disposed below the recess RCS of the substrate 3. The impurity region 75 may extend in a first direction parallel to the upper surface of the substrate 3 (e.g., a direction similar to or the same direction as the direction in which the common source line 78 may extend). The impurity region 75 may have a conductivity type different from that of the substrate 3 adjacent to the impurity region 75. For example, the impurity region 75 may have n-type conductivity, and the substrate 3 adjacent to the impurity region 75 may have p-type conductivity. The impurity region 75 may include n-type impurities, and the substrate 3 may include p-type impurities.

[0047] Impurity region 75 and conductive pad 39 may have the same conductivity type. For example, impurity region 75 and conductive pad 39 may have n-type conductivity. Conductive pad 39 may be a drain region, and impurity region 75 may be a source region.

[0048] The channel structure 42 passing through the stack structure ST may be provided as a plurality of channel structures 42. For example, the channel structures 42 may be arranged in a zigzag form along the common source line 78, as shown in FIG. Figure 1 shown.

[0049] The second upper insulating layer 81 may be disposed on the first upper insulating layer 45 and the common source line 78. The contact plug 84 may pass through the first upper insulating layer 45 and the second upper insulating layer 81 and may be electrically connected to the conductive pad 39 of the channel structure 42. The bit line 87 may be disposed on the second upper insulating layer 81 to be electrically connected to the contact plug 84.

[0050] Figure 3 is a cross-sectional view of a semiconductor device including a common source line having a single region according to some example embodiments. Figure 3 Only the Figure 2 A cross section corresponding to the magnified area of ​​the groove RCS.

[0051] refer to Figure 3 , the common source line 78a may be disposed in a groove RCS formed in the upper surface of the substrate 3. The groove RCS may include a first region R1, a second region R2, and a third region R3 having different widths. The first width W1 of the first region R1 may be narrower than the second width W2 of the second region R2, and the second width W2 of the second region R2 may be narrower than the third width W3 of the third region R3.

[0052] The common source line 78a may contact the lowermost portion of the recess RCS (eg, the first region R1 of the recess RCS). Figure 2 Unlike the common source line 78 of FIG. 3 , the common source line 78 a may include a single region. The width of the common source line 78 a may become narrower as the common source line 78 a approaches the substrate 3 .

[0053] The thickness of the insulating partition wall 72a may be greater than Figure 2 The thickness of the insulating partition wall 72a disposed on the first lower mold insulating layer 5L may be the same as the sum of the widths of the two step portions SP contacting the insulating partition wall 72a. The lower portion of the insulating partition wall 72a may contact the second region R2 and the third region R3 of the groove RCS.

[0054] Figure 4 is a cross-sectional view of a semiconductor device including a groove having four regions of different widths according to some example embodiments. Figure 4 Only the Figure 2 A cross section corresponding to the magnified area of ​​the groove RCS.

[0055] refer to Figure 4 , the common source line 78b may be disposed in a groove RCS′ formed in the upper surface of the substrate 3. The groove RCS′ may include a first region R1, a second region R2, a third region R3, and a fourth region R4 having different widths. The first width W1 of the first region R1 may be narrower than the second width W2 of the second region R2, the second width W2 of the second region R2 may be narrower than the third width W3 of the third region R3, and the third width W3 of the third region R3 may be narrower than the fourth width W4 of the fourth region R4. The width of the step portion SP may be narrower than Figure 2 or Figure 3 The width of the step portion SP is narrow.

[0056] The common source line 78b may contact the lowermost portion of the groove RCS′ and a portion of the stepped portion SP. Figure 2Unlike the common source line 78 of FIG. 1 , the common source line 78 b may include a plurality of regions having different widths, so that the shape of the common source line 78 b may correspond to the shape of the groove RCS′. For example, the common source line 78 b may include three regions having different widths, so that the shape of the common source line 78 b may correspond to the shape of the groove RCS′.

[0057] The thickness of the insulating partition wall 72b may be less than Figure 2 The thickness of the insulating partition wall 72b disposed on the first lower mold insulating layer 5L may be similar to or the same as the width of a single stepped portion SP contacting the insulating partition wall 72b. A lower portion of the insulating partition wall 72b may contact the fourth region R4 of the groove RCS′.

[0058] FIG. 5A to FIG. 5I is a cross-sectional view of a method of manufacturing a semiconductor device according to some example embodiments. FIG. 5A to FIG. 5I Description of manufacturing Figure 1 or Figure 2 A method of a semiconductor device is shown in FIG. FIG. 5A to FIG. 5I is along Figure 1 A cross-sectional view taken along line II′.

[0059] refer to Figure 5A , a substrate 3 may be provided. The substrate 3 may be a semiconductor substrate. A plurality of molded insulating layers 8 and a plurality of sacrificial layers 13 may be formed to be alternately and repeatedly stacked on the substrate 3. The molded insulating layers 8 and the sacrificial layers 13 may constitute a molded structure. The molded insulating layer 8 may be formed of a material having an etching selectivity relative to a material of the sacrificial layer 13. For example, the molded insulating layer 8 may be formed of silicon oxide, and the sacrificial layer 13 may be formed of silicon nitride.

[0060] The molded insulating layer 8 may include a first lower molded insulating layer 5L, a second lower molded insulating layer 5U disposed on the first lower molded insulating layer 5L, a plurality of intermediate molded insulating layers 6 disposed on the second lower molded insulating layer 5U, and an upper molded insulating layer 7 disposed on the intermediate molded insulating layer 6 .

[0061] The first lower mold insulating layer 5L may be thinner than each of the intermediate mold insulating layers 6. The second lower mold insulating layer 5U may be thicker than each of the intermediate mold insulating layers 6. The upper mold insulating layer 7 may be thicker than each of the intermediate mold insulating layers 6. The sacrificial layer 13 may have a similar thickness or substantially the same thickness.

[0062] The channel hole CH may be formed by a molding structure (e.g., a molding insulating layer 8 and a sacrificial layer 13). The channel hole CH may be provided as a plurality of channel holes CH, and the substrate 3 may be exposed. While the channel hole CH is formed, a groove may be formed in an upper portion of the substrate 3. The channel hole CH may include an upper portion having a width greater than a lower portion.

[0063] By using the SEG process of the substrate 3 as a seed layer, a semiconductor pattern 38 may be formed in the groove below the channel hole CH. The semiconductor pattern 38 may be a silicon epitaxial layer. The upper surface of the semiconductor pattern 38 may be higher than the lower surface of the second lower mold insulating layer 5U, and may be lower than the upper surface of the second lower mold insulating layer 5U.

[0064] refer to Figure 5B , a first dielectric layer 21, a second dielectric layer 24, and a third dielectric layer 27 may be sequentially formed on the substrate 3 having the channel hole CH and the semiconductor pattern 38. A sacrificial partition wall 29 may be formed on the third dielectric layer 27 within the channel hole CH, and then the first dielectric layer 21, the second dielectric layer 24, and the third dielectric layer 27 may be anisotropically etched to expose the semiconductor pattern 38 by using the sacrificial partition wall 29 as an etching mask.

[0065] refer to Figure 5C , the sacrificial partition wall 29 may be removed, and the semiconductor layer 33 may be formed. The semiconductor layer 33 may be connected to the semiconductor pattern 38. When the sacrificial partition wall 29 is removed, the upper portion of the semiconductor pattern 38 may be partially etched to form a recessed region. In this case, the recessed region may be filled with the semiconductor layer 33. In some example embodiments, the semiconductor layer 33 may be formed without removing the sacrificial partition wall 29.

[0066] A filling insulating layer 36 may be formed on the semiconductor layer 33 to fill a portion of the channel hole CH, and a conductive pad 39 may be formed to fill the remaining portion of the channel hole CH and cover the semiconductor layer 33 and the filling insulating layer 36 .

[0067] The first dielectric layer 21, the second dielectric layer 24, and the third dielectric layer 27 may constitute a dielectric structure 30. The semiconductor pattern 38, the conductive pad 39, the semiconductor layer 33, the filling insulating layer 36, and the dielectric structure 30 may constitute a channel structure 42.

[0068] refer to Figure 5D, a first upper insulating layer 45 may be formed to cover the channel structure 42 and the upper mold insulating layer 7. A preliminary isolation region 51 may be formed in a second direction perpendicular to the upper surface of the substrate 3 by the first upper insulating layer 45, the mold insulating layer 8, and the sacrificial layer 13. While forming the preliminary isolation region 51, a first preliminary groove RC1 may be formed in the substrate 3. Subsequently, a lateral opening portion 52 may be formed by selectively removing the sacrificial layer 13 exposed by the preliminary isolation region 51. For example, when the sacrificial layer 13 is a silicon nitride layer and the mold insulating layer 8 is a silicon oxide layer, an isotropic etching process may be performed using an etchant containing phosphoric acid. The lateral opening portion 52 may extend from the preliminary isolation region 51 to the space between the mold insulating layers 8 in a horizontal direction so as to expose a portion of the lateral surface of the channel structure 42 and a portion of the lateral surface of the semiconductor pattern 38. By an oxidation process, an insulating layer 63 may be formed on the lateral surface of the semiconductor pattern 38 exposed by the lateral opening portion 52.

[0069] refer to Figure 5E , a fourth dielectric layer 54 and a conductive material layer 57 a may be formed to fill the lateral opening portion 52 .

[0070] The fourth dielectric layer 54 may be formed by forming an amorphous metal oxide film and then performing a heat treatment process for crystallization thereon. Alternatively, after the heat treatment process, the surface of the metal oxide film may be etched. The heat treatment process may be a spike rapid thermal processing (RTP) process performed in an inert gas environment.

[0071] Forming the conductive material layer 57 a may include forming a first conductive material layer 55 a covering the fourth dielectric layer 54 in the lateral opening portion 52 , and a second conductive material layer 56 a covering the first conductive material layer 55 a and filling the lateral opening portion 52 .

[0072] The fourth dielectric layer 54 and the conductive material layer 57a may also be formed on the lateral surfaces of the preliminary isolation region 51 and on the first upper insulating layer 45. The fourth dielectric layer 54 and the conductive material layer 57a may also be formed on the surface of the first preliminary groove RC1.

[0073] refer to Fig. 5F , the conductive layers 57 may be formed to be separated from each other in a second direction perpendicular to the upper surface of the substrate 3 .

[0074] Through the wet etching process, portions of the conductive material layer 57 a formed on the lateral surfaces of the preliminary isolation region 51 , on the first upper insulating layer 45 , and on the surface of the first preliminary groove RC1 may be removed.

[0075] In this operation, the molded insulating layer 8 may protrude further than the conductive layers 57. Each of the conductive layers 57 may include a first conductive layer 55 and a second conductive layer 56.

[0076] refer to Figure 5G , the isolation region OP may be formed by removing a protruding portion of the mold insulating layer 8 .

[0077] The protruding portion of the mold insulating layer 8 can be removed by a dry etching process. 4 F 6 Gas, C 4 F 8 The dry etching process is performed by using an etching gas of a gas or a combination thereof. The lateral surface of the conductive layer 57 may be coplanar with the lateral surface of the mold insulating layer 8 in the isolation region OP. Therefore, since a slit or a void (described later) may not be formed in the common source line 78 in the process of forming the common source line 78, the fluorine F remaining in the slit or the void may be reduced or prevented. 2 The gas melts the insulating partition walls 72. Furthermore, the portion of the first conductive layer 55 that may remain along the protruding portion of the molded insulating layer 8 may be removed altogether, and thus defects in bridges between the conductive layers 57 may be reduced or prevented.

[0078] In this operation, a second preliminary groove RC2 may be formed in the upper surface of the substrate 3. The second preliminary groove RC2 may be deeper than the first preliminary groove RC1. The second preliminary groove RC2 may have a side including a single step portion SP. The step portion SP may be formed by removing a protruding portion of the molded insulating layer 8 and then etching a portion of the substrate 3 below the protruding portion. The second preliminary groove RC2 may include an upper region and a lower region having different widths. The width of the upper region of the second preliminary groove RC2 may be greater than the width of the first preliminary groove RC1. The width of the lower region of the second preliminary groove RC2 may be substantially similar to or the same as the width of the first preliminary groove RC1.

[0079] refer to Figure 5H , the insulating partition walls 72 may be formed on the lateral surfaces of the isolation region OP.

[0080] The insulating partition wall 72 may be formed by forming an insulating material layer covering the lateral surfaces of the isolation region OP and the upper surface of the second preliminary groove RC2 and performing an etch-back process.

[0081] In this operation, a groove RCS may be formed in the substrate 3. The groove RCS may have a side having two stepped portions SP. An insulating partition wall 72 may be formed on the stepped portion SP of the groove RCS. A lower portion of the insulating partition wall 72 may include a bent portion formed along the shape of the groove RCS. A portion of the substrate 3 may be exposed through the isolation region OP.

[0082] The impurity region 75 may be formed below the recess RCS. Impurities may be implanted by an ion implantation process after or before the insulating partition wall 72 is formed. The impurity region 75 may include, for example, n-type impurities.

[0083] refer to Fig.5I , a common source line 78 may be formed to fill the space between the insulating partition walls 72 .

[0084] The isolation region OP can be filled by deposition ( Figure 5H ) and performing a planarization process to form a common source line 78. The common source line 78 may be formed of a conductive material. The conductive material may be formed of, for example, at least one of a metal nitride, a metal silicide, and a metal.

[0085] Reference again Figure 1 or Figure 2 , a second upper insulating layer 81 may be formed on the first upper insulating layer 45 and on the common source line 78. A contact plug 84 may be formed to pass through the first upper insulating layer 45 and the second upper insulating layer 81 and electrically connected to the conductive pad 39 of the channel structure 42. The contact plug 84 may be formed of a metal silicide, a metal nitride and / or a metal. A bit line 87 may be formed on the second upper insulating layer 81 to be electrically connected to the contact plug 84. The bit line 87 may be formed of a conductive material, for example, a metal nitride such as TiN or TaN and a metal such as W, Al or Cu.

[0086] Unlike the above-described manufacturing method, in the manufacturing method according to some example embodiments, the conductive layer 57 may be formed by a dry etching process so that the conductive layer 57 may be separated from each other in the second direction perpendicular to the upper surface of the substrate 3 .

[0087] Through the dry etching process, the portion of the conductive material layer 57a formed on the lateral surface of the preliminary isolation region 51, on the first upper insulating layer 45, and on the surface of the first preliminary groove RC1 may be removed first. Through the dry etching process, the portion of the mold insulating layer 8 exposed by removing the portion of the conductive material layer 57a covering the lateral surface of the preliminary isolation region 51 may be removed together with the portion of the conductive material layer 57a. Through the dry etching process, the mold insulating layer 8 and the conductive material layer 57a may be etched at a similar etching rate or the same etching rate.

[0088] As mentioned above, Figure 5G The lateral opening portion and the second preliminary groove similar to or the same as the lateral opening portion and the second preliminary groove can be formed by a dry etching process capable of etching the molded insulating layer 8 and the conductive material layer 57a together. 2 The dry etching process is performed using an etching gas of the gas.

[0089] Figure 6 According to some example embodiments, Figure 2 A cross-sectional view of a semiconductor device showing a semiconductor pattern.

[0090] and Figure 2 The semiconductor devices shown are different. Figure 6 The semiconductor device shown in FIG. 4 may include a channel structure 42 ′ without the semiconductor pattern 38 . Therefore, the semiconductor layer 33 may directly contact the substrate 3 .

[0091] Figure 6 The semiconductor device shown in FIG. Figure 5B The process after the process (not performed as in the above reference Figure 5A The SEG process for forming the semiconductor pattern 38 is used to manufacture the semiconductor pattern 38.

[0092] In the semiconductor device according to the foregoing, the stacked structure ST, the channel structure 42′, the common source line 78, the insulating partition wall 72, the impurity region 75 and the bit line 87 arranged on the substrate 3 may constitute a memory cell array region. A peripheral circuit region electrically connected to such a memory cell array region may be formed on the substrate 3 and may be arranged outside the memory cell array region. The peripheral circuit region may include a plurality of transistors. The arrangement of the peripheral circuit region is not limited thereto and may be modified.

[0093] Figure 7 is a cross-sectional view of a semiconductor device including a memory cell array region and a peripheral circuit region according to some example embodiments.

[0094] refer to Figure 7 The stacked structure ST, the channel structure 42, the common source line 78, the insulating partition wall 72, the impurity region 75 and the bit line 87 arranged on the substrate 3′ may constitute a memory cell array region “unit”. The peripheral circuit region “periphery” may be arranged below the memory cell array region “unit”. The memory cell array region “unit” may have the same Figure 2 The structure is the same as that shown in , but the substrate 3 ′ may include, for example, an amorphous or polycrystalline semiconductor material.

[0095] The peripheral circuit region "periphery" may be formed on the base substrate 103. The base substrate 103 may be a semiconductor substrate. The peripheral circuit region "periphery" may include a plurality of transistors TR and a plurality of wirings ML. The peripheral circuit region "periphery" may be covered by a lower insulating layer 110 between the base substrate 103 and the substrate 3'.

[0096] Figure 8is a cross-sectional view of a semiconductor device according to some example embodiments, wherein the thickness of the insulating partition wall varies such that the thickness close to the substrate is greater than the thickness far from the substrate.

[0097] refer to Figure 8 ,and Figure 2 Unlike the semiconductor device shown in , the insulating partition wall 72′ may have a first thickness T1′ at a portion on the lateral surface of the lowest gate electrode (e.g., the lateral surface of the lowest selection gate electrode 57g), and may have a second thickness T2′ at a portion on the lateral surface of the uppermost gate electrode (e.g., the lateral surface of the uppermost selection gate electrode 57s), and the first thickness T1′ may be greater than the second thickness T2′. The first distance between the lowest selection gate electrode 57g and the common source line 78 may be greater than the second distance between the uppermost selection gate electrode 57s and the common source line 78.

[0098] Fig. 9 is a cross-sectional view of a semiconductor device according to some example embodiments, wherein the thickness of the insulating partition wall varies such that the thickness close to the substrate is smaller than the thickness far from the substrate.

[0099] refer to Fig. 9 ,and Figure 2 Unlike the semiconductor device shown in , the insulating partition wall 72″ may have a first thickness T1″ at a portion on the lateral surface of the lowermost gate electrode (e.g., the lateral surface of the lowermost selection gate electrode 57g), and may have a second thickness T2″ at a portion on the lateral surface of the uppermost gate electrode (e.g., the lateral surface of the uppermost selection gate electrode 57s), and the first thickness T1″ may be smaller than the second thickness T2″. The first distance between the lowermost selection gate electrode 57g and the common source line 78 may be smaller than the second distance between the uppermost selection gate electrode 57s and the common source line 78.

[0100] As set forth above, according to some example embodiments, a semiconductor device can be provided, in which the occurrence of bridging defects between gate electrodes and between the gate electrode and the common source line can be reduced, and slits (or gaps) can be reduced or slits (or gaps) can be prevented from being formed in the common source line. In addition, a semiconductor device with improved reliability can be provided.

[0101] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the appended claims.

Claims

1. A semiconductor device, include: a substrate including a groove below the isolation region, the substrate defining a side of the groove to include a plurality of stepped portions; a plurality of gate electrodes spaced apart from each other on the substrate and stacked in a direction perpendicular to an upper surface of the substrate; a channel structure passing through the plurality of gate electrodes; The isolation region passes through the plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface; a common source line, within the isolation region and connected to the substrate at the lowest portion of the recess; as well as a partition wall between the common source line and the plurality of gate electrodes, the partition wall contacting the plurality of gate electrodes, Wherein, the lower portion of the partition wall includes a curved portion formed according to the plurality of stepped portions of the side portion of the groove.

2. The semiconductor device according to claim 1, in, The width of the upper portion of the groove is the same as the width of the lower portion of the isolation region, and The width of the upper portion of the groove is greater than the width of the lower portion of the groove.

3. The semiconductor device according to claim 1, in, The common source line comprises: a lower region contacting the substrate at a lowermost portion of the recess, and An upper region, on the lower region of the common source line, wherein a width of the upper region of the common source line is greater than a width of the lower region of the common source line.

4. The semiconductor device according to claim 1, in, A lower portion of the partition wall contacts the substrate at a side of the groove.

5. The semiconductor device according to claim 1, in, The partition wall has a first thickness in a first position contacting a lateral surface of a lowermost gate electrode among the plurality of gate electrodes, and has a second thickness in a second position contacting a lateral surface of an uppermost gate electrode among the plurality of gate electrodes, the second thickness being different from the first thickness.

6. The semiconductor device according to claim 1, further comprising: include: The impurity region is below the groove and has n-type impurities.

7. A semiconductor device, include: a substrate including a groove, the substrate defining the groove to include a first region, a second region, and a third region having different widths; A stacked structure comprising a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the substrate; as well as A common source line passes through the stack structure to contact the substrate at the first region of the groove, and the common source line extends on the substrate in one direction.

8. The semiconductor device according to claim 7, in, The second region is above the first region, the third region is above the second region, a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region.

9. The semiconductor device according to claim 8, in, A lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer among the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.

10. The semiconductor device according to claim 7, in, The common source line includes a plurality of regions having different widths.

11. The semiconductor device according to claim 7, in, A first interval between a lateral surface of a lowermost gate electrode among the plurality of gate electrodes and the common source line is different from a second interval between a lateral surface of an uppermost gate electrode among the plurality of gate electrodes and the common source line.

12. The semiconductor device according to claim 8, further comprising: include: A partition wall is between the stack structure and the common source line, and the partition wall contacts the substrate at the second region and the third region of the groove.

13. The semiconductor device according to claim 8, in, The groove further includes a fourth region above the third region, the fourth region having a fourth width greater than a third width of the third region, and The semiconductor device further includes a partition wall between the stack structure and the common source line, the partition wall contacting the substrate at a fourth region of the groove.

14. A semiconductor device, include: a substrate including a groove, the substrate defining the groove to include a first region having a first width, a second region having a second width greater than the first width, and a third region having a third width greater than the second width; A plurality of stacked structures, each stacked structure comprising a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the substrate; a plurality of channel structures passing through the plurality of stacked structures to extend in a direction perpendicular to an upper surface of the substrate; as well as A plurality of partition walls are disposed between the stacked structures, the plurality of partition walls contacting the substrate at the third region and extending on the substrate in one direction.

15. The semiconductor device according to claim 14, further comprising: include: A conductive layer is provided between the plurality of partition walls, wherein the conductive layer contacts the substrate at the lowest portion of the groove.

16. The semiconductor device according to claim 14, further comprising: include: The impurity region is below the groove and has n-type impurities.

17. The semiconductor device according to claim 14, in, Each of the plurality of partition walls has a first thickness at a first position on a lateral surface of a lowermost gate electrode among the plurality of gate electrodes, and has a second thickness at a second position on a lateral surface of an uppermost gate electrode among the plurality of gate electrodes, the second thickness being different from the first thickness.

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