Distributed Programmable Delay Line in the Clock Tree

Abstract

The present disclosure provides systems and methods for improving the operation of an integrated circuit device, the integrated circuit device including a logic region and a clock tree, the logic region including a plurality of logic gates that operate at least in part based on a clock signal to facilitate providing a target function, the clock tree including a clock switching block that receives a source clock signal from a clock source and branches communicatively coupled between the clock switching block and the logic region, wherein the branches operate to provide the clock signal to the logic region at least in part based on the source clock signal and one or more tunable delay buffers, the one or more tunable delay buffers being disposed at handover points of the clock network and operating to apply a delay to the clock signal at least in part based on a clock skew expected to be introduced by the branches.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure generally relates to integrated circuit devices, and more particularly to clock trees implemented in integrated circuit devices.

[0002] This section is intended to introduce to the reader various aspects of the prior art that may be relevant to various aspects of the present disclosure described and / or claimed below. This discussion is believed to be helpful to provide background information to the reader to facilitate a better understanding of various aspects of the present disclosure. Accordingly, it should be understood that these written descriptions are to be read in this sense and not as an admission of prior art.

[0003] Generally, an electronic device or an electrical system may include one or more integrated circuit (IC) devices. To improve operational flexibility, in some instances, the integrated circuit device may be a programmable logic device, such as a field programmable array (FPGA), which may provide one or more target (e.g., intended) functions based on programming (e.g., configuration) after manufacturing. To facilitate providing the target function, the integrated circuit device may include, for example, one or more logic elements (e.g., blocks and / or gates) programmed (e.g., configured) to operate at least in part based on corresponding configuration data.

[0004] In some instances, the logic elements in the integrated circuit device may be organized into multiple logic regions, e.g., each logic region provides a target function and / or multiple logic regions cooperate to provide a target function. Thus, in operation, the integrated circuit device may coordinate (e.g., synchronize) the operations of multiple logic regions. Since logic elements generally operate at least in part based on received clock signals, in some instances, the integrated circuit device may coordinate the operations of multiple logic regions by supplying clock signals to corresponding logic elements using a clock tree (e.g., an on-chip clock network). For example, the clock tree may include multiple branches, each branch transmitting a clock signal through a corresponding logic region.

[0005] However, in some instances, such as due to the length of a branch and / or stages (e.g., multiplexers or buffers) along the branch, when a clock signal is transmitted through a clock tree, the clock signal may become skewed (e.g., time offset or phase offset). In fact, the likelihood and / or magnitude of clock skew may increase as the size / depth of the clock tree increases, as the variation in branch length increases, and / or due to the programming of integrated circuit devices. Additionally, the arrival time of the clock signal may be affected by the temperature and instantaneous voltage of components of the clock, and may be affected by the process parameters of individual transistors within an instance of the chip. Since the parameters that have a certain amount of impact on skew can vary across specific instances of the device, over time, or across environmental factors, skew is unknown, although it has a range known as uncertainty based on the variation of the impact parameters. Since operation is at least partially based on the clock signal, clock skew may affect the operation of logic elements, and thus the operation of the integrated circuit device, for example, by reducing operation efficiency and / or increasing operation latency. SUMMARY OF THE INVENTION

[0006] The following presents a summary of the invention for specific embodiments disclosed herein. It should be understood that these aspects are provided merely to give the reader a concise summary of these specific embodiments and are not intended to limit the scope of the present disclosure. In fact, the present disclosure may cover aspects that may not be set forth below.

[0007] The present disclosure generally relates to integrated circuit (IC) devices that can operate to perform one or more target (or intended) functions in an electrical system. To facilitate the execution of the target functions, in some embodiments, the integrated circuit device may include one or more logic elements (e.g., blocks or gates) that operate at least partially based on a received clock signal to perform, for example, logical and / or arithmetic operations used in providing combinational, sequential, arithmetic, logical, and / or custom functions. Thus, in some embodiments, the integrated circuit device may include a clock tree (e.g., an on-chip clock network) that transmits the clock signal to various logic elements. However, in some cases, when the clock signal is transmitted through the clock tree, the clock signal may become skewed, thereby affecting the operation of the logic elements and thus the operation of the integrated circuit device.

[0008] Accordingly, the present disclosure provides techniques for improving the operation (e.g., operation efficiency and / or operation latency) of an integrated circuit device by reducing the likelihood of clock skew that affects the operation. In some embodiments, the integrated circuit device includes a logic region and a clock tree, the logic region including a plurality of logic gates that operate at least in part based on a clock signal to facilitate providing a target function, the clock tree including a clock switch block that receives a source clock signal from a clock source and branches communicatively coupled between the clock switch block and the logic region, wherein the branches operate to provide a clock signal to the logic region at least in part based on the source clock signal, and the branches include tunable delay buffers that operate to apply a delay to the clock signal at least in part based on a clock skew expected to be introduced by the branches.

[0009] In addition, in some embodiments, a tangible, non-transitory computer-readable medium stores instructions executable by one or more processors in an electrical system, wherein the instructions include instructions for performing the following operations: using the one or more processors to determine skew data that indicates a difference between first delays introduced on a source clock signal due to routing the source clock signal via a clock tree to a first portion of the integrated circuit device; and using the one or more processors to command one or more tunable delay buffers to adjust a delay applied to the source clock signal via the clock tree at least in part based on the skew data.

[0010] In addition, in some embodiments, tunable (e.g., programmable) delay buffers may be present at each handoff point or node of the clock network to allow adjustment of the clock signal through an entire subtree. In addition, in some embodiments, clock switch blocks may also be present at each node. In such embodiments, relative measurements of delays between branches of a node may be made by a delay measurement circuit, and a set of adjustments for each clock node may be determined using one or more processors to mitigate skew. In these embodiments, the clock adjustments may correspond proportionally to the depth of the clock tree. In other words, a hierarchical set of clock adjustments may be used to address clock skew based on the structure of the clock network.

[0011] Various improvements to the above features may exist with respect to various aspects of the present disclosure. Other features may also be incorporated into these various aspects. These improvements and additional features may exist alone, or in any combination. For example, the various features discussed below in connection with one or more of the illustrated embodiments may be incorporated alone or in any combination into any of the above aspects of the present disclosure. The brief summary presented above is only intended to familiarize the reader with specific aspects and contexts of embodiments of the present disclosure and does not limit the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Aspects of the present disclosure may be better understood when reading the following detailed description and with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of an integrated circuit device using the clock alignment techniques described herein according to an embodiment;

[0014] Figure 2 is according to an embodiment Figure 1 a block diagram of an array of logic elements included in an integrated circuit device of

[0015] Figure 3A and Figure 3B are block diagrams according to embodiments showing Figure 1 the implemented clock tree of an integrated circuit device of

[0016] Figure 4A and Figure 4B are according to an embodiment Figure 3A and Figure 3B block diagrams of portions of the clock tree of

[0017] Figure 5 is a block diagram of a programming system according to an embodiment for programming the operation of an integrated circuit device of Figure 1 ;

[0018] Figure 6 shows a timing diagram of a reference clock signal and a second clock signal according to an embodiment; and

[0019] Figure 7 shows a timing diagram of a reference clock signal, an adjustable delay setting, an output clock signal having a timing violation, and an output clock signal with jumps caused by changes in the delay setting subtracted according to an embodiment. DETAILED DESCRIPTION

[0020] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, all features of actual implementations are not described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints, which may vary between implementations. Additionally, it should be understood that such development work may be complex and time-consuming, but for those of ordinary skill in the art who benefit from the present disclosure, it is merely a routine task of design, fabrication, and preparation.

[0021] Generally, an integrated circuit device operates to provide one or more target functions in an electronic data processing system. For example, the target functions may include combinational functions, sequential functions, arithmetic functions, logical functions, and / or custom functions. Thus, in some embodiments, the integrated circuit device may operate to process data, analyze data, store data, and / or read data.

[0022] To help illustrate by way of example, Figure 1 An embodiment of an electronic data processing system 10 including an integrated circuit device 12 is shown. In some embodiments, the electronic data processing system 10 may be included in an industrial system, a manufacturing system, an automation system, etc., such as included in a manufacturing plant or factory. Additionally, in some embodiments, the electronic data processing system 10 may be included in an electronic device such as a handheld computing device, a tablet computing device, a laptop computer, a desktop computer, etc. Additionally, in some embodiments, the electronic data processing system 10 may be included in an automated system such as an airplane, a ship, or an automobile.

[0023] Thus, although one integrated circuit device 12 is depicted, it should be recognized that this is only for illustrative purposes and not a limitation. In other words, in other embodiments, the electronic data processing system 10 may include multiple integrated circuit devices 12. For example, the electronic data processing system 10 may include a first integrated circuit 12 (e.g., a central processing unit or a graphics processing unit) communicatively coupled to a second integrated circuit 12 (e.g., a random access memory).

[0024] In any case, as shown, the integrated circuit device 12 includes a logic element array 14, a clock tree 16, a delay measurement circuit 17, and a controller 18. In some embodiments, the controller 18 may control the operation of the logic element array 14 and / or the clock tree 16. To facilitate control of the operation, the controller 18 may include a controller processor 20 and a controller memory 22. In some embodiments, the controller 18 may control the operation at least in part based on circuit connections (e.g., logic gates) formed in the controller 18.

[0025] Alternatively or additionally, the controller processor 20 may execute instructions stored in the controller memory 22. Thus, in some embodiments, the controller processor 20 may include one or more general-purpose microprocessors, one or more dedicated processors (ASICs), one or more field-programmable logic arrays (FPGAs), and / or the like. Additionally, in some embodiments, the controller memory 22 may include one or more tangible, non-transitory computer-readable media. For example, the controller memory 22 may include random access memory (RAM), read-only memory (ROM), rewritable non-volatile memory (e.g., flash memory), and / or the like.

[0026] As described above, the integrated circuit device 12 can operate to perform one or more target functions in the electronic data processing system 10. To facilitate providing the target functions, the logic element array 14 can include communicatively coupled logic elements (e.g., blocks or gates) that operate to perform combinational functions, sequential functions, arithmetic functions, logical functions, and / or custom functions. Additionally, in some embodiments, the logic element array 14 can be divided into one or more logic regions, each logic region including one or more logic elements.

[0027] To help illustrate by way of example, Figure 2 An embodiment of the logic element array 14 organized into a plurality of logic regions 48 is shown in. Specifically, the depicted embodiment includes a first logic region 48A, a second logic region 48B, a third logic region 48C, and a fourth logic region 48D, each of which includes one or more logic elements 50. In some embodiments, the logic elements 50 can include one or more multiplexers, one or more flip-flops, one or more logic gates, one or more logic blocks, one or more look-up tables, and / or one or more registers.

[0028] In some embodiments, the logic element array 14 can be organized such that different logic regions 48 operate to perform different target functions. Alternatively or additionally, the logic element array 14 can be organized such that multiple logic regions 48 cooperate to perform a target function. Thus, to facilitate the proper operation of the integrated circuit device 12, the operations of different logic regions 48 can be coordinated (e.g., synchronized) and / or data communication can be provided.

[0029] To facilitate data communication, the logic element array 14 can include input / output circuitry 42, input / output pins 44, and an internal communication network 46 (e.g., a network-on-chip). In some embodiments, the input / output circuitry 42 can facilitate external data communication, for example, between the logic element array 14 and another integrated circuit device 12 via the input / output pins 44. Additionally, in some embodiments, the internal communication network 46 can facilitate internal data communication, for example, between the logic regions 48 and / or with the input / output circuitry 42. Thus, in some embodiments, the internal communication network 46 can include interconnects, for example, conductive lines and / or buses. Additionally, in some embodiments, the internal communication network 46 can include fixed interconnects and / or programmable interconnects.

[0030] In addition, in some embodiments, the logic elements 50 operate at least in part based on a received clock signal, and thus the logic regions 48 operate at least in part based on the received clock signal. Specifically, operations can be performed based on the rising edge and / or falling edge of the received clock signal. Thus, to facilitate coordination of the operations of the multiple logic regions 48, substantially the same clock signal can be transmitted to the corresponding logic elements 50 in the logic regions 48.

[0031] Returning to Figure 1 the integrated circuit device 12, the clock tree 16 can facilitate the transmission of clock signals to the respective logic regions 48. To help illustrate, Figure 3A an embodiment of the clock tree 16 is shown in. Specifically, in the depicted embodiment, the clock tree 16 has the topology of an H-tree built on components of a clock grid. It should be recognized that the described embodiment of the clock tree 16 is for illustrative purposes only and is not limiting. In other words, in other embodiments, the techniques described in this disclosure can be implemented in other clock tree configurations.

[0032] For the depicted embodiment, the clock tree 16 includes clock interconnects 63, clock switch blocks 64, and tunable delay buffers 72 (e.g., delay devices). In operation, the clock switch block 64 can receive a source clock signal from a clock source 62, e.g., directly from the clock source 62 and / or via an upstream clock switch block 64. Additionally, the clock switch block 64 can route the source clock via the block interconnect 63 and / or to a target logic region (e.g., Figure 2 48A, 48B, 48C, or 48D of) through one or more tunable delay devices 72.

[0033] In this way, the clock tree 16 can route the source clock signal to the logic elements 50 and / or the logic regions 48 in the logic element array 14. For example, in the depicted embodiment, the clock tree 16 includes a first branch 60A that can be used to route the source clock signal to the first logic region 48A. For example, in the depicted embodiment, the clock tree 16 includes a second branch 60B that can be used to route the source clock signal to the fourth logic region 48D.

[0034] In addition, in some embodiments, the integrated circuit device 12 may include one or more delay measurement circuits 17 implemented using hard logic and / or soft logic to effect relative clock measurements between different logic regions 48. That is, the delay measurement circuit 17 may be used to compare a clock signal routed through the first logic region 48A with a clock signal routed through the fourth logic region 48D to determine the delay or skew between the clock signals of each logic region 48. It should be appreciated that the delay measurement circuit 17 may alternatively or additionally be implemented to compare one or more branches 60 that route a source clock signal to other logic regions 48 (e.g., the second logic region 48D and / or the third logic region 48C).

[0035] As described above, in some instances, routing a clock signal through the clock tree 16 may introduce clock skew, e.g., due to variations in branch length, stages along the branch (e.g., multiplexers or buffers), and / or other electrical factors (e.g., process variations). However, as described above, clock skew may affect the operation of the logic elements 50 and thus the cooperation between different logic regions 48 in the integrated circuit device 12. Accordingly, in some embodiments, the operation of one or more tunable delay buffers 72 along the branch 60 may be controlled at least in part based on an expected clock skew.

[0036] The tunable delay buffer 72 may be constructed in several different ways, which will be discussed below, but as the name implies their primary function is to tune or vary the delay present in the clock signal. In other words, they are used in the circuit to increase or decrease the delay so that the clock signals are better aligned. Returning Figure 3A , the tunable delay buffer 72 is positioned at the end or leaf of the clock tree. As previously mentioned, the routing of the clock tree and variations in branch length may introduce clock skew into the clock signal. Thus, adjusting the clock signal using the tunable delay buffer 72 to address the skew at the end of the clock tree can facilitate more reliable timing in the target logic region (e.g., Figure 2 48A, 48B, 48C, or 48D). However, as the size of the clock tree grows, the skew of the clock signal at the leaf of the tree also increases, thus requiring the tunable delay buffer 72 to address a greater skew. As a result, it may be beneficial to place additional tunable delay buffers at an earlier part or stage of the tree, particularly at the juncture where individual branches split off.

[0037] As mentioned above, it may be beneficial to place tunable delay devices at each handoff point of the clock network. In such an embodiment, the amount of clock delay adjustment from the clock root to the leaf can be controlled to be proportional to the depth of the clock tree, and the actual clock delay uncertainty caused by the adjustable delay block 72 can be reduced. Figure 3B An embodiment of a clock network is shown having tunable delay buffers 72 present at each handoff point to enable clock adjustment through the entire subtree.

[0038] As Figure 3B shown, in some embodiments, at each handoff point or node of the clock network, tunable delay buffers 72 may be present on each side of the handoff point to allow clock signal adjustment through the entire subtree. In some embodiments, clock switch blocks 64 may also be present at each node. To aid in illustration, Figure 3B another embodiment of the clock tree 16' is shown. Figure 3B The illustrated embodiment is similar to the embodiment of the clock tree 16, but it may also include clock switch blocks 64 at each node of the clock network and / or tunable delay buffers 72 on each branch following the node. In such an embodiment, the delay measurement circuit 17 can be used to perform relative clock measurements of the delays between the branches of the nodes at each level within the tree. Since the relative clock measurements can be the result of variable clock skew in different parts of the tree, a system of algebraic equations can be used to determine where within the clock tree the delay can be adjusted. In other words, the controller 18 can process the clock measurement data using a set of equations representing the connections for distributing the clock in the clock network, and once these equations are solved, several delay settings can be produced that minimize the skew at various points in the clock distribution network. With these settings, the controller 18 can command one or more tunable delay buffers 72 to adjust the applied delay, as mentioned above.

[0039] Some aspects of measurement error and clock variability may not be captured by the algebraic system. Thus, in some embodiments, oversampling of the data (by measuring all adjacent boundaries between clock zones) together with best fit analysis can be used as a technique to minimize uncertainty. In these embodiments, the relative error between the measurement and the best fit analysis model can help refine the actual uncertainty, which can be decomposed into placement and routing solutions.

[0040] In addition, in embodiments where one or more tunable delay blocks 72 are present at each node of the clock network, uncertainty can be reduced because skews that are alternatives to or in addition to the skews at the ends or leaves of the branches of the tree can be removed. By removing the skews before the leaves, there may be more delays in the common nodes, which can reduce the contribution of the tunable delay buffers 72 themselves to clock uncertainty. This hierarchical solution for removing skews can also be more stable than removing skews at the leaves, where there may be more equivalent solutions.

[0041] Turning now to a discussion of tunable delay devices, Figure 4A A portion 74 of the clock tree 16 is shown. As shown, the portion 74 includes a first clock switch block 64A communicatively coupled to a second clock switch block 64B via a clock interconnect 63 through a tunable delay device 72. Additionally, as shown, a controller 18 is communicatively coupled to the tunable delay device 72. In this way, the controller 18 can command the tunable delay buffer 72 to adjust the delay applied to the corresponding clock interconnect 63 at least in part based on an expected clock skew.

[0042] In another embodiment, as Figure 4B shown, a portion 74' of the clock tree 16 can alternatively be configured with a clock switch block 64' that can include one or more tunable delay buffers 72 within the clock switch block component itself. The tunable delay buffers 72 can be implemented in a variety of ways. In one embodiment, the tunable delay buffer can include a buffer and / or a string of inverters that can be combined with a multiplexer to select one of the clock outputs as the delayed output. In another embodiment, one or more bias transistors can be used to change the digital drive pull-up and / or pull-down impedance. This embodiment can also include a digitally programmable voltage that drives the gates of the bias transistors. In yet another embodiment, one or more loads (e.g., capacitors) can be added to the clock switch block 64' to implement the tunable delay buffer, and the loads can be programmably controlled such that the loads can slow down one or more buffers and / or strings of inverters. By means of these and any other methods of constructing tunable delay buffers, tunable delay buffer components 72 can be constructed within the various stages of the clock switch block 64'. As previously mentioned, additionally / alternatively, tunable delay buffer components 72 can be present in the clock tree 16, separate from the clock switch block component 64.

[0043] In some embodiments, the clock tree 16 can be programmed and / or reprogrammed. That is, the routing of the source clock signal from the clock source 62 to the logic region 48 can be dynamically set. In such embodiments, the clock switch block 64 can control the routing of the clock signal in a manner that facilitates implementing the corresponding clock routing configuration (e.g., the implementation of the branch 60 in the clock tree 16).

[0044] To help illustrate, Figure 5 An embodiment of a programming system 88 that can be used to program (e.g., configure) the operation of the integrated circuit device 12 is shown. In some embodiments, the programming system 88 can implement the programming operation of the integrated circuit device 12 using, for example, a mask programming arrangement during semiconductor manufacturing. Additionally, in some embodiments, the programming system 88 can use, for example, fuses and / or antifuses to implement one-time programming of the integrated circuit device 12 after manufacturing.

[0045] Furthermore, in some embodiments, when the integrated circuit device 12 is a programmable (e.g., reconfigurable) logic device (e.g., a field programmable gate array (FPGA)), the programming system 88 can implement dynamic programming (e.g., reprogramming) of the operation of the integrated circuit device 12. In some embodiments, design software 90 (e.g., a version of Intel TM Quartus) can be used to program the integrated circuit device 12. Additionally, the design software 90 can use a compiler 92 to generate configuration data 94, e.g., a low-level circuit design kernel program, which is sometimes referred to as a program object file.

[0046] To program the integrated circuit device 12, the configuration data 94 can be stored in, for example, Figure 2 the configuration memory 52 shown. In some embodiments, the configuration memory 52 can be implemented as random access memory (RAM) cells. Since these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). Based at least in part on the configuration data, control signals can be generated to control the operation 96 of the integrated circuit device 12.

[0047] For example, at least in part based on target function configuration data, a control signal can be applied to the gate of a metal oxide semiconductor (e.g., logic element 50) to control the operation in a manner that implements the corresponding target function. In some embodiments, at least in part based on data routing configuration data, a control signal can be supplied to the internal communication network 46 to control data routing in a manner that facilitates implementation of the corresponding target data routing configuration. Alternatively or additionally, at least in part based on clock routing configuration data, a control signal can be supplied to the clock switch block 64 to control clock signal routing in a manner that facilitates implementation of the corresponding clock routing configuration (e.g., implementation of the branch 60 in the clock tree 16).

[0048] In some instances, programming (e.g., reprogramming) the integrated circuit device 12 to adjust the operation and / or configuration of the clock tree 16 can have an impact on electrical factors. For example, reprogramming the branch 60 from a first routing configuration to a second routing configuration can affect the branch length and / or the stages (e.g., multiplexers or buffers) along the branch 60. Thus, in such instances, programming (e.g., reprogramming) the integrated circuit device 12 can further increase the likelihood and / or magnitude of clock skew introduced by the clock tree 16.

[0049] To facilitate reducing the likelihood of clock skew that affects the operation of the integrated circuit device 12, the delay measurement circuit 17 can determine skew (e.g., phase shift or time shift) data. As described above, in some embodiments, the clock skew expected to be introduced by one branch 60 can be determined with reference to the clock skew introduced by another branch 60 in the clock tree 16. In other words, in such embodiments, a reference clock signal can be received from a different branch 60 compared to the clock signal for which skew is being adjusted or the second clock signal. For example, Figure 3A in the case of, the delay measurement circuit 17 can receive a first clock signal from a first branch 60A and a second clock signal from a second branch 60B. Thus, to determine the clock skew on the second branch 60B, the delay measurement circuit 17 can use the first clock signal as the reference clock signal. In other embodiments, the reference clock signal can be pre-determined (e.g., by time shifting and / or phase shifting the source clock signal).

[0050] The delay measurement circuit 17 can determine skew data based at least in part on whether the rising edge on the reference clock signal leads or lags the corresponding (e.g., the closest in time) rising edge on the second clock signal and the duration between the rising edge on the reference clock signal and the corresponding rising edge on the second clock signal. Alternatively or additionally, the delay measurement circuit 17 can determine skew data based at least in part on whether the falling edge on the reference clock signal leads or lags the corresponding (e.g., the closest in time) falling edge on the second clock signal and the duration between the falling edge on the reference clock signal and the corresponding falling edge on the second clock signal.

[0051] Based at least in part on the skew data, the controller 18 can command one or more tunable delay buffers 72 to adjust the applied delay. In some embodiments, the controller 18 can receive the skew data from the delay measurement circuit 17 and transmit a control signal (e.g., a command) to the tunable delay buffer 72 indicating the amount of delay that should be applied to the source clock signal to be transmitted next. In this way, the operation of the tunable delay buffer 72 can be controlled to reduce the likelihood and / or magnitude of clock skew variations introduced by different branches 60, which can improve the operation of the integrated circuit device 12, for example, by facilitating coordinated operation of multiple logic regions 48 with improved operation efficiency and / or reduced operation delay.

[0052] To help illustrate the skew adjustment process, Figure 6 a timing diagram 108 depicting the clock signals is provided in. Specifically, the first timing diagram 108A includes a first waveform 110 representing a clock signal. Additionally, the second timing diagram 108B includes a second waveform 112 representing a second clock signal, and the third timing diagram 108C includes a third waveform 114 representing a third clock signal.

[0053] Based on the rising and / or falling edges of the first waveform 110 and the second waveform 112, the delay measurement circuit 17 can determine skew data indicating that the second waveform 112 lags the first waveform 110 by approximately one-eighth of a clock period (T). Thus, based at least in part on the skew data, the controller 18 can command one or more tunable delay buffers 74 on the corresponding branch 60 to reduce the delay applied to the source clock signal to be transmitted next, such that the resulting first signal 108B is expected to be delayed by an additional seven-eighths of a clock period (T). Alternatively or additionally, the controller 18 can command one or more tunable delay buffers 74 on the corresponding branch 60 to reduce the delay applied to the source clock signal to be transmitted next, such that the resulting signal 108B is expected to lead by one-eighth of a clock period (T).

[0054] In addition, based on the rising edge and / or falling edge of the first waveform 110 and the third waveform 114, the delay measurement circuit 17 can determine skew data indicating that the third waveform 114 leads the first waveform 110 by approximately one-eighth of a clock period (T). Thus, at least in part based on the skew data, the controller 18 can command one or more tunable delay buffers 74 on the corresponding branch 60 to increase the delay applied to the source clock signal to be transmitted next, so that the resulting third waveform 114 is expected to be delayed by an additional one-eighth of a clock period (T). Alternatively or in addition, the controller 18 can command one or more tunable delay buffers 74 on the corresponding branch 60 to decrease the delay applied to the source clock signal to be transmitted next, so that the resulting third waveform 114 is expected to lead by seven-eighths of a clock period (T).

[0055] Since the tunable delay buffer can shorten and / or extend the clock delay, it can affect the current clock period in which it changes. The change in the clock delay may cause a timing violation on the path included in the clock domain driven by the tunable delay buffer. Figure 7The timing violation is demonstrated using timing diagram 116. Specifically, the first timing diagram 116A includes a first waveform 118 representing a reference or input clock signal. The second timing diagram 116B includes an adjustable delay setting 120 introduced to the first waveform 118 of the input clock signal by an element such as a tunable delay buffer 72. The third timing diagram 116C demonstrates the effect of the delay setting 116B on the first waveform 118 and the resulting timing violation 126 through an output clock waveform 122. In the third timing diagram 116C, the timing violation 126 occurs between the second and third falling edges 128A and 128B respectively on the output clock waveform 122, at the position where the delay setting changes from the length of delay N-1 120A to the length of delay N 120B. Since the length of the delay is shortened, the falling edges 128A and 128B of the second clock period 132 and the third clock period 134 are too close to each other, resulting in a timing violation 126 that may affect the behavior of the logic region 48 receiving the clock signal. The fourth timing diagram 116D can illustrate a more desirable result in the waveform diagram, where the jump in the delay length from delay N-1 120A to delay N 120B is ignored so that the output clock minus the jump waveform 124 has an extended time period between the first falling edge 128C’ of the first period 130 and the next falling edge 128D, thereby skipping the timing violation. By using the tunable delay buffer 72 to skip the jump, the undesired behavior caused by the timing violation can be prevented from occurring in the logic region 48. Therefore, in some embodiments, the tunable delay buffer may need the ability to skip jumps, whether the jumps are rising and / or falling edges of clock cycles, to allow the extension and / or shortening of the time period between the affected cycle edges to avoid timing violations.

[0056] The techniques described and claimed herein refer to and apply to physical objects and specific examples of practical utility, which improve the technical field in a demonstrable manner and are thus not abstract, intangible, or purely theoretical. Additionally, if any claim appended to the end of this specification includes one or more elements designated as "means for performing... function" or "step for performing... function", then it is intended that such elements be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim that includes elements designated in any other manner, it is intended that such elements not be interpreted in accordance with 35 U.S.C. 112(f).

[0057] Although the embodiments set forth in this disclosure may readily admit of various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that this disclosure is not intended to be limited to the particular forms disclosed. This disclosure will cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the following appended claims.

[0058] Embodiments of the present application

[0059] The numbered clauses below define embodiments of the current application.

[0060] Clause A1. An integrated circuit device, comprising:

[0061] A first logic region including a first plurality of logic gates that operate at least in part based on a first clock signal to facilitate providing a target function;

[0062] A clock tree, comprising:

[0063] A first clock switch block that receives a source clock signal from a clock source;

[0064] A first branch communicatively coupled between the first clock switch block and the first logic region, wherein:

[0065] The first branch operates to provide the first clock signal to the first logic region at least in part based on the source clock signal; and

[0066] A set of one or more tunable delay buffers disposed at each junction of the clock tree, the one or more tunable delay buffers operating to apply a delay to a clock signal at least in part based on a clock skew expected to be introduced by a subtree of the junction, the set of one or more tunable delay buffers including a first tunable delay buffer that operates to apply a first delay to the first clock signal at least in part based on a first clock skew expected to be introduced by the first branch.

[0067] Clause A2. The integrated circuit device according to Clause A1, including a second logic region including a second plurality of logic gates that operate at least in part based on a second clock signal to cooperate with the first logic region to provide a target function;

[0068] wherein the clock tree includes a second branch communicatively coupled between the first clock switch block and the second logic region, wherein the second branch operates to provide the second clock signal to the second logic region at least in part based on the source clock signal.

[0069] Clause A3. The integrated circuit device according to any one of the foregoing clauses, including a delay measurement circuit configured to determine a skew between two or more clock signals.

[0070] Clause A4. The integrated circuit device according to Clause A3, wherein the two or more clock signals include the first clock signal and the source clock signal.

[0071] Clause A5. The integrated circuit device according to any one of Clauses A1, A2, or A3, including a controller configured to command the first tunable delay buffer to apply the first delay based at least in part on the first clock skew and a set of equations representing connections of the clock tree.

[0072] Clause A6. The integrated circuit device according to Clause A5, wherein the controller is configured to command the first tunable delay buffer to apply the first delay based at least in part on an additive delay including a sum of the first delay and the second delay, and command a second tunable delay buffer in the set of one or more tunable delay buffers to apply a second delay, wherein the second tunable delay buffer is disposed at a handover point in a subtree of the first branch, and wherein the additive delay is based at least in part on a clock skew expected to be introduced by leaves of the subtree of the first branch.

[0073] Clause A7. The integrated circuit device according to any one of Clauses A1, A2, A3, or A5, wherein the first delay adjusts a period of a clock cycle of the first clock signal to avoid a timing violation.

[0074] Clause A8. The integrated circuit device according to any one of Clauses A1, A2, A3, A5, or A7, wherein the first branch includes:

[0075] a first clock interconnect communicatively coupling the first clock switch block to the first tunable delay buffer; and

[0076] a second clock interconnect communicatively coupling the first tunable delay buffer to a second clock switch block.

[0077] Clause A9. The integrated circuit device according to any one of Clauses A1, A2, A3, A5, A7, or A8, wherein:

[0078] the first logic region includes a multiplexer, a flip-flop, a logic block, a look-up table, a register, or any combination thereof, and

[0079] the target function includes a combinational function, a sequential function, an arithmetic function, a logical function, a custom function, or any combination thereof.

[0080] Clause A10. An integrated circuit device according to any one of Clauses A1, A2, A3, A5, A7, A8, or A9, wherein the integrated circuit device includes a field programmable gate array.

[0081] Clause A11. An integrated circuit device, comprising:

[0082] A clock tree including one or more handover points;

[0083] A set of one or more clock switch blocks disposed at each of the one or more handover points for receiving a source clock signal from a clock source, the set of one or more clock switch blocks including:

[0084] A circuit for selectively routing the source clock signal between:

[0085] A first branch in the clock tree that enables at least a first logic region of the integrated circuit device communicatively coupled to the first branch to operate at least partially based on the source clock signal; and

[0086] A second branch in the clock tree that enables at least a second logic region of the integrated circuit device communicatively coupled to the second branch to operate at least partially based on the source clock signal; and

[0087] A tunable delay buffer that operates to apply a first delay to a first clock signal at least partially based on a first clock skew expected to be introduced by the first branch.

[0088] Clause A12. The integrated circuit device according to Clause A11, including a delay measurement circuit configured to determine skew data between the first clock signal and the source clock signal.

[0089] Clause A13. The integrated circuit device according to Clause A12, wherein the skew data indicates whether the first clock signal leads the source clock signal, whether the first clock signal lags the source clock signal, a first duration for which the first clock signal leads the source clock signal, a second duration for which the first clock signal lags the source clock signal, or any combination thereof.

[0090] Clause A14. The integrated circuit device according to any one of Clauses A11 or A12, wherein the tunable delay buffer includes a plurality of bias transistors configured to change a digital drive pull-up impedance, pull-down impedance, or a combination thereof.

[0091] Clause A15. An integrated circuit device according to any one of Clauses A11, A12, or A14, wherein the tunable delay buffer includes one or more buffer strings.

[0092] Clause A16. An integrated circuit device according to Clause A15, wherein a plurality of loads are configured to slow down the one or more buffer strings.

[0093] Clause A17. A machine-implemented method, comprising:

[0094] Determining skew data at each handover point of a clock network of an integrated circuit, the skew data indicating a difference between first delays introduced on a source clock signal due to routing the source clock signal via a clock tree to a first portion of the integrated circuit device; and

[0095] Commanding one or more tunable delay buffers to adjust at least in part a delay imposed on the source clock signal by the clock tree based on the skew data to facilitate coordination of operations of the first portion of the integrated circuit device.

[0096] Clause A18. The machine-implemented method according to Clause A17, wherein the integrated circuit includes a plurality of logic regions, each logic region includes a plurality of logic gates, and the logic gates operate at least in part based on the source clock signal to provide a target function.

[0097] Clause A19. The machine-implemented method according to Clause A18, including oversampling the skew data, wherein oversampling the skew data includes determining skew data and best-fit analysis at adjacent boundaries between pairs of logic regions for each pair of logic regions among the plurality of logic regions.

[0098] Clause A20. The machine-implemented method according to any one of Clauses A17 or A18, including storing configuration data in a configuration memory of the integrated circuit device, wherein the configuration data:

[0099] Adjusts a first operation performed by the first portion of the integrated circuit device;

[0100] Adjusts a second operation performed by a second portion of the integrated circuit device;

[0101] Routes the source clock signal through the clock tree to the first portion of the integrated circuit device;

[0102] Routes the source clock signal through the clock tree to the second portion of the integrated circuit device; or

[0103] Any combination of the above.

[0104] Clause B1. An integrated circuit device, comprising:

[0105] A first logic region, comprising a first plurality of logic gates that operate at least in part based on a first clock signal to facilitate providing a target function;

[0106] A clock tree, comprising:

[0107] A first clock switching block that receives a source clock signal from a clock source;

[0108] A first branch communicatively coupled between the first clock switching block and the first logic region, wherein:

[0109] The first branch operates to provide the first clock signal to the first logic region at least in part based on the source clock signal; and

[0110] A set of one or more tunable delay buffers disposed at each junction point of the clock tree, the one or more tunable delay buffers operating to apply a delay to a clock signal at least in part based on a clock skew expected to be introduced by a subtree of the junction point, the set of one or more tunable delay buffers including a first tunable delay buffer that operates to apply a first delay to the first clock signal at least in part based on a first clock skew expected to be introduced by the first branch.

[0111] Clause B2. The integrated circuit device according to Clause B1, comprising a second logic region, the second logic region comprising a second plurality of logic gates that operate at least in part based on a second clock signal to cooperate with the first logic region to provide a target function;

[0112] Wherein, the clock tree includes a second branch communicatively coupled between the first clock switching block and the second logic region, wherein, the second branch operates to provide a second clock signal to the second logic region at least in part based on the source clock signal.

[0113] Clause B3. The integrated circuit device according to any one of Clauses B1 or B2, comprising a delay measurement circuit configured to determine a skew between two or more clock signals.

[0114] Clause B4. The integrated circuit device according to Clause B3, wherein the two or more clock signals include the first clock signal and the source clock signal.

[0115] Clause B5. The integrated circuit device according to any one of Clauses B1, B2, or B3, includes a controller configured to command the first tunable delay buffer to apply the first delay based at least in part on the first clock skew and a set of equations representing the connections of the clock tree.

[0116] Clause B6. The integrated circuit device according to Clause B5, wherein the controller is configured to command the first tunable delay buffer to apply the first delay based at least in part on an additive delay including the sum of the first delay and the second delay, and to command a second tunable delay buffer in the set of one or more tunable delay buffers to apply a second delay, wherein the second tunable delay buffer is disposed at a handover point in a subtree of the first branch, and wherein the additive delay is based at least in part on the clock skew expected to be introduced by the leaves of the subtree of the first branch.

[0117] Clause B7. The integrated circuit device according to any one of Clauses B1, B2, B3, or B5, wherein the first delay adjusts a period of a clock cycle of the first clock signal to avoid a timing violation.

[0118] Clause B8. The integrated circuit device according to any one of Clauses B1, B2, B3, B5, or B7, wherein the first branch includes:

[0119] a first clock interconnect communicatively coupling the first clock switch block to the first tunable delay buffer; and

[0120] a second clock interconnect communicatively coupling the first tunable delay buffer to a second clock switch block.

[0121] Clause B9. The integrated circuit device according to any one of Clauses B1, B2, B3, B5, B7, or B8, wherein:

[0122] the first logic region includes a multiplexer, a flip-flop, a logic block, a look-up table, a register, or any combination thereof, and

[0123] the target function includes a combinational function, a sequential function, an arithmetic function, a logical function, a custom function, or any combination thereof.

[0124] Clause B10. The integrated circuit device according to any one of Clauses B1, B2, B3, B5, B7, B8, or B9, wherein the integrated circuit device includes a field programmable gate array.

[0125] Clause B11. An integrated circuit device, comprising:

[0126] A clock tree, which includes one or more handover points;

[0127] A set of one or more clock switch blocks that receive a source clock signal from a clock source and are disposed at each of the one or more handover points, the set of one or more clock switch blocks including:

[0128] A circuit that selectively routes the source clock signal between:

[0129] A first branch in the clock tree that enables the communication of the integrated circuit device coupled to a first logic region of the first branch to operate at least partially based on the source clock signal; and

[0130] A second branch in the clock tree that enables the communication of the integrated circuit device coupled to a second logic region of the second branch to operate at least partially based on the source clock signal; and

[0131] A tunable delay buffer that operates to apply a first delay to a first clock signal based at least in part on a first clock skew expected to be introduced by the first branch.

[0132] Clause B12. The integrated circuit device according to Clause B11, including a delay measurement circuit configured to determine skew data between the first clock signal and the source clock signal.

[0133] Clause B13. The integrated circuit device according to Clause B12, wherein the skew data indicates whether the first clock signal leads the source clock signal, whether the first clock signal lags the source clock signal, a first duration for which the first clock signal leads the source clock signal, a second duration for which the first clock signal lags the source clock signal, or any combination thereof.

[0134] Clause B14. The integrated circuit device according to any one of Clauses B11 or B12, wherein the tunable delay buffer includes a plurality of bias transistors configured to change a digital-driven pull-up impedance, a pull-down impedance, or a combination thereof.

[0135] Clause B15. The integrated circuit device according to any one of Clauses B11, B12, or B14, wherein the integrated circuit device includes one or more buffer strings.

[0136] Clause B16. The integrated circuit device according to Clause B15, wherein the plurality of loads are configured to slow down the one or more buffer strings.

[0137] Clause B17. A machine-implemented method, including:

[0138] Determine skew data at each handover point of a clock network of an integrated circuit, the skew data indicating a difference between first delays introduced on a source clock signal due to routing the source clock signal via a clock tree to a first portion of an integrated circuit device; and

[0139] Command one or more tunable delay buffers to adjust, at least in part based on the skew data, a delay imposed by the clock tree on the source clock signal to facilitate coordination of operations of the first portion of the integrated circuit device.

[0140] Clause B18. The machine-implemented method according to clause B17, wherein the integrated circuit includes a plurality of logic regions, each logic region includes a plurality of logic gates, and the logic gates operate at least in part based on the source clock signal to provide a target function.

[0141] Clause B19. The machine-implemented method according to clause B18, including oversampling the skew data, wherein oversampling the skew data includes determining skew data at an adjacent boundary between a pair of logic regions of the plurality of logic regions for each pair of the logic regions and performing a best-fit analysis.

[0142] Clause B20. The machine-implemented method according to any one of clauses B17 or B18, including storing configuration data in a configuration memory of the integrated circuit device, wherein the configuration data:

[0143] Adjust a first operation performed by the first portion of the integrated circuit device;

[0144] Adjust a second operation performed by a second portion of the integrated circuit device;

[0145] Route the source clock signal through the clock tree to the first portion of the integrated circuit device;

[0146] Route the source clock signal through the clock tree to the second portion of the integrated circuit device; or

[0147] Any combination of the above.

[0148] Clause B21. A tangible non-transitory machine-readable medium including machine-readable instructions that, when executed by one or more processors, cause the processors to perform the machine-implemented method according to any one of clauses B17, B18, or B20.

[0149] Clause C1. An integrated circuit device, comprising:

[0150] A first logic region, which includes a first plurality of logic gates that operate at least in part based on a first clock signal to facilitate providing a target function;

[0151] A clock tree, which includes:

[0152] A first clock switch block that receives a source clock signal from a clock source;

[0153] A first branch communicatively coupled between the first clock switch block and the first logic region, wherein:

[0154] The first branch operates to provide the first clock signal to the first logic region at least in part based on the source clock signal; and

[0155] A set of one or more tunable delay buffers disposed at each handover point of the clock tree, the one or more tunable delay buffers operating to apply a delay to a clock signal at least in part based on a clock skew expected to be introduced by a subtree of the handover point, the set of one or more tunable delay buffers including a first tunable delay buffer that operates to apply a first delay to the first clock signal at least in part based on a first clock skew expected to be introduced by the first branch.

[0156] Clause C2. The integrated circuit device according to Clause C1, including a second logic region, the second logic region including a second plurality of logic gates that operate at least in part based on a second clock signal to cooperate with the first logic region to provide a target function;

[0157] Wherein, the clock tree includes a second branch communicatively coupled between the first clock switch block and the second logic region, wherein, the second branch operates to provide a second clock signal to the second logic region at least in part based on the source clock signal.

[0158] Clause C3. The integrated circuit device according to any one of Clauses C1 or C2, including a delay measurement circuit configured to determine a skew between two or more clock signals.

[0159] Clause C4. The integrated circuit device according to any one of Clauses C1, C2 or C3, including a controller configured to command the first tunable delay buffer to apply the first delay at least in part based on the first clock skew and a set of equations representing the connections of the clock tree.

[0160] Clause C5. The integrated circuit device according to Clause C4, wherein the controller is configured to command the first tunable delay buffer to apply the first delay based at least in part on an additive delay including the sum of the first delay and the second delay, and command a second tunable delay buffer in the set of one or more tunable delay buffers to apply a second delay, wherein the second tunable delay buffer is set at a handover point in a subtree of the first branch, and wherein the additive delay is at least in part based on a clock skew expected to be introduced by leaves of the subtree of the first branch.

[0161] Clause C6. The integrated circuit device according to any one of Clauses C1, C2, C3, or C4, wherein the first delay adjusts a period of a clock cycle of the first clock signal to avoid a timing violation.

[0162] Clause C7. The integrated circuit device according to any one of Clauses C1, C2, C3, C4, or C6, wherein the first branch includes:

[0163] A first clock interconnect that communicatively couples the first clock switch block to the first tunable delay buffer; and

[0164] A second clock interconnect that communicatively couples the first tunable delay buffer to a second clock switch block.

[0165] Clause C8. The integrated circuit device according to any one of Clauses C1, C2, C3, C4, C6, or C7, wherein:

[0166] The first logic region includes a multiplexer, a flip-flop, a logic block, a lookup table, a register, or any combination thereof, and

[0167] The target function includes a combinational function, a sequential function, an arithmetic function, a logical function, a custom function, or any combination thereof.

[0168] Clause C9. The integrated circuit device according to any one of Clauses C1, C2, C3, C4, C6, C7, or C8, wherein the integrated circuit device includes a field programmable gate array.

[0169] Clause C10. A tangible non-transitory machine-readable medium including machine-readable instructions that, when executed by one or more processors, cause the processors to:

[0170] Command a set of one or more clock switch blocks that receive a source clock signal from a clock source at each of one or more handover points of a clock tree to selectively route the source clock signal between:

[0171] a first branch in the clock tree to cause a first logic region of the integrated circuit device communicatively coupled to the first branch to operate at least in part based on the source clock signal; and

[0172] a second branch in the clock tree to cause a second logic region of the integrated circuit device communicatively coupled to the second branch to operate at least in part based on the source clock signal; and

[0173] commanding a tunable delay buffer to apply a first delay to a first clock signal based at least in part on a first clock skew expected to be introduced by the first branch.

[0174] Clause C11. The machine-readable medium according to Clause C10, comprising instructions to command a delay measurement circuit to determine skew data between a first clock signal and the source clock signal, wherein the skew data indicates whether the first clock signal leads the source clock signal, whether the first clock signal lags the source clock signal, a first duration for which the first clock signal leads the source clock signal, a second duration for which the first clock signal lags the source clock signal, or any combination thereof.

[0175] Clause C12. The machine-readable medium according to Clause C10 or C11, wherein the tunable delay buffer includes a plurality of bias transistors configured to change a pull-up impedance, a pull-down impedance, or a combination thereof of a digital drive, one or more buffer strings, or a combination thereof.

[0176] Clause C13. A machine-implemented method, comprising:

[0177] determining skew data at each handoff point of a clock network of an integrated circuit, the skew data indicating a difference between first delays introduced on the source clock signal due to routing the source clock signal via a clock tree to a first portion of the integrated circuit device; and

[0178] commanding one or more tunable delay buffers to adjust delays applied to the source clock signal by the clock tree based at least in part on the skew data to facilitate coordination of operation of the first portion of the integrated circuit device.

[0179] Clause C14. The machine-implemented method according to Clause C13, including oversampling the skew data, wherein oversampling the skew data includes determining skew data and best-fit analysis at an adjacency boundary between pairs of logic regions for each pair of logic regions in a plurality of logic regions, wherein the integrated circuit includes a plurality of logic regions, each logic region including a plurality of logic gates operating at least in part based on the source clock signal to provide a target function.

[0180] Clause C15. A machine-implemented method according to any one of Clauses C13 or C14, including storing configuration data in a configuration memory of the integrated circuit device, wherein the configuration data:

[0181] Adjusts a first operation performed by the first part of the integrated circuit device;

[0182] Adjusts a second operation performed by the second part of the integrated circuit device;

[0183] Routes the source clock signal through the clock tree to the first part of the integrated circuit device;

[0184] Routes the source clock signal through the clock tree to the second part of the integrated circuit device; or

[0185] Any combination of the above.

Claims

1. An integrated circuit device, comprising: A first logic region that includes a first plurality of logic gates that operate at least in part based on a first clock signal to facilitate a target function; A clock tree that includes: A first clock switch block that receives a source clock signal from a clock source; A first branch communicatively coupled between the first clock switch block and the first logic region, wherein: The first branch operates to provide the first clock signal to the first logic region at least in part based on the source clock signal; and A set of one or more tunable delay buffers disposed at each junction point of the clock tree, the one or more tunable delay buffers operating to apply a delay to a clock signal at least in part based on clock skew expected to be introduced by a subtree of the junction point, the set of one or more tunable delay buffers including a first tunable delay buffer that operates to apply a first delay to the first clock signal at least in part based on first clock skew expected to be introduced by the first branch.

2. The integrated circuit device according to claim 1, comprising a second logic region, the second logic region including a second plurality of logic gates, the second plurality of logic gates operating at least in part based on a second clock signal to cooperate with the first logic region to provide the target function; Wherein, The clock tree includes a second branch communicatively coupled between the first clock switch block and a second logic region, wherein the second branch operates to provide the second clock signal to the second logic region at least in part based on the source clock signal.

3. The integrated circuit device according to any one of the preceding claims, comprising a delay measurement circuit configured to determine a skew between two or more clock signals.

4. The integrated circuit device according to claim 3, wherein, The two or more clock signals include the first clock signal and the source clock signal.

5. The integrated circuit device according to any one of claims 1 or 2, comprising a controller configured to command the first tunable delay buffer to apply the first delay at least in part based on the first clock skew and a set of equations representing the connections of the clock tree.

6. The integrated circuit device according to claim 5, wherein, The controller is configured to command the first tunable delay buffer to apply the first delay and command a second tunable delay buffer in the set of one or more tunable delay buffers to apply the second delay at least in part based on an additive delay that includes a sum of the first delay and a second delay, wherein the second tunable delay buffer is disposed at a junction point in a subtree of the first branch, and wherein the additive delay is at least in part based on clock skew expected to be introduced by leaves of the subtree of the first branch.

7. The integrated circuit device according to any one of claims 1 or 2, wherein, The first delay adjusts a period of a clock cycle of the first clock signal to avoid a timing violation.

8. The integrated circuit device according to any one of claims 1 or 2, wherein, The first branch includes: A first clock interconnect that communicatively couples the first clock switch block to the first tunable delay buffer; and A second clock interconnect that communicatively couples the first tunable delay buffer to a second clock switch block.

9. The integrated circuit device according to any one of claims 1 or 2, wherein: The first logic region includes a multiplexer, a flip-flop, a logic block, a look-up table, a register, or any combination thereof, and The target function includes a combinational function, a sequential function, an arithmetic function, a logic function, a custom function, or any combination thereof.

10. The integrated circuit device according to any one of claims 1 or 2, wherein, The integrated circuit device includes a field programmable gate array.

11. An integrated circuit device, comprising: A clock tree that includes one or more junction points; A set of one or more clock switch blocks that receive a source clock signal from a clock source, the set of one or more clock switch blocks disposed at each of the one or more junction points, the set of one or more clock switch blocks including: Circuitry that selectively routes the source clock signal between: A first branch in the clock tree that enables communication of the integrated circuit device coupled to the first logic region of the first branch to operate at least in part based on the source clock signal; and A second branch in the clock tree that enables communication of the integrated circuit device coupled to the second logic region of the second branch to operate at least in part based on the source clock signal; and A tunable delay buffer that operates to apply a first delay to a first clock signal based at least in part on a first clock skew expected to be introduced by the first branch.

12. The integrated circuit device according to claim 11, comprising a delay measurement circuit configured to determine skew data between the first clock signal and the source clock signal.

13. The integrated circuit device according to claim 12, wherein The skew data indicates whether the first clock signal leads the source clock signal, whether the first clock signal lags the source clock signal, a first duration for which the first clock signal leads the source clock signal, a second duration for which the first clock signal lags the source clock signal, or any combination thereof.

14. The integrated circuit device according to any one of claims 11 or 12, wherein The tunable delay buffer includes a plurality of bias transistors configured to change a digital-driven pull-up impedance, a pull-down impedance, or a combination thereof.

15. The integrated circuit device according to any one of claims 11 or 12, wherein The tunable delay buffer includes one or more buffer strings.

16. The integrated circuit device according to claim 15, wherein A plurality of loads are configured to slow down the one or more buffer strings.

17. A machine-implemented method, comprising: Determine skew data at each handover point of the clock network of the integrated circuit, the skew data indicating a difference between first delays introduced on the source clock signal due to routing the source clock signal via the clock tree to a first portion of the integrated circuit device; And Command one or more tunable delay buffers to adjust at least in part based on the skew data the delay applied to the source clock signal by the clock tree to facilitate coordination of the operation of the first portion of the integrated circuit device.

18. The machine-implemented method according to claim 17, wherein The integrated circuit includes a plurality of logic regions, each of the plurality of logic regions including a plurality of logic gates that operate at least in part based on the source clock signal to provide a target function.

19. The machine-implemented method according to claim 18, comprising oversampling the skew data, wherein Oversampling the skew data includes determining the skew data at adjacent boundaries between each pair of the logic regions of the plurality of logic regions and a best fit analysis.

20. The machine-implemented method according to any one of claims 17 or 18, comprising storing configuration data in a configuration memory of the integrated circuit device, wherein The configuration data: Adjust a first operation performed by the first portion of the integrated circuit device; Adjust a second operation performed by the second portion of the integrated circuit device; Route the source clock signal through the clock tree to the first portion of the integrated circuit device; Route the source clock signal through the clock tree to the second portion of the integrated circuit device; or Any combination of the above.

21. A tangible non-transitory machine-readable medium including machine-readable instructions that, when executed by one or more processors, cause the processors to perform the machine-implemented method according to any one of claims 17, 18, or 20.

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