Code generation method, device and equipment based on chip clock tree prototype graph

Abstract

The application relates to a code generation method, device and equipment based on a chip clock tree prototype graph. The method comprises the following steps: obtaining a clock tree prototype graph of to-be-generated code, analyzing the clock tree prototype graph, obtaining the type of components in the clock tree prototype graph and the connection relationship of the components, and generating the code corresponding to the clock tree prototype graph according to the type of the components and the connection relationship of the components. According to the type of the components and the connection relationship of the components, the code corresponding to the clock tree prototype graph can be directly and accurately generated. Chip design engineers do not need to design the corresponding code while designing the clock tree prototype graph. The code corresponding to the clock tree prototype graph can be automatically generated by only maintaining or modifying the clock tree prototype graph.

Description

Code generation method, apparatus, and equipment based on chip clock tree prototype diagram Technical Field

[0001] This application relates to the field of chip technology, and in particular to a code generation method, apparatus and device based on a chip clock tree prototype diagram. Background Technology

[0002] Currently, the uncertainty of clock requirements for IPs and chip application scenarios in System-on-Chips (SoCs) leads to changes in clock requirements. This necessitates simultaneous modifications to the clock tree architecture and corresponding code. Modifying these files inevitably results in errors, leading to lengthy and inefficient design, verification, and review processes, thus extending the overall development cycle. Due to the uncertainty of chip market demand and application scenarios, chip specifications constantly change during the chip design process. Common specification changes include adding IPs, adding clock sources, and modifying clock frequencies. For example, when chip IP clock requirements change, chip design engineers need to modify the code and update the clock tree diagram, which is then verified by chip verification engineers. Simultaneously, backend engineers require SoC clock tree architecture diagrams from chip design engineers. More detailed architecture diagrams allow for more efficient and convenient backend implementation of the chip clock tree, optimizing chip area and power consumption.

[0003] Frequent changes in chip clock requirements lead to chip design engineers frequently modifying code and clock tree architecture diagrams. Frequent iterations inevitably result in errors, as well as low design and verification efficiency and longer development cycles.

[0004] Existing technologies include solutions for generating clock tree code using tables. However, since tables are not as intuitive as prototype diagrams, the code generated by this solution is not intuitive or accurate for complex clock trees. Furthermore, tables cannot assist chip verification engineers and backend engineers in chip verification and implementation. Summary of the Invention

[0005] In view of the above, this application provides a code generation method, apparatus and device based on a chip clock tree prototype diagram, the purpose of which is to provide an intuitive and accurate method for generating clock tree code.

[0006] Firstly, this application provides a code generation method based on a chip clock tree prototype diagram, the method comprising:

[0007] Obtain the clock tree prototype diagram of the code to be generated;

[0008] Analyze the clock tree prototype diagram to obtain the types of components and their connection relationships.

[0009] Based on the type of the component and the connection relationship of the component, generate the code corresponding to the clock tree prototype diagram.

[0010] Secondly, this application provides a code generation apparatus based on a chip clock tree prototype diagram, the code generation apparatus based on the chip clock tree prototype diagram comprising:

[0011] Acquisition module: Used to acquire the clock tree prototype diagram of the code to be generated;

[0012] Parsing module: used to parse the clock tree prototype diagram to obtain the types of components and the connection relationships of the components in the clock tree prototype diagram;

[0013] Generation module: Used to generate the code corresponding to the clock tree prototype diagram based on the type of the component and the connection relationship of the component.

[0014] Thirdly, this application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0015] Memory, used to store computer programs;

[0016] When a processor executes a program stored in memory, it implements the steps of the code generation method based on a chip clock tree prototype diagram as described in any embodiment of the first aspect.

[0017] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the code generation method based on a chip clock tree prototype diagram as described in any embodiment of the first aspect.

[0018] The technical solutions provided in this application have the following advantages compared with the prior art:

[0019] The code generation method, apparatus, and device proposed in this application based on chip clock tree prototype diagrams offer several advantages. Since prototype diagrams are more intuitive than tables, for complex clock trees, this application analyzes the clock tree prototype diagram to obtain the types of components and their connection relationships. Based on these component types and connections, the code corresponding to the clock tree prototype diagram can be generated more intuitively and accurately. Chip design engineers no longer need to design the corresponding code while designing the clock tree prototype diagram; they only need to maintain or modify the diagram to automatically generate the corresponding code. This significantly reduces workload and improves efficiency. Engineers can focus solely on designing the clock tree prototype diagram, leading to a more complete diagram. Verification engineers can more easily decompose test / verification points based on the clock tree prototype diagram, effectively shortening the chip verification cycle and ensuring design reliability. Furthermore, a more complete clock tree prototype diagram allows back-end design engineers to better understand the clock tree structure (e.g., clock source selection, synchronous / asynchronous relationships between clocks, and clock paths). Back-end engineers with this information can achieve clock network designs with smaller area, lower power consumption, and higher performance, thereby improving chip competitiveness. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a flowchart illustrating a preferred embodiment of the code generation method based on a chip clock tree prototype diagram in this application.

[0023] Figure 2 is a schematic diagram of a glitch-free clock selector assembly according to an embodiment of this application;

[0024] Figure 3 is a schematic diagram of a clock selector component according to an embodiment of this application;

[0025] Figure 4 is a schematic diagram of the clock gating unit component according to an embodiment of this application;

[0026] Figure 5 is a schematic diagram of a clock divider assembly according to an embodiment of this application;

[0027] Figure 6 is a schematic diagram of the clock source phase-locked loop assembly according to an embodiment of this application;

[0028] Figure 7 is a schematic diagram of a clock tree prototype according to an embodiment of this application;

[0029] Figure 8 is a schematic diagram of the signal terminals with connection relationships in the clock tree prototype diagram of an embodiment of this application;

[0030] Figure 9 is a schematic diagram of signal terminals without connection relationships in the clock tree prototype diagram of an embodiment of this application;

[0031] Figure 10 is a schematic diagram of a preferred embodiment of the code generation device based on a chip clock tree prototype diagram of this application.

[0032] Figure 11 is a schematic diagram of a preferred embodiment of the electronic device of this application;

[0033] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0035] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0036] This application provides a code generation method based on a chip clock tree prototype diagram. Referring to Figure 1, a flowchart illustrating an embodiment of the code generation method based on a chip clock tree prototype diagram is shown. This method can be executed by an electronic device, which can be implemented in software and / or hardware. The code generation method based on a chip clock tree prototype diagram includes:

[0037] Step S10: Obtain the clock tree prototype diagram of the code to be generated;

[0038] Step S20: Parse the clock tree prototype diagram to obtain the types of components and the connection relationships of the components in the clock tree prototype diagram;

[0039] Step S30: Generate the code corresponding to the clock tree prototype diagram based on the type of the component and the connection relationship of the component.

[0040] Due to the uncertainty of chip market demand and application scenarios, chip specifications are constantly changing during chip design. Common specification changes include adding IP, adding clock sources, and modifying clock frequencies. When chip IP clock requirements change, chip design engineers can modify the clock tree prototype. In this embodiment, the clock tree prototype for the code to be generated can be pre-built according to the actual requirements of the chip IP clock, or it can be a modified clock tree prototype based on actual requirements.

[0041] After obtaining the clock tree prototype diagram, parsing it reveals the types of components and their connections. For example, if clk_o[0] in the clock source phase-locked loop component is connected to i[0] in the glitch-free clock selector component, then the clock source phase-locked loop component and the glitch-free clock selector component are connected. The components in the clock tree prototype diagram may include:

[0042] The clock tree prototype includes at least one of the following: a glitch-free clock selector component, a clock selector component, a clock gating unit component, a clock divider component, and a clock source phase-locked loop component. It should be noted that, depending on the actual needs of the chip IP clock, special components can be added to the clock tree prototype without affecting the automatic generation of the clock tree code, demonstrating strong scalability. Using a clock tree prototype composed of standard digital logic components, circuit redesign is unnecessary when the implementation process changes; only macro definitions are needed to differentiate between processes. This results in high reusability and reliability, effectively shortening the chip design cycle and reducing chip costs.

[0043] Figure 2 shows a schematic diagram of a glitch-free clock selector component according to an embodiment of this application. The glitch-free clock selector (glitchfree clk_mux) component takes a clock signal as its input. When the selection signal changes, the output clock switches smoothly without generating abnormal pulses. The bit width of the clock input and selection signal in the clock tree prototype diagram can generate the corresponding glitch-free clock selector code.

[0044] Figure 3 shows a schematic diagram of the clock selector component according to an embodiment of this application. The clock selector (clk_mux) component takes a clock signal as its input. When the selection signal changes, the output clock is directly switched, and an abnormal pulse will appear during the switching. The bit width of the clock input and selection signal in the clock tree prototype diagram can generate the corresponding clock selector code.

[0045] Figure 4 shows a schematic diagram of the clock gating unit component in an embodiment of this application. The clock gating unit (clk_gating) component takes a clock signal and an enable signal as inputs. When the enable signal (en[n]) is equal to 1, the corresponding clock input (i[n]) is output to clk_o[n]. When the enable signal (en[n]) is equal to 0, the corresponding clock output (clk_o[n]) is equal to 0. The bit width of the clock input and enable signal in the clock tree prototype diagram can generate the corresponding clock gating unit code.

[0046] Figure 5 shows a schematic diagram of the clock divider component in an embodiment of this application. The clock divider (clk_div) component takes reset, clock and division coefficient as input. When the division coefficient changes, clk_o = clk_i / div[n:0]. The div bit width in the clock tree prototype diagram can generate the corresponding clock divider code.

[0047] Figure 6 shows a schematic diagram of the clock source phase-locked loop (PLL) component according to an embodiment of this application. The input of the clock source phase-locked loop (PLL) component is the reset, reference clock, and configuration signals of each output clock. When the frequency division coefficient of clk*_cfg[31:0] changes, clk_o[*] = ref_clk*clk*_cfg[31:0]. The bit width of clk*_cfg[31:0] in the clock tree prototype diagram can generate the corresponding clock source phase-locked loop code.

[0048] Based on the component types and connection relationships obtained by parsing the clock tree prototype diagram, the code corresponding to the clock tree prototype diagram is generated, where the code refers to Verilog code.

[0049] Figure 7 shows a schematic diagram of the clock tree prototype according to an embodiment of this application. The input terminals of the pll_* components are generated as input signals for the component code during code generation. The sel of the glitchfree_clk_mux and clk_mux components are also generated as input signals for the component code during code generation. The rst_n of the glitchfree_clk_mux component is generated as an input signal for the component code. The rst_n and div of the clk_div component are also generated as input signals for the component code. The en of the clk_gating component is also generated as an input signal for the component code. The ddr_clk and cpu_clk are generated as output signals for the clock gating unit code.

[0050] The glitchfree_clk_mux component in Figure 7 consists of two inputs i[0] and i[1] and one output o. In other practical projects, it could be 2 n One input and one output;

[0051] pll_* components are analog circuits, and a PLL will typically output 4 clock cycles.

[0052] The clk_div component can be parameterized based on div[2:0], div[3:0], and div[x:0] in the component, where x determines the maximum value of the frequency division coefficient, and the maximum frequency division coefficient is 2x;

[0053] The clk_gating component in Figure 7 consists of two clock inputs i[0] and i[1], two clock output enablers en[0] and en[1], and two outputs clk_o[0] and clk_o[1]. The number of clock inputs, clock output enablers, and clock outputs can be varied in other practical projects.

[0054] Specifically, based on the type of the component and the connection relationship of the component, the code corresponding to the clock tree prototype diagram is generated, including:

[0055] Obtain the parameterizable code for each component in the clock tree prototype diagram, wherein each component has corresponding parameterizable code;

[0056] Based on the connection relationship of the components, determine the first set of signal terminals in the clock tree prototype diagram that have connection relationships between components, and the second set of signal terminals in the clock tree prototype diagram that do not have connection relationships.

[0057] Based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals, the code corresponding to the clock tree prototype diagram is generated.

[0058] Each component in the clock tree prototype diagram corresponds to a parameterizable code. Based on the parsed connection relationships between components, the signal terminals with connections between components in the clock tree prototype diagram are determined, denoted as the first set of signal terminals. The signal terminals within the dashed boxes in Figure 8 represent those with connections. Conversely, the signal terminals without connections between components in the clock tree prototype diagram are determined, denoted as the second set of signal terminals. The signal terminals within the dashed boxes in Figure 9 represent those without connections. Based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals, the Verilog code corresponding to the clock tree prototype diagram is generated.

[0059] Further, based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals, code corresponding to the clock tree prototype diagram is generated, including:

[0060] The first signal terminal set is converted into code based on the parameterizable code;

[0061] Determine the component to which each signal terminal in the second set of signal terminals belongs;

[0062] The code of each signal terminal is obtained from the parameterizable code of the component to which each signal terminal belongs, thus obtaining the code of the second set of signal terminals;

[0063] By combining the code of the first signal terminal set and the code of the second signal terminal set, the code corresponding to the clock tree prototype diagram is obtained.

[0064] The first set of signal terminals consists of signal terminals in the clock tree prototype diagram that are connected to each other. Since each component corresponds to parameterizable code, the code corresponding to the first set of signal terminals can be generated. The second set of signal terminals consists of signal terminals in the clock tree prototype diagram that are not connected to each other. After determining the component to which each signal terminal belongs in the second set of signal terminals, the code for each signal terminal can be obtained from the parameterizable code of the component to which each signal terminal belongs, thus obtaining the code for the second set of signal terminals. Combining the code from the first set of signal terminals and the code from the second set of signal terminals yields the code corresponding to the clock tree prototype diagram. Specifically, the generated code corresponding to the clock tree prototype diagram is as follows:

[0065]

[0066]

[0067] Since prototype diagrams are more intuitive than tables, this application parses the clock tree prototype diagram to obtain the component types and connection relationships in complex clock trees. Based on these component types and connections, the corresponding code can be generated more intuitively and accurately. Chip design engineers no longer need to design the corresponding code while designing the clock tree prototype diagram; they only need to maintain or modify the clock tree prototype diagram to automatically generate the corresponding code, greatly reducing workload and improving efficiency. Engineers can focus solely on designing the clock tree prototype diagram, making it more complete. Verification engineers can more easily decompose test / verification points based on the clock tree prototype diagram, effectively shortening the chip verification cycle and ensuring design reliability. Furthermore, a more complete clock tree prototype diagram allows back-end design engineers to better understand the clock tree structure (e.g., clock source selection, synchronous / asynchronous relationships between clocks, and clock paths). Back-end engineers who understand this information can achieve clock network designs with smaller area, lower power consumption, and higher performance, thereby improving chip competitiveness.

[0068] In one embodiment, before obtaining the clock tree prototype diagram of the code to be generated, the method further includes:

[0069] Receive editing commands based on chip IP clock requirements;

[0070] Based on the editing instructions, the types and number of components required to construct the clock tree prototype diagram are calculated.

[0071] Construct the clock tree prototype diagram according to the required component types and number of components.

[0072] Users (e.g., chip design engineers) can input editing instructions based on the chip IP clock requirements. These instructions can specify the component types and quantities corresponding to the chip IP clock requirements. Based on the user-input editing instructions, the system calculates the required component types and quantities for constructing a clock tree prototype. For example, it calculates the quantity of each type of component used and constructs the clock tree prototype based on the required component types and quantities. Chip design engineers can then construct the corresponding clock tree prototype according to actual needs. It is understood that when changes are needed to the clock tree prototype, chip design engineers can also add or remove components from the clock tree prototype.

[0073] In one embodiment, after generating the code corresponding to the clock tree prototype diagram, the method further includes:

[0074] The code corresponding to the clock tree prototype diagram is compiled using a preset code compilation tool.

[0075] Compiling the generated code using a pre-defined code compilation tool ensures the feasibility of the generated clock tree prototype code. The pre-defined code compilation tool can be a compiled Verilog simulator.

[0076] Referring to Figure 10, this is a schematic diagram of the functional modules of the code generation device 100 based on the chip clock tree prototype diagram of this application.

[0077] The code generation device 100 based on a chip clock tree prototype diagram described in this application can be installed in an electronic device. Depending on the functions implemented, the code generation device 100 based on the chip clock tree prototype diagram may include an acquisition module 110, a parsing module 120, and a generation module 130. The module described in this application can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0078] In this embodiment, the functions of each module / unit are as follows:

[0079] Module 110: Used to obtain the clock tree prototype diagram of the code to be generated;

[0080] Parsing module 120: used to parse the clock tree prototype diagram to obtain the types of components and the connection relationships of the components in the clock tree prototype diagram;

[0081] Generation module 130: Used to generate code corresponding to the clock tree prototype diagram based on the type of the component and the connection relationship of the component.

[0082] In one embodiment, the code generation apparatus 100 based on a chip clock tree prototype diagram further includes a construction module, which is used for:

[0083] Receive editing commands based on chip IP clock requirements;

[0084] Based on the editing instructions, the types and number of components required to construct the clock tree prototype diagram are calculated.

[0085] Construct the clock tree prototype diagram according to the required component types and number of components.

[0086] In one embodiment, the component includes at least one of: a glitch-free clock selector component, a clock selector component, a clock gating unit component, a clock divider component, and a clock source phase-locked loop component.

[0087] In one embodiment, the code generation apparatus 100 based on a chip clock tree prototype diagram further includes a compilation module, which is used for:

[0088] The code corresponding to the clock tree prototype diagram is compiled using a preset code compilation tool.

[0089] In one embodiment, the step of generating the code corresponding to the clock tree prototype diagram based on the type of the component and the connection relationship of the component includes:

[0090] Obtain the parameterizable code for each component in the clock tree prototype diagram, wherein each component has corresponding parameterizable code;

[0091] Based on the connection relationship of the components, determine the first set of signal terminals in the clock tree prototype diagram that have connection relationships between components, and the second set of signal terminals in the clock tree prototype diagram that do not have connection relationships.

[0092] Based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals, the code corresponding to the clock tree prototype diagram is generated.

[0093] In one embodiment, generating the code corresponding to the clock tree prototype diagram based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals includes:

[0094] The first signal terminal set is converted into code based on the parameterizable code;

[0095] Determine the component to which each signal terminal in the second set of signal terminals belongs;

[0096] The code of each signal terminal is obtained from the parameterizable code of the component to which each signal terminal belongs, thus obtaining the code of the second set of signal terminals;

[0097] By combining the code of the first signal terminal set and the code of the second signal terminal set, the code corresponding to the clock tree prototype diagram is obtained.

[0098] Referring to FIG11, it is a schematic diagram of a preferred embodiment of the electronic device 1 of this application.

[0099] The electronic device 1 includes, but is not limited to, a memory 11, a processor 12, a display 13, and a communication interface 14. The electronic device 1 can connect to a network via the communication interface 14. The network can be an intranet, the Internet, a Global System for Mobile communication (GSM), a Wideband Code Division Multiple Access (WCDMA) network, a 4G network, a 5G network, Bluetooth, Wi-Fi, a voice communication network, or other wireless or wired networks.

[0100] The memory 11 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as the hard disk or memory of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. of the electronic device 1. Of course, the memory 11 may include both the internal storage unit and the external storage device of the electronic device 1. In this embodiment, the memory 11 is typically used to store the operating system and various application software installed on the electronic device 1, such as the program code of the code generation program 10 based on the chip clock tree prototype diagram. In addition, the memory 11 can also be used to temporarily store various types of data that have been output or will be output.

[0101] In some embodiments, processor 12 may be a central processing unit (CPU), controller, microcontroller, microprocessor, or other data processing chip. Processor 12 is typically used to control the overall operation of the electronic device 1, such as performing data interaction or communication-related control and processing. In this embodiment, processor 12 is used to run program code stored in memory 11 or process data, for example, running program code from code generation program 10 based on a chip clock tree prototype.

[0102] The display 13 may be referred to as a display screen or display unit. In some embodiments, the display 13 may be an LED display, a liquid crystal display, a touch liquid crystal display, or an organic light-emitting diode (OLED) touch screen, etc. The display 13 is used to display information processed in the electronic device 1 and to display a visual working interface.

[0103] The communication interface 14 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface), which is typically used to establish a communication connection between the electronic device 1 and other electronic devices.

[0104] Figure 11 shows only an electronic device 1 with components 11-14 and a code generation program 10 based on a chip clock tree prototype diagram. However, it should be understood that it is not required to implement all the components shown, and more or fewer components may be implemented instead.

[0105] In the above embodiments, when the processor 12 executes the code generation program 10 based on the chip clock tree prototype diagram stored in the memory 11, it can perform the following steps:

[0106] Obtain the clock tree prototype diagram of the code to be generated;

[0107] Analyze the clock tree prototype diagram to obtain the types of components and their connection relationships.

[0108] Based on the type of the component and the connection relationship of the component, generate the code corresponding to the clock tree prototype diagram.

[0109] The storage device can be the memory 11 of the electronic device 1, or it can be other storage devices that are communicatively connected to the electronic device 1.

[0110] For a detailed description of the above steps, please refer to Figure 10, which shows the functional block diagram of the code generation device 100 based on the chip clock tree prototype diagram, and Figure 1, which shows the flowchart of the code generation method based on the chip clock tree prototype diagram.

[0111] Furthermore, this application also proposes a computer-readable storage medium, which can be non-volatile or volatile. This computer-readable storage medium can be any one or any combination of several of the following: hard disk, multimedia card, SD card, flash memory card, SMC, read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, etc. The computer-readable storage medium includes a data storage area and a program storage area. The program storage area stores a code generation program 10 based on a chip clock tree prototype diagram. When executed by a processor, the code generation program 10 based on the chip clock tree prototype diagram performs the following operations:

[0112] Obtain the clock tree prototype diagram of the code to be generated;

[0113] Analyze the clock tree prototype diagram to obtain the types of components and their connection relationships.

[0114] Based on the type of the component and the connection relationship of the component, generate the code corresponding to the clock tree prototype diagram.

[0115] The specific implementation of the computer-readable storage medium in this application is largely the same as the specific implementation of the code generation method based on the chip clock tree prototype diagram described above, and will not be repeated here.

[0116] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, apparatus, article, or method. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0117] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, electronic device, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0118] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A code generation method based on a chip clock tree prototype diagram, characterized in that, The method includes: obtaining a clock tree prototype diagram of the code to be generated; parsing the clock tree prototype diagram to obtain the types of components and their connection relationships; generating code corresponding to the clock tree prototype diagram based on the types of components and their connection relationships; wherein, generating code corresponding to the clock tree prototype diagram based on the types of components and their connection relationships includes: obtaining parameterizable code for each component in the clock tree prototype diagram, wherein each component has corresponding parameterizable code; determining a first set of signal terminals with connection relationships between components in the clock tree prototype diagram, and a second set of signal terminals without connection relationships in the clock tree prototype diagram, based on the connection relationships of the components. The process involves generating code corresponding to the clock tree prototype diagram based on the parameterizable code, the first signal terminal set, and the second signal terminal set. This includes: converting the first signal terminal set into code based on the parameterizable code; determining the component to which each signal terminal in the second signal terminal set belongs; obtaining the code for each signal terminal from the parameterizable code of the component to which each signal terminal belongs, thus obtaining the code for the second signal terminal set; and combining the code for the first signal terminal set and the code for the second signal terminal set to obtain the code corresponding to the clock tree prototype diagram.

2. The code generation method based on chip clock tree prototype diagram as described in claim 1, characterized in that, Before obtaining the clock tree prototype diagram of the code to be generated, the method further includes: receiving an editing instruction based on the chip IP clock requirement input; calculating the component types and number of components required to construct the clock tree prototype diagram according to the editing instruction; and constructing the clock tree prototype diagram according to the required component types and number of components.

3. The code generation method based on a chip clock tree prototype diagram as described in claim 1 or 2, characterized in that, The components include at least one of the following: a glitch-free clock selector component, a clock selector component, a clock gating unit component, a clock divider component, and a clock source phase-locked loop component.

4. The code generation method based on a chip clock tree prototype diagram as described in claim 1, characterized in that, After generating the code corresponding to the clock tree prototype diagram, the method further includes: compiling the code corresponding to the clock tree prototype diagram using a preset code compilation tool.

5. A code generation device based on a chip clock tree prototype diagram, characterized in that, The device includes: an acquisition module for acquiring a clock tree prototype diagram of the code to be generated; a parsing module for parsing the clock tree prototype diagram to obtain the types of components and their connection relationships in the clock tree prototype diagram; and a generation module for generating code corresponding to the clock tree prototype diagram based on the types of components and their connection relationships. The step of generating code corresponding to the clock tree prototype diagram based on the types of components and their connection relationships includes: acquiring parameterizable code for each component in the clock tree prototype diagram, wherein each component has corresponding parameterizable code; determining, based on the connection relationships of the components, a first set of signal terminals with connection relationships between components in the clock tree prototype diagram, and a set of signal terminals without connection relationships in the clock tree prototype diagram. The second set of signal terminals in the relationship; generating the code corresponding to the clock tree prototype diagram based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals; the step of generating the code corresponding to the clock tree prototype diagram based on the parameterizable code, the first set of signal terminals, and the second set of signal terminals includes: converting the first set of signal terminals into the code of the first set of signal terminals based on the parameterizable code; determining the component to which each signal terminal in the second set of signal terminals belongs; obtaining the code of each signal terminal from the parameterizable code of the component to which each signal terminal belongs, to obtain the code of the second set of signal terminals; combining the code of the first set of signal terminals and the code of the second set of signal terminals to obtain the code corresponding to the clock tree prototype diagram.

6. The code generation device based on a chip clock tree prototype diagram as described in claim 5, characterized in that, The components include at least one of the following: a glitch-free clock selector component, a clock selector component, a clock gating unit component, a clock divider component, and a clock source phase-locked loop component.

7. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor, when executing the program stored in the memory, implements the steps of the code generation method based on the chip clock tree prototype diagram as described in any one of claims 1 to 4.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the code generation method based on the chip clock tree prototype diagram as described in any one of claims 1 to 4.

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