Dual soldering method for ultra-high density first level interconnects

Abstract

An apparatus comprising an integrated circuit (IC) package having at least one solder joint pad; a die having at least one solder joint pad, wherein the die is joined to the IC package by at least one solder joint between the at least one solder joint pad of the die and the at least one solder joint pad of the IC package; and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

Description

Background Technology

[0001] As increasing demands are placed on microelectronic packaging technologies to reduce package footprint and thickness, interconnect dimensions must also shrink. With the reduction in first-level interconnect (FLI) pitch for building ultra-high-density architectures, challenges arise in bonding integrated circuit dies to the package substrate. One issue is the incidence of solder bridging. Another issue is the low yield of completed packages due to incomplete solder joint formation (e.g., non-contact openings) associated with warpage between the bonding pads on the two dies and the substrate during thermocompression bonding operations. Attached Figure Description

[0002] Embodiments of this disclosure will be more fully understood from the specific description given below and from the accompanying figures of various embodiments of this disclosure; however, it should not be construed as limiting this disclosure to the specific embodiments, but is intended for explanation and understanding only.

[0003] Figure 1 The illustration shows a cross-sectional view of a first embodiment of a package according to some embodiments of the present disclosure, which, according to some embodiments of the present disclosure, has a dual-solder joint embodiment with underfill between the die and the substrate.

[0004] Figure 2A-2G The illustrations show cross-sectional views of a first embodiment of a method for manufacturing a package according to some embodiments of the present disclosure, the package having a dual-solder joint embodiment with underfill between a die and a substrate.

[0005] Figures 3A-3F The illustrations show cross-sectional views of a second embodiment of a method for manufacturing a package according to some embodiments of the present disclosure, the package having a dual-solder joint embodiment with underfill between a die and a substrate.

[0006] Figure 4 The illustration shows a cross-sectional view of a second embodiment of a package according to some embodiments of the present disclosure, the package having a dual-solder joint embodiment without underfill between the die and the substrate.

[0007] Figures 5A-5D Cross-sectional views of methods for manufacturing a package according to some embodiments of the present disclosure are illustrated, the package having a dual-solder joint embodiment without underfill between the die and the substrate.

[0008] Figure 6 The illustration shows a package manufactured according to the disclosed method as part of a system-on-a-chip (SoC) package in an implementation of a computing device according to some embodiments of the present disclosure, the package having a dual-solder joint embodiment between the die and the substrate. Detailed Implementation

[0009] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring embodiments of the present disclosure.

[0010] Here, the term "package" generally refers to a separate carrier having one or more dies, wherein the dies are attached to a package substrate and sealed for protection, and have integrated or wire-bonded interconnects between the die(s) and leads, pins, or protrusions on the external portion of the package substrate. A package may contain a single die or multiple dies providing a specific function. Packages are typically mounted on printed circuit boards for interconnection with other packaged integrated circuits (ICs) and discrete components to form larger circuits.

[0011] Here, the term "dielectric" generally refers to any number of non-conductive materials that make up the structure of the package substrate. For the purposes of this disclosure, the dielectric material may be incorporated into the IC package as a layer of a laminated film or as a resin molded on top of an IC die mounted on the substrate.

[0012] Here, the term "metallization" generally refers to a metal layer formed on top of the dielectric material of a package substrate. This metal layer is typically patterned to form metallic structures such as traces and bonding pads. Metallization of the package substrate can be confined to a single layer or comprised of multiple layers separated by multiple dielectric layers.

[0013] Here, the term "bonding pad" generally refers to the metallized structure that terminates integrated traces and vias in microelectronic packages and dies.

[0014] Here, the term "solder bump" generally refers to a solder layer formed on the bonding pads. The solder layer is usually circular in shape, hence the term "solder bump".

[0015] Here, the term "liquid" generally refers to the liquid state of a molten metal mixture (such as solder). Since solder melts within a certain temperature range, it does not have a specific melting point. The liquid state is the state in which the mixture is completely melted.

[0016] Here, the term "solid" generally refers to the solid state of a solid metal mixture (such as solder). As for the liquid state, since liquid mixtures solidify within a certain temperature range, there is no specific solidification temperature. The solidus temperature is the temperature at which the mixture completely solidifies.

[0017] Here, the term "metallurgy" generally refers to alloy composition. In this disclosure, "metallurgy" is used, for example, to refer to solder alloy composition.

[0018] This document discloses a method for touch and bonding dual solder metallurgy on a die and a package substrate, and a structure fabricated by the disclosed method. The method includes a touch and bonding process in which two solder layers are deposited on bonding pads of the die and the package substrate. The solder layers have different compositions having different liquidus temperatures. In some embodiments, the two solder layers are formed separately, including layers having a first liquidus temperature T. L1 The first solder layer of the solder composition is deposited on the die, and includes a second liquidus temperature (T0). L2 T L2 Greater than T L1 A second solder layer of the solder composition is deposited on the substrate. The solder layer is then bonded by placing bonding pads between the die and the substrate.

[0019] In some embodiments, two solder layers are formed sequentially on the bonding pads of the die or on the substrate. In some embodiments, a first solder layer is formed on the bonding pads of the substrate and then heated to a temperature in which an intermetallic compound (IMC) is formed between the material of the bonding pad (e.g., copper) and one or more metallic elements (e.g., tin) of the solder layer. The IMC has a melting point significantly higher than the liquidus temperatures of both solder components.

[0020] A second solder layer is formed on the bonding pads of the die. The bonding pads of the die and the substrate are juxtaposed. According to some embodiments, the juxtaposed bonding pads on the die and the substrate are brought into contact under pressure and heated. As an example, the die and the substrate are brought into contact using a thermocompression bonding (TCB) tool. The temperature is raised to a first (e.g., lower) liquidus temperature, where the first solder layer melts and reflows to form a partial solder joint between the bonding pads of the die and the substrate. According to an embodiment, the volume of solder contained in the first solder layer is relatively low compared to the volume of solder contained in the second solder layer. Therefore, the partial solder joint is small, and a temporary bond is formed between the die and the substrate. The temporary bond is used as a mechanical stabilizing unit to hold the die and the substrate together for further processing before a full solder joint is formed. Since the first temperature is too low to melt the second layer, the second solder layer remains as is.

[0021] As noted above, solder bridging frequently occurs when bonding (e.g., flip-chip bonding) dies and substrates using a high-density FLI architecture. In some embodiments, an underfill material is injected between the die and substrate and then cured to embed a portion of the solder joint within the underfill material. The embedded portion of the solder joint includes an unaltered second solder layer. In a subsequent operation, this portion of the solder joint is heated to a second liquidus temperature (T0). L2(1) or more, wherein the second solder layer melts and reflows to form a permanent solder joint between the die and the substrate bonding pads. During the reflow of the second solder layer, the melt is confined within a cavity in the surrounding underfill material, and the larger volume of liquid solder (relative to the volume of the first solder layer) cannot overflow into the nearby bonding pad pair. In this way, solder bridging is eliminated.

[0022] In an alternative embodiment, a second solder layer is formed on the bonding pads of the substrate. The second solder layer formed on each bonding pad can be in the shape of a ball or a bump. Typically, the height of the bump can vary by 10-20% in thickness on each bonding pad during formation. This variation can translate to a difference of as much as 10 micrometers on the solder bump. Although natural warping will occur in the die and substrate, the substrate and die remain flat if bonded in a TCB or similar tool. However, variations in bump height may result in some non-contact openings (NCOs) or failure to form solder joints between some bonding pad pairs.

[0023] To avoid variations in solder bump height, the solder bumps are flattened by pressing them down in a TCB tool, for example, thereby flattening the bumps to substantially equal height before subsequent bonding operations.

[0024] Throughout this specification and in the claims, the term “connected” means a direct connection, such as an electrical, mechanical, or magnetic connection between connected things, without any intermediate means.

[0025] The term “coupled” refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the connected things, or an indirect connection through one or more passive or active intermediate devices.

[0026] The terms “circuit” or “module” can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of “a,” “an,” and “the” include plural references. The meanings of “in” include “in” and “on”.

[0027] The vertical orientation is in the z-direction, and it is understood that the terms "top," "bottom," "above," and "below" refer to relative positions in the z-dimension in the usual sense. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figures.

[0028] The terms “basically,” “near,” “almost,” “in the vicinity,” and “approximately” generally refer to within + / - 10% of the target value (unless specifically specified). Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe ordinary objects merely indicates different instances of the same object being referred to, and is not intended to imply that the objects so described must be in a given order, whether temporal, spatial, ranked, or in any other way.

[0029] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0030] Views labeled "sectional," "side," and "plan" correspond to orthogonal planes within the Cartesian coordinate system. Therefore, sectional and side views are obtained in the xz plane, and plan views are obtained in the xy plane. Typically, the side view in the xz plane is a sectional view. Where appropriate, axis markings are used to indicate the orientation of the drawings.

[0031] Figure 1 The illustration shows a cross-sectional view of a first embodiment of a package 100 according to some embodiments of the present disclosure, the package 100 having a dual solder joint embodiment with underfill between a die and a substrate.

[0032] exist Figure 1 In this embodiment, package 100 includes a die 101 and a substrate 102. Solder joints 103 are located between and bonded to bonding pads 104 on the die 101 and bonding pads 105 on the substrate 102. Solder joints 103 are composed of a metallurgical (alloy) that may include, but is not limited to, metals such as tin, silver, copper, bismuth, zinc, indium, gold, aluminum, and germanium. In some embodiments, solder joints 103 include a tin concentration gradient between bonding pads 104 and 105. In some embodiments, solder joints 103 include a higher concentration of tin adjacent to bonding pads 104 on the die 101 than the concentration of tin adjacent to bonding pads 105 on the substrate 102.

[0033] In some embodiments, solder joint 103 includes a compositional gradient of gold concentration between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a certain concentration of gold adjacent to bonding pad 105, which is higher than the concentration of gold adjacent to bonding pad 104.

[0034] In some embodiments, solder joint 103 includes a gold concentration gradient between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a gold concentration adjacent to bonding pad 104 that is higher than the gold concentration adjacent to bonding pad 105.

[0035] In some embodiments, solder joint 103 includes a zinc concentration gradient between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a zinc concentration adjacent to bonding pad 104 that is higher than the zinc concentration adjacent to bonding pad 105.

[0036] In some embodiments, solder joint 103 includes a zinc concentration gradient between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a zinc concentration adjacent to bonding pad 105 that is higher than the zinc concentration adjacent to bonding pad 104.

[0037] In some embodiments, solder joint 103 includes a compositional gradient of aluminum concentration between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a certain concentration of aluminum adjacent to bonding pad 105, which is higher than the concentration of zinc adjacent to bonding pad 104.

[0038] In some embodiments, solder joint 103 includes a compositional gradient of aluminum concentration between bonding pad 104 and bonding pad 105. In some embodiments, solder joint 103 includes a certain concentration of aluminum adjacent to bonding pad 104, which is higher than the concentration of zinc adjacent to bonding pad 105.

[0039] In some embodiments, underfill 106 is located between die 101 and substrate 102. In some embodiments, solder joints 103 are embedded in underfill 106. Underfill 106 may comprise materials comprising a patented formulation used in products used in microelectronic packaging assemblies. Underfill 106 strengthens the solder bond between die 101 and substrate 102.

[0040] Figure 2A-2G The illustrations show cross-sectional views of a first embodiment of a method for manufacturing a package 100 according to some embodiments of the present disclosure, the package 100 having a dual-solder joint embodiment with underfill between a die and a substrate.

[0041] exist Figure 2A In the operation shown, a substrate 102 is received. In some embodiments, the substrate 102 includes a core 201, a dielectric 202, and bonding pads 105 embedded in the dielectric 202.

[0042] exist Figure 2BIn the operation shown, a first solder bump 203 is formed on the bonding pad 105. In some embodiments, the first solder bump 203 is formed by a deposition process, which is any of the following processes: electrodeless plating, electrolytic plating (electroplating), or paste printing. According to some embodiments, the first solder bump 203 is reflowed after the deposition process. In some embodiments, the first solder bump 203 comprises a first solder metallurgical composition. According to some embodiments, for example, the z-height of the as-deposited first solder bump 203 can vary by as much as 20%.

[0043] In some embodiments, the first solder metallurgical composition comprises a mixture containing any element of gold, aluminum, germanium, zinc, tin, bismuth, and indium. An exemplary composition of the first solder metallurgical composition may include 80% gold and 20% tin. A second example composition of the first solder metallurgical composition may include 95% zinc and 5% aluminum. Here, percentages are based on molar ratios. In some embodiments, the first solder bump 203 has a first liquidus line ranging from 280°C to 485°C. In some embodiments, the first liquidus line temperature (T0) of the first solder bump 203 is... L1 It depends on the composition of the first solder bump 203.

[0044] exist Figure 2C In the operation illustrated, the first solder bump 203 is compressed to reduce its z-height to a predetermined value. In some embodiments, the substrate 102 is mounted in a thermocompression bonding (TCB) tool and clamped between pressure plates. In some embodiments, the first solder bump 203 is flexible enough to be compressed without heat application. During compression, the substrate 102 remains flat, and the first solder bump 203 is substantially planarized with other solder bumps on the substrate 102. According to some embodiments, die bonding, such as flip-chip bonding, is facilitated because the likelihood of contact between a single solder bump on the substrate 102 and a bonding pad or bump on the die is significantly increased during die (chip) bonding in subsequent operations.

[0045] exist Figure 2D In the operation shown, the die 101 is received using a second solder bump 204 formed on the bonding pad 104 in an earlier operation. In some embodiments, the second solder bump 204 is deposited by one of electrodeless deposition, electrolytic plating, or paste printing. In some embodiments, the second solder bump 204 has a volume significantly smaller than that of the first solder bump 203. Figure 2D In the operation shown, die 101 is aligned with substrate 102 such that first solder bump 203 and solder bump 204 are aligned and juxtaposed. In some embodiments, die 101 and substrate 102 are mounted in a TCB tool.

[0046] In some embodiments, the second solder bump 204 includes a second solder metallurgical composition. In some embodiments, the second solder metallurgical composition includes metals such as, but not limited to, tin, silver, zinc, copper, bismuth, and indium. An exemplary composition of the second solder metallurgical composition may include 95.5% tin, 4% silver, and 0.5% copper. A second example composition of the second solder metallurgical composition may include 89% tin, 8% zinc, and 3% bismuth. Here, percentages are based on molar ratios. In some embodiments, the second solder bump 204 has a second liquidus line (T). L2 The temperature range is from 138°C to 227°C. In some embodiments, the second liquidus temperature depends on the composition of the second solder bump 204. In some embodiments, T L2 Less than T L1 .

[0047] exist Figure 2E In the operation shown, die 101 is pressed against substrate 102 so that the second solder bump 204 is abutted against the first solder bump 203. In some embodiments, this operation is performed in a TCB tool head. Die 101 and substrate 102 are compressed between heated plates. In some embodiments, the temperature of the plates is raised to a second liquidus temperature T. L2 or above, but below T L1 The second solder bump 204 is on T. L2 Location or T L2 The above liquefies and flows. In some embodiments, the platen temperature is sloping down to allow the second solder bump to resolidify.

[0048] In some embodiments, the second solder bump 204 reflows over the first solder bump 203, which does not melt during the operation. A metallic bond is formed between the first solder bump 203 and the second solder bump 204. In some embodiments, the relatively small volume of the second solder bump 204 creates a partial solder joint 205 without flowing to nearby solder bumps. In this way, solder bridging between nearby bonding pads is prevented or substantially mitigated. In some embodiments, the partial solder joint 205 is temporary and, in subsequent operations, acts as a pin to hold the die 101 to the substrate 102 before a permanent solder joint is formed by the reflow operation of the first solder bump 203 described below.

[0049] exist Figure 2FIn the operation shown, capillary bottom filler (CUF) 206 is introduced between die 101 and substrate 102. In some embodiments, CUF 206 is injected between die 101 and substrate 102. In some embodiments, CUF 206 is introduced between die 101 and substrate 102 via capillary action. Methods for introducing CUF 206 between die 101 and substrate 102 are known in the industry and can be employed to introduce CUF 206.

[0050] In some embodiments, the CUF 206 protects the solder joints and helps harden the bond between the die 101 and the substrate 102. According to some embodiments, the CUF 206 confines solder from the first solder bump 203 to prevent it from bridging into nearby solder bumps, as described below.

[0051] exist Figure 2G In the operation shown, the temperature of the pressure plate is raised to the first liquidus temperature T. L1 Or above. The first solder bump 203 is at T L1 Location or T L1 The solder liquefies and flows. Simultaneously, the second solder bump 204 liquefies. In some embodiments, the liquid solder from the second solder bump 204 mixes with the liquid solder from the first solder bump 203. In some embodiments, a composition gradient is formed during reflow, wherein elements in the first solder bump 203 have the highest concentration near the bonding pads 105 of the substrate 102, while having a decreasing concentration toward the bonding pads 104 of the die 101. Conversely, elements in the second solder bump 204 have the highest concentration near the bonding pads 105 of the die 101, while having a decreasing concentration toward the bonding pads 104 of the substrate 102. In some embodiments, the composition of the solder becomes homogenized during reflow.

[0052] Because the volume of the first solder bump 203 is larger than that of the second solder bump 204, solder bridges will normally occur in the absence of the CUF 206. In some embodiments, the CUF 206 confines the liquid solder from the molten first solder bump 203 to prevent lateral flow. In some embodiments, the solder bump 203 reflows and mixes with the solder bump 204, as described above, thereby forming a permanent solder joint 207. In some embodiments, the platen temperature is ramped down to allow the second solder bump to resolidify.

[0053] Figures 3A-3F The illustrations show cross-sectional views of a second embodiment of a method for manufacturing a package 100 according to some embodiments of the present disclosure, the package 100 having a dual-solder joint embodiment with underfill between a die and a substrate.

[0054] exist Figure 3A In the operation shown, a die 101 and a substrate 102 are received. The die 101 includes bonding pads 104, and the substrate 102 includes bonding pads 105.

[0055] exist Figure 3B In the operation shown, a first solder bump 203 is formed on the bonding pad 104 at the die 101. In some embodiments, the first solder bump 203 is formed by a deposition process, which is any of the following processes: electrodeless plating, electrolytic plating (electroplating), or paste printing.

[0056] exist Figure 3C In the operation shown, a second solder bump 204 is formed over the first solder bump 203. In some embodiments, the second solder bump 204 is formed by a deposition process, which is any of the processes of electrodeless plating, electrolytic plating (electroplating), or paste printing. In some embodiments, the second solder bump 204 has a relatively smaller volume than the first solder bump 203 to reduce the risk of solder bridging during reflow, as described above. In some embodiments, the composition of the first solder bump 203 and the second solder bump 204 is similar to that described above (e.g., Figure 2D )same.

[0057] exist Figure 3D In the operation shown, bonding pads 104 and 105 are juxtaposed to align the second solder bump 204 with the bonding pad 105 on the substrate. In some embodiments, die 101 and substrate 102 are mounted on a heated platen of the TCB tool head, with bonding pads 104 and 105 facing each other in preparation for bonding operations such as flip-chip bonding (C4). Die 101 and substrate 102 are pressed together such that the second solder bump 204 is pressed against the bonding pad 105 on the substrate. In some embodiments, the temperature of the TCB tool head is raised to a second liquidus temperature T. L2 This causes the second bonding pad 204 to liquefy and reflow. In some embodiments, solder from the second solder bump 204 flows over the bonding pad 105 and the first solder bump 203, thereby creating a partial solder joint between the first solder bump 203 and the bonding pad 205 on the substrate 102.

[0058] Because this portion of the solder joint is formed using the first solder bump 203, it may be relatively weak. However, this portion of the solder joint is temporary and will hold the die 101 firmly to the substrate 102 during subsequent operations.

[0059] exist Figure 3EIn the operation shown, CUF 206 is introduced. In some embodiments, CUF 206 is injected between die 101 and substrate 102. In some embodiments, CUF 206 is introduced between die 101 and substrate 102 via capillary action. Methods for introducing CUF 206 between die 101 and substrate 102 are known in the industry and can be employed to introduce CUF 206.

[0060] In some embodiments, the CUF 206 protects the solder joints and helps harden the bond between the die 101 and the substrate 102, as described above. According to some embodiments, the CUF 206 confines solder from the first solder bump 203 to prevent it from bridging into nearby solder bumps, as described below.

[0061] exist Figure 3F In the operation shown, the temperature of the pressure plate rises to the first liquidus temperature T. L1 Or above. The first solder bump 203 is at T L1 Location or T L1 The solder liquefies and flows. Simultaneously, the second solder bump 204 melts and reflows. In some embodiments, the liquid solder from the second solder bump 204 mixes with the liquid solder from the first solder bump 203. In some embodiments, a composition gradient is formed during reflow, wherein the elements of the first solder bump 203 have the highest concentration near the bonding pads 104 at the die 101, while having a decreasing concentration towards the bonding pads 105 at the substrate 102. Conversely, the elements of the second solder bump 204 have the highest concentration near the bonding pads 105 at the substrate 102, while having a decreasing concentration towards the bonding pads 104 at the die 101. In some embodiments, the composition of the solder becomes homogenized during reflow.

[0062] Because the volume of the first solder bump 203 is larger than that of the second solder bump 204, solder bridges will normally occur in the absence of CUF 206. In some embodiments, CUF 206 confines the liquid solder from the molten first solder bump 203 to prevent lateral flow. In some embodiments, the solder bump 203 reflows and mixes with the solder bump 204, as described above, thereby forming a permanent solder joint 207. In some embodiments, the platen temperature is ramped down to allow the second solder bump to resolidify.

[0063] Figure 4 The illustration shows a cross-sectional view of a second embodiment of a package 400 according to some embodiments of the present disclosure, the package 400 having a dual solder joint embodiment without underfill between the die and the substrate.

[0064] exist Figure 4In the package 400, a die 101 and a substrate 102 are included. The die 101 includes bonding pads 104, and the substrate 102 includes bonding pads 105. Solder joints 401 are bonded between bonding pads 104 and 105. Solder joints 103 are composed of metallurgy, which may include, but is not limited to, metals such as tin, silver, copper, bismuth, zinc, indium, gold, aluminum, and germanium. In some embodiments, solder joints 103 include a tin concentration gradient between bonding pads 104 and 105. In some embodiments, solder joints 103 include a tin concentration adjacent to bonding pads 104 on the die 101 that is higher than the tin concentration adjacent to bonding pads 105 on the substrate 102.

[0065] In some embodiments, an intermetallic compound (IMC) is formed at the interface between the bonding pad 105 and the solder joint 103 on the substrate 102. In some embodiments, the IMC comprises copper and gold. In some embodiments, the IMC comprises copper and zinc. In some embodiments, the IMC comprises copper and silver. In some embodiments, the IMC comprises copper and bismuth. In some embodiments, the IMC comprises copper and tin. In some embodiments, the IMC comprises copper and indium. In some embodiments, the IMC comprises copper and gallium. In some embodiments, the IMC has a melting temperature exceeding 500°C.

[0066] Figures 5A-5D Cross-sectional views of methods for manufacturing a package 400 according to some embodiments of the present disclosure are illustrated, the package 400 having a dual-solder joint embodiment without underfill between a die and a substrate.

[0067] exist Figure 5A In the operation shown, a substrate 102 receives a first solder bump 203 deposited above bonding pads 105 in an earlier operation. In some embodiments, the first solder bump 203 is formed by a deposition process, which is any of electrodeless plating, electrolytic plating (e.g., electroplating), or paste printing. In some embodiments, the first solder bump 203 comprises a first solder metallurgical composition. In some embodiments, the first solder metallurgical composition comprises a mixture containing any of the elements gold, aluminum, germanium, zinc, tin, bismuth, and indium. An exemplary composition of the first solder metallurgical composition may include 80% gold and 20% tin. A second example composition of the first solder metallurgical composition may include 95% zinc and 5% aluminum. Here, percentages are based on molar ratios. In some embodiments, the first solder bump 203 has a first liquidus line ranging in temperature from 280°C to 485°C. In some embodiments, the first liquidus line temperature (T0) of the first solder bump 203 is... L1 It depends on the composition of the first solder bump 203.

[0068] In some embodiments, the solder bump 203 is compressed to the flatness (substantially flat profile) of the previous operation to reduce its z-height to a predetermined value. In some embodiments, the substrate 102 is mounted in a thermal compression bonding (TCB) tool and clamped between pressure plates. In some embodiments, the first solder bump 203 is flexible enough to be compressed without heat. During compression, the substrate 102 remains flat, and the first solder bump 203 is substantially planarized with other solder bumps on the substrate 102. According to some embodiments, die bonding, such as flip-chip bonding, is facilitated because the likelihood of contact between the individual solder bumps on the substrate 102 and the bonding pads or bumps on the die is greatly increased during die (chip) bonding in subsequent operations.

[0069] exist Figure 5B In the operation shown, the substrate 102 is heated to T L1 Intermetallic compound (IMC) 401 is formed at the following temperature. L1 This is the liquidus temperature of the first solder bump 203. The IMC is formed by thermally driven interdiffusion of atoms at the interface between the two metals. In some embodiments, the IMC 401 is formed from the first solder bump 203 by a temperature-cycled substrate 102 mounted in a TCB tool. In some embodiments, interdiffusion of copper atoms at the interface from the bonding pad 105 to the first solder bump 203 contributes to the formation of the IMC 401.

[0070] In some embodiments, IMC 401 comprises copper and gold. In some embodiments, IMC comprises copper and zinc. In some embodiments, IMC 401 comprises copper and silver. In some embodiments, IMC 401 comprises copper and bismuth. In some embodiments, IMC comprises copper and tin. In some embodiments, IMC 401 comprises copper and indium. In some embodiments, IMC 401 has a melting temperature exceeding 500°C.

[0071] exist Figure 5CIn the operation shown, a die 101 is received. In some embodiments, the die 101 is bumped using a second solder bump 204. In some embodiments, the second solder bump 204 is formed by a deposition process, which is any of the following processes: electrodeless plating, electrolytic plating (e.g., electroplating), or paste printing. In some embodiments, the second solder bump 204 includes a second solder metallurgical composition. In some embodiments, the second solder metallurgical composition includes metals such as, but not limited to, tin, silver, zinc, copper, bismuth, and indium. An exemplary composition of the second solder metallurgical composition may include 95.5% tin, 4% silver, and 0.5% copper. A second example composition of the second solder metallurgical composition may include 89% tin, 8% zinc, and 3% bismuth. All percentages are based on molar ratios. In some embodiments, the second solder bump 204 has a second liquidus line (T). L2 The temperature range of the second liquidus temperature is from 138°C to 227°C. In some embodiments, the second liquidus temperature depends on the composition of the second solder bump 204.

[0072] In some embodiments, die 101 is aligned with substrate 102, and second solder bump 204 is juxtaposed with IMC 401. In some embodiments, die 101 and substrate 102 are mounted in a heated TCB tool head. In some embodiments, second solder bump 204 is positioned close to IMC 401 to prepare for solder bonding.

[0073] exist Figure 5D In the operation shown, solder joint 402 is formed. In some embodiments, this is achieved by raising the TCB head temperature to the liquidus temperature T of the second solder bump 204. L2 The second solder bump 204 is reflowed at a temperature of 500°C or above. In some embodiments, since the IMC 401 has a melting point above 500°C, the solder joint 402 is a permanent solder joint and does not melt during the reflow of the second solder bump 204. In some embodiments, the solder bump 204 has a volume small enough to form a meniscus above the IMC 401 when liquefied, and does not flow laterally, and remains above the IMC 401. In some embodiments, no components such as... Figure 3E and 3F Underfillers such as CUF 206 are used because they essentially reduce the risk of weld bridge formation.

[0074] Figure 6 The illustration shows a package manufactured according to the disclosed method as part of a system-on-a-chip (SoC) package in an implementation of a computing device according to some embodiments of the present disclosure, the package having a dual-solder joint embodiment between the die and the substrate.

[0075] Figure 6The illustration shows a block diagram of an embodiment of a mobile device in which a flat surface interface connector can be used. In some embodiments, computing device 600 represents a mobile computing device, such as a computing tablet device, a mobile phone or smartphone, a wirelessly enabled e-reader, or other wireless mobile device. It will be understood that some components are generally shown, but not all components of such a device are shown in computing device 600.

[0076] In some embodiments, computing device 600 includes a first processor 610. Various embodiments of this disclosure may also include a network interface, such as a wireless interface, within 670 to allow system embodiments to be incorporated into wireless devices, such as cellular phones or personal digital assistants.

[0077] In one embodiment, processor 610 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. Processing operations performed by processor 610 include the execution of an operating platform or operating system on which application and / or device functions are performed. Processing operations include operations related to I / O (input / output) utilizing a human user or other devices, operations related to power management, and / or operations related to connecting computing device 600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0078] In one embodiment, computing device 600 includes an audio subsystem 620, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, encoders / decoders) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone outputs, and microphone inputs. Devices for such functionality may be integrated into or connected to computing device 600. In one embodiment, a user interacts with computing device 600 by providing audio commands, which are received and processed by processor 610.

[0079] Display subsystem 630 represents hardware (e.g., display device) and software (e.g., driver) components that provide a user with visual and / or tactile displays to interact with computing device 600. Display subsystem 630 includes display interface 632, which includes a specific screen or hardware device used to provide a display to the user. In one embodiment, display interface 632 includes logic decoupled from processor 610 to perform at least some display-related processing. In one embodiment, display subsystem 630 includes a touchscreen (or touchpad) device that provides both output and input to the user.

[0080] I / O controller 640 represents hardware devices and software components relating to user interaction. I / O controller 640 is operable to manage hardware that is part of audio subsystem 620 and / or display subsystem 630. Additionally, I / O controller 640 illustrates connection points for attached devices that connect to computing device 600 through which a user can interact with the system. For example, devices that can be attached to computing device 600 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, or other I / O devices for use with specific applications such as card readers or other devices.

[0081] As mentioned above, the I / O controller 640 can interact with the audio subsystem 620 and / or the display subsystem 630. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 600. Additionally, audio output can be provided in place of or in addition to display output. In another example, if the display subsystem 630 includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 640. Additional buttons or switches may also be present on the computing device 600 to provide I / O functionality managed by the I / O controller 640.

[0082] In one embodiment, the I / O controller 640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the computing device 600. Inputs may be part of direct user interaction, as well as providing environmental inputs to the system to affect its operation (such as filtering for noise, adjusting the display for brightness detection, applying flash or other features to the camera).

[0083] In one embodiment, computing device 600 includes power management 650, which manages battery power usage, battery charging, and features related to power-saving operation. Memory subsystem 660 includes memory devices for storing information in computing device 600. The memory may include non-volatile (its state does not change if power to the memory device is interrupted) and / or volatile (its state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to performing applications and functions of computing device 600.

[0084] Elements of the embodiments may also be provided as machine-readable media (e.g., memory 660) for storing computer-executable instructions. Machine-readable media (e.g., memory 660) may include, but are not limited to, flash memory, optical disc, CD-ROM, DVD-ROM, RAM, EPROM, EEPROM, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of this disclosure may be downloaded as a computer program (e.g., BIOS) that can be transmitted from a remote computer (e.g., server) to a requesting computer (e.g., client) via a communication link (e.g., modem or network connection) by means of data signals.

[0085] The connection via network interface 670 includes hardware devices (e.g., wireless and / or wired connectors and / or communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 600 to communicate with external devices. Computing device 600 can be a standalone device, such as other computing devices, wireless access points or base stations, and peripheral devices such as headsets, printers or other devices.

[0086] Network interface 670 can include various types of connections. In general, the illustration shows computing device 600 having cellular connectivity 672 and wireless connectivity 674. Cellular connectivity 672 generally refers to a cellular network connection provided by a wireless operator, such as via GSM (Global System for Mobile Communications) or its variations or derivatives, CDMA (Code Division Multiple Access) or its variations or derivatives, TDM (Time Division Multiplexing) or its variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 674 refers to a non-cellular wireless connection and may include personal area networks (such as Bluetooth, NFC, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMax) or other wireless communications.

[0087] Peripheral connectivity 680 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for peripheral connectivity. It will be understood that computing device 600 can be a peripheral device to other computing devices (“to” 682), and has peripheral devices connected to it (“from” 684). Computing device 600 typically has a “dock” connector to connect to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on computing device 600. Additionally, the dock connector may allow computing device 600 to connect to certain peripheral devices that allow computing device 600 to control content output, for example, to an audiovisual system or other system.

[0088] In addition to patented mating connectors or other patented connection hardware, computing device 600 can be peripherally connected 680 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a variety of different hardware interfaces), display ports including Micro DisplayPort (MDP), High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0089] References to "embodiment," "one embodiment," "some embodiments," or "other embodiments" in the specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "may," or "can" be included, then including that particular component, feature, structure, or characteristic is not required. If the specification or claims refer to "a" or "one" element, it does not mean that only one of the elements exists. If the specification or claims refer to "additional" element, it does not exclude the existence of more than one additional element.

[0090] Furthermore, specific features, structures, functions, or characteristics can be combined in one or more embodiments in any suitable manner. For example, a first embodiment can be combined with a second embodiment anywhere that the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0091] Although this disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of this disclosure are intended to encompass all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0092] Furthermore, for the sake of brevity of description and discussion, well-known power / ground connections for integrated circuit (IC) chips and other components may or may not be shown in the presented figures, and so as not to obscure this disclosure. Additionally, arrangements may be shown in block diagram form to avoid obscuring this disclosure, also taking into account the fact that the details of the implementation of such block diagram arrangements are highly dependent on the platform within which this disclosure is to be implemented (i.e., such details should be entirely within the view of those skilled in the art). In setting forth specific details (e.g., circuits) to describe exemplary embodiments of this disclosure, it should be apparent to those skilled in the art that this disclosure can be practiced without these specific details or with variations thereof. This description is therefore to be regarded as illustrative rather than restrictive.

[0093] The following examples relate to other embodiments. The details in the examples can be used anywhere in one or more embodiments. All optional features of the apparatus described herein can also be implemented with respect to a method or process.

[0094] Example 1 is an apparatus comprising: an integrated circuit (IC) package having at least one solder bonding pad; a die having at least one solder bonding pad, wherein the die is bonded to the IC package via at least one solder joint between at least one bonding pad of the die and at least one bonding pad of the IC package; and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

[0095] Example 2 includes all the features of Example 1, wherein the first metallurgy includes one of the following: gold, aluminum, germanium, zinc, tin, bismuth, or indium.

[0096] Example 3 includes all the features of Example 1, wherein the second metallurgy includes one of the following: tin, silver, zinc, copper, bismuth, or indium.

[0097] Example 4 includes all the features of any one of Examples 1 to 3, wherein at least one solder joint includes a composition gradient, the composition gradient including a higher concentration of tin near at least one bonding pad of the die than near at least one bonding pad of the IC package.

[0098] Example 5 includes all the features of any one of Examples 1 to 3, wherein at least one solder joint includes a composition gradient, the composition gradient including a higher concentration of tin near at least one substrate bonding pad of the IC package than near at least one bonding pad of the die.

[0099] Example 6 includes all the features of any of Examples 1 to 5, wherein the protrusion is above at least one bonding pad of the IC package, and wherein the top of the protrusion is substantially flat.

[0100] Example 7 includes all the features of Example 6, wherein the protrusion comprises an intermetallic compound, which includes any one of gold, aluminum or germanium.

[0101] Example 8 is a system including a memory and a processor coupled to the memory, the processor comprising: an integrated circuit (IC) package having at least one solder joint pad; a die having at least one solder joint pad, wherein the die is bonded to the IC package via at least one solder joint between at least one solder joint pad of the die and at least one solder joint pad of the IC package; and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metal and a second metal, wherein the processor is wirelessly coupled to an external device.

[0102] Example 9 includes all the features of Example 8, wherein one or more solder joints include an intermetallic compound above the bonding pads of the IC package substrate, the intermetallic compound including one of copper and tin.

[0103] Example 10 includes all the features of Example 8 or 9, wherein at least one solder joint includes a composition gradient, which includes a higher concentration of tin near at least one bonding pad on the die than near at least one bonding pad on the IC package.

[0104] Example 11 includes all the features of Example 8 or 9, wherein at least one solder joint includes a composition gradient, which includes a higher concentration of tin near at least one bonding pad of the IC package than near at least one bonding pad of the die.

[0105] Example 12 includes all the features of any one of Examples 8 to 11, wherein the first metallurgy includes one of the following: gold, aluminum, germanium, zinc, tin, bismuth or indium.

[0106] Example 13 includes all the features of any one of Examples 8 to 11, wherein the second metallurgy includes one of the following: tin, silver, zinc, copper, bismuth, or indium.

[0107] Example 14 is an IC package comprising: at least one solder bonding pad; a die having at least one solder bonding pad, wherein the die is bonded to the IC package via at least one solder joint between the solder bonding pad of the die and the solder bonding pad of the IC package, wherein the at least one solder joint includes a first portion adjacent to a second portion, wherein the first portion has a substantially flat profile, and wherein the first portion includes a first metallurgy, and the second portion includes a second metallurgy; and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint includes the first metallurgy and the second metallurgy.

[0108] Example 15 includes all the features of Example 14, wherein the first portion of the solder joint has a substantially flat profile and includes an intermetallic compound, and wherein the intermetallic compound includes any one of the following: gold, silver, copper, aluminum, zinc, bismuth, tin, indium, germanium.

[0109] Example 16 is a method comprising: aligning a die with an IC package for bonding, wherein the die is pressed against the IC package, wherein a first bonding pad on the die is juxtaposed over a second bonding pad on the IC package, and including an interface between a first layer having a first solder metallurgy and a second layer having a second solder metallurgy between the first bonding pad on the die and the second bonding pad on the IC package, wherein the first layer is adjacent to the first bonding pad and the second layer is adjacent to the second bonding pad; reflowing the first layer to form a partial solder joint between the first and second bonding pads; and reflowing the second layer to form a complete solder joint between the first and second bonding pads, wherein the second reflow temperature is higher than the first reflow temperature.

[0110] Example 17 includes all the features of Example 16, wherein the liquidus temperature of the first layer is lower than that of the second layer.

[0111] Example 18 includes all the features of Example 16 or 17, wherein aligning the die with the IC package substrate includes: depositing a first layer over a first bonding pad, depositing a second layer over a second bonding pad, flattening the second layer, placing the first bonding pad over the second bonding pad, and pressing the first bonding pad onto the second bonding pad.

[0112] Example 19 includes all the features of any one of Examples 16 to 18, wherein aligning the die with the IC package includes: depositing a first layer over a first bonding pad, depositing a second layer over a second bonding pad, flattening the second layer, forming a saturated intermetallic compound between the second layer and the second bonding pad, juxtaposing the first bonding pad over the second bonding pad, and pressing the first bonding pad against the second bonding pad.

[0113] Example 20 includes all the features of any one of Examples 16 to 19, wherein aligning the die with the IC package includes: depositing a first layer over a first bonding pad, depositing a second layer over a second bonding pad, flattening the second layer, placing the first bonding pad over the second bonding pad, and pressing the first bonding pad against the second bonding pad.

[0114] Example 21 includes all the features of any of Examples 16 to 20, wherein reflowing the first layer to form a partial solder joint between the first bonding pad and the second bonding pad includes: reflowing the first layer at a first reflow temperature.

[0115] Example 22 includes all the features of any of Examples 16 to 21, wherein reflowing the second layer to form a complete solder joint between the first bonding pad and the second bonding pad includes: reflowing the second layer at a second reflow temperature, wherein the second reflow temperature is higher than the first reflow temperature.

[0116] Example 23 includes all the features of any one of Examples 16 to 22, and further includes: injecting capillary underfill material between the die and the IC packaging substrate to embed a portion of the solder joint, and curing the capillary underfill material.

[0117] Example 24 includes all the features of any of Examples 20 to 23, wherein the deposition of a second layer over the second bonding pad includes one of: electrodeless plating, electrolytic plating, or paste printing.

[0118] Example 25 includes all the features of any of Examples 16 to 24, wherein pressing the first bonding pad onto the second bonding pad includes: pressing the die onto the IC package substrate in a thermoforming bonding tool.

[0119] An abstract is provided, which will allow the reader to ascertain the features and essence of the disclosed technology. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are incorporated into the detailed description in such a manner that each claim stands alone as a separate embodiment.

Claims

1. An integrated circuit (IC) packaging substrate, comprising: At least one first bonding pad; A die including at least one second bonding pad, wherein the die is bonded to the IC package substrate via at least one solder joint between the first bonding pad and the second bonding pad. as well as The bottom filler material between the IC packaging substrate and the die. The solder joint is embedded in the underfill material, and the solder joint includes a first composition gradient and a second composition gradient across its thickness. The first composition gradient includes a higher concentration of tin adjacent to the first bonding pad and a lower concentration of tin adjacent to the second bonding pad. The second composition gradient includes a higher concentration of either gold or zinc adjacent to the second bonding pad and a lower concentration of either gold or zinc adjacent to the first bonding pad. An intermetallic compound (IMC) is formed at the interface between the first bonding pad and the solder joint, wherein the intermetallic compound (IMC) has a melting temperature exceeding 500°C.

2. The IC packaging substrate of claim 1, wherein the second component gradient includes a gold gradient and the solder joint further includes silver and copper.

3. The IC packaging substrate of claim 1, wherein the second composition gradient includes a gold gradient and the solder joint further includes zinc and bismuth.

4. The IC packaging substrate according to any one of claims 1 to 3, wherein the second composition gradient comprises a zinc gradient and the solder joint further comprises aluminum.

5. The IC packaging substrate according to any one of claims 1 to 3, wherein the second composition gradient comprises a zinc gradient and the solder joint further comprises bismuth.

6. The IC packaging substrate according to claim 5, wherein the intermetallic compound (IMC) comprises any one of gold, silver, copper, aluminum, zinc, bismuth, tin, indium, or germanium.

7. A system comprising: Memory; as well as A processor coupled to the memory, the processor comprising: An integrated circuit (IC) packaging substrate, comprising at least one first bonding pad; A die including at least one second bonding pad, wherein the die is bonded to the IC package substrate via at least one solder joint between the first bonding pad and the second bonding pad; and The bottom filler material between the IC packaging substrate and the die. The solder joint is embedded in the underfill material, and the solder joint includes a first composition gradient and a second composition gradient across its thickness. The first composition gradient includes a higher concentration of tin adjacent to the first bonding pad and a lower concentration of tin adjacent to the second bonding pad. The second composition gradient includes a higher concentration of either gold or zinc adjacent to the second bonding pad and a lower concentration of either gold or zinc adjacent to the first bonding pad. An intermetallic compound (IMC) is formed at the interface between the first bonding pad and the solder joint, wherein the intermetallic compound (IMC) has a melting temperature exceeding 500°C.

8. The system of claim 7, wherein the second component gradient comprises a gold gradient and the solder joint further comprises silver and copper.

9. The system of claim 7, wherein the second component gradient comprises a gold gradient and the solder joint further comprises zinc and bismuth.

10. The system of claim 7, wherein the second component gradient comprises a zinc gradient and the solder joint further comprises aluminum.

11. The system according to any one of claims 7 to 10, wherein the second component gradient comprises a zinc gradient and the solder joint further comprises bismuth.

12. The system according to any one of claims 7 to 10, wherein the intermetallic compound (IMC) comprises any one of gold, silver, copper, aluminum, zinc, bismuth, tin, indium, or germanium.

13. An IC packaging substrate, comprising: At least one first bonding pad; A die including at least one second bonding pad, wherein the die is bonded to the IC package substrate via at least one solder joint between the first and second bonding pads of the IC package substrate, wherein the solder joint includes a first composition gradient and a second composition gradient across the thickness of the solder joint, the first composition gradient including a higher concentration of one of gold or zinc adjacent to the first bonding pad and a lower concentration of one of gold or zinc adjacent to the second bonding pad, and the second composition gradient including a higher concentration of tin adjacent to the second bonding pad and a lower concentration of tin adjacent to the first bonding pad; and The bottom filler material between the IC packaging substrate and the die. The solder joints are embedded in the underfill material, and An intermetallic compound (IMC) is formed at the interface between the first bonding pad and the solder joint, wherein the intermetallic compound (IMC) has a melting temperature exceeding 500°C.

14. The IC packaging substrate of claim 13, wherein the second composition gradient comprises a gold gradient and the solder joint further comprises silver and copper.

15. A method for manufacturing an IC package, comprising: Align the die with the IC package for bonding, wherein: The die is pressed onto the IC package, wherein a first bonding pad on the die is positioned above a second bonding pad on the IC package; and The interface of a first layer having a first solder metallurgy and a second layer having a second solder metallurgy is located between a first bonding pad on the die and a second bonding pad on the IC package, wherein the first layer is adjacent to the first bonding pad and the second layer is adjacent to the second bonding pad. The first layer is reflowed to form partial solder joints between the first bonding pad and the second bonding pad; and The second layer is reflowed to form a complete solder joint between the first and second bonding pads, wherein the second reflow temperature is higher than the first reflow temperature. The liquidus temperature of the first layer is lower than that of the second layer; The reflowing of the first layer to form a partial solder joint between the first bonding pad and the second bonding pad includes reflowing the first layer at a first reflow temperature; and The reflowing of the second layer to form a complete solder joint between the first and second bonding pads includes reflowing the second layer at a second reflow temperature, wherein the second reflow temperature is higher than the first reflow temperature, further comprising: An intermetallic compound (IMC) is formed at the interface between the first bonding pad and the solder joint, wherein the intermetallic compound (IMC) has a melting temperature exceeding 500°C.

16. The method for fabricating an IC package according to claim 15, wherein aligning the die with the IC package substrate comprises: Deposit the first layer on the first bonding pad; Deposit the second layer on the second bonding pad; Make the second layer flat; The first bonding pad is placed juxtaposed above the second bonding pad; and Press the first bonding pad onto the second bonding pad.

17. The method for fabricating an IC package according to claim 16, wherein aligning the die with the IC package comprises: The first layer is deposited over the first bonding pad; Deposit the second layer over the second bonding pad; Make the second layer flat; A saturated intermetallic compound is formed between the second layer and the second bonding pad; The first bonding pad is placed juxtaposed above the second bonding pad; and Press the first bonding pad onto the second bonding pad.

18. The method for fabricating an IC package according to any one of claims 15 to 17, wherein aligning the die with the IC package comprises: The first layer is deposited over the first bonding pad; Deposit the second layer over the second bonding pad; Make the second layer flat; The first bonding pad is placed juxtaposed above the second bonding pad; and Press the first bonding pad onto the second bonding pad.

19. The method for manufacturing an IC package according to any one of claims 15 to 17, further comprising: A capillary bottom filler material is injected between the die and the IC packaging substrate to embed the partial solder joints; and The filler material at the bottom of the capillary tube is cured.

20. The method for fabricating an IC package according to claim 18, wherein depositing the second layer over the second bonding pad comprises one of electrodeless plating, electrolytic plating, or paste printing.

21. The method for making an IC package of any of claims 15-17, wherein pressing the first bond pad to the second bond pad comprises: The die is pressed onto the IC package substrate in a thermoforming tool.

Images