Apparatus and method for multiplying, summing and accumulating sets of packed bytes

Abstract

This application provides apparatus and methods for multiplying, summing, and accumulating multiple groups of compressed bytes. An apparatus and method for performing multiplication, addition, inversion, sign extension, and accumulation of compressed bytes. For example, one embodiment of the processor includes: a decoder for decoding an instruction to generate a decoded instruction including an opcode and a plurality of operands identifying a plurality of compressed data source registers and a compressed data destination register; a first source register for storing a first plurality of compressed signed bytes; a second source register for storing a second plurality of compressed signed bytes; and execution circuitry for executing the decoded instruction, the execution circuitry including: a multiplier circuitry for multiplying each compressed signed byte from the first source register with a corresponding compressed signed byte from the second source register to generate a plurality of temporary products; an adder circuitry for adding the plurality of temporary products to generate a plurality of temporary sums; an inverting and expanding circuitry for inverting each temporary sum in the temporary sums and expanding each temporary sum to a double-word sum; and an accumulator circuitry for adding each double-word sum in the double-word sums to a double word from a third source register to generate a final double-word result; and a compressed data destination register for storing the final double-word result in a specified data element location.

Description

Background Technology Technical Field

[0001] The embodiments of the present invention generally relate to the field of computer processors. More specifically, the embodiments relate to apparatus and methods for multiplying, summing, and accumulating multiple sets of compressed bytes.

[0002] Related technical descriptions

[0003] The instruction set, or instruction set architecture (ISA), is the programming-related part of a computer architecture, including primitive data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this article generally refers to macro-instructions—that is, instructions provided to the processor for execution—rather than micro-instructions or micro-operations—that is, the result of the processor's decoder decoding macro-instructions. Micro-instructions or micro-operations can be configured to instruct execution units on the processor to perform operations to implement the logic associated with macro-instructions.

[0004] An instruction set assembly (ISA) differs from a microarchitecture, which is a collection of processor design techniques used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Pentium 4 processor, Core TM (Core TM The processors, and several processors from Advanced Micro Devices, Inc. in Sunnyvale, California, implement nearly identical versions of the x86 instruction set (with some extensions added with newer versions), but with different internal designs. For example, the same register architecture of the ISA can be implemented differently in different microarchitectures using known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using register renaming mechanisms (e.g., using register alias tables (RATs), reorder buffers (ROBs), and retired register files). Unless otherwise specified, the phrases “register architecture,” “register file,” and “register” are used herein to refer to the register architecture, register file, and register as visible to the software / programmer and to how registers are specified in instructions. Where distinction is required, the adjectives “logical,” “architectural,” or “software visible” will be used to indicate registers / register files within a register architecture, while different adjectives will be used to specify registers (e.g., physical registers, reorder buffers, retired registers, register pools) within a given microarchitecture.

[0005] Multiplication-accumulation is a common digital signal processing operation that calculates the product of two numbers and adds that product to an accumulated value. Existing Single Instruction Multiple Data (SIMD) microarchitectures implement multiplication-accumulation by executing a sequence of instructions. For example, multiplication instructions followed by a 4-way addition, and then accumulation using the destination four-word data, can be used to perform multiplication-accumulation to produce two 64-bit saturated results. Attached Figure Description

[0006] A better understanding of the present invention can be obtained from the following detailed embodiments, in conjunction with the accompanying drawings, wherein:

[0007] Figure 1A and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention;

[0008] Figures 2A-2C This is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0009] Figure 3 This is a block diagram of a register architecture according to an embodiment of the present invention; and

[0010] Figure 4A The diagram illustrates both an exemplary ordered fetch, decode, and de-fetch pipeline and an exemplary out-of-order release / execution pipeline for register renaming, according to an embodiment of the present invention.

[0011] Figure 4B This is a block diagram illustrating an exemplary embodiment of an ordered fetch, decode, and retire core to be included in a processor, and an exemplary out-of-order release / execution architecture core for register renaming, according to an embodiment of the present invention;

[0012] Figure 5A It is a block diagram of a single processor core and its connection to the interconnect network on the die;

[0013] Figure 5B The figure illustrates an embodiment of the present invention. Figure 5A An expanded diagram of the processor core in the image;

[0014] Figure 6 This is a block diagram of a single-core processor and a multi-core processor having an integrated memory controller and a graphics device according to embodiments of the present invention;

[0015] Figure 7 The figure shows a block diagram of a system according to an embodiment of the present invention;

[0016] Figure 8 The figure shows a block diagram of a second system according to an embodiment of the present invention;

[0017] Figure 9 The figure illustrates a block diagram of a third system according to an embodiment of the present invention;

[0018] Figure 10 The figure illustrates a block diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention;

[0019] Figure 11 The figure illustrates a block diagram illustrating the conversion of binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter, according to an embodiment of the present invention.

[0020] Figure 12 The figure illustrates a processor architecture on which embodiments of the present invention can be implemented;

[0021] Figure 13 The figure illustrates multiple compressed data elements containing real and complex values ​​according to one embodiment;

[0022] Figure 14 The diagram illustrates an embodiment of a compact data processing architecture; and

[0023] Figure 15 The figure illustrates a method according to an embodiment of the present invention. Detailed Implementation

[0024] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the fundamental principles of embodiments of the invention.

[0025] Exemplary processor architecture, instruction format, and data types

[0026] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify the operation to be performed (opcode) and the operand(s) to which the operation will be performed, etc. Some instruction formats are further decomposed by defining instruction templates (or subformats). For example, an instruction template for a given instruction format can be defined as a different subset of the fields of that instruction format (the included fields are generally in the same order, but at least some fields have different bit positions because fewer fields are included), and / or defined as a given field that is interpreted in a different way. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, according to a given instruction template in the instruction template of that instruction format) and includes fields for specifying the operation and operands. For example, the exemplary ADD (addition) instruction has a specific opcode and instruction format, which includes an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will cause specific content in the operand field to select a specific operand.

[0027] Examples of the instructions described herein can be embodied in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Examples of the instructions can be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0028] General Vector-Friendly Instruction Format

[0029] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., the existence of specific fields dedicated to vector operations). Although an embodiment in which both vector and scalar operations are supported via a vector-friendly instruction format has been described, alternative embodiments use only vector operations via the vector-friendly instruction format.

[0030] Figure 1A-Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention. Figure 1A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention; and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector-friendly instruction format 100, both of which include instruction templates for no memory access 105 and instruction templates for memory access 120. In the context of the vector-friendly instruction format, the term "general" means an instruction format that is not bound to any particular instruction set.

[0031] Although embodiments of the invention described herein support the following in the case of vector-friendly instruction formats: 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, the 64-byte vector consists of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); Byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); however, alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) with larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0032] Figure 1A The Class A instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a full rounding control operation 110 without memory access and an instruction template showing a data transformation operation 115 without memory access; and 2) within the instruction template for memory access 120, an instruction template showing the timeliness of memory access 125 and the timelessness of memory access 130. Figure 1B The B-type instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a partial rounding control type operation 112 for write mask control without memory access and an instruction template showing a vsize type operation 117 for write mask control without memory access; and 2) within the instruction template for memory access 120, an instruction template showing write mask control 127 for memory access.

[0033] The general vector-friendly instruction format 100 includes the following as listed in Figure 1A-Figure 1B The fields in the order shown in the diagram are as follows.

[0034] Format field 140 – A specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format, and thus indicates that the instruction appears in the instruction stream in the vector-friendly instruction format. Therefore, this field is not required for instruction sets that only have a general vector-friendly instruction format, and in this sense, it is optional.

[0035] Basic Operation Field 142 – Its content distinguishes different basic operations.

[0036] Register index field 144—its contents, either directly or generated from addresses, specify the location of the source or destination operand in a register or in memory. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources, where one of these sources also serves as the destination; up to three sources, where one of these sources also serves as the destination; up to two sources and one destination).

[0037] The modifier field 146 distinguishes between instructions in the generic vector instruction format that specify memory access and those that do not; that is, it differentiates between instruction templates with no memory access 105 and instruction templates with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values ​​in registers to specify source and destination addresses), while non-memory access operations do not (e.g., the source and / or destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0038] The extended operation field 150 distinguishes which of the various operations to be performed in addition to the basic operation. This field is context-dependent. In one embodiment of the invention, this field is divided into a class field 168, an α field 152, and a β field 154. The extended operation field 150 allows multiple sets of common operations to be performed in a single instruction, rather than two, three, or four instructions.

[0039] Ratio field 160 — its contents allow for use in memory address generation (e.g., for using...)

[0040] (2 比例 The content of the index field is scaled proportionally by the address generated by the index + base address.

[0041] Displacement field 162A – its contents are used as part of memory address generation (e.g., for use with (2 比例 Address generation (index + base address + offset).

[0042] The displacement factor field 162B (note that the offset field 162A directly indicates the use of one or the other on the offset factor field 162B) – its contents are used as part of the address generation; it specifies the displacement factor that will scale the size (N) of the memory access – where N is the number of bytes in the memory access (e.g., for use with (2 比例 *Address generation (index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore the contents of the displacement factor field are multiplied by the total memory operand size (N) to generate the final displacement that will be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. Displacement field 162A and displacement factor field 162B are not used in the instruction template for no memory access 105 and / or different embodiments may implement only one of them or neither of them; in this sense, displacement field 162A and displacement factor field 162B are optional.

[0043] The data element width field 164—its content distinguishes which of the multiple data element widths will be used (in some embodiments for all instructions; in other embodiments for only some instructions). This field is unnecessary if only one data element width is supported and / or if one aspect of the opcode is used to support the data element width; in this sense, the field is optional.

[0044] The write mask field 170—its contents control, element-by-element position, whether the position of data elements in the destination vector operand reflects the results of the base and augmentation operations. Type A instruction templates support merge-write masking, while Type B instruction templates support both merge-write masking and zero-write masking. When merging, the vector mask allows protecting any set of elements in the destination from updates during the execution of any operation (specified by the base and augmentation operations); in another embodiment, it preserves the old value of each element in the destination where the corresponding mask bit has a 0. Conversely, when zeroing, the vector mask allows zeroing any set of elements in the destination during the execution of any operation (specified by the base and augmentation operations); in one embodiment, the elements in the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the modified elements do not necessarily have to be consecutive. Thus, the write mask field 170 allows for some vector operations, including load, store, arithmetic, logical, etc. Although an embodiment of the invention has been described in which the content of the write mask field 170 selects one of a plurality of write mask registers containing the write mask to be used (and thus the content of the write mask field 170 indirectly identifies the mask to be performed), alternative embodiments may alternatively or additionally allow the content of the mask write field 170 to directly specify the mask to be performed.

[0045] Immediate number field 172 – its contents allow for the specification of immediate numbers. This field is optional in implementations of generic vector-friendly formats that do not support immediate numbers and in instructions that do not use immediate numbers.

[0046] Class field 168 – its content distinguishes instructions from different classes. (See reference) Figure 1A-Figure 1B The content of this field allows selection between Class A and Class B instructions. Figure 1A-Figure 1B In this context, rounded rectangles are used to indicate that a specific value exists in a field (e.g., in...). Figure 1A-Figure 1B The two fields are used for class field 168 (Class A 168A and Class B 168B, respectively).

[0047] Type A Instruction Template

[0048] In the case of the instruction template for Class A non-memory access 105, the α field 152 is interpreted as the RS field 152A, whose content distinguishes which of the different extended operation types to be performed (e.g., the instruction templates for rounding operation 110 and data transformation operation 115 without memory access specify rounding 152A.1 and data transformation 152A.2, respectively). The β field 154 distinguishes which of the specified types of operations to be performed. In the instruction template for non-memory access 105, the scaling field 160, the displacement field 162A, and the displacement-scale field 162B are absent.

[0049] Instruction template without memory access – fully round-control operation

[0050] In the instruction template of a fully round-controlled operation 110 without memory access, the β field 154 is interpreted as a rounding control field 154A that provides static rounding for its(plural) contents. Although the rounding control field 154A in the described embodiment of the invention includes a suppress all floating-point exception (SAE) field 156 and a rounding operation control field 158, alternative embodiments may support both concepts, which may be encoded as the same field, or only one or the other of these concepts / fields may be present (e.g., only the rounding operation control field 158 may be present).

[0051] SAE field 156 – Its content distinguishes whether exception event reporting is disabled; when the content of SAE field 156 indicates that suppression is enabled, the given instruction does not report any kind of floating-point exception flags and does not invoke any floating-point exception handlers.

[0052] The rounding operation control field 158 distinguishes which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Thus, the rounding operation control field 158 allows the rounding mode to be changed instruction-by-instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0053] Instruction template without memory access – data transformation operations

[0054] In the instruction template of the data transformation operation 115 without memory access, the β field 154 is interpreted as the data transformation field 154B, the contents of which distinguish which of the multiple data transformations to be performed (e.g., no data transformation, mixing, broadcasting).

[0055] In the case of instruction template 120 for Class A memory access, field 152 is interpreted as eviction hint field 152B, the content of which distinguishes which eviction hint to use (in... Figure 1A In the instruction template for memory access timing 125 and memory access non-timing 130, timing 152B.1 and non-timing 152B.2 are specified respectively, while the β field 154 is interpreted as a data manipulation field 154C, the contents of which distinguish which of the multiple data manipulation operations (also called primitives) to be performed (e.g., no manipulation, broadcast, source upcast, and destination downcast). The instruction template for memory access 120 includes a scaling field 160 and optionally includes a displacement field 162A or a displacement scaling field 162B.

[0056] Vector memory instructions use translation support to perform vector loads from and vector stores to memory. Like regular vector instructions, vector memory instructions transfer data to / from memory in an element-by-element manner, where the actual elements transferred are specified by the contents of a vector mask selected as the write mask.

[0057] Instruction templates for memory access – time-sensitive

[0058] Time-sensitive data is data that can be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint entirely.

[0059] Instruction templates for memory access – non-time-sensitive

[0060] Non-time-sensitive data is data that is unlikely to be reused quickly enough to benefit from cache operations in the L1 cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint entirely.

[0061] Type B Instruction Template

[0062] In the case of the B-type instruction template, the α field 152 is interpreted as the write mask control (Z) field 152C, the content of which distinguishes whether the write mask controlled by the write mask field 170 should be merged or zeroed.

[0063] In the case of instruction template B-type non-memory access 105, a portion of β field 154 is interpreted as RL field 157A, the content of which distinguishes which of the different extended operation types to be performed (for example, the instruction template for instruction template of write mask control type operation 112 for non-memory access and instruction template for write mask control type operation 117 for non-memory access specify rounding 157A.1 and vector length (VSIZE) 157A.2, respectively), while the remainder of β field 154 distinguishes which of the specified types of operations to be performed. In instruction template of non-memory access 105, the scaling field 160, the displacement field 162A, and the displacement scaling field 162B are absent.

[0064] In the instruction template of the write mask control section round control operation 110 without memory access, the remainder of the β field 154 is interpreted as the round operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0065] Rounding operation control field 159A—like rounding operation control field 158—distinguishes which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Thus, rounding operation control field 159A allows the rounding mode to be changed instruction-by-instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of rounding operation control field 150 overrides that register value.

[0066] In the instruction template of write mask control VSIZE type operation 117 without memory access, the remainder of β field 154 is interpreted as vector length field 159B, the contents of which distinguish which of the multiple data vector lengths to be executed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0067] In the case of the instruction template for Class B memory access 120, a portion of the β field 154 is interpreted as a broadcast field 157B, the content of which distinguishes whether a broadcast data manipulation operation is to be performed, while the remainder of the β field 154 is interpreted as a vector length field 159B. The instruction template for memory access 120 includes a scaling field 160 and optionally includes a displacement field 162A or a displacement-scaling field 162B.

[0068] For the general vector-friendly instruction format 100, the complete opcode field 174 is shown to include a format field 140, a basic operation field 142, and a data element width field 164. Although one embodiment is shown in which the complete opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the complete opcode field 174 includes fewer than all of them. The complete opcode field 174 provides the operation code (opcode).

[0069] The expanded operation field 150, data element width field 164, and write mask field 170 allow these features to be specified on an instruction-by-instruction basis in a generic vector-friendly instruction format.

[0070] Combining the write mask field and the data element width field creates various types of instructions, as these instructions allow the mask to be applied based on different data element widths.

[0071] The various instruction templates appearing within classes A and B are advantageous in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both. For example, a high-performance general-purpose out-of-order core designed for general-purpose computing may support only class B, a core designed primarily for graphics and / or scientific (throughput) computing may support only class A, and a core designed for both general-purpose computing and graphics and / or scientific (throughput) computing may support both class A and class B (of course, cores with some mixture of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the invention). Similarly, a single processor may include multiple cores, all of which support the same class, or different cores that support different classes. For example, in a processor with separate graphics cores and general-purpose cores, one graphics core designed primarily for graphics and / or scientific computing may support only class A, while one or more general-purpose cores may be high-performance general-purpose cores with out-of-order execution and register renaming designed for general-purpose computing and supporting only class B. Another processor, which does not have a separate graphics core, may include one or more general-purpose ordered or out-of-order cores that support both Class A and Class B. Of course, in different embodiments of the invention, features from one class may also be implemented in other classes. This will enable programs written in high-level languages ​​to become (e.g., just-in-time compiled or statically compiled) various different executable forms, including: 1) forms having only instructions from the class(s) supported by the target processor(s) for execution; or 2) forms having alternative routines and control flow code that uses different combinations of instructions from all classes, the control flow code selecting these routines to execute based on instructions supported by the processor currently executing the code.

[0072] VEX command format

[0073] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides three-operand (or more) syntax. For example, the previous two-operand instructions performed operations such as A = A + B, which overwrite the source operand. The use of the VEX prefix allows operands to perform non-destructive operations such as A = B + C.

[0074] Figure 2A The diagram illustrates an exemplary AVX instruction format, including the VEX prefix 202, the actual opcode field 230, the Mod R / M byte 240, the SIB byte 250, the offset field 262, and the IMM8 272. Figure 2B The diagram shows the source Figure 2A Which fields constitute the complete opcode field 274 and the basic operation field 241? Figure 2C The diagram shows the source Figure 2A Which fields constitute register index field 244?

[0075] The VEX prefix (bytes 0-2) 202 is encoded in three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide special capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bits [7]-R), the VEX.X bit field (VEX byte 1, bits [6]-X), and the VEX.B bit field (VEX byte 1, bits [5]-B). The other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] – mmmmmm) contains the content used to encode the implicit preamble opcode byte. The W field 264 (VEX byte 2, bits [7] – W) is represented by the notation VEX.W and provides different functions depending on the instruction. The function of VEX.vvvv 220 (VEX byte 2, bits [6:3] – vvvv) can be as follows: 1) VEX.vvvv encodes the first source register operand specified in reverse (two's complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in two's complement form for some vector shift; or 3) VEX.vvvv does not encode any operand, this field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bits [2]-L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0]-pp) provides additional bits for the basic operation field 241.

[0076] The actual opcode field 230 (byte 3) is also known as the opcode byte. Part of the opcode is specified in this field.

[0077] The MOD R / M field 240 (byte 4) includes the MOD field 242 (bits [7-6]), the Reg field 244 (bits [5-3]), and the R / M field 246 (bits [2-0]). The Reg field 244 may encode the destination register operand or the source register operand (rrr of Rrrr); or it may be treated as an opcode extension and not used to encode any instruction operand. The R / M field 246 may encode the instruction operand that references a memory address; or it may encode the destination register operand or the source register operand.

[0078] The scale, index, base address (SIB) field 250 (byte 5) contains SS252 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned for register indices Xxxx and Bbbb.

[0079] The displacement field 262 and the immediate numeric field (IMM8) 272 contain data.

[0080] Exemplary Register Architecture

[0081] Figure 3 This is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 512-bit wide vector registers 310; these registers are referenced as zmm0 to zmm31. The lower-order 256 bits of the lower 6 zmm registers are overlaid on registers ymm0-15. The lower-order 128 bits of the lower 6 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0082] General Purpose Register 325 — In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used in conjunction with existing x86 addressing modes for addressing memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0083] A scalar floating-point stack register file (x87 stack) 345 is overlaid with an MMX compact integer flat register file 350. In the illustrated embodiment, the x87 stack is an octal stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions; while the MMX registers are used to perform operations on 64-bit compact integer data and to store operands for some operations performed between the MMX and XMM registers.

[0084] Alternative embodiments of the invention may use wider or narrower registers. Furthermore, alternative embodiments of the invention may use more, fewer, or different register files and registers.

[0085] Exemplary core architectures, processors, and computer architectures

[0086] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) CPUs, which include one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors, which include one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. These different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU; 2) coprocessors in the same package as the CPU but on a separate die; 3) coprocessors on the same die as the CPU (in this case, such coprocessors are sometimes referred to as dedicated logic or dedicated cores, such as integrated graphics and / or scientific (throughput) logic); and 4) systems-on-a-chip that can include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die. Exemplary core architectures are then described, followed by exemplary processors and computer architectures. Circuits (units) including example cores, processors, etc., are described in detail herein.

[0087] Exemplary core architecture

[0088] Figure 4A This is a block diagram illustrating an exemplary ordered pipeline and an exemplary out-of-order release / execution pipeline for register renaming according to various embodiments of the present invention. Figure 4B This is a block diagram illustrating exemplary embodiments of ordered architecture cores to be included in a processor according to various embodiments of the present invention, and exemplary out-of-order release / execution architecture cores with register renaming. Figures 4A-4B The solid-line boxes in the diagram illustrate ordered pipelines and ordered cores, while the optional additions to the dashed boxes illustrate register renaming, out-of-order release / execution pipelines, and cores. Since the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0089] exist Figure 4AIn the processor pipeline 400, there are fetch stage 402, length decoding stage 404, decoding stage 406, allocation stage 408, renaming stage 410, scheduling (also known as dispatch or issue) stage 412, register read / memory read stage 414, execution stage 416, write-back / memory write stage 418, exception handling stage 422 and commit stage 424.

[0090] Figure 4B A processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. Core 490 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 490 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0091] Front-end unit 430 includes branch prediction unit 432 coupled to instruction cache unit 434 coupled to instruction translation lookup buffer (TLB) 436 coupled to instruction fetch unit 438 coupled to decoding unit 440. Decoding unit 440 (or decoder) decodes instructions and generates one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, the original instructions or derived from them. Decoding unit 440 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 490 includes microcode ROM or other media (e.g., in decoding unit 440 or otherwise within front-end unit 430) storing microcode for certain macro instructions. The decoding unit 440 is coupled to the rename / allocator unit 452 in the execution engine unit 450.

[0092] Execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set 456 of one or more scheduler units. The scheduler units 456 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 456 are coupled to physical register file units 458. Each physical register file unit in the physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 458 include vector register units and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. Multiple physical register file units 458 are overlapped by retirement units 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using multiple reorder buffers and multiple retirement register files; using multiple future files, multiple history buffers, and multiple retirement register files; using register mappings and register pools, etc.). Retirement units 454 and multiple physical register file units 458 are coupled to multiple execution clusters 460. Multiple execution clusters 460 include a set 462 of one or more execution units and a set 464 of one or more memory access units. Execution units 462 can perform various operations (e.g., shift, addition, subtraction, multiplication) and can perform operations on various data types (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit 456, physical register file unit 458, and execution cluster 460 are shown as possibly multiple, because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines each having their own scheduler unit, physical register file unit, and / or execution cluster—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of that pipeline has multiple memory access units 464). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be out-of-order deployment / execution, and the remaining pipelines may be ordered.

[0093] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472, which is coupled to a data cache unit 474, which is coupled to a Level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access unit 464 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. An instruction cache unit 434 is also coupled to the Level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0094] As an example, the exemplary register renaming out-of-order release / execution core architecture can implement pipeline 400 as follows: 1) Instruction fetch 438 executes fetch stage 402 and length decoding stage 404; 2) Decoding unit 440 executes decoding stage 406; 3) Rename / allocator unit 452 executes allocation stage 408 and rename stage 410; 4) (multiple) scheduler units 456 execute scheduling stage 412; 5) (multiple) physical register file units 458 and memory units 470 execute register read / memory read stage 414; execution cluster 460 executes execution stage 416; 6) memory unit 470 and (multiple) physical register file units 458 execute write-back / memory write stage 418; 7) each unit may involve exception handling stage 422; and 8) retirement unit 454 and (multiple) physical register file units 458 execute commit stage 424.

[0095] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California; the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, Core 490 includes logic for supporting compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of compressed data to perform operations used by many multimedia applications.

[0096] It should be understood that a core can support multithreading (execution of two or more parallel operations or a set of threads), and this multithreading can be accomplished in various ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread in the simultaneous multithreading of the physical core), or combinations thereof (e.g., time-division fetching and decoding, and subsequent operations such as...). Simultaneous multithreading in hyper-threading technology.

[0097] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can also be used in ordered architectures. While the illustrated processor embodiment also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0098] Specific exemplary ordered core architecture

[0099] Figures 5A-5B The diagram illustrates a more specific exemplary ordered core architecture, where the core is one of several logic blocks within a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed functional logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0100] Figure 5A This is a block diagram of a single processor core according to an embodiment of the invention, its connection to an on-die interconnect network 502, and a local subset 504 of its second-level (L2) cache. In one embodiment, the instruction decoder 500 supports the x86 instruction set with a compact data instruction set extension. The L1 cache 506 allows low-latency access to cache memory into the scalar and vector units. Although in one embodiment (for simplicity), the scalar unit 508 and the vector unit 510 use separate sets of registers (scalar register 512 and vector register 514, respectively), and data transferred between these registers is written to memory and subsequently read back from the first-level (L1) cache 506, alternative embodiments of the invention may use different methods (e.g., using a single set of registers or including a communication path that allows data to be transferred between these two register sets without being written and read back).

[0101] The local subset 504 of the L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and is dumped from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0102] Figure 5B This is an embodiment of the present invention. Figure 5A An expanded diagram of a portion of the processor core. Figure 5B This includes the L1 data cache 506A portion of L1 cache 504, and further details regarding vector unit 510 and vector register 514. Specifically, vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. This VPU supports mixing of register inputs via mixing unit 520, numerical conversion via value conversion units 522A-B, and copying of memory inputs via copy unit 524.

[0103] Processor with integrated memory controller and graphics device

[0104] Figure 6 This is a block diagram of a processor 600 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 6 The solid-line box illustration shows a processor 600 having a single core 602A, a system agent 610, and a set 616 of one or more bus controller units, while the optional additional illustration with dashed boxes shows an alternative processor 600 having multiple cores 602A-N, a set 614 of one or more integrated memory controller units from the system agent units 610, and dedicated logic 608.

[0105] Therefore, different implementations of processor 600 may include: 1) a CPU, wherein dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 602A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, wherein cores 602A-N are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 602A-N are a large number of general-purpose ordered cores. Thus, processor 600 may be a general-purpose processor, coprocessor, or dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 600 may be part of one or more substrates, and / or may be implemented on one or more substrates using any of a variety of process technologies (e.g., BiCMOS, CMOS, or NMOS).

[0106] The memory hierarchy includes one or more cache levels within cores 604A-N, a set 606 of one or more shared cache units, and external memory (not shown) coupled to a set 614 of integrated memory controller units. The set 606 of shared cache units may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 612 interconnect integrated graphics logic 608, the set 606 of shared cache units, and system proxy units 610 / (multiple) of integrated memory controller units 614, alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 606 and cores 602A-N.

[0107] In some embodiments, one or more cores 602A-N can be multithreaded. System agent 610 includes those components that coordinate and operate core 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or may include, the logic and components required to regulate the power state of core 602A-N and integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0108] The 602A-N cores can be homogeneous or heterogeneous in terms of their instruction set architecture; that is, two or more cores in the 602A-N cores may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0109] Exemplary computer architecture

[0110] Figures 7-10 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0111] Now for reference Figure 7 The diagram illustrates a block diagram of a system 700 according to an embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, the controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); the GMCH 790 includes memory and a graphics controller, to which a memory 740 and a coprocessor 745 are coupled; the IOH 750 couples an input / output (I / O) device 760 to the GMCH 790. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with the memory 740 and the coprocessor 745 directly coupled to the processor 710, and the controller hub 720 and the IOH 750 residing on a single chip.

[0112] The optionality of the additional processor 715 is in Figure 7 The numbers are indicated by dashed lines. Each processor 710, 715 may include one or more of the processing cores described herein, and may be a version of processor 600.

[0113] The memory 740 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 720 communicates with the processors(s)(s) 710, 715 via a multi-branch bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 795.

[0114] In one embodiment, the coprocessor 745 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0115] There can be various differences between physical resources 710 and 715 in terms of a range of quality metrics, including architecture, microarchitecture, thermal and power consumption characteristics.

[0116] In one embodiment, processor 710 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as having a type that should be executed by an attached coprocessor 745. Therefore, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 on a coprocessor bus or other interconnect. Coprocessors 745(a) receive and execute the received coprocessor instructions.

[0117] See now Figure 8 The diagram shown is a block diagram of a first, more specific, exemplary system 800 according to an embodiment of the present invention. Figure 8 As shown, the multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0118] Processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its bus controller unit; similarly, the second processor 880 includes PP interfaces 886 and 888. Processors 870 and 880 can exchange information via a PP interface 850 using point-to-point (PP) interface circuits 878 and 888. Figure 8 As shown, IMC 872 and 882 couple the processor to the corresponding memory, namely memory 832 and memory 834, which may be portions of the main memory locally attached to the corresponding processor.

[0119] Processors 870 and 880 can each exchange information with chipset 890 via their respective PP interfaces 852 and 854 using point-to-point interface circuits 876, 894, 886, and 898. Chipset 890 can optionally exchange information with coprocessor 838 via high-performance interface 892. In one embodiment, coprocessor 838 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0120] A shared cache (not shown) may be included in either processor or external to both processors but connected to them via a PP interconnect, such that if the processors are in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0121] Chipset 890 can be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a peripheral component interconnect (PCI) bus or a bus such as PCI fast bus or another I / O interconnect bus, but the scope of the invention is not limited thereto.

[0122] like Figure 8 As shown, various I / O devices 814 may be coupled to a first bus 816 together with a bus bridge 818, which couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 816. In one embodiment, the second bus 820 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage unit 828, such as a disk drive that may include instruction / code and data 830, or other mass storage devices. Additionally, audio I / O 824 may be coupled to the second bus 820. Note that other architectures are possible. For example, instead of… Figure 8 The point-to-point architecture allows the system to implement multi-branch buses or other similar architectures.

[0123] Now for reference Figure 9 The diagram shown is a block diagram of a second, more specific, exemplary system 900 according to an embodiment of the present invention. Figure 8 and 9 Similar elements in the figure use similar reference numerals, and from Figure 9 The middle part is omitted Figure 8certain aspects to avoid confusion Figure 9 Other aspects.

[0124] Figure 9 The illustrated processors 870 and 880 may include integrated memory and I / O control logic (“CL”) 971 and 982, respectively. Therefore, CL 972 and 982 include an integrated memory controller unit and I / O control logic. Figure 9 The diagram shows that not only are the memories 832 and 834 coupled to CLs 972 and 982, but the I / O device 914 is also coupled to the control logic 972 and 982. The conventional I / O device 915 is coupled to the chipset 890.

[0125] Now for reference Figure 10 The diagram shown is a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in the figure use similar reference numerals. Additionally, dashed boxes are optional features on more advanced SoCs. Figure 10 In this configuration, multiple interconnect units 1002 are coupled to: an application processor 1010, which includes a set of one or more cores 602A-N, cache units 604A-N, and multiple shared cache units 606; a system proxy unit 610; multiple bus controller units 616; multiple integrated memory controller units 614; a set of one or more coprocessors 1020, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, the multiple coprocessors 1020 include dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, or embedded processors, etc.

[0126] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0127] Program code (such as, Figure 8The code 830 shown in the diagram is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0128] The program code can be implemented using a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if needed. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0129] One or more aspects of at least one embodiment can be implemented by representational instructions stored on a machine-readable medium, which represent various logics in a processor, and which, when read by a machine, cause the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on tangible machine-readable media and can be supplied to various customers or production facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0130] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks; any other type of disk, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase-change memory (PCM); magnetic cards or optical cards; or any other type of medium suitable for storing electronic instructions.

[0131] Therefore, embodiments of the invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a hardware description language (HDL), that defines the architectures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0132] Simulation (including binary transformation, code transformation, etc.)

[0133] In some cases, instruction translators can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform instructions (e.g., using static binary transformation, including dynamically compiled binary transformation), modify, emulate, or otherwise convert them into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on and partially off the processor.

[0134] Figure 11 This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 11 A program of the form of a high-level language 1102 can be compiled using a first compiler 1104 to generate first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 having at least one first instruction set core. In some embodiments, a processor 1116 having at least one first instruction set core represents any processor that performs substantially the same function as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of an Intel x86 instruction set core, or 2) a version of object code for an application or other software aimed at running on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., object code) in the first instruction set, which can be executed on the processor 1116 having at least one first instruction set core, with or without additional linking processing. Similarly, Figure 11A program of the form of a high-level language 1102 can be compiled using an alternative instruction set compiler 1108 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California). An instruction converter 1112 is used to translate the first binary code 1106 into code that can be natively executed by the processor 1114 that does not have a first instruction set core. This translated code is unlikely to be identical to the alternative instruction set binary code 1110 because an instruction converter capable of doing so would be difficult to manufacture; however, the translated code will perform general operations and consists of instructions from the alternative instruction set. Therefore, the instruction converter 1112 represents, through emulation, simulation, or any other process, software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first instruction set processor or core to execute the first binary code 1106.

[0135] Apparatus and method for digital signal processing instructions

[0136] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuitry and logic for performing DSP operations are integrated into... Figure 4B The execution engine unit 450 shown is integrated within the various cores described above (see, for example, Figure 6 and Figure 10 (in the nucleus 602A-N) and / or in Figure 5A Within the vector unit 510 shown in the diagram. For example, various source and destination registers can be... Figure 4B SIMD registers and / or physical register file units 458 in (multiple) Figure 3 Vector register 310 in the above-described architecture. Multiplication circuitry, adder circuitry, accumulator circuitry, and other circuitry described below can be integrated within the execution component of the architecture described above, by way of example and not limitation, which includes... Figure 4B The invention comprises (multiple) execution units 462. However, it should be noted that the basic principles of the invention are not limited to these specific architectures.

[0137] One embodiment of the invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. Specifically, one embodiment includes a multiplication-accumulation (MAC) architecture with eight 16×16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiplication and MAC operations on 128-bit compressed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. Additionally, some instructions have direct support for highly efficient Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering, as well as post-processing of accumulated data through shift, rounding, and saturation operations.

[0138] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and several instructions in the SSE / SSE2 / AVX instructions for post-processing of data disposal are used in conjunction with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0139] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0140] 1) It has more than 16 bits of Q31 data type for signals that require analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC);

[0141] 2) The Q15 data type commonly used in DSP algorithms;

[0142] 3) 16-bit complex number data type; and

[0143] 4) 32-bit complex number data type.

[0144] The instruction set architecture described in this paper is designed for a wide range of standard DSPs (e.g., FFT, filtering, pattern matching, correlation, multinomial estimation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0145] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a broad range of instructions applicable to deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion using Kalman filtering, and other major DSP applications. Given a weight sequence {w1, w2, ... w... k} and the input sequence {x1,x2,x3,…x} n Many image processing and machine learning tasks require computation of y i =w1x i +w2xi+1 +…+w k x i+k-1 The defined result sequence {y1,y2,y3,…y n+1-k}

[0146] Figure 12 The illustration shows an exemplary processor 1255 on which embodiments of the present invention can be implemented, the exemplary processor 1255 including multiple cores 0-N for executing multiple instruction threads simultaneously. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within a decoder 1230 and DSP instruction execution circuitry / logic 1241 within an execution unit 1240. These pipeline components can perform the operations described herein in response to the decoding and execution of DSP instructions. Although in Figure 12 Details of only a single core (core 0) are shown, but it will be understood that each of the other cores of the processor 1255 may include similar components.

[0147] Before describing the specific details of embodiments of the invention, a description of the components of an exemplary processor 1255 is provided directly below. Multiple cores 0-N may each include a memory management unit 1290 for performing memory operations (e.g., load / store operations), a set of general-purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are compressed into each vector register 1206, each vector register 1206 may have a 512-bit width for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the basic principles of the invention are not limited to any particular size / type of vector data. In one embodiment, mask register 1207 includes eight 64-bit operand mask registers (e.g., implemented as mask registers k0-k7 as described herein) for performing bitmasking operations on the values ​​stored in vector registers 1206. However, the basic principles of the invention are not limited to any particular mask register size / type.

[0148] Each core 0-N may include a dedicated Level 1 (L1) cache 1212 and a Level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored in each processor cache are managed at the granularity of cache lines, which may be of fixed size (e.g., 64 bytes, 128 bytes, or 512 bytes in length). Each core in this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or a shared Level 3 (L3) cache 1216. The instruction fetch unit 1210 includes various known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from memory 1200 (or one of the caches); a translation lookup buffer (ITLB) 1204 for storing a mapping of recently used virtual to physical instruction addresses to improve address translation speed; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0149] As mentioned, the decoding unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops" and DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The write-back / retreat unit 1250 retres the executed instructions and writes back the results.

[0150] Examples for multiplying, summing, and accumulating multiple groups of compressed bytes

[0151] One embodiment of the invention includes instructions for performing vector compaction multiplication of multiple sets of signed bytes in first and second source registers. The multiplication outputs are summed, inverted, and sign-expanded to double words (32 bits), and each of these double words is accumulated with each of the corresponding double words in an accumulator register. As an example, one embodiment of the invention is referred to herein as VPNDPBSSD xmm1,xmm2,xmm3 / m128, where xmm2 is the first source register, xmm3 is the second source register (where m128 indicates that data can be stored in memory), and xmm1 is both a source register and a destination register (i.e., storing the accumulated value).

[0152] In one embodiment, xmm1, xmm2, and xmm3 registers are 128-bit compact data registers that store two quad-word values, four double-word values, eight-word values, or sixteen bytes. Figure 13The figure illustrates exemplary data elements and bit distributions for exemplary source and / or destination registers. As shown, data elements can be compressed into source and / or destination registers in bytes (8 bits), words (16 bits), double words (32 bits), and / or quad words (64 bits).

[0153] Figure 14 The diagram illustrates an exemplary architecture for executing instructions that perform vector compaction multiplication of multiple groups of signed bytes in a first source register 1401 and a second source register 1402, summing and inverting the output, sign-expanding it to a double word (32 bits), and accumulating it with a double word in a third source register 1460 (which is also the destination register). Specifically, a set of multipliers 1405 multiplies each byte in the first source register 1401 with the corresponding byte in the second source register 1402. For example, byte B0 at data element positions [7:0] in source register 1401 is multiplied with byte B0 at data element positions [7:0] in source register 1402, byte B1 at data element positions [15:8] in source register 1401 is multiplied with byte B1 at data element positions [15:8] in source register 1402, and so on, resulting in 16 concurrent multiplication operations to generate 16 temporary products. In one embodiment, these temporary products are grouped into four groups of four.

[0154] In one embodiment, adder networks 1410-1411 sum the four temporary products in each group to generate four temporary sums, which are stored in four temporary storage locations (e.g., TEMP1-4 as discussed below, which may be registers or memory locations). In another embodiment, adder networks 1410-1411 (or other circuitry) invert each temporary sum and sign-extend each temporary sum to 32 bits, and accumulators 1420-1421 combine these 32-bit sign-extended results with corresponding double words (DW0-DW3) from source / destination registers 1460.

[0155] One embodiment of the present invention operates according to the following code sequence:

[0156] TEMP0[17:0]←((SRC2[31:24]*SRC3[31:24])+

[0157] (SRC2[23:16]*SRC3[23:16])+

[0158] (SRC2[15:8]*SRC3[15:8])+

[0159] (SRC2[7:0]*SRC3[7:0]));

[0160] TEMP1[17:0]←((SRC2[63:56]*SRC3[63:56])+

[0161] (SRC2[55:48]*SRC3[55:48])+

[0162] (SRC2[47:40]*SRC3[47:40])+

[0163] (SRC2[39:32]*SRC3[39:32]));

[0164] TEMP2[17:0]←((SRC2[95:88]*SRC3[95:88])+

[0165] (SRC2[87:80]*SRC3[87:80])+

[0166] (SRC2[79:72]*SRC3[79:72])+

[0167] (SRC2[71:64]*SRC3[71:64]));

[0168] TEMP3[17:0]←((SRC2[127:120]*SRC3[127:120])+

[0169] (SRC2[119:112]*SRC3[119:112])+

[0170] (SRC2[111:104]*SRC3[111:104])+

[0171] (SRC2[103:96]*SRC3[103:96]));

[0172] TEMP4[17:0]←(~TEMP0[17:0]+1'b1);

[0173] TEMP5[17:0]←(~TEMP1[17:0]+1'b1);

[0174] TEMP6[17:0]←(~TEMP2[17:0]+1'b1);

[0175] TEMP7[17:0]←(~TEMP3[17:0]+1'b1);

[0176] DEST[31:0]←AddToDword({14{TEMP4

[17] },TEMP4[17:0]},DEST[31:0]);

[0177] DEST[63:32]←AddToDword({14{TEMP5

[17] },TEMP5[17:0]},DEST[63:32]);

[0178] DEST[95:64]←AddToDword({14{TEMP6

[17] },TEMP6[17:0]},DEST[95:64]);

[0179] DEST[127:96]←AddToDword({14{TEMP7

[17] },TEMP7[17:0]},DEST[127:96]);;

[0180] Therefore, the bytes at positions [31:24], [23:16], [15:8], and [7:0] in the first source register 1401 are multiplied by the corresponding bytes at positions [31:24], [23:16], [15:8], and [7:0] in the second source register 1402. These four products are then summed and stored in TEMP0[17:0]. The same multiplication and addition operations are performed on bytes [63:56], [55:48], [47:40], and [39:32], and the results are stored in TEMP1[17:0]; on bytes [95:88], [87:80], [79:72], and [71:64], and the results are stored in TEMP2[17:0]; and on bytes [127:120], [119:112], [111:104], and [103:96], and the results are stored in TEMP3[17:0].

[0181] In one embodiment, the results in TEMP0[17:0], TEMP1[17:0], TEMP2[17:0], and TEMP3[17:0] are inverted using two's complement (e.g., within adder networks 1410-1411 or other circuitry). The inverted results are then stored in temporary storage locations TEMP4[17:0], TEMP5[17:0], TEMP6[17:0], and TEMP7[17:0]. In alternative implementations, other techniques, such as zero-spread, may be employed.

[0182] Subsequently, the inverted values ​​in TEMP4[17:0], TEMP5[17:0], TEMP6[17:0], and TEMP7[17:0] are sign-extended to 32 bits (e.g., within adder networks 1410-1411, accumulators 1420-1421, or other circuitry). Each double word in the resulting double word is added to each double word in source / destination register 1460, and the final double word result is stored back to the same location in source / destination register 1460. For example, in the code sequence above, the double word value in DEST[31:0] is added to the inverted, zero-extended value from TEMP4[17:0], and the result is stored back in DEST[31:0].

[0183] exist Figure 15 The figure illustrates a method according to an embodiment of the present invention. This method can be implemented within the context of the processor and system architecture described above, but is not limited to any particular system architecture.

[0184] At 1501, an instruction is fetched having fields for an opcode, a first source operand, a second source operand, a third source operand, and a destination operand, the first and second source operands indicating compressed signed bytes, the third source operand indicating a compressed signed double word, and the destination operand indicating a compressed signed double word. At 1502, the instruction is decoded to generate a decoded instruction (e.g., decoded to perform multiple micro-operations of the described multiplication, addition, and other operations). At 1503, compressed signed bytes are retrieved for the first and second operands (e.g., from memory, data cache, etc.) and stored in the first and second source registers, respectively. As mentioned, in one embodiment, the third source register and the destination register are the same register storing the third source operand. The signed byte values ​​and double word values ​​described herein may be stored in 128-bit compressed data source registers (e.g., each register stores 16 bytes).

[0185] At 1504, decoded instructions (more precisely, micro-operations generated by decoding) are executed to multiply each compacted signed byte from the first source register with the corresponding compacted signed byte from the second source register to generate a first result. In at least one embodiment, these first results are 18-bit temporary products stored in temporary storage locations (e.g., in registers or system / cache memory). Multiple sets of first results are then combined to generate a second result. For example, four sets, each consisting of four temporary products, can be grouped together and added to generate four sums. Each of these four sums is stored in an 18-bit temporary storage location, the four sums are inverted (e.g., using two's complement inversion as previously described), and sign-extended to a 32-bit result. The resulting four 32-bit results are accumulated (e.g., added) with four double-word values ​​from the third source / destination register to generate four double-word results, which are then stored back into the destination register at 1505.

[0186] In the foregoing description, embodiments of the invention have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0187] Embodiments of the present invention may include the steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by a special-purpose hardware component containing hard-wired logic for performing these steps, or by any combination of a programmed computer component and a custom hardware component.

[0188] As described herein, instructions can refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have a predetermined function, or software instructions stored in memory embodied in a non-transitory computer-readable medium. Therefore, the techniques illustrated in the figures can be implemented using code and data stored on and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer-readable media such as non-transitory computer-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transient computer-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals—such as carrier waves, infrared signals, digital signals, etc.) to store and transmit code and data (internally and / or via a network with other electronic devices). Additionally, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. The coupling of this processor set with other components is typically via one or more buses and bridges (also referred to as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on one or more processor sets of that electronic device. Of course, one or more portions of embodiments of the invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details have been set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described exhaustively so as not to obscure the subject matter of the invention. Therefore, the scope and spirit of the invention should be determined based on the appended claims.

Claims

1. A processor for multiplying and adding condensed bytes, comprising: A decoder is used to decode instructions to generate decoded instructions, the instructions including an opcode and multiple operands, the multiple operands identifying multiple compressed data source registers and compressed data destination registers; The first source register is used to store the first plurality of compacted signed bytes; The second source register is used to store a second set of compacted signed bytes; An execution circuit for executing decoded instructions, the execution circuit comprising: A multiplier circuit is used to multiply each compacted signed byte from the first source register with a corresponding compacted signed byte from the second source register to generate multiple temporary products; An adder circuit is used to combine multiple sets of temporary product phases to generate multiple temporary sums. Inverting and expanding circuitry is used to invert each temporary sum in the temporary sum and expand each temporary sum to a double word sum; and An accumulator circuit is used to add each double-word sum in the double-word sum to the double-word from the third source register to generate the final double-word result; and A compact data destination register is used to store the final double-word result in the specified data element location.

2. The processor as claimed in claim 1, wherein, The third source register and the compressed data destination register are the same register.

3. The processor as claimed in claim 1 or 2, wherein, The multiple compressed signed bytes include 16 compressed signed bytes in each of the first source register and the second source register.

4. The processor as claimed in claim 1 or 2, wherein, The temporary product is used to store in an 18-bit temporary storage location.

5. The processor as claimed in claim 1 or 2, wherein, The inverting and expanding circuitry is used to perform a two's complement inversion on the temporary sum by reversing the bits of each temporary sum in the temporary sum and adding 1.

6. The processor as claimed in claim 1 or 2, wherein, The inverting and expanding circuitry includes a sign expanding circuitry for performing sign expanding to generate a double word sum.

7. The processor as claimed in claim 2, wherein, The final double-word result comprises four double-word results, wherein each double-word result is used to be stored in the compact data destination register in the data element position corresponding to the position of the double word used to generate the double-word result.

8. A method for multiplying and adding condensed bytes, comprising: The instruction is decoded to generate a decoded instruction, which includes an opcode and multiple operands that identify multiple compressed data source registers and compressed data destination registers; Store the first plurality of compacted signed bytes in the first source register; Store the second set of compacted signed bytes in the second source register; Each compacted signed byte from the first source register is multiplied by a corresponding compacted signed byte from the second source register to generate multiple temporary products; Multiple temporary sums are generated by combining the temporary products of multiple groups; Invert each temporary sum in the temporary sum and extend each temporary sum to a double word sum; as well as Each double-word sum in the double-word sum is added to the double-word from the third source register to generate the final double-word result; as well as The final double-word result is stored in the specified data element location in the compact data destination register.

9. The method of claim 8, wherein, The third source register and the compressed data destination register are the same register.

10. The method of claim 8 or 9, wherein, The multiple compressed signed bytes include 16 compressed signed bytes in each of the first source register and the second source register.

11. The method of claim 8 or 9, wherein, The temporary product is used to store in an 18-bit temporary storage location.

12. The method of claim 8 or 9, wherein, Inversion and expansion include performing a two's complement inversion on the temporary sum by reversing the bits of each temporary sum in the temporary sum and adding 1.

13. The method of claim 8 or 9, wherein, Inversion and expansion further include: performing symbol expansion to generate double words and.

14. The method of claim 9, wherein, The final double-word result comprises four double-word results, wherein each double-word result is used to be stored in the compact data destination register in the data element position corresponding to the position of the double word used to generate the double-word result.

15. A machine-readable medium for multiplying and adding condensed bytes, having program code stored thereon, which, when executed by a machine, causes the machine to perform the following operations: The instruction is decoded to generate a decoded instruction, which includes an opcode and multiple operands that identify multiple compressed data source registers and compressed data destination registers; Store the first plurality of compacted signed bytes in the first source register; Store the second set of compacted signed bytes in the second source register; Each compacted signed byte from the first source register is multiplied by a corresponding compacted signed byte from the second source register to generate multiple temporary products; Multiple temporary sums are generated by combining the temporary products of multiple groups; Invert each temporary sum in the temporary sum and extend each temporary sum to a double word sum; as well as Each double-word sum in the double-word sum is added to the double-word from the third source register to generate the final double-word result; as well as The final double-word result is stored in the specified data element location in the compact data destination register.

16. The machine-readable medium of claim 15, wherein, The third source register and the compressed data destination register are the same register.

17. The machine-readable medium as claimed in claim 15 or 16, wherein, The multiple compressed signed bytes include 16 compressed signed bytes in each of the first source register and the second source register.

18. The machine-readable medium as claimed in claim 15 or 16, wherein, The temporary product is used to store in an 18-bit temporary storage location.

19. The machine-readable medium as claimed in claim 15 or 16, wherein, Inversion and expansion include performing a two's complement inversion on the temporary sum by reversing the bits of each temporary sum in the temporary sum and adding 1.

20. The machine-readable medium as claimed in claim 15 or 16, wherein, Inversion and expansion further include: performing symbol expansion to generate double words and.

21. The machine-readable medium of claim 16, wherein, The final double-word result comprises four double-word results, wherein each double-word result is used to be stored in the compact data destination register in the data element position corresponding to the position of the double word used to generate the double-word result.

22. A device for multiplying and adding condensed bytes, comprising: A means for decoding an instruction to generate a decoded instruction, the instruction including an opcode and a plurality of operands, the plurality of operands identifying a plurality of compressed data source registers and a compressed data destination register; A means for storing a first plurality of compacted signed bytes in a first source register; A means for storing a second plurality of compacted signed bytes in a second source register; A means for multiplying each compacted signed byte from the first source register with a corresponding compacted signed byte from the second source register to generate a plurality of temporary products; A device for generating multiple temporary sums by combining multiple sets of temporary product phases; A means for inverting each temporary sum in a temporary sum and extending each temporary sum to a double word sum; as well as A means for adding each double-word sum in a double-word sum to a double-word from a third source register to generate the final double-word result; as well as A means for storing the final double-word result at the specified data element location in a compressed data destination register.

23. The device as claimed in claim 22, wherein, The third source register and the compressed data destination register are the same register.

24. The device as claimed in claim 22 or 23, wherein, The multiple compressed signed bytes include 16 compressed signed bytes in each of the first source register and the second source register.

25. The device as claimed in claim 22 or 23, wherein, The temporary product is used to store in an 18-bit temporary storage location.

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