Apparatus and method for adding packed data elements using rotation and halving

Abstract

An apparatus and method for performing addition of signed packed data values ​​using rotate and halve. The processor includes: a decoder that decodes an instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand; a first source register that stores a first plurality of packed signed words; a second source register that stores a second plurality of packed signed words; an execution circuit that executes the decoded instruction, including: an adder circuit that adds each packed signed word from the first source register to a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuit selecting each packed signed word from the second source register based on a rotate value in an immediate value of the instruction, the rotate value indicating an amount of rotate to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and a destination register that stores the plurality of signed word results in specified data element positions of the destination register.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of computer processors. More particularly, embodiments relate to apparatus and methods for adding packed data elements using rotations and halving. Background Art

[0002] An instruction set or instruction set architecture (ISA) is the part of a computer's architecture that is relevant to programming, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this article generally refers to macroinstructions—which are instructions provided to a processor for execution—as opposed to microinstructions or micro-operations—which are the result of a processor's decoder decoding a macroinstruction. Microinstructions or micro-operations can be configured to instruct the execution units on the processor to perform operations to implement the logic associated with the macroinstruction.

[0003] An ISA is distinct from a microarchitecture, which is a collection of processor design technologies used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel® Pentium 4 processor, the Intel® Core™ processor, and processors from Advanced Micro Devices, Inc. of Sunnyvale, California, implement nearly identical versions of the x86 instruction set (some extensions have been added with newer versions), but have different internal designs. For example, the same register architecture of an ISA can be implemented differently in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a register file). Unless otherwise specified, the phrases "register architecture," "register file," and "registers" are used herein to refer to what is visible to software / programmers and how instructions specify registers. Where a distinction is necessary, the adjectives "logical", "architectural", or "software visible" will be used to refer to registers / files within a register architecture, while different adjectives will be used to designate registers within a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pools).

[0004] Multiply-accumulate is a common digital signal processing operation that computes the product of two numbers and adds the product to an accumulated value. Existing single-instruction, multiple-data (SIMD) microarchitectures implement multiply-accumulate operations by executing a sequence of instructions. For example, a multiply-accumulate can be implemented using a multiply instruction, followed by a 4-way add, and then an accumulation of the target quadword data to generate two 64-bit saturated results. Summary of the Invention

[0005] A processor according to a first aspect of the present invention comprises:

[0006] a decoder for decoding an instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register;

[0007] a first source register for storing a first plurality of packed signed words;

[0008] a second source register for storing a second plurality of packed signed words;

[0009] An execution circuit, configured to execute the decoded instruction, the execution circuit comprising:

[0010] an adder circuit for adding each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results,

[0011] the adder circuit to select each packed signed word from the second source register based on a rotate value in an immediate value of the instruction, the rotate value indicating an amount of rotation to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and

[0012] A destination register is provided for storing the plurality of signed word results in designated data element positions of the destination register.

[0013] A method for adding packed data elements using rotation and halving according to a second aspect of the present invention comprises:

[0014] decoding the instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register;

[0015] storing a first plurality of packed signed words in a first source register;

[0016] storing a second plurality of packed signed words in a second source register;

[0017] adding each packed signed word from the first source register to selected packed signed words from the second source register to generate a plurality of signed word results,

[0018] selecting each packed signed word for addition from the second source register according to a rotate value in an immediate data of the instruction, the rotate value indicating an amount of rotation to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and

[0019] The plurality of signed word results are stored in designated data element positions of a destination register.

[0020] According to a third aspect of the present invention, a machine-readable medium has program code stored thereon, which, when executed by a processor, causes the processor to perform the following operations:

[0021] decoding the instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register;

[0022] storing a first plurality of packed signed words in a first source register;

[0023] storing a second plurality of packed signed words in a second source register;

[0024] adding each packed signed word from the first source register to selected packed signed words from the second source register to generate a plurality of signed word results,

[0025] selecting each packed signed word for addition from the second source register according to a rotate value in an immediate data of the instruction, the rotate value indicating an amount of rotation to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and

[0026] The plurality of signed word results are stored in designated data element positions of a destination register. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A better understanding of the present invention may be obtained from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1A and 1B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention;

[0029] Figure 2A -C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0030] Figure 3 is a block diagram of a register architecture according to one embodiment of the present invention; and

[0031] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, and retirement pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0032] Figure 4Bis a block diagram illustrating an exemplary embodiment of both an in-order fetch, decode, retire core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention;

[0033] Figure 5A is a block diagram of a single processor core and its connections to the on-die interconnect network;

[0034] Figure 5B FIG. 1 shows an embodiment of the present invention. Figure 5A An expanded view of a portion of a processor core in FIG;

[0035] Figure 6 is a block diagram of a single-core processor and a multi-core processor with integrated memory controller and graphics elements according to an embodiment of the present invention;

[0036] Figure 7 A block diagram of a system according to one embodiment of the present invention is illustrated;

[0037] Figure 8 A block diagram of a second system according to an embodiment of the present invention is illustrated;

[0038] Figure 9 A block diagram of a third system according to an embodiment of the present invention is illustrated;

[0039] Figure 10 FIGURE 1 illustrates a block diagram of a system on chip (SoC) according to an embodiment of the present invention;

[0040] Figure 11 A block diagram illustrating a method of converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention is shown;

[0041] Figure 12 illustrates a processor architecture upon which embodiments of the present invention may be implemented;

[0042] Figure 13 illustrates a plurality of packed data elements containing real and complex values ​​according to one embodiment;

[0043] Figure 14 illustrates an embodiment of a packaged data processing architecture; and

[0044] Figure 15 A method according to one embodiment of the present invention is illustrated. DETAILED DESCRIPTION

[0045] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the basic principles of the embodiments of the present invention.

[0046] Exemplary processor architectures, instruction formats, and data types

[0047] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (opcode) and the operand(s) on which the operation is to be performed. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, instruction templates for a given instruction format can be defined to have different subsets of the instruction format's fields (the included fields generally have the same order, but at least some have different bit positions because they include fewer fields) and / or to have given fields interpreted differently. Thus, each instruction of an ISA is represented using a given instruction format (and, if defined, within a given instruction template of that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and instruction format, including an opcode field for specifying the opcode and operand fields (source1 / destination and source2) for selecting operands. Each occurrence of this ADD instruction in an instruction stream will have specific content in the operand field that selects a specific operand.

[0048] The embodiments of the instruction(s) described herein may be embodied in various formats. Additionally, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of the instruction(s) described may be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0049] Generic vector-friendly instruction format

[0050] The vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields dedicated to vector operations). Although embodiments are described that support both vector and scalar operations through the vector friendly instruction format, alternative embodiments only use vector operations of the vector friendly instruction format.

[0051] Figures 1A-1B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention. Figure 1Ais a block diagram illustrating a general vector friendly instruction format and its class A instruction template according to an embodiment of the present invention; and Figure 1B 1 is a block diagram illustrating a generic vector-friendly instruction format and its class B instruction templates according to an embodiment of the present invention. Specifically, class A and class B instruction templates are defined for the generic vector-friendly instruction format 100, and neither class A nor class B instruction templates include the memory access 105 instruction template and the memory access 120 instruction template. The term "generic" in the context of the vector-friendly instruction format refers to an instruction format that is not tied to any particular instruction set.

[0052] Also described are embodiments of the invention in which the vector-friendly instruction format supports: 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector consists of 16 doubleword-sized elements, or alternatively, 8 quadword-sized elements); 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0053] Figure 1A The Class A instruction templates include: 1) within the no memory access 105 instruction template, the no memory access, full rounding control type operation 110 instruction template and the no memory access, data transformation type operation 115 instruction template are shown; and 2) within the memory access 120 instruction template, the memory access, temporary 125 instruction template and the memory access, non-temporal 130 instruction template are shown. Figure 1B The Class B instruction templates include: 1) within the no memory access 105 instruction template, the no memory access, write mask control, partial rounding control type operation 112 instruction template and the no memory access, write mask control, VSIZE type operation 117 instruction template are shown; and 2) within the memory access 120 instruction template, the memory access, write mask control 127 instruction template is shown.

[0054] The general vector friendly instruction format 100 includes Figures 1A-1B The following fields are listed below in the order shown in the following.

[0055] Format field 140 - The specific value in this field (the instruction format identifier value) uniquely identifies the vector friendly instruction format, and therefore the vector friendly instruction format, as the instruction appears in the instruction stream. Therefore, this field is optional, as it is not needed for instruction sets that only have the generic vector friendly instruction format.

[0056] Basic operation field 142 - its content distinguishes different basic operations.

[0057] Register index field 144 - its contents specify the location of the source and destination operands, whether in registers or in memory, either directly or through address generation. These include a sufficient number of bits to select N registers from a register file of size P × Q (e.g., 32 × 512, 16 × 128, 32 × 1024, 64 × 1024). While in one embodiment, N may be up to three sources and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources may be supported, one of which also serves as the destination, up to three sources may be supported, one of which also serves as the destination, or up to two sources and one destination).

[0058] Modifier field 146 - its content distinguishes between occurrences of instructions in the generic vector instruction format that specify memory access and those that do not; that is, between the no memory access 105 instruction template and the memory access 120 instruction template. Memory access operations read and / or write to the memory hierarchy (in some cases using values ​​in registers to specify the source and / or destination addresses), while no memory access operations do not read and / or write to the memory hierarchy (e.g., the source and destination are registers). Although, in one embodiment, this field also selects between three different ways to implement memory address calculations, alternative embodiments may support more, fewer, or different ways to implement memory address calculations.

[0059] Extended Operation Field 150 - Its contents distinguish which of various operations are to be performed in addition to the basic operations. This field is context specific. In one embodiment of the present invention, this field is divided into a class field 168, an alpha field 152, and a beta field 154. The extended operation field 150 allows a common group of operations to be performed in a single instruction rather than in two, three, or four instructions.

[0060] Scale field 160 - its content allows scaling of the contents of the index field for memory address generation (e.g., for use with 2 scale * Index(2 缩放 * indexing) + basic address generation).

[0061] Displacement field 162A - its contents are used as part of memory address generation (e.g., for use with 2 scale * Address generation of index+base+displacement).

[0062] Displacement Factor field 162B (note that the juxtaposition of displacement field 162A directly over displacement factor field 162B indicates that one or the other is used) - its contents are used as part of address generation; it specifies the displacement factor, which is scaled by the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for addresses using 2 scale *Address generation of index + base + scaled displacement). Redundant low-order bits are ignored, and therefore, the contents of the displacement factor field are multiplied by the total size of the memory operand (N) to generate the final displacement used to calculate the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. Displacement field 162A and displacement factor field 162B are optional because they are not used in the No Memory Access 105 instruction template and / or different embodiments may implement only one or neither of them.

[0063] Data element width field 164 - its contents distinguish which of multiple data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some instructions). This field is optional, as it is not needed if only one aspect of the opcode is used to support one data element width and / or multiple data element widths.

[0064] Writemask field 170—its contents control, on a per-data-element basis, whether the data element position in the destination vector operand reflects the results of the base and augmentation operations. Class A instruction templates support merge-writemasking, while class B instruction templates support both merge-writemasking and zero-writemasking. When merged, vector masking allows any set of elements in the destination to be protected from updates during any operation (specified by the base and augmentation operations); in another embodiment, the old value of each element of the destination whose corresponding mask bit has a value of 0 is preserved. Conversely, when zeroed, vector masking allows any set of elements in the destination to be zeroed during any operation (specified by the base and augmentation operations); in one embodiment, elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element modified); however, the modified elements do not need to be contiguous. Therefore, writemask field 170 enables some vector operations, including loads, stores, arithmetic, logical, and more. While embodiments of the present invention are described in which the contents of the write mask field 170 select one of a plurality of write mask registers containing a write mask to be used (and thus the contents of the write mask field 170 indirectly identify the mask to be implemented), alternative or additional alternative embodiments allow the contents of the mask write field 170 to directly specify the mask to be implemented.

[0065] Immediate field 172 - its contents allow specification of an immediate value. This field is optional, as it is not present in implementations that do not support the generic vector-friendly format for immediate values, and it is not present in instructions that do not use immediate values.

[0066] Class field 168 - its content distinguishes different classes of instructions. Figure 1A -B, the contents of this field select between class A and class B instructions. Figure 1A -B, rounded squares are used to indicate the presence of a specific value in a field (e.g. Figure 1A -B, class A 168A and class B 168B for class field 168, respectively).

[0067] Class A instruction template

[0068] In the case of the non-memory access 105 instruction templates of class A, the α field 152 is interpreted as the RS field 152A, whose content distinguishes which of the different extended operation types is to be implemented (e.g., round 152A.1 and data transform 152A.2 are specified for the no-memory-access, round-type operation 110 and no-memory-access, data transform-type operation 115 instruction templates, respectively), while the β field 154 distinguishes which operation of the specified type is to be implemented. In the no-memory-access 105 instruction templates, the scale field 160, displacement field 162A, and displacement-scale field 162B are not present.

[0069] No memory access instruction templates - full rounding control type operations

[0070] In the no memory access full round control type operation 110 instruction template, the beta field 154 is interpreted as a round control field 154A, whose content(s) provide static rounding. Although in the described embodiment of the present invention, the round control field 154A includes a suppress all floating point exceptions (SAE) field 156 and a round operation control field 158, alternative embodiments may support encoding all of these concepts in the same field or having only one or the other of these concepts / fields (e.g., only having the round operation control field 158).

[0071] SAE field 156 - its content distinguishes whether exception event reporting is disabled; when the content of SAE field 156 indicates that suppression is enabled, the given instruction will not report any kind of floating point exception flags and will not raise any floating point exception handler.

[0072] Round operation control field 158 - its contents distinguish which of a set of rounding operations is to be performed (e.g., round up, round down, round toward zero, and round toward nearest). Thus, round operation control field 158 allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the present invention where the processor includes a control register for specifying the rounding mode, the contents of round operation control field 150 override the register value.

[0073] No memory access instruction template - data transformation type operation

[0074] In the no memory access data transform type operation 115 instruction template, the beta field 154 is interpreted as a data transform field 154B, the contents of which distinguish which of multiple data transforms is to be performed (eg, no data transform, swizzle, broadcast).

[0075] In the case of a memory access 120 instruction template of class A, the alpha field 152 is interpreted as an eviction hint field 152B, the contents of which distinguish which eviction hint is to be used (in Figure 1A152B.1 and non-temporal 152B.2 are designated for the memory access, temporary 125 instruction template and the memory access, non-temporal 130 instruction template, respectively), while the beta field 154 is interpreted as a data manipulation field 154C, the contents of which distinguish which of a plurality of data manipulation operations (also referred to as primitives) is to be performed (e.g., no manipulation; broadcast; upconversion of the source; and downconversion of the destination). The memory access 120 instruction template includes a scale field 160 and optionally a displacement field 162A or a displacement scale field 162B.

[0076] Vector memory instructions perform vector loads from memory and vector stores to memory if supported by the conversion. Like regular vector instructions, vector memory instructions transfer data to / from memory in an element-by-data-element manner, where the actual elements transferred are dictated by the contents of the vector mask selected as the writemask.

[0077] Memory Access Instruction Templates - Temporary

[0078] Temporary data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0079] Memory Access Instruction Templates - Non-Temporal

[0080] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from being cached in the first level cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0081] Class B instruction template

[0082] In the case of instruction templates of class B, the alpha field 152 is interpreted as a writemask control (Z) field 152C, the content of which distinguishes whether the writemask controlled by the writemask field 170 should be merge or zero.

[0083] In the case of the non-memory access 105 instruction templates of class B, a portion of the β field 154 is interpreted as an RL field 157A, the contents of which distinguish which of the different extended operation types is to be implemented (e.g., round 157A.1 and vector length (VSIZE) 157A.2 are specified for the no memory access, write mask control, partial round control type operation 112 instruction template and the no memory access, write mask control, VSIZE type operation 117 instruction template, respectively), while the remainder of the β field 154 distinguishes which operation of the specified type is to be implemented. In the no memory access 105 instruction templates, the scale field 160, displacement field 162A, and displacement scale field 162B are not present.

[0084] In the no memory access, write mask control, partial round control type operation 110 instruction template, the remainder of the beta field 154 is interpreted as the round operation field 159A and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flags and does not raise any floating-point exception handlers).

[0085] Round Operation Control Field 159A - As with round operation control field 158, its contents distinguish which of a set of rounding operations (e.g., round up, round down, round toward zero, and round toward nearest) is to be performed. Thus, round operation control field 159A allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the present invention where the processor includes a control register for specifying the rounding mode, the contents of round operation control field 159A override the register value.

[0086] In the no memory access, write mask control, VSIZE type operation 117 instruction template, the remainder of the beta field 154 is interpreted as a vector length field 159B, the contents of which distinguish which of multiple data vector lengths (eg, 128, 256, or 512 bytes) is to be implemented.

[0087] In the case of memory access 120 instruction templates of class B, a portion of the beta field 154 is interpreted as a broadcast field 157B, the contents of which distinguish whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 154 is interpreted as a vector length field 159B. The memory access 120 instruction templates include a scale field 160 and, optionally, a displacement field 162A or a displacement scale field 162B.

[0088] With respect to the generic vector friendly instruction format 100, a full opcode field 174 is shown that includes the format field 140, the basic operation field 142, and the data element width field 164. Although one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes less than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0089] The augment operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0090] The combination of the write mask field and the data element width field creates a typed instruction because they allow masking to be applied based on different data element widths.

[0091] The various instruction templates found within classes A and B can be beneficial in different situations. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both. (Of course, cores with some mix of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the present invention.) Furthermore, a single processor may include multiple cores, all supporting the same class, or different cores supporting different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more general-purpose cores may be high-performance general-purpose cores supporting only class B, with out-of-order execution and register renaming intended for general-purpose computing. Another processor without a separate graphics core may include a second general-purpose in-order or out-of-order core that supports both classes A and B. Of course, in different embodiments of the present invention, features from one class may also be implemented in another class. A program written in a high-level language will be formed (e.g., just-in-time or statically compiled) into a variety of different executable forms, including: 1) a form with only instructions of the class(es) supported by the target processor for execution; or 2) a form with alternative routines written using different combinations of instructions from all classes and with control flow code that selects the routine to execute based on the instructions supported by the processor currently executing the code.

[0092] VEX instruction format

[0093] VEX encoding allows instructions with more than two operands and SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or higher) syntax. For example, previous two-operand instructions implemented operations such as A=A+B, which overwrote the source operands. The use of the VEX prefix enables non-destructive operations such as A=B+C.

[0094] Figure 2A An exemplary AVX instruction format is illustrated, comprising a VEX prefix 202 , a real opcode field 230 , a Mod R / M byte 240 , a SIB byte 250 , a displacement field 262 , and an IMM8 272 . Figure 2B The diagram shows Figure 2A Which fields constitute the complete operation code field 274 and the basic operation field 241. Figure 2C The diagram shows Figure 2A Which fields of constitute the register index field 244.

[0095] The VEX prefix (bytes 0-2) 202 is encoded in a three-byte format. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include multiple bit fields that provide specific capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bits [7] - R), the VEX.X bit field (VEX byte 1, bits [6] - X), and the VEX.B bit field (VEX byte 1, bits [5] - B). As is known in the art, the other fields of the instruction encode the lower three bits of the register index (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 215 (VEX byte 1, bits [4:0] - mmmmm) contains the contents used to encode the implied leading opcode byte. The W field 264 (VEX byte 2, bits [7] - W) is represented by the symbol VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand and is reserved and should contain 1111b. If the VEX.L268 size field (VEX byte 2, bit [2]-L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0]-pp) provides additional bits for the basic operation field 241.

[0096] The real opcode field 230 (byte 3) is also called the opcode byte. A portion of the opcode is specified in this field.

[0097] The MOD R / M field 240 (byte 4) includes a MOD field 242 (bits [7-6]), a Reg field 244 (bits [5-3]), and an R / M field 246 (bits [2-0]). The Reg field 244 can be used to encode a destination register operand or a source register operand (Rrrr's rrr), or it can be treated as an opcode extension and not used to encode any instruction operand. The R / M field 246 can be used to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0098] The contents of the scale, index, base (SIB)-scale field 250 (byte 5) include SS 252 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned with respect to register indexes Xxxx and Bbbb.

[0099] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0100] Exemplary Register Architecture

[0101] Figure 3 is a block diagram of a register architecture 300 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310, each 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower-order 256 bits of the lower six zmm registers overlap registers ymm0-15. The lower-order 128 bits of the lower six zmm registers (the lower-order 128 bits of the ymm registers) overlap registers xmm0-15.

[0102] General purpose registers 325 - In the embodiment shown, there are 16 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0103] A scalar floating point stack register file (x87 stack) 345 on which the MMX packed integer flat register file 350 is aliased - in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for some operations performed between MMX and XMM registers.

[0104] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0105] Exemplary Core Architectures, Processors, and Computer Architectures

[0106] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; 2) a coprocessor including one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as a dedicated core); and 4) a system on a chip, which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the above-mentioned coprocessor, and additional functionality on the same die. An exemplary core architecture is described below, followed by a description of an exemplary processor and computer architecture. Detailed herein are circuits (units) including exemplary cores, processors, etc.

[0107] Exemplary core architecture

[0108] Figure 4A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the present invention. Figure 4B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figure 4A The solid boxes in B illustrate the in-order pipeline and in-order core, while the optional dashed boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0109] exist Figure 4A , processor pipeline 400 includes a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a rename stage 410, a schedule (also known as dispatch or issue) stage 412, a register read / memory read stage 414, an execute stage 416, a write back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0110] Figure 4BA processor core 490 is shown, comprising a front end unit 430 coupled to an execution engine unit 450, and both the front end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. The core 490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternate core type. Alternatively, the core 490 may be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, or the like.

[0111] Front end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, which is coupled to an instruction translation lookaside buffer (TLB) 436. Instruction translation lookaside buffer (TLB) 436 is coupled to an instruction fetch unit 438, which is coupled to a decode unit 440. Decode unit 440 (or decoder) can decode instructions and generate as output one or more micro-ops, microcode entry points, microinstructions, other instructions, or other control signals, which are decoded from, or otherwise reflect or derive from, the original instructions. Decode unit 440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and the like. In one embodiment, core 490 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 440 or within front end unit 430). Decode unit 440 is coupled to rename / allocator unit 452 in execution engine unit 450.

[0112] Execution engine unit 450 includes a rename / allocator unit 452, which is coupled to a retirement unit 454 and a set of one or more scheduler units 456. Scheduler unit(s) 456 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. Scheduler unit(s) 456 are coupled to physical register file(s) 458. Each of physical register file(s) 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, status (e.g., an instruction pointer, which is the address of the next instruction to be executed), and the like. In one embodiment, physical register file(s) 458 include vector register units and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. Physical register file(s) unit(s) 458 are overlaid by retirement unit(s) 454 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using reorder buffer(s) and retirement register file(s); using future stack(s), history buffer(s), and retirement register file(s); using register maps and register pools; etc.). Retirement unit(s) 454 and physical register file(s) unit(s) 458 are coupled to execution cluster(s) 460. Execution cluster(s) 460 include a set of one or more execution units 462 and a set of one or more memory access units 464. Execution units 462 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit(s) 456, physical register file(s) units 458, and execution cluster(s) 460 are shown as possibly plural because some embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file(s) units, and / or execution cluster—and in the case of a separate memory access pipeline, some embodiments are implemented in which only the execution cluster of that pipeline has memory access unit(s) 464).It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution while the rest are in-order issue / execution.

[0113] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472 coupled to a data cache unit 474, which is coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is also coupled to a level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0114] As an example, the exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 400 as follows: 1) instruction fetch unit 438 implements fetch stage 402 and length decode stage 404; 2) decode unit 440 implements decode stage 406; 3) rename / allocator unit 452 implements allocate stage 408 and rename stage 410; 4) (one or more) scheduler units 456 implement schedule stage 412; 5) (one or more) physical register file units 458 and memory units 470 implement register read / memory read stage 414; execution cluster 460 implements execute stage 416; 6) memory unit 470 and (one or more) physical register file units 458 implement write back / memory write stage 418; 7) various units may be involved in exception handling stage 422; and 8) retirement unit 454 and (one or more) physical register file units 458 implement commit stage 424.

[0115] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies of Sunnyvale, California; the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, California (with optional additional extensions such as NEON), including the instruction(s) described herein. In one embodiment, core 490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be implemented using packed data.

[0116] It should be understood that a core can support multithreading (executing a collection of two or more operations or threads in parallel) and can do so in a variety of ways, including time-partitioning multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-partitioning fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0117] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the embodiment of the processor shown also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches, the external caches being external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0118] Specific exemplary in-order core architecture

[0119] Figure 5A Figure 2-B illustrates a more specific block diagram of an exemplary in-order core architecture, which would be one of several logic blocks in a chip (including other cores of the same and / or different types). The logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network), depending on the application.

[0120] Figure 5A 5 is a block diagram of a single processor core and its connections to an on-die interconnect network 502 and a local subset of its level 2 (L2) cache 504, according to an embodiment of the present invention. In one embodiment, instruction decoder 500 supports the x86 instruction set with the packed data instruction set extension. L1 cache 506 allows low-latency access to cache memory in the scalar and vector units. While in one embodiment (to simplify the design), scalar unit 508 and vector unit 510 use separate register sets (scalar registers 512 and vector registers 514, respectively), and data transferred between them is written to memory and then read back from level 1 (L1) cache 506, alternative embodiments of the present invention may use a different approach (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0121] The local subset 504 of the L2 cache is part of the global L2 cache, which is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its local subset 504 of the L2 cache and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own local subset 504 of the L2 cache and is flushed from other subsets as needed. The ring network ensures the relevance of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0122] Figure 5B According to an embodiment of the present invention Figure 5A Expanded view of a portion of a processor core in . Figure 5B The L1 data cache 506A portion includes the local subset 504 of the L1 cache, as well as more details about the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 6-width vector processing unit (VPU) (see the 16-width ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports blending of register inputs using the blend unit 520, numerical conversion using the numerical conversion units 522A-B, and copying of memory inputs using the copy unit 524.

[0123] Processor with integrated memory controller and graphics element

[0124] Figure 6 is a block diagram of a processor 600 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have integrated graphics. Figure 6 The solid line box in the figure illustrates a processor 600 having a single core 602A, a system agent unit 610, and a set of one or more bus controller units 616, while the optionally added dashed line box illustrates an alternative processor 600 having multiple cores 602A-N, a set of one or more integrated memory controller units 614 in the system agent unit 610, and dedicated logic 608.

[0125] Thus, various implementations of processor 600 may include: 1) a CPU having dedicated logic 608 and cores 602A-N, where dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor having cores 602A-N, which are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor having cores 602A-N, which are a large number of general-purpose in-order cores. Thus, processor 600 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput multi-integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. Processor 600 may be implemented on and / or may be part of one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0126] The memory hierarchy includes one or more levels of cache within cores 604A-N, a set of one or more shared cache units 606, and external memory (not shown) coupled to a set of integrated memory controller units 614. The set of shared cache units 606 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller unit(s) 614, alternative embodiments may use any number of well-known techniques for interconnecting these units. In one embodiment, coherency is maintained between the one or more cache units 606 and the cores 602-AN.

[0127] In some embodiments, one or more of cores 602A-N may be multi-threaded. System agent unit 610 includes components that coordinate and operate cores 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include the logic and components necessary to regulate the power state of cores 602A-N and integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0128] Cores 602A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of cores 602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0129] Exemplary Computer Architecture

[0130] Figure 7-10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network appliances, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cell phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0131] Now refer to Figure 7 , shown is a block diagram of a system 700 according to one embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); GMCH 790 includes memory and graphics controllers coupled to memory 740 and coprocessor 745; and IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), memory 740 and coprocessor 745 are directly coupled to processor 710, and controller hub 720 and IOH 750 are on a single chip.

[0132] Figure 7 The optional nature of the additional processor 715 is indicated by dashed lines in FIG. 8 . Each processor 710 , 715 may include one or more processing cores described herein and may be some version of processor 600 .

[0133] The memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 720 communicates with the processor(s) 710, 715 via a multi-drop bus, such as a front-side bus (FSB), a point-to-point interface, or similar connection 795.

[0134] In one embodiment, coprocessor 745 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 720 may include an integrated graphics accelerator.

[0135] Various differences may exist between the processors 710 , 715 in terms of a range of measures of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0136] In one embodiment, processor 710 executes instructions that control general-purpose data processing operations. Embedded within the instructions may be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 745. Accordingly, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 over a coprocessor bus or other interconnect. Coprocessor(s) 745 accept and execute the received coprocessor instructions.

[0137] Now refer to Figure 8 , shown is a block diagram of a more specific first exemplary multi-processor system 800 according to an embodiment of the present invention. Figure 8 As shown in FIG, multiprocessor system 800 is a point-to-point interconnect system and includes a processor 870 and a processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the present invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0138] Processors 870 and 880 are shown, and processors 870 and 880 include integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its bus controller unit; similarly, processor 880 includes point-to-point (PP) interfaces 886 and 888. Processors 870, 880 can exchange information via point-to-point (PP) interconnect 850 using point-to-point (PP) interfaces 878, 888. Figure 8 As shown in FIG, integrated memory controllers (IMCs) 872 and 882 couple the processors to respective memories, namely, memory 832 and memory 834, which may be portions of main memory locally attached to the respective processors.

[0139] Processors 870, 880 may each exchange information with a chipset 890 via individual point-to-point (PP) interfaces 852, 854 using point-to-point (PP) interfaces 876, 894, 886, 898. Chipset 890 may optionally exchange information with a coprocessor 838 via a high-performance interface 892. In one embodiment, coprocessor 838 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0140] A shared cache (not shown) may be included in the processors or external to both processors but connected to the processors via the PP interconnect so that local cache information of either or both processors may be stored in the shared cache when the processors are in a low power mode.

[0141] Chipset 890 may be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or other I / O interconnect bus, although the scope of the invention is not limited in this regard.

[0142] like Figure 8 As shown in , various I / O devices 814 may be coupled to a first bus 816, as well as a bus bridge 818 which couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus. In one embodiment, the second bus 820 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, communication devices 827, and a storage unit 828, such as a disk drive or other mass storage device, which may include instructions / code and data 830. Additionally, an audio I / O 824 may be coupled to the second bus 820. Note that other architectures are possible. For example, instead of Figure 8 Instead of a point-to-point architecture, the system may implement a multi-point bus or other such architecture.

[0143] Now refer to Figure 9 , shown is a block diagram of a more specific second exemplary system 900 according to an embodiment of the present invention. Figure 8 and 9 Like elements in FIG. 1 have like reference numerals, and Figure 8 Some aspects of Figure 9 Omitted to avoid ambiguity Figure 9 other aspects.

[0144] Figure 9 The illustrated processors 870, 880 may include integrated memory and I / O control logic ("CL") 972 and 982, respectively. Thus, the CL 972, 982 includes an integrated memory controller unit and includes I / O control logic. Figure 9 It is shown that not only are memories 832, 834 coupled to the CLs 972, 982, but also that I / O devices 914 are coupled to the control logic 972, 982. Legacy I / O devices 915 are coupled to the chipset 890.

[0145] Now refer to Figure 10 , showing a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in the SoC have similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Figure 10 In the embodiment, interconnect unit(s) 1002 couples to: application processor 1010, comprising a set of one or more cores 102A-N, cache units 604A-N, and shared cache unit(s) 606; system agent unit 610; bus controller unit(s) 616; integrated memory controller unit(s) 614; one or more coprocessors 1020, which may include integrated graphics logic, image processors, audio processors, and video processors; static random access memory (SRAM) unit 1030; direct memory access (DMA) unit 1032; and display unit 1040 for coupling to one or more external displays. In one embodiment, coprocessor(s) 1020 include specialized processors such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, and the like.

[0146] The embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0147] Program code (such as Figure 8The code 830 shown in FIG. 8 can be applied to input instructions to implement the functionality described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0148] The program code can be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0149] One or more aspects of at least one embodiment may be implemented through representative instructions stored on a machine-readable medium, which represent various logic within a processor and, when read by a machine, causes the machine to fabricate logic to implement the described techniques. Such representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into the fabrication machines that actually make the logic or processor.

[0150] Such machine-readable storage media may include, but are not limited to, non-transitory tangible devices of articles manufactured or formed by a machine or apparatus, including: storage media such as hard disks; any other type of disk including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM); magnetic or optical cards or any other type of medium suitable for storing electronic instructions.

[0151] Therefore, embodiments of the present invention also include non-transitory, tangible, machine-readable media containing instructions or containing design data (such as hardware description language (HDL) that defines the structures, circuits, devices, processors, and / or system features described herein. These embodiments may also be referred to as program products.

[0152] Simulation (including binary transformation, code deformation, etc.)

[0153] In some cases, an instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can transform (e.g., using static binary transformation, including dynamic binary transformation for dynamic compilation), morph, emulate, or otherwise convert an instruction into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0154] Figure 11 1 is a block diagram illustrating a method for converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 It is shown that a program in a high-level language 1102 can be compiled using a first compiler 1104 to generate a first binary code (e.g., x86) 1106 that can be natively executed by a processor having at least one first instruction set core 1116. In some embodiments, a processor having at least one first instruction set core 1116 represents any processor that can implement substantially the same functionality as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of an Intel x86 instruction set core or (2) an object code version of an application or other software that is targeted to run on an Intel processor having at least one x86 instruction set core so as to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler that is operable to generate a first binary code 1106 (e.g., object code) of a first instruction set that can be executed on a processor having at least one first instruction set core 1116 with or without additional link processing. Similarly, Figure 11A program in a high-level language 1102 is shown to be compiled using an alternative instruction set compiler 1108 to generate alternative instruction set binary code 1110 that can be natively executed by a processor that does not have at least one first instruction set core 1114 (e.g., a processor that has a core that executes the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California and / or the ARM instruction set of ARM Holdings, Inc. of Sunnyvale, California). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by a processor that does not have the first instruction set core 1114. This converted code is unlikely to be identical to the alternative instruction set binary code 1110 because an instruction converter that can do so would be difficult to manufacture; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Thus, instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 1106 through emulation, simulation, or any other process.

[0155] Apparatus and method for digital signal processing instructions

[0156] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuitry and logic for implementing DSP operations are integrated into Figure 4B In the execution engine unit 450 shown in FIG, the various cores (see, for example, Figure 6 and 10 in cores 602A-N) and / or in Figure 5A For example, the various source and destination registers may be Figure 4B The physical register file(s) 458 and / or Figure 3 The SIMD registers in the vector register 310 in the following description of the multiplication circuit, adder circuit, accumulation circuit and other circuits can be integrated into the execution unit of the above architecture (including as an example but not limited to Figure 4B However, it should be noted that the underlying principles of the invention are not limited to these particular architectures.

[0157] One embodiment of the present invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture with eight 16×16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions directly support efficient fast Fourier transform (FFT) and finite impulse response (FIR) filtering, as well as post-processing of accumulated data, through shift, rounding, and saturation operations.

[0158] One embodiment of the new DSP instructions uses opcode encodings based on the VEX.128 prefix, and several SSE / SSE2 / AVX instructions that handle post-processing of data are used with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands may have relaxed memory alignment requirements.

[0159] In one embodiment, the instruction also supports various integer and fixed-point data types, including:

[0160] 1) Q31 data type, used for signals that require analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) with more than 16 bits;

[0161] 2) Q15 data types commonly used in DSP algorithms;

[0162] 3) complex 16-bit data type; and

[0163] 4) Complex 32-bit data type.

[0164] The instruction set architecture described in this article targets a wide range of standard DSP (e.g., FFT, filtering, pattern matching, correlation, polynomial evaluation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0165] Target applications of embodiments of the present invention include sensors for computer vision, audio, classification tasks, and speech recognition. The DSP ISA described herein includes a wide range of instructions suitable for: deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion in the context of Kalman filtering, and other major DSP applications. Given a weight sequence {w1, w2, ... w k} and the input sequence {x1, x2, x3, ... x n}, many image processing and machine learning tasks require computing the i =w1x i +w2x i +1+.................+wk x i+k-1定义的结果序列{ y1, y2, y3, ... y n+1-k}.

[0166] Figure 12 An exemplary processor 1255 is illustrated on which embodiments of the present invention may be implemented, the exemplary processor 1255 including multiple cores 0-N for executing multiple instruction threads simultaneously. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decode unit 1230 and DSP instruction execution circuitry / logic 1341 within execution unit 1240. These pipeline components may perform the operations described herein in response to the decoding and execution of DSP instructions. Although Figure 12 Only details of a single core (core 0) are shown in FIG, but it will be understood that each of the other cores of processor 1255 may include similar components.

[0167] Before describing the specific details of an embodiment of the present invention, a description of the various components of an exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N may include a memory management unit 1290 for performing memory operations (e.g., such as load / store operations), a set of general purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are packed into each vector register 1206. Each vector register 1206 may have a width of 512 bits for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, and so on. However, the underlying principles of the present invention are not limited to any particular size / type of vector data. In one embodiment, mask registers 1207 include eight 64-bit operand mask registers (e.g., implemented as mask registers k0-k7 as described herein) for performing bit-masking operations on the values ​​stored in the vector registers 1206. However, the underlying principles of the present invention are not limited to any particular mask register size / type.

[0168] Each core 0-N may include a dedicated level 1 (L1) cache 1212 and a level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored in the various processor caches are managed at the granularity of a cache line, which may be a fixed size (e.g., 64, 128, or 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or a shared level 3 (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); an instruction translation lookaside buffer (ITLB) 1204 for storing mappings of recently used virtual to physical instruction addresses to increase the speed of address translation; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0169] As described, decode unit 1230 includes DSP instruction decode circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops," and execution unit 1240 includes DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. Writeback / retirement unit 1250 retires executed instructions and writes back the results.

[0170] Embodiments for adding packed data elements using rotation and halving

[0171] One embodiment of the present invention includes an instruction for performing a vector signed add of packed words (16-bit data elements) with rotation and optional halving. Specifically, one embodiment includes a vector signed ADD of words in each of two packed data registers with a rotation of the data element in the second source register specified by bits in the immediate value (e.g., 0°, 90°, 180°, or 270° as indicated by imm8[1:0]). As used herein, an ADD operation refers to the addition or subtraction of two positive numbers, where a negative packed data value is added to a positive value. Depending on the implementation, the result can be halved based on the additional immediate value bits (e.g., halved if imm8[2] is set) and the result is written to the corresponding word location in the packed destination register, such as xmm1. One specific implementation of this instruction is referred to herein as VPCADDROTSRAWxmm1,xmm2,xmm3 / m128,imm8.

[0172] In one embodiment, the xmm1, xmm2, and xmm3 registers are 128-bit packed data registers that store a double quadword value, four doubleword values, or eightword values, and xmm3 / m128 indicates that the corresponding 128-bit source value can be retrieved from memory or a register (xmm3). Although certain embodiments described herein operate on complex word values, the underlying principles of the invention can be implemented with complex and non-complex values ​​and other packed data sizes, including, for example, quadwords, doublewords, or bytes. The complex addition operations described herein can be used for various types of operations, including, but not limited to, Q15 radix-4 fast Fourier transform (FFT) calculations.

[0173] Figure 13 The diagram illustrates exemplary data elements and bit distributions for exemplary source and / or destination registers (SRCx / DESTx). As illustrated, data elements can be packed into the source and / or destination registers as words (16 bits), doublewords (32 bits), and / or quadwords (64 bits). In some embodiments processing complex numbers, the real and imaginary parts can be stored in adjacent data element positions. For example, the real part can be stored as data element A, and the corresponding imaginary part can be stored as data element B. However, in some embodiments described herein, packed data elements AH can represent all complex numbers or all real numbers.

[0174] Figure 14 An exemplary architecture for instructions that implement the addition of packed complex numbers with rotations and (optional) halving is illustrated. The complex numbers may be stored in source registers SRC1 1401 and SRC2 1402, shown as packed data elements AH. In one embodiment, adder networks 1410-1411 implement eight concurrent ADD operations, adding a word value selected from SRC1 1401 to a word value selected from SRC2 1402. Different packed data values ​​may be routed to the appropriate adder circuits by input multiplexer 1403.

[0175] In one embodiment, the immediate value of the instruction includes a first set of one or more control bits for selecting the data elements to be added from each source register 1401-1402. For example, a two-bit field of the immediate value (e.g., imm8[1:0]) can specify each packed complex word in the first source register 1401 to be added to / subtracted from each packed complex word in the first source register 1401. In one implementation, the immediate value of the instruction includes a second set of one or more control bits for indicating whether the result of each addition / subtraction operation is halved (e.g., if imm8[2]=1, the result is halved). The result is then stored in a packed data element position in the SRC3 / DEST destination register 1460 that corresponds to the source packed data element position of the first source register.

[0176] One embodiment of the present invention operates according to the following code sequence:

[0177]

[0178]

[0179] Thus, if the first set of immediate bits specifies a first value (e.g., imm8[1:0] == 2'b00), each signed packed word in the first source register 1401 is added to the corresponding signed packed word in the second source register 1402. As used herein, "corresponding" refers to the same packed data element position (e.g., the packed data element in SRC2[15:0] corresponds to the packed data element in SRC1[15:0]). Thus, the ADD operations for the first immediate value include: S1A+S2A, S1B+S2B, S1C+S2C, S1D+S2D, S1E+S2E, S1F+S2F, S1G+S2G, and S1H+S2H.

[0180] If the first set of immediate bits specifies a different value, the signed packed word from the second source register is added to the signed packed word in the second pattern except for the corresponding data element. In one embodiment, the signed packed word in the second source register is rotated by a specified amount based on the immediate bits. This can be implemented in different ways depending on the embodiment.

[0181] In one embodiment, the value in the second source register is physically rotated by a specified amount within the second source register, and the resulting rotated value correctly matches the corresponding data element position in the first source register. That is, after the rotation, the signed packed word in the first source register is simply added to the rotated packed signed word in the corresponding data element position in the second source register (e.g., the word at [15:0] in the first source is added to the rotated word at [15:0] in the second source).

[0182] In an alternative implementation, the "rotation" described herein is a logical rotation, meaning that the data elements are not physically rotated in the second source register prior to the ADD operation. Instead, the packed signed words in the second source register are selected for the ADD operation as if they had been physically rotated within the second source register. The code sequence above uses this representation to indicate the packed words in the second source register based on their original positions, prior to any operations performed by the execution circuitry.

[0183] In short, the underlying principles of the invention are not limited to any particular physical implementation of the instructions described herein. Thus, although the following discussion describes the packed words in the second source register as being rotated prior to the ADD operation, the rotation may be a physical rotation or a logical rotation as discussed above.

[0184] In one embodiment, the second value (e.g., imm8[1:0] == 2'b01) is then rotated 90° in the signed packed word in the second source register 1402 before the addition / subtraction operation is performed. As indicated by the code sequence above, rotating the value 90° in the second source register before the addition / subtraction results in the following operations: S1A-S2B, S1B+S2A, S1C-S2D, S1D+S2C, S1E-S2F, S1F+S2E, S1G-S2H, and S1H+S2G. Thus, for the immediate value, instead of adding the corresponding data elements in the first and second source registers, the present embodiment changes the sign of every other data element in the second source register starting with element B (i.e., changes the signs of elements B, D, F, and H), and then adds each data element in first source register 1401 to the data element in the adjacent position in second source register 1402 (producing a sum and difference determined for each pair of data elements in SRC 1401 and SRC 1402).

[0185] If the first set of immediate bits specifies a third value (e.g., imm8[1:0] == 2'b10), the signed packed word in the second source register 1402 is rotated 180° before performing the add / subtract operation. As indicated by the code sequence above, rotating the value 180° in the second source register before addition results in the following operations: S1A-S2B, S1B-S2A, S1C-S2D, S1D-S2C, S1E-S2F, S1F-S2E, S1G-S2H, and S1H-S2G. Thus, this embodiment changes the sign of each data element in the second source register (i.e., element AG) and then adds each data element in the first source register 1401 to the corresponding data element in the second source register 1402.

[0186] If the first set of immediate bits specifies a fourth value (e.g., imm8[1:0] == 2'b11), the signed packed word in the second source register 1402 is rotated 270° before the addition operation is performed. As indicated above, rotating the values ​​270° in the second source register 1402 before the addition results in the following operations: S1A + S2B, S1B - S2A, S1C + S2D, S1D - S2C, S1E + S2F, S1F - S2E, S1G + S2H, and S1H - S2G. Thus, this embodiment changes the sign of every other value in the second source register starting with element A (i.e., elements A, C, E, and G), and then adds each data element in the first source register 1401 to the data element in the adjacent position in the second source register 1402.

[0187] As described above, the immediate bit may indicate whether the data elements generated as a result of the above-described ADD operation should be halved before being stored in the destination register 1460. For example, in one embodiment, if imm8[2]=1, then each packed data value produced by the ADD operation is shifted right by 1 bit, resulting in the value being divided by 2 using binary arithmetic.

[0188] The shifted result or the non-shifted result is then routed by output multiplexer 1450 to be stored in a packed data element position in destination register 1460. In one embodiment, the position in the destination is selected to correspond to the data element position in first source register 1401. For example, for an ADD operation involving data element A in SRC1 1401, the result is stored in data element A position in destination register 1460.

[0189] Notice, Figure 14Some components shown in FIG1 , such as multiplier 1405 , accumulation circuits 1420 - 1421 , and saturation circuits 1440 - 1441 , are not necessary to perform the operations described. In this case, it is assumed that data passes through or bypasses these circuits without modification.

[0190] Figure 15 A method according to an embodiment of the present invention is illustrated in FIG. The method can be implemented in the context of the above-mentioned processor and system architecture, but is not limited to any particular system architecture.

[0191] At 1501, an instruction is fetched, the instruction having fields for: an opcode, first and second source operands indicating packed signed words, and a destination operand, and an immediate value. At 1502, the instruction is decoded to generate a first decoded instruction (e.g., into a plurality of micro-operations implementing the rotate, shift, and ADD operations described herein). At 1503, packed signed word values ​​are retrieved (e.g., from memory, a data cache, etc.) for the first and second operands and stored in first and second source registers, respectively. As described, in one embodiment, the signed word values ​​are stored in a 128-bit packed data source register.

[0192] At 1504, the decoded instruction (or, more specifically, the micro-operations generated by the decode) are executed to identify packed signed words in the second source register to be added to the packed signed word in the second source register. The packed signed word values ​​from the second source register can be selected by evaluating certain bits of the immediate value (e.g., imm8[1:0] as described above). For example, if the immediate bits specify a first value, each packed signed word value in the first source register is added to the packed signed word value in the corresponding position in the second source register. If the immediate bits specify a second value, the packed signed word in the second source register is rotated 90° before the addition operation is performed; if the immediate bits specify a third value, the packed signed word in the second source register is rotated 180° before the addition operation is performed; and if the immediate bits specify a fourth value, the packed signed word in the second source register is rotated 270° before the addition operation is performed. As described above, the rotation may require changing the sign and / or position of the data elements.

[0193] At 1505, different portions of the immediate value (e.g., specific bits such as imm8[2]) are evaluated to determine whether the result of each ADD operation is to be halved. If the portion of the immediate value has a first value (e.g., imm8[2]=1), the result is halved at 1506 to generate a second result. As described above, halving the results can include shifting each result right by 1 bit. At 1507, the first or second result is stored as a signed packed word data element in the destination register.

[0194] In the foregoing description, embodiments of the present invention have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

[0195] Embodiments of the present invention may include the various steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by specific hardware components that contain hard-wired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0196] As used herein, instructions may refer to specific configurations of hardware (such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have predetermined functions) or software instructions stored in memory embodied in non-transitory computer-readable media. Thus, the techniques illustrated in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., end stations, network elements, etc.). Such electronic devices use computer-readable media, such as non-transitory computer-readable storage media (e.g., magnetic disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transitory computer-readable communication media (e.g., electrical, optical, acoustical, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.) to store and transmit code and data (internally and / or with other electronic devices over a network). Furthermore, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The collection of processors and other components are typically coupled via one or more buses and bridges (also known as bus controllers). The storage device and the signal carrying the network business represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device generally stores code and / or data for execution on a set consisting of one or more processors of the electronic device. Of course, different combinations of software, firmware and / or hardware can be used to implement one or more parts of the embodiments of the present invention. Throughout this detailed description, for the purpose of explanation, many specific details have been set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without some of these specific details. In some cases, well-known structures and functions have not been described in detail to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be judged according to the following claims.

Claims

1. A processor, comprising: a decoder for decoding an instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register; a first source register for storing a first plurality of packed signed words; a second source register for storing a second plurality of packed signed words; An execution circuit, configured to execute the decoded instruction, the execution circuit comprising: an adder circuit for adding each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuit being configured to select each packed signed word from a second source register based on a rotate value in an immediate value of the instruction, the rotate value being configured to indicate an amount of rotate to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and A destination register is provided for storing the plurality of signed word results in designated data element positions of the destination register.

2. The processor of claim 1 , further comprising: A halving circuit is configured to divide each signed word result into half to generate a halved result if the designated bit of the immediate number has a first value indicating a 0° rotation, wherein the halved result is to be stored in the destination register instead of the plurality of signed word results.

3. The processor of claim 2, wherein: The halving circuit includes a shift circuit configured to right-shift the signed word result by one bit to generate the halved result.

4. A processor as claimed in claim 1 or 3, wherein the packed signed words from the first and second source registers comprise complex values, and wherein rotating comprises changing the sign of one or more of the signed words. 5 . The processor of claim 1 , wherein the rotation value comprises a first value indicating a 0° rotation, a second value indicating a 90° rotation, a third value indicating a 180° rotation, or a fourth value indicating a 270° rotation.

6. The processor of claim 5, wherein if the rotated value includes the first value, each packed signed word from the first source register is to be added to the packed signed word from the corresponding data element position in the second source register.

7. The processor of claim 6 , wherein if the rotated value includes the second value, each packed signed word from the first source register is added to the packed signed word from the adjacent data element position in the second source register, and wherein the signs of half of the packed signed words in the second source register are changed.

8. The processor of claim 7 , wherein if the rotated value includes the third value, each sign of each packed signed word from the second source register is changed, and each packed signed word from the first source register is added to the packed signed word from the second source register at the corresponding data element position with the changed sign.

9. The processor of claim 8 , wherein if the rotated value includes the fourth value, each packed signed word from the first source register is added to the packed signed word from the adjacent data element position in the second source register, and wherein the signs of different halves of the packed signed words in the second source register are changed.

10. A method for adding packed data elements using rotation and halving, comprising: decoding the instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register; storing a first plurality of packed signed words in a first source register; storing a second plurality of packed signed words in a second source register; adding each packed signed word from the first source register to selected packed signed words from the second source register to generate a plurality of signed word results, selecting each packed signed word for addition from the second source register based on a rotate value in an immediate value of the instruction, the rotate value indicating an amount of rotation to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and The plurality of signed word results are stored in designated data element positions of a destination register.

11. The method of claim 10, further comprising: If the designated bits of the immediate value have a first value indicating a 0° rotation, each signed word result is divided in half to generate a halved result, wherein the halved results are to be stored in the destination register instead of the plurality of signed word results.

12. The method of claim 11, wherein: Dividing includes right shifting the signed word result by 1 bit to generate the halved result.

13. The method of claim 10 or 12, wherein the packed signed words from the first and second source registers comprise complex values, and wherein rotating comprises changing the sign of one or more of the signed words.

14. The method according to claim 10, wherein: The rotation value includes a first value indicating a 0° rotation, a second value indicating a 90° rotation, a third value indicating a 180° rotation, or a fourth value indicating a 270° rotation.

15. The method of claim 14, wherein if the rotated value includes the first value, each packed signed word from the first source register is added to the packed signed word from the corresponding data element position in the second source register.

16. The method of claim 15 , wherein if the rotated value includes the second value, each packed signed word from the first source register is added to the packed signed word from the adjacent data element position in the second source register, and wherein the signs of half of the packed signed words in the second source register are changed.

17. The method of claim 16 , wherein if the rotated value includes the third value, each sign of each packed signed word from the second source register is changed, and each packed signed word from the first source register is added to the packed signed word from the second source register having the changed sign at the corresponding data element position.

18. The method of claim 17 , wherein if the rotated value includes the fourth value, each packed signed word from the first source register is added to the packed signed word from the adjacent data element position in the second source register, and wherein the signs of different halves of the packed signed words in the second source register are changed.

19. A machine-readable medium having program code stored thereon, the program code, when executed by a processor, causing the processor to perform the following operations: decoding the instruction to generate a decoded instruction, the instruction including an opcode, an immediate value, and an operand identifying a plurality of packed data source registers and a packed data destination register; storing a first plurality of packed signed words in a first source register; storing a second plurality of packed signed words in a second source register; adding each packed signed word from the first source register to selected packed signed words from the second source register to generate a plurality of signed word results, selecting each packed signed word for addition from the second source register based on a rotate value in an immediate value of the instruction, the rotate value indicating an amount of rotation to be applied to the packed signed words in the second source register before the adder circuit performs the addition; and The plurality of signed word results are stored in designated data element positions of a destination register.

20. The machine-readable medium of claim 19, further comprising program code for causing the processor to: If the designated bits of the immediate value have a first value indicating a 0° rotation, each signed word result is divided in half to generate a halved result, wherein the halved results are to be stored in the destination register instead of the plurality of signed word results.

21. The machine-readable medium of claim 20, wherein: Dividing includes right shifting the signed word result by 1 bit to generate the halved result.

22. The machine-readable medium of claim 19, wherein the packed signed words from the first and second source registers comprise complex values, and wherein rotating comprises changing the sign of one or more of the signed words.

23. The machine-readable medium of claim 19 or 22, wherein the rotation value comprises a first value indicating a 0° rotation, a second value indicating a 90° rotation, a third value indicating a 180° rotation, or a fourth value indicating a 270° rotation.

24. The machine-readable medium of claim 23, wherein if the rotated value includes the first value, each packed signed word from the first source register is to be added to the packed signed word from the corresponding data element position in the second source register.

25. The machine-readable medium of claim 24 , wherein if the rotated value includes the second value, each packed signed word from the first source register is added to the packed signed word from the adjacent data element position in the second source register, and wherein the signs of half of the packed signed words in the second source register are changed.

26. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 10 to 18.

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