Printed circuit boards (PCBs) with three-dimensional interconnections to other printed circuit boards

Abstract

A system for a three-dimensional ("3D") printed circuit board ("PCB") to PCB interface is provided. A first PCB includes a first landing pad disposed on one or more edges of the first PCB. The first landing pad is electrically coupled to a conductive pin or a second landing pad disposed on a second PCB. The second landing pad can be disposed in a slot in the second PCB. The interface between the first landing pad and the second landing pad can provide various advantages over conventional PCB-to-PCB interfaces, such as improved signal integrity, improved power integrity, increased contact density, reduced clock jitter, and the like.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for three-dimensional printed circuit board to printed circuit board interconnection. Background Art

[0002] Existing random access memory ("RAM") modules include a memory die mounted on a printed circuit board ("PCB"). The RAM module PCB typically includes landing pads on both the front and rear surfaces and is used to make electrical connections to the motherboard PCB. Electrical connections to the motherboard PCB are typically made by mounting the RAM module PCB orthogonally on the motherboard PCB between conductive pins, allowing the conductive pins to make contact with the landing pads on the front and rear surfaces of the RAM module PCB. The motherboard's conductive pins are stamped pins and can be solder mounted to landing pads (in sockets) on the motherboard PCB. The conductive pins can also be mounted to the motherboard PCB using through-holes.

[0003] These prior art techniques negatively impact the signal integrity and power integrity between the motherboard PCB and the RAM module PCB. For example, both conductive pins and vias extend the electrical path between the two PCBs, thereby introducing discontinuities, crosstalk, and transmission line losses into the electrical path. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Features and advantages of various embodiments of the claimed subject matter will become apparent from the following detailed description and with reference to the accompanying drawings, in which like numerals represent like parts, and in which:

[0005] Figure 1A 、 1B , 1C, 1D, 1E, and 1F are diagrams depicting views of an illustrative system employing a three-dimensional ("3D") printed circuit board ("PCB") interface between two or more PCBs according to one embodiment;

[0006] Figure 2A 、 2B and 2C are diagrams depicting views of an illustrative system employing a 3D PCB interface between two or more PCBs according to one embodiment;

[0007] Figure 3A and 3B is a diagram depicting a view of an illustrative system including edge-to-edge connections interfacing with a 3D PCB according to one embodiment;

[0008] Figure 4A 、 4B and 4C are diagrams depicting views of an illustrative system including edge-to-edge connections interfacing with a 3D PCB according to one embodiment;

[0009] Figure 5 is a diagram depicting a view of an illustrative system including edge-to-edge connections interfacing with a 3D PCB according to one embodiment;

[0010] Figure 6 is a graph illustrating potential crosstalk improvements from implementation of the disclosed 3D PCB interface, according to one embodiment;

[0011] Figure 7 is a graph illustrating potential signal reflection improvements from an implementation of the disclosed 3D PCB interface, according to one embodiment;

[0012] Figure 8 is a high-level flow chart of an illustrative method for manufacturing a printed circuit board having 3D interconnects to other printed circuit boards, according to one embodiment; and

[0013] Figure 9 is a block diagram of an illustrative processor-based device including at least one 3D PCB interface according to one embodiment.

[0014] Although the following detailed description will proceed with reference to exemplary embodiments thereof, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. DETAILED DESCRIPTION

[0015] Disclosed herein is a system for a three-dimensional ("3D") printed circuit board ("PCB") to printed circuit board interface. A first PCB includes a first landing pad disposed on one or more edges of the first PCB. The first landing pad is electrically coupled to a conductive pin or a second landing pad disposed on a second PCB. The second landing pad can be disposed in a slot in the second PCB. The first PCB can be a daughter card or a PCB for a communication cable. The second PCB can be a motherboard. According to various embodiments, the first and second PCBs can be coupled together orthogonally (e.g., edge to surface) or coplanarly (e.g., edge to edge). The interface between the first landing pad and the second landing pad can provide various advantages over conventional PCB to PCB interfaces, such as improved signal integrity, improved power integrity, increased contact density, reduced clock jitter, etc.

[0016] Figure 1A 、 1B, 1C, 1D, 1E, and 1F show various views of a system 100 for employing a three-dimensional ("3D") printed circuit board ("PCB") interface between two or more PCBs according to one embodiment. The system 100 may correspond to a computing device, including but not limited to a server, a workstation computer, a desktop computer, a laptop computer, a tablet computer (e.g., iPad®, Galaxy Tab®, etc.), an ultraportable computer, an ultramobile computer, a netbook computer, and / or a sub-notebook computer; a mobile phone, including but not limited to a smartphone (e.g., iPhone®, an Android®-based phone, a BlackBerry®-based phone, a Symbian®-based phone, a Palm®-based phone, etc.), and / or a feature phone.

[0017] Figure 1A An illustrative perspective view of a system 100 for a 3D PCB interface, according to one embodiment, is depicted. According to one embodiment, system 100 includes a first PCB 102 coupled to a second PCB 104 using a 3D PCB interface. According to one embodiment, first PCB 102 is a daughter card that carries a plurality of memory die 106 and is configured as interchangeable random access memory ("RAM") memory modules (e.g., single or dual in-line memory modules ("SIMMs" or "DIMMs")). According to one embodiment, second PCB 104 is a motherboard that is configured to physically and electrically couple to first PCB 102 to access and communicate with the plurality of memory die 106. According to one embodiment, the 3D PCB interface employed by system 100 uses one or more edges of first PCB 102 to electrically couple first PCB 102 to second PCB 104. According to one embodiment, using the edges of first PCB 102 to electrically couple first PCB 102 to second PCB 104 results in a shorter electrical connection than conventional RAM memory module interconnects. According to various embodiments, the disclosed 3D PCB interface may improve signal integrity, power integrity, noise immunity, context density, and PCB routing flexibility.

[0018] In accordance with one embodiment, the plurality of memory dies 106 may be RAM, or may be persistent storage devices, such as an SSD. In accordance with one embodiment, each of the plurality of memory dies 106 may be a single memory die. In accordance with one embodiment, the plurality of memory dies 106 may include non-volatile memory, for example, a storage medium that does not require power to maintain a data state stored by the storage medium. The plurality of memory dies 106 may include, but are not limited to, NAND non-volatile memory (e.g., single-level cell (“SLC”), multi-level cell (“MLC”), quad-level cell (“QLC”), triple-level cell (“TLC”), or some other NAND), NOR memory, solid-state memory (e.g., planar or three-dimensional (3D) NAND non-volatile memory or NOR non-volatile memory), a memory device using a sulfide phase change material (e.g., chalcogenide glass), a byte-addressable non-volatile memory device, a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (“SONOS”) memory, a polymer memory (e.g., a ferroelectric polymer memory), a byte-addressable random-access 3D XPoint memory device. TM memory, ferroelectric transistor random access memory ("Fe-TRAM"), magnetoresistive random access memory ("MRAM"), phase change memory ("PCM", "PRAM"), resistive memory, ferroelectric memory ("F-RAM", "FeRAM"), spin transfer torque memory ("STT"), thermally assisted switching memory ("TAS"), millisecond memory, floating junction gate memory ("FJG RAM"), magnetic tunnel junction ("MTJ") memory, electrochemical cell ("ECM") memory, binary oxide filament cell memory, interface switch memory, battery-backed RAM, transistor memory, nanowire memory, electrically erasable programmable read-only memory ("EEPROM"), etc. In some embodiments, byte-addressable random access 3D XPoint TM The memory according to various embodiments may include a transistor-free stackable crossbar structure, where memory cells are located at the intersection of word lines and bit lines and are individually addressable, and where bit storage is based on changes in bulk resistance.

[0019] Figure 1BAn exemplary bottom-referenced exploded view of system 100 is depicted. According to one embodiment, first PCB 102 includes a first surface 108 and a second surface 110 laterally opposed to first surface 108. According to one embodiment, first surface 108 is separated from second surface 110 by a thickness 112 that forms an edge around the perimeter of first surface 108. According to one embodiment, the edge includes a bottom edge 114, a top edge 116, a left edge 118, and a right edge 120. According to one embodiment, the bottom, top, left, and right orientations are used for ease of simplicity and description of system 100 and may vary based on various different orientations that may be applied to first PCB 102 and second PCB 104. According to one embodiment, bottom edge 114 may be a first edge, top edge 116 may be a second edge, left edge 118 may be a third edge, and right edge 120 may be a fourth edge, which together form the perimeter of first surface 108 and second surface 110.

[0020] According to one embodiment, first PCB 102 includes a plurality of landing pads 122 disposed on bottom edge 114 for electrically coupling first PCB 102 to second PCB 104. According to one embodiment, plurality of landing pads 122 are electrically coupled to one or more conductive traces or conductive planes of first PCB 102. As used herein, according to one embodiment, "a plurality of landing pads disposed on an edge and electrically coupled to one or more conductive traces or conductive planes of a printed circuit board" means that the plurality of landing pads (e.g., plurality of landing pads 122) are electrically coupled to conductive traces, electrically coupled to conductive planes, or electrically coupled to both conductive traces and conductive planes of a printed circuit board (e.g., first PCB 102). In one embodiment, some or all of plurality of landing pads 122 are electrically coupled to one or more traces located on first surface 108 and / or located on second surface 110. In one embodiment, some or all of the plurality of landing pads 122 are electrically coupled to one or more conductive planes disposed between the first surface 108 and the second surface 110. In one embodiment, some or all of the plurality of landing pads 122 are electrically coupled to one or more conductive traces disposed between the first surface 108 and the second surface 110. In one embodiment, the one or more conductive planes disposed between the first surface 108 and the second surface 110 include, but are not limited to, a voltage plane, a ground plane, and a reference plane. According to one embodiment, the one or more conductive traces or planes are electrically coupled to the plurality of memory dies 106 and / or to other components mounted to and / or carried by the first PCB 102. Thus, according to one embodiment, the plurality of landing pads 122 are electrically coupled (via the one or more conductive traces or planes) to the plurality of memory dies 106 and / or other components mounted to and / or carried by the first PCB 102.

[0021] According to one embodiment, a plurality of landing pads 122 may replace or supplement the plurality of landing pads 124 disposed on first surface 108 and second surface 110 (not shown). The plurality of landing pads 124 represents a simplified example of landing pads typically found on a conventional random access memory ("RAM") dual in-line memory module ("DIMM"). According to one embodiment, the plurality of landing pads 124 may be disposed on first surface 108 and / or second surface 110. According to one embodiment, the plurality of landing pads 124 are contacted via conductive pins 126. Conductive pins 126 are mechanically raised pins that couple to first PCB 102 in two dimensions ("2D"). That is, conductive pins 126 couple to first PCB 102 along first surface 108 and second surface 110. According to one embodiment, conductive pins 126 are typically formed from stamped metal and attached to second PCB 104 through holes 128 and vias 130. The holes 128 pass through the second PCB 104 and enable the conductive pins 126 to be electrically coupled to one or more conductive traces and / or conductive planes of the second PCB 104 .

[0022] The configuration of the conductive pins 126 and the vias 130 is relatively standardized within the RAM DIMM manufacturing industry. However, the length, width, thickness, proximity to other pins, and other characteristics of the conductive pins 126 and vias 130 increase the signal path from the second PCB 104 to the first PCB 102 and to the plurality of memory dies 106 and may introduce undesirable signal characteristics. Examples of undesirable signal characteristics introduced by the conventional configuration of the conductive pins 126 include, but are not limited to, reflections, bandwidth limitations, signal distortion, crosstalk, and other transmission line losses. As described below, according to one embodiment, the use of the landing pads 122 provides superior signal integrity, signal noise, and other signal characteristics compared to the conductive pins 126. Additionally, according to one embodiment, the characteristics and functionality of the plurality of landing pads 122 may enhance the operational characteristics of the conductive pins 126.

[0023] According to one embodiment, the plurality of conductive pins 126 may be held in place, heat sunk, or otherwise supported by the shield 131 .

[0024] According to one embodiment, bottom edge 114 can be electrically coupled to second PCB 104 via a plurality of conductive pins 132 disposed between landing pads on the second PCB and landing pads 122. According to one embodiment, conductive pins 132 are cylindrical pins and can be secured to landing pads on second PCB 104 or to landing pads 122 on first PCB 102. According to one embodiment, conductive pins 132 have a length 134 that is significantly less than a length 136 of conductive pins 126. According to one embodiment, the shorter length of conductive pins 132 reduces electromagnetic reflections, reduces near-end crosstalk, reduces far-end crosstalk, reduces transmission line losses, and reduces the distance of the signal path between second PCB 104 and first PCB 102.

[0025] According to one embodiment, the first PCB 102 may further include one or more additional landing pads disposed on one or more of the other edges of the first PCB 102. For example, according to one embodiment, the first PCB 102 may include a landing pad 138 disposed on the left edge 118 to provide additional electrical coupling between the first PCB 102 and the second PCB 104. According to one embodiment, the conductive pins 140 may electrically couple the second PCB 104 to the first PCB 102 via the landing pad 138.

[0026] Figure 1C An illustrative top-referenced exploded view of system 100 is depicted, according to one embodiment. The top-referenced exploded view of system 100 illustrates a slot 142 into which first PCB 102 may be inserted, according to one embodiment. Inserting first PCB 102 into slot 142 of second PCB 104 provides structural support for the physical interface between first PCB 102 and second PCB 104, according to one embodiment. Second PCB 104 includes a plurality of landing pads 144 carrying conductive pins 132, according to one embodiment. Conductive pins 132 may be attached to, or compressed by, the plurality of landing pads 144 to establish electrical coupling between first PCB 102 and second PCB 104 along bottom edge 114 and slot 142, according to one embodiment.

[0027] According to one embodiment, landing pads 122, conductive pins 132, and landing pads 144 enable direct connection between one or more conductive planes 146 and one or more conductive planes 148. According to one embodiment, one or more conductive planes 146 represent one or more of a voltage plane, a ground plane, and a reference plane disposed within the thickness of second PCB 104. According to one embodiment, one or more conductive planes 148 represent one or more of a voltage plane, a ground plane, and a reference plane disposed within the thickness of first PCB 102.

[0028] Figure 1D An illustrative partial side view of system 100 is depicted in accordance with one embodiment. The illustrative side view of system 100 shows first PCB 102 inserted into slot 142 of second PCB 104 in accordance with one embodiment. Also shown is one of landing pads 122 coupled to one of conductive pins 132, which is coupled to one of landing pads 144 to provide 3D electrical coupling between first PCB 102 and second PCB 104 in accordance with one embodiment.

[0029] Figure 1E An illustrative partial perspective view of a first PCB 102 interconnected to a second PCB 104 via a landing pad 122 is depicted according to one embodiment. According to one embodiment, the landing pad 122 may be connected to one or more planes 148 ( Figure 1C According to one embodiment, the plurality of conductive fingers may partially extend through the first surface 108 ( Figure 1D ) and the second surface 110 ( Figure 1D ) between the first PCB 102.

[0030] Figure 1F An illustrative exploded view of one or more planes 146 peeled away from the rest of the second PCB 104 and one or more planes 148 peeled away from the rest of the first PCB 102 is depicted in accordance with one embodiment. According to one embodiment, the conductive pins 132 are connected or coupled to the one or more planes 146, and the landing pads 122 are connected to conductive fingers 150, which are used to electrically couple the one or more planes 148 to the landing pads 122. Although the one or more planes 146 and 148 are depicted as planes, in one embodiment, the one or more planes 146 and the one or more planes 148 are trace patterns integrated within the first PCB 102 and / or the second PCB 104, which, in accordance with one embodiment, are used to route signals between components on the second PCB 104 to components on the first PCB 102. Unlike conventional PCB-to-PCB connections, according to one embodiment, Figure 1F The embodiment depicted in provides a common and unified reference plane between the first PCB 102 (eg, a daughter card) and the second PCB 104 (eg, a female port).

[0031] Among other things, Figures 1A-1FEmbodiments of the disclosed 3D PCB interface (and the embodiments described below) can provide numerous advantages in technical areas such as PCB layout, PCB routing, PCB-to-PCB interfacing, component-to-PCB interfacing, signal integrity, and noise control. According to various embodiments, specific advantages that can be achieved through the disclosed 3D PCB interface embodiments include, but are not limited to, signal integrity, power integrity, noise immunity, context density, PCB routing flexibility, and the potential for reduced PCB form factor.

[0032] Some features of the disclosed embodiments improve signal integrity in PCB-to-PCB interfaces. For example, one or more conductive planes 148 may include a unified reference plane, which can reduce or mitigate reflections and crosstalk caused by the lack of a reference plane. Reference planes are rarely used in the prior art, even in prior art card edge connectors used in the industry. Therefore, according to one embodiment, multiple landing pads 122 enable the inclusion and electrical coupling to one or more conductive planes 148, which can reduce reflections and crosstalk.

[0033] Furthermore, according to various embodiments, the plurality of landing pads 122 enable more "direct connections" between PCBs, between a package and a PCB, and between a PCB and a cable. This direct connection reduces the use of vias and conductive pins similar to conductive pins 126. Reducing the use of vias and reducing the use of conductive pins similar to conductive pins 126 can result in shorter signal paths, which leads to reduced crosstalk and reduced reflections.

[0034] The physical properties of conductors used in signal paths for high-frequency signals can affect power integrity. Generally, the capacitance of a conductor increases with width, the capacitance of a conductor increases with width, and the resistance of a conductor increases with width. Conductive pins 126 are manufactured to be narrow to enable multiple signals to and from the RAM DIMM. The narrow dimensions of conductive pins 126 during use are typically very inductive and highly resistive. When conductive pins 126 are used for power delivery, their inductance influences and exacerbates simultaneous switching noise, resulting in significant dynamic voltage (IR) drop in the power delivery network (PDN). When conductive pins 126 are used for power delivery, their high resistance causes a significant static IR drop. The adverse effects of the inductance of conductive pins 126 are exacerbated when contact is made with a landing pad (e.g., landing pad 124). Because the landing pad 124 is wide, the landing pad 124 will have a higher capacitance than the conductive pin 126 , and the combination of the capacitance of the landing pad 124 and the inductance of the conductive pin 126 may cause resonance in the PDN, which may require additional decoupling caps to improve.

[0035] According to various embodiments, the landing pad 124 and the one or more conductive planes 148 provide a wider contact with less resistance, less inductance, and reduced / eliminated landing pad inductance compared to using pins such as the conductive pin 126 to provide power to the first PCB 102 to produce improved PDN power integrity over existing techniques.

[0036] In traditional PCB-to-PCB connections or in traditional cable-to-PCB connections, arranging noise-sensitive nets, such as the voltage reference net and crystal input / output nets used in Double Data Rate ("DDR") RAM, is difficult. Because clock / crystal signals and voltage references are routed adjacent to rapidly changing control and data signals, clock jitter and voltage reference corruption remain persistent issues for DDR RAM operation and represent a limitation to increasing the speed of clock, control, and data signals. According to various embodiments, the disclosed 3D PCB interface enables the separation / isolation of noise-sensitive nets (e.g., clock and voltage reference) from high-speed signals, which physically enhances the connection's noise immunity.

[0037] Existing solutions for mitigating crosstalk involve including more pins between one PCB and another to reduce the signal-to-ground ratio in the connector. More pins lead to greater congestion in the area beneath the connector. To alleviate routing congestion, larger connectors are employed, which can impose additional routing difficulties on the PCB layout. The disclosed 3D PCB interface utilizes contact pads (e.g., landing pads 122) in relatively unused areas of the PCB board (e.g., bottom edge 114), thereby adding more contact points without increasing routing congestion on the PCB board.

[0038] According to one embodiment, the disclosed 3D PCB interface enables signals to be sent to planes parallel to the top and bottom of the PCB as well as planes orthogonal to the top and bottom of the PCB, thereby improving PCB routing flexibility.

[0039] The disclosed 3D PCB interface (e.g., landing pads 122, conductive fingers 150, and / or one or more conductive planes 148) increases the total number of contacts between the first PCB 102 and the second PCB 104 while maintaining the same form factor. Thus, according to one embodiment, more electrical contacts per unit volume can be achieved without increasing the size of existing PCBs. By employing the disclosed 3D PCB interface, maintaining the same number of contacts as used on existing PCB packages results in a reduced size of the PCB package because more contacts are available per unit volume.

[0040] Figure 2A 、 2BFigures 2C and 2C illustrate perspective views of a PCB 200 having a 3D PCB interface according to another embodiment. According to one embodiment, PCB 200 can be used as an electrical connector for, for example, a cable interface between a motherboard and one or more peripheral devices. According to various embodiments, PCB 200 provides multi-dimensional connectivity that can be used in connectors for various communication standards, including, but not limited to, SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), PCIe (Peripheral Component Interconnect Express), NVMe (Non-Volatile Memory Express), SATA (Serial ATA), USB, and FireWire.

[0041] According to one embodiment, PCB 200 includes a first surface 202 laterally opposed to a second surface 204. According to one embodiment, second surface 204 is separated from first surface 202 by a thickness 206 that forms an edge about the periphery of PCB 200 between first surface 202 and second surface 204. According to one embodiment, PCB 200 may include a first edge 208, a second edge 210, and a third edge 212. According to one embodiment, first edge 208 may include a first conductive plane 214 that may be coupled to a plurality of landing pads 216. According to one embodiment, first conductive plane 214 may be a side power plane, and the plurality of landing pads 216 may be top power landing pads. According to one embodiment, second edge 210 may include a second conductive plane 218 electrically coupled to a plurality of landing pads 220. According to one embodiment, second conductive plane 218 may be a side ground plane, and the plurality of landing pads 220 may be top ground landing pads. According to one embodiment, a plurality of landing pads 220 may be disposed between a plurality of landing pads 221, which are configured to provide, for example, a high-speed input / output ("HSIO") interface. According to one embodiment, interleaving the ground landing pads 220 between the plurality of landing pads 221 may reduce crosstalk between signals carried by the plurality of landing pads 221. According to one embodiment, the third edge 212 may include a third plane 222 electrically coupled to the plurality of landing pads 224. According to one embodiment, the third plane 222 and the plurality of landing pads 224 may be used to couple a sensitivity net between the PCB 200 and a mainboard.

[0042] Figure 2CA partially transparent illustration of a PCB 200 according to one embodiment is depicted to illustrate multiple internal conductive planes that may be provided within PCB 200. According to one embodiment, the multiple internal conductive planes may be coupled from the periphery of PCB 200 to landing pads (e.g., landing pads 216, 220, 221, 224) and side conductive planes (e.g., conductive planes 214, 218, 222). According to one embodiment, PCB 200 includes a first internal conductive plane 226, a second internal conductive plane 228, a third internal conductive plane 230, and a fourth internal conductive plane 232. According to various embodiments, each of the first, second, third, and fourth internal conductive planes 226, 228, 230, and 232 may be implemented as a power plane, a ground plane, a reference plane, a sensitive net plane, etc. According to various embodiments, more or fewer planes may be provided within PCB 200.

[0043] Figure 3A and 3B A diagram of a system 300 according to one embodiment is depicted that includes multiple edge-to-edge connections between PCB 200 and PCB 302. According to various embodiments, various peripheral conductive planes and landing pads of PCB 200 can interface with one or more conductive planes 304 disposed within PCB 302. According to one embodiment, the conductive planes of PCB 200 can be coupled to the one or more conductive planes 304 via a plurality of conductive pins 306.

[0044] Figure 4A 、 4B4C depict an illustration of a system 400 including a first PCB 402 electrically and physically coupled to a second PCB 404 using 3D edge-to-edge coupling, consistent with embodiments of the present disclosure. According to one embodiment, the first PCB 402 has a first surface 406 laterally opposed to a second surface 408 and separated by a thickness between the first surface 406 and the second surface 408, forming an edge around the perimeter of the first PCB 402. System 400 illustrates that, according to one embodiment, both edges of the first PCB 402 can be used to interface with the second PCB 404. System 400 also illustrates that, according to one embodiment, the first PCB 402 can interface with the second PCB 404 within a recess 410 formed in the second PCB 404. According to one embodiment, the first PCB 402 can be coupled to the second PCB 404 via a plurality of conductive pins 412. According to one embodiment, the first PCB 402 can include a plurality of landing pads 414 disposed along a first edge 416 and can include a plurality of landing pads 418 disposed along a second edge 420. According to one embodiment, plurality of landing pads 414 may perform a first function (eg, power, ground, HSIO) and plurality of landing pads 418 may perform a second function (eg, power, ground, HSIO) for first PCB 402 .

[0045] Figure 5 A diagram of a system 500 is depicted, which includes a first PCB 502 electrically and physically coupled to a second PCB 504 using 3D edge-to-edge coupling, consistent with an embodiment of the present disclosure. According to one embodiment, the second PCB 504 includes one or more conductive planes 506 and landing pads 507, to which the first PCB 502 is electrically coupled using landing pads 508. According to one embodiment, the second PCB 504 includes a recess into which the first PCB 502 can be inserted. According to one embodiment, the first PCB 502 includes a first edge 514 electrically coupled to a first edge 516 of the second PCB 504 via the landing pads 507 and 508. The system 500 illustrates that according to one embodiment, one edge of the first PCB 502 can be used to interface with the second PCB 504.

[0046] The first PCB 502 may include one or more fastening mechanisms to maintain the first PCB 502 in electrical connection with the second PCB 504. In one embodiment, the fastening mechanisms enable the first PCB 502 to mate with the second PCB 504 by sliding along one axis (e.g., the X-axis) while restricting movement of the first PCB 502 along other axes. According to one embodiment, the first PCB 502 may include a first hole 518 and a second hole 520 that couple or mate with a ball detent or other fastening mechanism that reduces the likelihood of the first PCB inadvertently sliding away from the second PCB 504. Although not explicitly shown in the figures for other PCB-to-PCB interfaces, it should be understood that, according to various embodiments, any of the disclosed fastening mechanisms or another type of mechanical connector / connection or other mechanical fastening mechanism may be implemented with any of the disclosed embodiments of the PCB-to-PCB interface.

[0047] Figure 6 Graph 600 is an illustrative example of potential crosstalk improvements that can be achieved by adding the disclosed 3D PCB interface (e.g., edge landing pads) to a RAM DIMM, according to one embodiment. Graph 600 includes an x-axis representing frequency and a y-axis representing crosstalk (measured in decibels ("dB")). According to one implementation, the difference in crosstalk (e.g., for a cross-channel signal aggressor) between signal m3 (using a conventional DIMM connector) and signal m4 (using the disclosed 3D PCB interface) in a DIMM is approximately 59 dB at approximately 2.67 gigahertz ("GHz"). FEXT (far-end crosstalk) is crosstalk measured at the receiver end of a signal's propagation relative to an aggressor.

[0048] Figure 7 Graph 700 is an exemplary graph illustrating signal reflection reduction that can be achieved for a DIMM implementing techniques consistent with the present invention. Graph 700 includes an x-axis representing frequency and a y-axis representing reflection (measured in dB). According to one implementation, the difference in reflection between signal m1 (using a conventional DIMM connector) and signal m2 (using the disclosed 3D PCB interface) in a DIMM is approximately 1.3 dB at approximately 2.67 gigahertz ("GHz").

[0049] Figure 8 is a high-level logical flow diagram of an exemplary method 800 for fabricating a printed circuit board having 3D interconnects with other printed circuit boards, according to at least one embodiment described herein. The method begins at operation 802 .

[0050] At operation 804 , according to one embodiment, method 800 includes forming a printed circuit board having a first surface and a second surface laterally opposite the first surface and spaced apart from the first surface by a thickness forming an edge.

[0051] At operation 806 , method 800 includes providing a plurality of landing pads on an edge of a printed circuit board, according to one embodiment.

[0052] Method 800 ends at operation 808 .

[0053] Figure 9 is a block diagram of an exemplary processor-based device 900 equipped with a semiconductor package according to at least one embodiment described herein, including at least one 3D PCB interface (such as described above with reference to Figures 1A to 5 The following detailed description provides a brief, general description of the components that form an exemplary processor-based device 900, such as a smartphone, a wearable computing device, a portable computing device, or a similar device using semiconductor packaging, which includes a first PCB (e.g., PCB 102) and a second PCB (e.g., PCB 104) for facilitating communication between the first PCB (e.g., PCB 102) and the second PCB (e.g., PCB 104). Figures 1A to 5 At least one 3D PCB interface of any one of the features shown.

[0054] The processor-based device 900 includes a processor circuit 910 capable of executing a set of machine-readable instructions, reading data from a storage device 930, and writing data to the storage device 930. Those skilled in the relevant art will appreciate that the illustrated embodiments, as well as other embodiments, may be practiced with other circuit-based device configurations, including portable electronic or handheld electronic devices such as smartphones, portable computers, wearable computers, microprocessor-based or programmable consumer electronics, personal computers ("PCs"), network PCs, minicomputers, mainframe computers, and the like.

[0055] The processor circuit 910 may include any number of hardwired or configurable circuits, some or all of which may include programmable and / or configurable combinations of electronic components, semiconductor devices, and / or logic elements that are partially or entirely provided in a PC, server, or other computing system capable of executing machine-readable instructions. The processor-based device 900 includes the processor circuit 910 and a bus or similar communication link 916 that communicatively couples and facilitates the exchange of information and / or data between various system components, including system memory 920, one or more rotating data storage devices 930, and / or one or more solid-state storage devices 932. The processor-based device 900 may be referred to herein in the singular, but this is not meant to limit the embodiments to a single device and / or system, as in some embodiments, there will be more than one processor-based device 900 incorporating, including, or containing any number of communicatively coupled, parallel, or remotely networked circuits or devices.

[0056] Processor circuit 910 may include any number, type, or combination of devices. Sometimes, processor circuit 910 may be implemented in whole or in part in the form of semiconductor devices, such as diodes, transistors, inductors, capacitors, and resistors. Such implementations may include, but are not limited to, any currently or future developed single or multi-core processors or microprocessors, such as: one or more systems on a chip (SOC); central processing units (CPUs); digital signal processors (DSPs); graphics processing units (GPUs); application-specific integrated circuits (ASICs), programmable logic units, field-programmable gate arrays (FPGAs), etc. Unless otherwise specified, Figure 9 The architecture and operation of the various blocks shown in FIG9 are of conventional design. Therefore, further detailed description of these blocks is not required herein as they are understood by those skilled in the relevant art. The communication link 916 interconnecting at least some components of the processor-based device 900 can employ any known serial or parallel bus structure or architecture. The communication link 916 can include hardware such as a printed circuit board configured with one or more implementations of the 3D PCB interface disclosed herein.

[0057] The system memory 920 may include read-only memory ("ROM") 918 and random access memory ("RAM") 924. A portion of the ROM 918 may be used to store or otherwise retain a basic input / output system ("BIOS") 922. The BIOS 922 provides basic functionality to the processor-based device 900, for example by causing the processor circuit 910 to load one or more machine-readable instruction sets. In an embodiment, at least some of the one or more machine-readable instruction sets may cause at least a portion of the processor circuit 910 to provide, create, generate, convert, and / or function as a dedicated, unique, and specific machine, such as a word processor, digital image acquisition machine, media player, communication device, and the like. The RAM 924 may be a SIMM or DIMM memory module that includes one or more printed circuit boards configured with one or more implementations of the 3D PCB interface disclosed herein.

[0058] The processor-based device 900 may include one or more communicatively coupled non-transitory data storage devices, such as one or more hard disk drives 930 and / or one or more solid-state storage devices 932. The one or more data storage devices 930 may include any currently or future developed storage device, network, and / or device. Non-limiting examples of such data storage devices 930 may include, but are not limited to, any currently or future developed non-transitory storage device or device, such as one or more magnetic storage devices, one or more optical storage devices, one or more resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof. In some implementations, the one or more data storage devices 930 may include one or more removable storage devices, such as one or more non-volatile drives, non-volatile memories, non-volatile storage units, or similar devices or devices capable of being communicatively coupled to and decoupled from the processor-based device 900.

[0059] The one or more data storage devices 930 and / or the one or more solid-state storage devices 932 may include an interface or controller (not shown) that communicatively couples the corresponding storage devices or systems to the communication link 916. The one or more data storage devices 930 may store, retain, or otherwise contain machine-readable instruction sets, data structures, program modules, data stores, databases, logic structures, and / or other data useful to the processor circuit 910 and / or one or more applications executing on or by the processor circuit 910. In some examples, the one or more data storage devices 930 may be communicatively coupled to the processor circuit 910, for example, via the communication link 916 or via one or more wired communication interfaces (e.g., a universal serial bus or USB); one or more wireless communication interfaces (e.g., Bluetooth); ®, Near Field Communication or NFC); ​​one or more wired network interfaces (e.g., IEEE 802.3 or Ethernet); and / or one or more wireless network interfaces (e.g., IEEE 802.11 or WiFi ® ). One or more wired communication interfaces may include a connector or cable having one or more printed circuit boards configured with one or more implementations of the 3D PCB interfaces disclosed herein.

[0060] A set of machine-readable instructions 938 and other programs, applications, logic, and / or modules 940 may be stored, in whole or in part, in the system memory 920. Such a set of instructions 938 may be transferred, in whole or in part, from one or more data storage devices 930 and / or solid-state storage devices 932. The set of instructions 938 may be loaded, stored, or otherwise retained, in whole or in part, in the system memory 920 during execution by the processor circuit 910. The set of machine-readable instructions 938 may include machine-readable and / or processor-readable code, instructions, or similar logic capable of providing the voice guidance functions and capabilities described herein.

[0061] A system user can provide, input, or otherwise supply commands (e.g., selections, responses, confirmations, and the like) and information and / or data (e.g., subject identification information, color parameters) to the processor-based device 900 using one or more communicatively coupled input devices 950. The one or more communicatively coupled input devices 950 can be local to the processor-based device 900 or remotely located from the processor-based device 900. The input devices 950 may include one or more of: a text input device 951 (e.g., a keyboard); a pointing device 952 (e.g., a mouse, trackball, touch screen); an audio input device 953; a video input device 954; and / or a biometric input device 955 (e.g., a fingerprint scanner, facial recognition, iris print scanner, voice recognition circuitry). In embodiments, at least some of the one or more input devices 950 may include a wired or wireless interface that communicatively couples the input device 950 to the processor-based device 900.

[0062] A system user may receive output from the processor-based device 900 via one or more output devices 960. In at least some implementations, the one or more output devices 960 may include, but are not limited to, one or more of: a biometric output device 961; a visual output or display device 962; a tactile output device 963; an audio output device 964, or a combination thereof. In embodiments, at least some of the one or more output devices 960 may include a wired or wireless communicative coupling with the processor-based device 902.

[0063] For convenience, the network interface 970, the processor circuit 910, the system memory 920, the one or more input devices 950 and the one or more output devices 960 are shown as being communicatively coupled to each other via a communication link 916, thereby providing connectivity between the above components. In alternative embodiments, the above components may be implemented in a manner similar to that described above. Figure 9 916. For example, one or more of the components described above may be directly coupled to the other components, or may be coupled to each other via one or more intermediate components (not shown). In some embodiments, all or a portion of communication link 916 may be omitted, and the components may be directly coupled to each other using suitable wired or wireless connections.

[0064] In addition, the operation of the embodiments has been further described with reference to the above figures and accompanying examples. Some figures may include logic flows. Although the figures presented herein may include specific logic flows, it will be appreciated that the logic flows merely provide examples of how the general functionality described herein may be implemented. Furthermore, unless otherwise indicated, a given logic flow does not necessarily have to be executed in the order presented. The embodiments are not limited in this context.

[0065] Various features, aspects, and embodiments have been described herein. As will be appreciated by those skilled in the art, the features, aspects, and embodiments are susceptible to combination with one another and to variations and modifications. Therefore, the present disclosure should be construed as encompassing such combinations, variations, and modifications. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined solely in accordance with the appended claims and their equivalents.

[0066] The terms and expressions employed herein are used as terms of description rather than limitation, and in the use of such terms and expressions, there is no intention to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to encompass all such equivalents. Various features, aspects, and embodiments have been described herein. As will be appreciated by those skilled in the art, the features, aspects, and embodiments are susceptible to combination with one another and to variations and modifications. Accordingly, the present disclosure should be construed as encompassing such combinations, variations, and modifications.

[0067] Reference throughout this specification to "one embodiment," "an embodiment," or "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0068] As used in any embodiment herein, the term "logic" may refer to an application, software, firmware, and / or circuitry configured to perform any of the aforementioned operations. Software may be implemented as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware may be implemented as code, instructions, instruction sets, and / or data hard-coded in a memory device (e.g., non-volatile).

[0069] As used in any embodiment herein, "circuitry" may include, for example, individually or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, logic, and / or firmware that stores instructions executed by the programmable circuitry. The circuitry may be implemented as an integrated circuit, such as an integrated circuit chip. In some embodiments, the circuitry may be at least partially formed within a memory controller that executes code and / or instruction sets (e.g., software, firmware, etc.) corresponding to the functionality described herein, thereby converting a general-purpose processor into a specialized processing environment to perform one or more operations described herein. In some embodiments, the various components and circuits of the memory controller circuitry or other systems may be combined in a system-on-chip (SoC) architecture.

[0070] Embodiments of the operations described herein may be implemented in a computer-readable storage device having stored thereon instructions that, when executed by one or more processors, perform the methods. The processor may include, for example, a processing unit and / or a programmable circuit. The storage device may include a machine-readable storage device, including any type of tangible, non-transitory storage device, such as, for example, a floppy disk, an optical disk, a compact disk read-only memory (CD-ROM), a compact disk rewritable (CD-RW), and any type of disk for magneto-optical disks, a semiconductor device such as a read-only memory (ROM), a random access memory (RAM) such as dynamic and static RAM, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a non-volatile memory, a magnetic or optical card, or any type of storage device suitable for storing electronic instructions.

[0071] In some embodiments, a hardware description language (HDL) may be used to specify circuit and / or logic implementations for various logic and / or circuits described herein. For example, in one embodiment, the hardware description language may conform to or be compatible with Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), which may enable semiconductor fabrication of one or more circuits and / or logic described herein. VHDL may conform to or be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE 1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008, and / or other versions of the IEEE VHDL standard and / or other hardware description standards.

[0072] In some embodiments, the Verilog Hardware Description Language (HDL) can be used to specify circuit and / or logic implementations for the various logic and / or circuits described herein. For example, in one embodiment, the HDL can conform to or be compatible with IEEE Standard 62530-2011: SystemVerilog - Unified Hardware Design, Specification, and Verification Language, dated July 7, 2011; IEEE Std 1800™-2012: IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language, dated February 21, 2013; IEEE Standard 1364-2005: IEEE Standard for Verilog Hardware Description Language, dated April 18, 2006, and / or other versions of the Verilog HDL and / or SystemVerilog standards.

[0073] The present invention also includes the following technical solutions:

[0074] Technical Solution 1. A printed circuit board comprising:

[0075] a first surface;

[0076] a second surface laterally opposed to the first surface, the second surface being spaced apart from the first surface by a thickness forming an edge; and

[0077] A plurality of landing pads are disposed on the edge and electrically coupled to one or more conductive traces or planes of the printed circuit board.

[0078] Technical Solution 2. The printed circuit board of Technical Solution 1, wherein the plurality of landing pads are to electrically couple the one or more conductive traces or conductive planes to one or more external sources of electronic signals.

[0079] Technical Solution 3. The printed circuit board of Technical Solution 1, wherein the plurality of landing pads are a plurality of first landing pads, wherein the edge is a first edge, wherein the second surface is separated from the first surface by a thickness forming the second edge, and wherein the printed circuit board further comprises:

[0080] At least one second landing pad is disposed on the second edge, wherein the at least one second landing pad is electrically coupled to the one or more conductive traces or planes.

[0081] Technical Solution 4. A printed circuit board as described in Technical Solution 1, wherein the plurality of landing pads are to electrically couple the printed circuit board to a plurality of conductive pins of a second printed circuit board to extend one or more signal paths from the printed circuit board to the second printed circuit board.

[0082] Technical Solution 5. The printed circuit board according to Technical Solution 1, wherein the plurality of landing pads are a plurality of first landing pads, and wherein the printed circuit board further comprises:

[0083] a plurality of second landing pads disposed on the first surface; and

[0084] A plurality of third landing pads are disposed on the second surface.

[0085] Technical Solution 6. A printed circuit board as described in Technical Solution 5, wherein the plurality of second landing pads are to electrically contact a plurality of first conductive pins carried by the second printed circuit board, and wherein the plurality of third landing pads are to electrically contact a plurality of second conductive pins carried by the second printed circuit board.

[0086] Technical Solution 7. A printed circuit board as described in Technical Solution 1, wherein the first surface carries a plurality of first memory modules, wherein the second surface carries a plurality of second memory modules, and wherein the one or more conductive traces or conductive planes at least partially electrically couple the plurality of first memory modules and the plurality of second memory modules to the plurality of landing pads.

[0087] Technical Solution 8. The printed circuit board as described in Technical Solution 1, wherein the one or more conductive traces or conductive planes include one or more of a power plane or a reference plane.

[0088] Technical Solution 9. The printed circuit board according to Technical Solution 1, wherein the printed circuit board is part of a communication cable connector for coupling a first computing device to a second computing device.

[0089] Technical Solution 10. A printed circuit board system comprising:

[0090] A first printed circuit board comprising:

[0091] a first surface;

[0092] a second surface laterally opposed to the first surface, the second surface being spaced apart from the first surface by a first thickness forming a first edge; and

[0093] a plurality of first landing pads disposed on the first printed circuit board; and

[0094] a second printed circuit board attachable to the first printed circuit board, comprising:

[0095] third surface;

[0096] a fourth surface laterally opposed to the third surface, the fourth surface being spaced apart from the third surface by a second thickness forming a second edge; and

[0097] A second plurality of landing pads is disposed on the second edge and coupled to one or more conductive traces or planes of the printed circuit board.

[0098] Technical Solution 11. The printed circuit board system according to Technical Solution 10, wherein the first printed circuit board is a mainboard and the second printed circuit board is a memory module printed circuit board.

[0099] Technical Solution 12. The printed circuit board system according to Technical Solution 10, wherein the first printed circuit board is a mainboard and the second printed circuit board is part of a communication cable connector.

[0100] Technical Solution 13. The printed circuit board system according to Technical Solution 10, further comprising:

[0101] a groove in the first surface, wherein the plurality of first landing pads are disposed in the groove on the first surface of the first printed circuit board, wherein the groove is configured to receive the second edge of the second printed circuit board to electrically couple the plurality of first landing pads to the plurality of second landing pads.

[0102] Technical Solution 14. The printed circuit board system according to Technical Solution 13, further comprising:

[0103] A plurality of conductive pins are attached to the plurality of first landing pads or the plurality of second landing pads to facilitate electrically coupling the plurality of first landing pads to the plurality of second landing pads.

[0104] Technical Solution 15. A printed circuit board system as described in Technical Solution 10, wherein the plurality of first landing pads are arranged on the first edge of the first printed circuit board so as to enable edge-to-edge electrical coupling with the plurality of second landing pads arranged on the second edge of the second printed circuit board.

[0105] Technical Solution 16. The printed circuit board system according to Technical Solution 10, further comprising:

[0106] A groove is formed in the first surface and the second surface of the first thickness of the first printed circuit board, the groove being adapted to receive the second printed circuit board, the groove comprising at least three edges formed by the first thickness.

[0107] Technical Solution 17. The printed circuit board system according to Technical Solution 16, wherein the first edge is one of the at least three edges of the groove of the first printed circuit board.

[0108] Technical Solution 18. A printed circuit board comprising:

[0109] a first surface;

[0110] a second surface laterally opposed to the first surface, the second surface being spaced apart from the first surface by a first thickness forming a first edge; and

[0111] A first plurality of landing pads is disposed on the printed circuit board for electrically coupling to a second plurality of landing pads disposed on a second edge of a second printed circuit board attachable to the printed circuit board.

[0112] Technical Solution 19. The printed circuit board according to Technical Solution 18, wherein the printed circuit board is a mainboard and the second printed circuit board is a memory module printed circuit board.

[0113] Technical Solution 20. The printed circuit board according to Technical Solution 18, wherein the printed circuit board is a main board and the second printed circuit board is part of a communication cable connector.

[0114] Technical Solution 21. The printed circuit board according to Technical Solution 18, further comprising:

[0115] a groove in the first surface, wherein the plurality of first landing pads are disposed in the groove on the first surface of the printed circuit board, wherein the groove is configured to receive the second edge of the second printed circuit board to electrically couple the plurality of first landing pads to the plurality of second landing pads.

[0116] Technical Solution 22. A printed circuit board as described in Technical Solution 18, wherein the plurality of first landing pads are arranged on the first edge of the printed circuit board so as to enable edge-to-edge electrical coupling with the plurality of second landing pads arranged on the second edge of the second printed circuit board.

[0117] Technical Solution 23. A method comprising:

[0118] forming a printed circuit board having a first surface and a second surface laterally opposite the first surface and spaced apart from the first surface by a thickness forming an edge; and

[0119] A plurality of landing pads are provided on the edge of the printed circuit board.

[0120] Technical Solution 24. A method as described in Technical Solution 23, wherein the plurality of landing pads are electrically coupled to one or more conductive traces or conductive planes of the printed circuit board, and the one or more conductive traces or conductive planes are to electrically couple the plurality of landing pads to one or more electronic components carried by the printed circuit board.

[0121] Technical Solution 25. The method of Technical Solution 24, wherein the one or more electronic components include a memory die.

[0122] Technical Solution 26. The method of Technical Solution 23, wherein the plurality of landing pads are a plurality of first landing pads, wherein the printed circuit board is a first printed circuit board, and the method further comprises:

[0123] A plurality of second landing pads are provided on the first surface and the second surface to electrically couple to conductive pins carried by a second printed circuit board, wherein the second printed circuit board is a motherboard for one of a desktop computer, a laptop computer, a mobile device, a smart phone, or a networking device.

[0124] Example

[0125] Examples of the present disclosure include subject matter such as memory controllers, methods, and systems related to improving memory array read rates, as described below.

[0126] Example 1. According to this example, a printed circuit board is provided. The printed circuit board may include a first surface; a second surface laterally opposite the first surface, the second surface being spaced apart from the first surface by a thickness forming an edge; and a plurality of landing pads disposed on the edge and electrically coupled to one or more conductive traces or conductive planes of the printed circuit board.

[0127] Example 2. This example includes the element of Example 1, wherein the plurality of landing pads electrically couple the one or more conductive traces or planes to one or more external sources of electronic signals.

[0128] Example 3. This example includes elements of Example 1, wherein the plurality of landing pads is a plurality of first landing pads, wherein the edge is a first edge, wherein the second surface is separated from the first surface by a thickness forming the edge, wherein the printed circuit board further comprises at least one second landing pad disposed on the second edge, wherein the at least one second landing pad is electrically coupled to one or more conductive traces or conductive planes.

[0129] Example 4. This example includes the elements of Example 1, wherein the plurality of landing pads are to electrically couple the printed circuit board to a plurality of conductive pins of a second printed circuit board to extend one or more signal paths from the printed circuit board to the second printed circuit board.

[0130] Example 5. This example includes the elements of Example 1, wherein the plurality of landing pads is a plurality of first landing pads, wherein the printed circuit board further comprises a plurality of second landing pads disposed on the first surface; and a plurality of third landing pads disposed on the second surface.

[0131] Example 6. This example includes the element of Example 1, wherein the plurality of second landing pads are to electrically contact the plurality of first conductive pins carried by the second printed circuit board, and wherein the plurality of third landing pads are to electrically contact the plurality of second conductive pins carried by the second printed circuit board.

[0132] Example 7. This example includes the elements of Example 1, wherein the first surface carries a plurality of first memory modules, wherein the second surface carries a plurality of second memory modules, wherein one or more conductive traces or conductive planes at least partially electrically couple the plurality of first memory modules and the plurality of second memory modules to the plurality of landing pads.

[0133] Example 8. This example includes the element of Example 1, wherein the one or more conductive traces or conductive planes include one or more of a power plane or a reference plane.

[0134] Example 9. This example includes the elements of Example 1, wherein the printed circuit board is part of a communication cable connector for coupling a first computing device to a second computing device.

[0135] Example 10. According to this example, a printed circuit board system is provided. The printed circuit board system may include a first printed circuit board. The first printed circuit board may include a first surface; a second surface laterally opposite the first surface, the second surface being separated from the first surface by a first thickness forming a first edge; and a plurality of first landing pads disposed on the first printed circuit board. The printed circuit board system may include a second printed circuit board attachable to the first printed circuit board. The second printed circuit board may include a third surface; a fourth surface laterally opposite the third surface, the fourth surface being separated from the third surface by a second thickness forming a second edge; and a plurality of second landing pads disposed on the second edge and coupled to one or more conductive traces or conductive planes of the printed circuit board.

[0136] Example 11. This example includes the elements of Example 10, wherein the first printed circuit board is a motherboard and the second printed circuit board is a memory module printed circuit board.

[0137] Example 12. This example includes the element of Example 10, wherein the first printed circuit board is a motherboard and the second printed circuit board is part of a communication cable connector.

[0138] Example 13. This example includes the elements of Example 10, further comprising a groove in the first surface, wherein the plurality of first landing pads are disposed in the groove of the first surface of the first printed circuit board, wherein the groove is configured to receive a second edge of the second printed circuit board to electrically couple the plurality of first landing pads to the plurality of second landing pads.

[0139] Example 14. This example includes the elements of Example 13, further comprising a plurality of conductive pins attached to the plurality of first landing pads or the plurality of second landing pads to facilitate electrically coupling the plurality of first landing pads to the plurality of second landing pads.

[0140] Example 15. This example includes the elements of Example 10, wherein a first plurality of landing pads is disposed on a first edge of a first printed circuit board to enable edge-to-edge electrical coupling with a second plurality of landing pads disposed on a second edge of a second printed circuit board.

[0141] Example 16. This example includes the element of Example 10, further comprising a groove in the first surface and the second surface through the first thickness of the first printed circuit board, the groove being for receiving the second printed circuit board, the groove including at least three edges formed by the first thickness.

[0142] Example 17. This example includes the element of Example 16, wherein the first edge is one of at least three edges of the recess of the first printed circuit board.

[0143] Example 18. According to this example, a printed circuit board is provided. The printed circuit board may include a first surface; a second surface laterally opposite the first surface, the second surface being separated from the first surface by a thickness forming an edge; and a plurality of first landing pads disposed on the printed circuit board for electrically coupling to a plurality of second landing pads disposed on a second edge of a second printed circuit board that is attachable to the printed circuit board.

[0144] Example 19. This example includes the elements of Example 18, wherein the printed circuit board is a motherboard and the second printed circuit board is a memory module printed circuit board.

[0145] Example 20. This example includes the element of Example 18, wherein the printed circuit board is a motherboard and the second printed circuit board is part of a communication cable connector.

[0146] Example 21. This example includes the elements of Example 18, further comprising a groove in the first surface, wherein the plurality of first landing pads are disposed in the groove of the first surface of the first printed circuit board, wherein the groove is used to receive a second edge of the second printed circuit board to electrically couple the plurality of first landing pads to the plurality of second landing pads.

[0147] Example 22. This example includes the elements of Example 18, wherein a first plurality of landing pads are disposed on a first edge of a first printed circuit board to enable edge-to-edge electrical coupling with a second plurality of landing pads disposed on a second edge of a second printed circuit board.

[0148] Example 23. According to this example, a method is provided. The method may include forming a printed circuit board having a first surface and a second surface laterally opposite the first surface and spaced apart from the first surface by a thickness forming an edge; and providing a plurality of landing pads on the edge of the printed circuit board.

[0149] Example 24. This example includes the elements of Example 23, wherein the plurality of landing pads are electrically coupled to one or more conductive traces or conductive planes of a printed circuit board, the one or more conductive traces or conductive planes electrically coupling the plurality of landing pads to one or more electronic components carried by the printed circuit board.

[0150] Example 25. This example includes the element of Example 24, wherein the one or more electronic components include a memory die.

[0151] Example 26. This example includes elements of Example 23, wherein the plurality of landing pads is a plurality of first landing pads, wherein the printed circuit board is a first printed circuit board, and the method may further include providing a plurality of second landing pads on the first surface and the second surface to electrically couple to conductive pins carried by the second printed circuit board, wherein the second printed circuit board is a motherboard for one of a desktop computer, a laptop computer, a mobile device, a smart phone, or a connected device.

[0152] Example 27. According to this example, a printed circuit board is provided. The printed circuit board may include a first surface; a second surface laterally opposite the first surface, the second surface being separated from the first surface by a thickness forming an edge; and a device for providing electrical interconnection at the edge of the printed circuit board.

[0153] Example 28. This example includes the elements of Example 27, wherein the means for providing electrical interconnection on an edge of a printed circuit board includes electrically coupling one or more conductive traces or planes of the printed circuit board to one or more external sources of electronic signals.

[0154] Example 29. This example includes the elements of Example 27, wherein the apparatus for providing electrical interconnection on an edge of a printed circuit board includes a plurality of first landing pads, wherein the edge is a first edge, wherein the second surface is separated from the first surface by a thickness forming the edge, wherein the apparatus for providing electrical interconnection on an edge of the printed circuit board may further include at least one second landing pad disposed on the second edge, wherein the at least one second landing pad is electrically coupled to one or more conductive traces or conductive planes of the printed circuit board.

[0155] Example 30. This example includes the elements of Example 27, wherein the means for providing electrical interconnection on an edge of a printed circuit board is to electrically couple the printed circuit board to a plurality of conductive pins of a second printed circuit board to extend one or more signal paths from the printed circuit board to the second printed circuit board.

[0156] Example 31. This example includes elements of Example 27, wherein the apparatus for providing electrical interconnection on an edge of a printed circuit board includes a plurality of first landing pads, wherein the printed circuit board may include a plurality of second landing pads disposed on the first surface; and a plurality of third landing pads disposed on the second surface.

[0157] Example 32. This example includes the elements of Example 31, wherein the plurality of second landing pads are to electrically contact the plurality of first conductive pins carried by the second printed circuit board, and wherein the plurality of third landing pads are to electrically contact the plurality of second conductive pins carried by the second printed circuit board.

[0158] Example 33. This example includes the elements of Example 27, wherein the first surface carries a plurality of first memory modules, wherein the second surface carries a plurality of second memory modules, wherein the printed circuit board includes one or more conductive traces or conductive planes to at least partially electrically couple the plurality of first memory modules and the plurality of second memory modules to a device for providing electrical interconnection on an edge of the printed circuit board.

[0159] Example 34. This example includes the elements of Example 27, further comprising:

[0160] The one or more conductive traces or conductive planes are one or more of a power plane or a reference plane.

[0161] Example 35. This example includes the element of example 27, wherein the printed circuit board is part of a communication cable connector for coupling a first computing device to a second computing device.

[0162] Example 36. According to this example, there is provided an apparatus comprising means for performing the method of any one of Examples 23 to 26.

[0163] Example 37. According to this example, there is provided a computer-readable storage device having stored thereon instructions that, when executed by one or more processors, result in operations including the method according to any one of Examples 23 to 26.

[0164] Example 38. According to this example, there is provided a printed circuit board system according to any one of Examples 10 to 17, further comprising a processor circuit and a network interface.

[0165] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and in the use of such terms and expressions, there is no intention to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Claims

1. A printed circuit board system comprising: A first printed circuit board comprising: a first surface; a second surface laterally opposed to the first surface, the second surface being spaced apart from the first surface by a thickness forming an edge, wherein the edge has a first edge surface perpendicular to the first surface and the second surface; and a first plurality of landing pads disposed on the first edge surface and electrically coupled to one or more conductive traces or planes of the first printed circuit board; and A second printed circuit board comprising: a third surface and a fourth surface laterally opposite the third surface; a groove in the third surface; and a plurality of second landing pads on the bottom surface of the slot carrying corresponding conductive pins, The first printed circuit board is inserted into the slot, and electrical coupling is established between the first printed circuit board and the second printed circuit board along the first edge surface and the slot via the plurality of first landing pads, the corresponding conductive pins, and the plurality of second landing pads.

2. The printed circuit board system of claim 1, wherein the plurality of first landing pads are to electrically couple the one or more conductive traces or planes to one or more external sources of electronic signals.

3. The printed circuit board system of claim 1 , wherein the edge has a second edge surface perpendicular to the first surface and the second surface, and wherein the first printed circuit board further comprises: At least one third landing pad is disposed on the second edge surface, wherein the at least one third landing pad is electrically coupled to the one or more conductive traces or planes.

4. The printed circuit board system of claim 1, wherein the second printed circuit board is a motherboard and the first printed circuit board is a memory module printed circuit board.

5. The printed circuit board system of claim 1 , wherein the first printed circuit board further comprises: a plurality of fourth landing pads disposed on the first surface; as well as A plurality of fifth landing pads are disposed on the second surface.

6. The printed circuit board system of claim 5 , wherein the plurality of fourth landing pads are to electrically contact a plurality of second conductive pins carried by the second printed circuit board, and wherein the plurality of fifth landing pads are to electrically contact a plurality of third conductive pins carried by the second printed circuit board.

7. The printed circuit board system of claim 1 , wherein the first surface carries a plurality of first memory modules, wherein the second surface carries a plurality of second memory modules, and wherein the one or more conductive traces or conductive planes at least partially electrically couple the plurality of first memory modules and the plurality of second memory modules to the plurality of first landing pads.

8. The printed circuit board system of claim 1, wherein the one or more conductive traces or planes include one or more of a power plane or a reference plane.

9. The printed circuit board system of claim 1, wherein the first printed circuit board is part of a communication cable connector for coupling a first computing device to a second computing device and the second printed circuit board is a motherboard.

10. A printed circuit board system comprising: A first printed circuit board comprising: a first surface; a second surface laterally opposed to the first surface and spaced apart from the first surface by a first thickness; and a groove in the first surface; and a second printed circuit board attachable to the first printed circuit board, comprising: third surface; a fourth surface laterally opposed to the third surface and spaced apart from the third surface by a second thickness; and a first edge and a second edge between the third surface and the fourth surface, the first edge comprising a first conductive plane coupled to a first plurality of landing pads of the second printed circuit board, and the second edge comprising a second conductive plane coupled to a second plurality of landing pads of the second printed circuit board, The second printed circuit board is disposed in the groove of the first printed circuit board, and the first conductive plane and the second conductive plane are electrically coupled to one or more conductive planes of the first printed circuit board via corresponding conductive pins.

11. The printed circuit board system of claim 10, wherein the first printed circuit board is a motherboard and the second printed circuit board is a memory module printed circuit board.

12. The printed circuit board system of claim 10, wherein the first printed circuit board is a motherboard and the second printed circuit board is part of a communication cable connector.

13. A printed circuit board system comprising: A first printed circuit board comprising: a first surface; a second surface laterally opposed to the first surface and spaced apart from the first surface by a first thickness; grooves in the first surface; and a plurality of first landing pads disposed in the slot; and a second printed circuit board attachable to the first printed circuit board, comprising: third surface; a fourth surface laterally opposed to the third surface and spaced apart from the third surface by a second thickness; and a plurality of second landing pads disposed on an edge of the second printed circuit board, The second printed circuit board is disposed in the slot of the first printed circuit board, and the plurality of first landing pads are electrically coupled to the plurality of second landing pads via corresponding conductive pins.

14. The printed circuit board system of claim 13, wherein the first printed circuit board is a motherboard and the second printed circuit board is a memory module printed circuit board.

15. The printed circuit board system of claim 13, wherein the first printed circuit board is a motherboard and the second printed circuit board is part of a communication cable connector.

16. The printed circuit board system of claim 13, wherein the plurality of first landing pads are disposed on an edge of the first printed circuit board to enable edge-to-edge electrical coupling with the plurality of second landing pads disposed on the edge of the second printed circuit board.

17. A method comprising: forming a first printed circuit board having a first surface and a second surface laterally opposite the first surface and spaced apart from the first surface by a thickness forming an edge, wherein the edge has a first edge surface perpendicular to the first surface and the second surface; providing a plurality of first landing pads on the first edge surface of the first printed circuit board; forming a second printed circuit board comprising: a third surface and a fourth surface laterally opposite the third surface; a slot in the third surface; and a plurality of second landing pads on a bottom surface of the slot carrying corresponding conductive pins; inserting the first printed circuit board into the slot; and An electrical coupling is established between the first printed circuit board and the second printed circuit board via the plurality of first landing pads, the corresponding conductive pins, and the plurality of second landing pads along the first edge surface and the groove.

18. The method of claim 17 , wherein the plurality of first landing pads are electrically coupled to one or more conductive traces or conductive planes of the first printed circuit board, the one or more conductive traces or conductive planes being to electrically couple the plurality of first landing pads to one or more electronic components carried by the first printed circuit board.

19. The method of claim 18, wherein the one or more electronic components include a memory die.

20. The method of claim 17, wherein the method further comprises: A plurality of individual landing pads are provided on the first surface and the second surface to electrically couple to other conductive pins carried by the second printed circuit board, wherein the second printed circuit board is a motherboard for one of a desktop computer, a laptop computer, a mobile device, a smart phone, or an internet-connected device.

21. A computer-readable storage device having stored thereon instructions that, when executed by one or more processors, result in operations comprising: A method according to any one of claims 17 to 20.

22. A printed circuit board system according to any one of claims 1 to 16, further comprising: processor circuit; as well as Network interface.

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