Electronic components with direct bonded copper substrates

Abstract

The metal island is disposed between the first metal bus and the second metal bus. The first metal strip is isolated from the metal island by a first dielectric barrier. At least a parallel portion of the first metal strip is substantially parallel to the first metal bus, and the second metal strip is isolated from the second metal bus by a second dielectric barrier. Each terminal of the first semiconductor is coupled to the first metal bus and the metal island. Each terminal of the second semiconductor is coupled to the metal island and the second metal bus.

Description

Technical Field

[0001] The present disclosure relates to an electronic assembly having a direct bonded copper substrate. Background Art

[0002] In some prior art, a direct copper bonded (DCB) substrate refers to a circuit board in which a copper layer (e.g., copper foil) and an aluminum oxide layer are directly bonded or fused in a process at a sufficiently high temperature. In some embodiments, the electronic assembly includes a heat generating component, such as a semiconductor, a current measuring device, or both, which generates a heat load that can cause heating of the substrate and circuit traces on the substrate. Due to the heat generating components, additional heat dissipation may be required to maintain a target operating temperature range for the electronic assembly. If the target operating temperature range is exceeded, certain electronic components or dielectric insulators may fail or fail to perform to specifications. Therefore, there is a need for an electronic assembly having a direct copper bonded substrate that is configured to improve thermal performance. Summary of the invention

[0003] According to one embodiment, an electronic component includes: a direct copper bonded dielectric substrate, the direct copper bonded dielectric substrate including a dielectric layer. A first metal bus covers the dielectric layer, and the first metal bus has a bus width. A second metal bus covers the dielectric layer and is substantially parallel to the first metal bus. The first metal bus and the second metal bus are associated with a DC terminal. A metal island is disposed between the first metal bus and the second metal bus. A strip width of the first metal strip is less than the bus width. The first metal strip is isolated from the metal island by a first dielectric barrier (e.g., at a position where at least a parallel portion of the first metal strip is substantially parallel to the first metal bus). A strip width of the second metal strip is less than the bus width, and the second metal strip is isolated from the second metal bus by a second dielectric barrier. Each first semiconductor has at least one primary terminal and a secondary terminal, at least one primary terminal is coupled to the first metal bus and the secondary terminal is coupled to the metal island. Each second semiconductor has at least one primary terminal and a secondary terminal, at least one primary terminal is coupled to the metal island and the secondary terminal is coupled to the second metal bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a first perspective view of one embodiment of an electronic assembly.

[0005] Figure 2 yes Figure 1 A second perspective view of an embodiment of an electronic assembly is shown in FIG.

[0006] Figure 3 yes Figure 1 00145] Figure 2 is a third perspective view of an embodiment of an electronic assembly shown in FIG.

[0007] Figure 4 is based on Figure 1 Block diagram of the current measurement system with electronic components. DETAILED DESCRIPTION

[0008] According to one embodiment, Figure 1 An electronic assembly 11 is shown that includes a dielectric layer 12 and a first metal bus 14 overlying the dielectric layer 12. The first metal bus 14 has a bus width 16 (e.g., a first bus width) and a bus height or thickness. A second metal bus 18 overlies the dielectric layer 12 and is generally parallel to the first metal bus 14, wherein the first metal bus 14 and the second metal bus 18 are associated with DC terminals 20. For example, the DC terminals 20 are associated with positive and negative DC inputs to power the DC bus.

[0009] In one embodiment, the metal island 22 is disposed between the first metal bus 14 and the second metal bus 18. The metal island 22 is electrically isolated from the first metal bus 14 and the second metal bus by the interposed dielectric region of the dielectric layer 12. In one example, the metal island 22 represents an output bus or is electrically connected to or shared with an output bus. The metal island 22 or the output bus is associated with a corresponding output terminal, output terminal pad, or output conductive pad 66.

[0010] In one configuration, an optional current measuring device or shunt resistor 62 covers a portion of the metal island 22 or output conductive pad 66 associated with an output (e.g., a phase of an inverter or converter embodying the electronic component 11). In particular, the shunt resistor 62 can be welded, brazed, or otherwise electrically and mechanically connected to the metal island 22 or output terminal pad via the solder layer 13. In one configuration, the space above the output conductive pad 66 or metal island 22 (which space may otherwise be empty) can be filled with an optional current measuring device (e.g., shunt resistor 62) to achieve greater circuit density or reduced package size of the electronic component 11 compared to other possible methods. In another configuration, the optional current measuring device or shunt resistor 62 serves as both an output terminal and a shunt resistor 62. The shunt resistor 62 has a central hole 86 which may be substantially cylindrical and tapped or threaded to receive a fastener associated with a conductive cable or output conductor (e.g., a conductor terminated in a connector having an opening or eyelet for receiving the fastener).

[0011] The shunt resistor 62 can operate as a current shunt (e.g., one terminal of the shunt resistor 62 is coupled to ground) and an output terminal, wherein the current shunt has bond wires that connect the current shunt to a conductive pad 77 on the direct copper-bonded dielectric substrate 10 for a "Kelvin connection." The "Kelvin connection" supports accurate voltage measurement across the terminals of the shunt resistor 62 because parasitic or auxiliary voltage drops associated with the resistance or impedance of the surrounding bus structure are reduced or eliminated in the voltage measurement.

[0012] The first metal strip 24 (e.g., an elevated first metal strip) has a strip width 26 that is less than the bus width 16 (e.g., a first bus width). The first metal strip 24 is electrically isolated from the metal island 22 by a first dielectric barrier 28 (e.g., a dielectric bridge). In one embodiment, the first metal strip 24 includes an elevated first metal strip 24 that is elevated above the substrate, the metal island 22, or both by a dielectric barrier (e.g., a dielectric bridge). For example, the first dielectric barrier 28 can be configured as a dielectric bridge having a pillar, leg, or other vertical support 29 that rests on, is fixed to, or is adhesively bonded to the metal island 22.

[0013] The second metal strip 30 has a strip width 26 (e.g., a second strip width) that is less than the bus width 16. The second metal strip 30 is electrically isolated from the second metal bus 18 by a second dielectric barrier 32 (e.g., a dielectric bridge). The second metal strip 30 is spaced apart from and electrically isolated from the first metal strip 24. In one embodiment, the second metal strip 30 includes an elevated second metal strip 30 that is elevated above the substrate, the metal island 22, or both by a dielectric barrier (e.g., a dielectric bridge). For example, the second dielectric barrier 32 can be configured as a dielectric bridge having a post, leg, or other vertical support 29 that rests on, is fixed to, or is adhesively bonded to the second metal bus 18.

[0014] A group (e.g., a row) of one or more first semiconductors 34 is associated with the electronic component 11. Each first semiconductor 34 has at least one primary terminal 36, a secondary terminal 38 (e.g., a conductive pad on the bottom of the semiconductor 34), and a tertiary terminal 44. For one or more first semiconductors 34, at least one primary terminal 36 is connected to the first metal bus 14; the secondary terminal 38 (e.g., a conductive pad on the bottom of the semiconductor 34) is connected to the metal island 22; and the tertiary terminal 44 is connected to the first metal strip 24. In one embodiment, the primary terminal 36 and the secondary terminal 38 are collectively referred to as the switch terminal of each corresponding first semiconductor, and the tertiary terminal 44 includes the control terminal of each corresponding first semiconductor 34. As shown, the secondary terminal 38 includes a conductive pad that is integral with the package of the first semiconductor 34. In one embodiment, if the first semiconductor 34 includes a transistor, the switch terminal includes an emitter and a collector, or a source and a drain. As shown, at least one primary terminal 36 may include a plurality of leads (e.g., bonding wires) that are configured in parallel to increase the current carrying capacity of the first semiconductor device relative to a smaller number of leads.

[0015] A group (e.g., a row) of one or more second semiconductors 40 is associated with the electronic component 11. Each second semiconductor 40 has at least one primary terminal 36, a secondary terminal 38 (e.g., a conductive pad on the bottom side of the second semiconductor 40), and a tertiary terminal 44. At least one primary terminal 36 is connected to the metal island 22; the secondary terminal 38 is connected to the second metal bus 18; and the tertiary terminal 44 is connected to the second metal strip 30. In one embodiment, the primary terminal 36 and the secondary terminal 38 are collectively referred to as the switch terminal of each corresponding second semiconductor 40, and the tertiary terminal 44 includes the control terminal of each corresponding second semiconductor 40. As shown, the secondary terminal 38 includes a conductive pad that is integral with the package of the second semiconductor 40. As shown, at least one primary terminal 36 may include a plurality of leads (e.g., bonding wires) that are configured in parallel to increase the current carrying capacity of the second semiconductor device 40 relative to a smaller number of leads.

[0016] according to Figure 1, one embodiment of an electronic assembly 11 includes a dielectric layer 12 of a direct copper bonded dielectric substrate 10 (e.g., a ceramic substrate) and a first metal bus 14 covering a first side of the dielectric layer 12. The first metal bus 14 has a bus width 16. A second metal bus 18 covers the dielectric substrate and is substantially parallel to the first metal bus 14, wherein the first metal bus 14 and the second metal bus 18 are associated with a DC terminal 20. The bus width of the second metal bus 18 can be equal to or different from the bus width 16 of the first metal bus 14. A strip width 26 of a first metal strip 24 is less than the bus width, and at least a parallel portion of the first metal strip 24 is substantially parallel to a second metal strip 30 (e.g., or the first metal bus 14). A strip width 26 of the second metal strip 30 is less than the bus width, wherein at least a parallel portion of the second metal strip 30 is substantially parallel to the first metal strip 24 (e.g., or the first metal bus 14). The strip width 26 of the first metal strip 24 can be the same as or different from the strip width of the second metal strip 30.

[0017] In one embodiment, the switch assembly includes a group of one or more first semiconductors 34 and another group of one or more second semiconductors 40, the first semiconductors 34 and the second semiconductors 40 being combined by their respective conductive traces 14, 18, 22 on the substrate 10. As shown, the first semiconductors 34 and the second semiconductors 40 are arranged in corresponding rows. In one embodiment, each first semiconductor 34 has at least one primary terminal 36, a secondary terminal 38, and a tertiary terminal 44, which are coupled to the corresponding circuit traces of the direct copper-bonded dielectric substrate 10. Each second semiconductor 40 in the group of one or more second semiconductors 40 has at least one primary terminal 36, a secondary terminal 38, and a tertiary terminal 44, which are coupled to the corresponding circuit traces 14, 18, 22 of the direct copper-bonded dielectric substrate.

[0018] In one embodiment, the second side 43 of the direct copper bonded dielectric substrate 10 is opposite to the first side 41; the second side 43 is associated with a copper layer or a copper alloy layer that is directly bonded to the base layer 17 on the dielectric layer 12. Thus, the direct copper bonded dielectric substrate 10 has a double-sided configuration with conductive traces on the first side 41 and the second side 43. Figure 3 As shown, the heat sink 83 is welded or brazed to the second side 43 of the direct copper bonded dielectric substrate 10 via the solder layer 15, wherein the second side 43 has a metal layer 85, such as a metal ground plane or conductive pad, the size and shape of which correspond to and cooperate with the corresponding size and shape of the heat sink 83. In an alternative embodiment, the heat sink 83 can be welded, fused, directly bonded, thermally and mechanically bonded, or metallurgically bonded to the second side 43.

[0019] In one embodiment, the heat sink 83 comprises a generally planar heat sink 83 (e.g., a metal, metal alloy, or aluminum heat sink). The upper side 51 of the heat sink 83 faces or contacts the dielectric substrate 10, while the lower side 53 of the heat sink 83 may include an external portion of the electronic component 11, which is used to dissipate thermal energy to the surrounding environment via air cooling, liquid cooling, or both. For example, in an alternative embodiment, the lower side 53 of the heat sink 83 may have fins, protrusions, or projections extending outwardly from the generally planar surface 84 to enhance heat dissipation by air cooling.

[0020] In one embodiment, the dielectric substrate 10 includes a direct copper bonded (DCB) substrate. The DCB dielectric substrate 10 refers to a circuit board in which a copper layer (e.g., copper foil) and a base layer 17 are directly bonded or fused in a process at a sufficiently high temperature. The base layer 17 is composed of aluminum oxide (i.e., aluminum oxide), aluminum nitride, aluminum carbide, or other oxide, carbide, or nitride compounds. The copper layer and the base layer 17 can be etched, removed, formed, or otherwise configured into conductive traces, such as a first metal bus 14, a second metal bus 18, and a metal island 22. In addition, metal foils can be attached, photolithography, chemical processing, electroplating, electroless plating, or three-dimensional printing can be used to form other conductive traces, such as a first metal strip 24 and a second metal strip 30. In some embodiments, the electronic component 11 includes a heat-generating component, such as a semiconductor, a current measuring device, or both.

[0021] On the DCB dielectric substrate 10, conductors or conductive traces can sometimes be made thicker (taller), wider, or both to support a corresponding threshold current carrying capacity. In one embodiment, the thickness or height of any metal trace can be increased by using thicker copper foil, metal sputtering, electroless plating, electroplating, deposition, or other processes. If the applicable design constraints of inductance in the conductive traces and the requirements of the available space on the DCB dielectric substrate 10 are met, the DCB dielectric substrate 10 can be configured to have higher thermal conductivity and higher current carrying capacity than traditional circuit boards (such as ceramic or fiberglass boards with copper traces). Here, the configuration of the conductive traces, buses, strips, or conductors on the substrate supports thermal performance and heat dissipation suitable for power electronics applications.

[0022] In one embodiment, the first metal bus 14, the second metal bus 18, and the first metal island 22 are composed of copper or a copper alloy, which is directly bonded to the dielectric layer 12 through the base layer 17. The first metal bus 14, the second metal bus 18, the first metal strip 24, and the second metal strip 30 are composed of copper or a copper alloy.

[0023] Each first semiconductor 34 includes a tertiary terminal 44 coupled to the first metal strip 24. Each second semiconductor 40 includes another tertiary terminal 44 coupled to the second metal strip 30. As for the first semiconductors 34 and the second semiconductors 40, the tertiary terminals 44 include bond wires directly bonded to the respective first metal strips 24 and second metal strips 30. At least one primary terminal 36 includes a set of multiple bond wires 46 in parallel to support greater current handling capabilities.

[0024] The secondary terminal 38 of the first semiconductor comprises a conductive pad on the lower surface 50 of the first semiconductor. The secondary terminal 38 of the second semiconductor comprises a conductive pad on the lower surface 50 of the second semiconductor 40.

[0025] The primary terminal 36 and the secondary terminal 38 comprise a switch terminal of each first semiconductor 34, and wherein the tertiary terminal 44 comprises a control terminal of each first semiconductor 34. The primary terminal 36 and the secondary terminal 38 comprise a switch terminal of each second semiconductor, and wherein the tertiary terminal 44 comprises a control terminal of each second semiconductor 40.

[0026] The first metal strip 24 has a vertical portion 54 that is substantially perpendicular to the parallel portion (e.g., 24). The first metal bus 14 and the second metal bus 18 are associated with the DC terminal 20 having a corresponding hole 56. The first metal bus 14, the second metal bus 18, the first metal strip 24, and the second metal strip 30 have a connecting piece 58 that is perpendicular or substantially perpendicular to a corresponding one of the first metal bus 14, the second metal bus 18, the first metal strip 24, and the second metal strip 30. In one configuration, each connecting piece 58 terminates at a corresponding substantially oval portion 60 having a corresponding oval opening.

[0027] In one embodiment, the current measurement system is associated with or installed in the electronic assembly 11. For example, the current measurement system can be associated with a switch assembly to form the electronic assembly 11. In one embodiment, the current measurement system includes the shunt resistor 62 alone, or includes the shunt resistor 62 and the current measurement device in combination, which is combined with the current measurement system. Figure 4 Will explain in more detail.

[0028] In one embodiment, the shunt resistor 62 is a substantially cylindrical device mounted on the dielectric substrate 10 and spaced apart from the first semiconductor 34 and the second semiconductor 40. For example, the shunt resistor 62 also includes a first annular member 64 covering the metal island 22 or the output conductive pad 66 on the dielectric layer 12. The first annular member 64 is composed of a conductive material, such as a metal or a metal alloy. The first annular member 64 has a base 68, a middle portion 69 located above the base 68, and an outer portion 70 located above the middle portion 69 or neck. The middle portion 69 or neck can have an intermediate outer diameter 57 that is smaller than the first outer diameter 59 of the first annular member 64 or the second outer diameter 53 of the second annular member 72. Therefore, the thinner wall of the middle portion 69 having the intermediate outer diameter 57 provides a higher resistance or impedance to the output signal (e.g., the AC output for the output phase of the inverter); therefore, the voltage drop is greater than that of the entire cylindrical shunt resistor 62.

[0029] In one embodiment, the second annular member 72 is overmolded, molded around or coaxially engaged with the middle portion 69 or neck of the first annular member 64. The second annular member 72 is constructed of a dielectric material with the terminals of the shunt resistor 62 electrically and mechanically connected to the base 68 and the outer portion 70.

[0030] In an alternative embodiment, the second annular member 72 is constructed of a flexible elastomer that need not be overmolded or molded onto the first annular member 64 , but can elastically and non-deformably expand to fit around the first annular member 64 .

[0031] In one embodiment, a temperature sensor 74 is embedded in the second annular member 72. In one illustrative example, the terminals of the temperature sensor 74 and the terminals of the shunt resistor 62 are connected to corresponding pads 77 via bonding wires 75 or conductors. During operation of the electrical assembly 10, the shunt resistor 62 heats up and the conductivity of the conductor or material may change. The temperature sensor 74 can measure the actual observed temperature of the shunt resistor 62 to correct the current offset because the temperature-dependent conductivity changes. The temperature sensor 74 can be placed or embedded in the second annular member 72 and as close as possible to the key location of the current sensor for proper temperature measurement.

[0032] In one configuration, the second annular member 72 is constructed of a dielectric material, such as a plastic, polymer, or fiber-filled plastic or polymer, that is located between the temperature sensor 74 and the output terminal (e.g., the phase output terminal) for electrical isolation, wherein the thickness of the dielectric material between the temperature sensor 74 and the output terminal can be selected based on the maximum current and maximum voltage level in the output terminal. In one embodiment, the plastic, polymer, or fiber-filled plastic or polymer having a high elastic modulus can be selected so that the second annular member 72 does not deform in response to the expected thermal and mechanical stresses associated with the shunt resistor 62 and the output terminal to which the cable or conductor is attached via the center hole 86. In addition, the plastic having a high elastic modulus provides structural support for the intermediate portion 69 to resist tensile stress or shear stress or both.

[0033] In one embodiment, the shunt resistor 62 covers a portion of the metal island 22 or the output conductive pad 66 associated with the output signal of the electronic component 11. If the electronic component 11 includes an inverter or converter, the output signal of the inverter or converter can be an AC output signal, a pulse width modulated output signal, or a sinusoidal signal. The shunt resistor 62 has a central hole 86 and an output terminal 89 to provide the output signal. The shunt resistor 62 is very suitable for acting as both the output terminal 89 and the shunt resistor 62 to save space area on the surface of the direct copper-bonded dielectric substrate 10 and minimize the size of the electronic component 11 for vehicle applications (such as highway or off-road vehicle applications). In one configuration, the lower portion 80 of the shunt resistor 62 is welded, soldered or otherwise electrically and mechanically connected to the metal island 22 or the output terminal pad; the upper portion 82 of the shunt resistor 62 has a flat surface 84 and a hole 86 for receiving a cable or conductor, which is terminated in an electrical connector to make an electrical and mechanical connection via a fastener. In one embodiment, the terminals of the temperature sensor 74 and the terminals of the shunt resistor 62 are connected to corresponding pads 77 via bond wires 75 or other conductors.

[0034] In another example, if Figure 4As shown, a voltage measurement circuit 78 is coupled to the terminals of the shunt resistor 62 to measure a voltage drop across the shunt resistor 62, which is proportional to the current flowing in the shunt resistor 62. If the electronic assembly 11 includes an inverter, the current can represent the output current of one phase of the inverter. In one example, the voltage measurement circuit 78 detects the voltage drop between the terminals of the shunt resistor 62 to estimate the corresponding current flowing in the shunt resistor 62 according to Ohm's law. The voltage measurement circuit 78 can be coupled to an input analog-to-digital converter 79, which converts the measured voltage drop into a digital value. The output of the analog-to-digital converter 79 is coupled to an electronic data processor 91, which communicates with a data storage device 92 via a data bus 94. The electronic data processor 19 may include a microcontroller, a microcontroller, a programmable logic array, a digital signal processor, an application specific integrated circuit, an arithmetic logic unit, or other data processor. In one embodiment, data storage device 92 includes a lookup table 93, another data structure, or software instructions (eg, a mathematical equation) that can be used to estimate the current based on the corresponding digital value of the measured voltage.

[0035] In one embodiment, the electronic assembly 11 can be constructed by first bonding copper or a copper layer directly to a base layer 17 of aluminum oxide, aluminum nitride, aluminum silicon carbide, or aluminum oxide. Second, the copper layer can be etched (e.g., chemically or by photolithography) to produce circuit traces, such as the first metal bus 14, the second metal bus 18, the metal island 22, the output conductive pad 66 and other conductive pads 77, and other pads or conductors. Third, the first semiconductor 34 and the second semiconductor 40 are soldered to their respective circuit traces or pads. Fourth, certain terminals of the first semiconductor 34 and the second semiconductor are connected to corresponding circuit traces on the DCB dielectric substrate by bonding wires. Fifth, dielectric barriers 28, 32 are placed above the conductive traces 14, 18, 22 on the circuit board assembly or dielectric substrate 10 to support the first conductive strips 24 and the second conductive strips 30, which can carry control signals to the first semiconductor 34 and the second semiconductor 40, respectively (e.g., through the tertiary terminals 44). The combination of the first dielectric barrier 28 and the first conductive strip 24 may be referred to as a first signal carrying bridge. Similarly, the combination of the second dielectric barrier 32 and the second conductive strip 30 may be referred to as a second signal carrying bridge.

[0036] In one configuration, the assembly may be placed in a housing and filled with a dielectric filler or potting, such as a silicone potting, to shield against contaminants, maintain dielectric insulation, and (structurally) support components, such as the first semiconductor 34 , the second semiconductor 40 , and the shunt resistor 62 .

[0037] In one embodiment, the electronic assembly 11 may include an inverter or converter, such as an inverter for converting a DC input to an AC output. The electronic assembly 11 is well suited for maintaining semiconductor devices, buses, connectors, current measurement devices, and any other heat generating components within a target operating temperature range to achieve proper full-function operation within thermal specifications. By combining the shunt resistor 62 and the output terminal into a single dual-purpose device, the current measurement system or shunt resistor 62 uses less space on the circuit board or direct copper-bonded dielectric substrate 10 than would otherwise be possible. In addition, by combining the shunt resistor 62 and the output terminal into a single dual-purpose device, the total number of solder joints in the electronic assembly 11 is reduced, which is achieved by avoiding solder joints using a dual-purpose device. The reduction in the number of solder joints can be associated with higher reliability and life of the electronic assembly 11 because the elimination of any solder joints eliminates the possibility of intermittent or unreliable electrical connections.

[0038] The resistance of the shunt resistor is sufficiently low because the heat load or heat generation capacity of the current resistor shunt is minimal. In contrast, the mass shunt of the metal body of the current resistor (which extends above the circuit board or direct copper-bonded substrate 10) facilitates cooling or heat dissipation from the metal island 22 or output pad 66, which tends to receive heat (e.g., through thermal conduction) from the semiconductor device (e.g., 34, 40).

[0039] Having described one or more preferred embodiments, it will be apparent that various modifications may be made without departing from the scope of the invention as defined in the appended claims.

Claims

1. An electronic component comprising: A direct copper bonded dielectric substrate, the direct copper bonded dielectric substrate comprising a dielectric layer; A first metal bus, the first metal bus covering the dielectric layer, the first metal bus having a bus width; a second metal bus overlying the dielectric layer and substantially parallel to the first metal bus, wherein the first metal bus and the second metal bus are associated with a DC terminal; a metal island region, wherein the metal island region is between the first metal bus and the second metal bus; A first metal strip, wherein the strip width of the first metal strip is smaller than the bus width, and the first metal strip is isolated from the metal island region by a first dielectric barrier; a second metal strip, wherein the strip width of the second metal strip is smaller than the width of the bus, and the second metal strip is isolated from the second metal bus by a second dielectric barrier; a set of one or more first semiconductors, each of the first semiconductors having at least one primary terminal and a secondary terminal, the at least one primary terminal of the first semiconductor being coupled to the first metal bus and the secondary terminal of the first semiconductor being coupled to the metal island; and a set of one or more second semiconductors, each of the second semiconductors having at least one primary terminal and a secondary terminal, the at least one primary terminal of the second semiconductor being coupled to the metal island region and the secondary terminal of the second semiconductor being coupled to the second metal bus, The first dielectric barrier and the second dielectric barrier are dielectric bridges with vertical supports, the first metal strip is elevated above the metal island through the first dielectric barrier, and the second metal strip is elevated above the second metal bus through the second dielectric barrier.

2. The electronic component according to claim 1, wherein: The first metal bus, the second metal bus and the metal island region are made of copper or copper alloy and are directly bonded to the dielectric layer via a base layer.

3. The electronic component according to claim 1, wherein: The first metal bus, the second metal bus, the first metal strip, and the second metal strip are made of copper or a copper alloy.

4. The electronic component according to claim 1, wherein: Each of the first semiconductors further includes a tertiary terminal coupled to the first metal strip; Each of the second semiconductors further comprises another tertiary terminal coupled to the second metal strip.

5. The electronic component according to claim 4, wherein: The tertiary terminals of the first semiconductor and the second semiconductor include bond wires directly bonded to the respective first and second metal strips.

6. The electronic component according to claim 4, wherein: The at least one primary terminal of the first semiconductor and the second semiconductor includes a set of a plurality of bond wires connected in parallel to support a greater current handling capability.

7. The electronic component according to claim 1, wherein: The secondary terminal of the first semiconductor includes a conductive pad on a lower surface of the first semiconductor, wherein the secondary terminal of the second semiconductor includes a conductive pad on a lower surface of the second semiconductor.

8. The electronic component according to claim 4, wherein: The primary terminal and the secondary terminal of the first semiconductor comprise a switch terminal of each of the first semiconductors, and wherein the tertiary terminal of the first semiconductor comprises a control terminal of each of the first semiconductors.

9. The electronic component according to claim 4, wherein: The primary terminal and the secondary terminal of the second semiconductor comprise a switch terminal of each second semiconductor, and wherein the tertiary terminal of the second semiconductor comprises a control terminal of each second semiconductor.

10. The electronic component according to claim 1, wherein The first metal strip has a parallel portion that is substantially parallel to the first metal bus, and wherein the first metal strip has a vertical portion that is substantially perpendicular to the parallel portion.

11. The electronic component according to claim 1, wherein: The first metal bus and the second metal bus are associated with DC terminals having corresponding holes.

12. The electronic component according to claim 1, wherein: Each of the first metal bus, the second metal bus, the first metal strip, and the second metal strip has a connection piece that is perpendicular to a corresponding one of the first metal bus, the second metal bus, the first metal strip, and the second metal strip.

13. The electronic component according to claim 12, wherein: The connecting piece terminates in a generally oval portion having a corresponding oval opening.

14. The electronic assembly according to claim 7, further comprising: A shunt resistor is mounted on the dielectric substrate and is spaced apart from the first semiconductor and the second semiconductor.

15. The electronic component according to claim 14, wherein: The shunt resistor also includes: a first annular member covering the metal island or the conductive pad on the dielectric layer, the first annular member being made of a conductive material, the first annular member having a base, a middle portion above the base, and an outer portion above the middle portion; and A second annular member coaxially engages the intermediate portion of the first annular member, the second annular member being constructed of a dielectric material, wherein terminals of the shunt resistor electrically and mechanically connect the base and the exterior.

16. The electronic assembly of claim 15, further comprising: A temperature sensor is embedded in the second annular member.

17. The electronic assembly of claim 16, further comprising: A plurality of terminals of the temperature sensor and terminals of the shunt resistor are connected to pads via bonding wires.

18. The electronic assembly of claim 15, further comprising: A current measurement circuit is coupled to the terminals of the shunt resistor to measure a voltage drop across the shunt resistor, the voltage drop being proportional to a current flowing in the shunt resistor.

19. An electronic component comprising: A direct copper bonded dielectric substrate, the direct copper bonded dielectric substrate comprising a dielectric layer; A first metal bus, the first metal bus covering the dielectric layer, the first metal bus having a bus width; a second metal bus overlying the dielectric layer and substantially parallel to the first metal bus, wherein the first metal bus and the second metal bus are associated with a DC terminal; A metal island region, the metal island region is between the first metal bus and the second metal bus, and the metal island region includes an output terminal pad; A first metal strip, wherein the strip width of the first metal strip is smaller than the bus width, and the first metal strip is isolated from the metal island region by a first dielectric barrier; a second metal strip, wherein the strip width of the second metal strip is smaller than the width of the bus, and the second metal strip is isolated from the second metal bus by a second dielectric barrier; a set of one or more first semiconductors, each first semiconductor having at least one primary terminal and a secondary terminal, the at least one primary terminal of the first semiconductor being coupled to the first metal bus and the secondary terminal of the first semiconductor being coupled to the metal island; a set of one or more second semiconductors, each second semiconductor having at least one primary terminal and a secondary terminal, the at least one primary terminal of the second semiconductor being coupled to the metal island and the secondary terminal of the second semiconductor being coupled to the second metal bus; and a shunt resistor covering a portion of the metal island or the output terminal pad associated with an output signal of the electronic component, the shunt resistor having a central hole and providing an output terminal for the output signal, The first dielectric barrier and the second dielectric barrier are dielectric bridges with vertical supports, the first metal strip is elevated above the metal island through the first dielectric barrier, and the second metal strip is elevated above the second metal bus through the second dielectric barrier.

20. The electronic assembly of claim 19, further comprising: a lower portion of the shunt resistor, the lower portion of the shunt resistor being electrically and mechanically connected to the metal island or the output terminal pad; The upper portion of the shunt resistor has a flat surface and a hole for receiving a cable or conductor that is terminated in an electrical connector to make an electrical and mechanical connection via a fastener.

21. The electronic assembly according to claim 20, wherein: The shunt resistor is used as both an output terminal and a shunt resistor to save space area on the surface of the direct-bonded copper dielectric substrate.

22. The electronic assembly of claim 19, wherein the first metal strip comprises at least a parallel portion that is substantially parallel to the first metal bus.

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