Interconnection method of isolated electrodes

Abstract

The invention discloses an interconnection method of isolated electrodes. The method comprises the following steps of: primarily filling an isolation trench of a chip with an electric isolation structure by using benzocyclobutene resin; first coating of metal stripping glue and photoresist is carried out on the wafer surface of the chip and in the isolation trench after preliminary filling; opening a to-be-thickened electrode window on the surface of the chip, and covering a first metal layer on the surface of the whole wafer through first thin gold sputtering; coating the metal stripping glue and the photoresist for the second time; opening a to-be-thickened electrode window on the surface of the chip through a photoetching technology, and covering a second metal layer on the surface of the wafer through secondary thin gold sputtering; electroplating the wafer integrally covered with the second metal layer; the electroplated chip is placed in an organic solvent for gold layer stripping, and metal layers formed after sputtering and electroplating of other functional areas are removed. The technical problem that an electric isolation structure cannot be spanned by an electroplating process is solved, and the reliability and the conductivity of electrode connection can be effectively ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for interconnecting isolation electrodes. Background Art

[0002] With the development of the integrated semiconductor industry, high-integration semiconductor lasers (such as EML, TEML, ITLA, etc.) have been widely used, and the requirements for chip performance are getting higher and higher. Among them, thickening the P-side electrode is one of the important means to improve optoelectronic performance. However, with the improvement of the integration degree of the functional area, the electrical isolation structure inside the chip has become an inevitable design requirement. Although the electrical isolation structure can effectively separate different functional areas, it also leads to the breakage of the current path, making the traditional electroplating process unable to meet the requirements, seriously restricting the production efficiency and yield of the chip.

[0003] The current mainstream solutions mainly include thickening the electrode by means of multiple electrode evaporation, sputtering, etc., or ensuring electrode connection by sacrificing the yield. However, these methods all have obvious deficiencies. Although the evaporation or sputtering technology can form electrodes in different regions, it cannot effectively solve the current interruption problem caused by the isolation structure, and in some cases, it will lead to a decrease in the chip yield. In addition, the method of sacrificing the chip yield will directly increase the production cost. It can be seen that the existing processes cannot balance the thickening of the electrode, the yield, and the cost control.

[0004] Therefore, the present invention proposes a method for interconnecting isolation electrodes to solve the technical problem that the electroplating process cannot cross the electrical isolation structure. By using two thin gold sputtering and electroplating to thicken the electrode area, and at the same time cooperating with the LOR glue coating technology, the reliability and conductivity of the electrode connection are effectively improved, and the yield reduction caused by the complication of the electroplating process is avoided. Through this innovative method, the chip performance is improved, the manufacturing cost is reduced, and the application of high-integration semiconductor lasers in a wider range of fields is promoted. Summary of the Invention

[0005] In view of this, the present invention provides a method for interconnecting isolation electrodes to solve the technical problems that the electroplating process cannot cross the electrical isolation structure, resulting in low chip yield and high production cost.

[0006] To achieve the above technical purpose, the present invention adopts the following technical solutions:

[0007] The present invention provides a method for interconnecting isolation electrodes, including:

[0008] Performing a deposition process on a chip with an electrical isolation structure to form an electrode on the chip surface, and preliminarily filling the isolation trench in the chip with benzocyclobutene resin;

[0009] Perform the first coating of metal stripping glue and photoresist on the wafer surface of the chip and in the isolation trenches after preliminary filling, so that the coated glue surfaces are at the same horizontal plane;

[0010] Open the electrode windows to be thickened on the chip surface through lithography technology, and cover the first metal layer on the surface of the entire wafer through the first thin gold sputtering;

[0011] Perform the second coating of metal stripping glue and photoresist on the first metal layer, and the distance between the edge of the coated colloid and the edge of the isolation trench is greater than the distance during the first coating;

[0012] Open the electrode windows to be thickened on the chip surface through lithography technology, and cover the second metal layer on the wafer surface through the second thin gold sputtering;

[0013] Electroplate the wafer entirely covered with the second metal layer to thicken the chip metal layer in the window opening area and ensure the contact performance of the electrodes;

[0014] Place the electroplated chip in an organic solvent for gold layer stripping to retain the thickened area of the electrode metal layer and remove the metal layers formed in other functional areas after sputtering and electroplating.

[0015] Further, the preliminary filling of the isolation trenches in the chip with benzocyclobutene resin includes:

[0016] Coat the benzocyclobutene resin on the wafer surface through a spin coater;

[0017] After exposure under preset exposure parameters, perform development and passivation operations.

[0018] Further, the thickness of the benzocyclobutene resin is 500 nm.

[0019] Further, the first coating of metal stripping glue and photoresist on the wafer surface of the chip and in the isolation trenches after preliminary filling includes:

[0020] Coat HMDS by spin coating and bake for the first duration at the first temperature condition;

[0021] Coat LOR glue and bake for the second duration at the second temperature condition;

[0022] Coat a layer of photoresist and then perform exposure and development;

[0023] Rinse with deionized water and blow dry.

[0024] Further, the first temperature condition is 120 °C and the first duration is three minutes.

[0025] Further, the second temperature condition is 170 °C, and the second duration is three minutes.

[0026] Further, the photoresist uses a positive photoresist with a thickness of 1 μm.

[0027] Further, the thickness ranges of the metal layers formed after the first thin gold deposition and the second thin gold deposition are both 10 - 50 nm.

[0028] Further, opening the electrode window to be thickened on the chip surface through photolithography technology includes:

[0029] Performing a developing operation after exposure under the condition that the exposure dose is 150 - 300 mj / cm 2 ².

[0030] Further, the thickness of the thickened metal layer of the electrode is within 2 μm.

[0031] Compared with the prior art, the advantages of the isolation electrode interconnection method provided by the present invention are as follows:

[0032] (1) By filling the isolation trench with benzocyclobutene resin, the flatness of the chip surface can be effectively improved.

[0033] (2) Through two LOR photoresist coating operations, the normal progress of the stripping process after electroplating is ensured.

[0034] (3) Through two thin gold sputtering technologies, not only the connection between the bottom electrode and the first thin gold layer is ensured, but also the thickness of the electrode surface is guaranteed, making the electrode have better conductivity and reliability.

[0035] In summary, the isolation electrode interconnection method provided by the present invention realizes the electrode interconnection of the chip with an isolation structure by a simple process, solves the technical problem that the electroplating process cannot cross the electrical isolation structure. By using two thin gold sputtering and electroplating to thicken the electrode area, and cooperating with the LOR photoresist coating technology, the reliability and conductivity of the electrode connection can be effectively guaranteed, and at the same time, the yield reduction caused by the complication of the electroplating process is avoided. Through the innovative method provided by the present invention, the chip performance can be effectively improved, the manufacturing cost can be reduced, thereby promoting the application of high-integration semiconductor lasers in a wider range of fields. Brief Description of the Drawings

[0036] Figure 1 is a schematic flow chart of the isolation electrode interconnection method provided by the present invention;

[0037] Figure 2 is a schematic cross-sectional view of a chip with an electrical isolation structure provided by the present invention;

[0038] Figure 3Schematic cross - sectional view of the chip after being filled with benzocyclobutene resin and completed the first coating provided by the present invention;

[0039] Figure 4 Schematic structural view of the chip after the first thin gold plating provided by the present invention;

[0040] Figure 5 Schematic structural view of the chip after the second coating provided by the present invention;

[0041] Figure 6 Schematic structural view of the chip after the second thin gold plating provided by the present invention;

[0042] Figure 7 Schematic structural view of the chip after electroplating provided by the present invention;

[0043] Figure 8 Schematic structural view of the chip finally completed with the thickening of the electrode metal layer provided by the present invention. Detailed implementation manners

[0044] The following combines the drawings to specifically describe the preferred embodiments of the present invention. Among them, the drawings constitute a part of this application and are used together with the embodiments of the present invention to explain the principle of the present invention, rather than to limit the scope of the present invention.

[0045] Please refer to Figures 1 - 8 , the embodiment of the present invention provides an interconnection method for isolation electrodes, including the following manufacturing steps:

[0046] Step S101: Perform a deposition process on the chip with an electrical isolation structure to form electrodes on the chip surface, and use benzocyclobutene resin to preliminarily fill the isolation trenches in the chip; as Figure 2 shows the schematic cross - sectional view of the chip with an electrical isolation structure after completing the electrode sputtering process;

[0047] Step S102: Perform the first coating of metal lift - off glue and photoresist on the wafer surface of the chip and in the preliminarily filled isolation trenches, so that the coated glue surfaces are at the same horizontal plane; as Figure 3 shown, Figure 3 shows the schematic cross - sectional view of the chip after being filled with benzocyclobutene resin and completed the first coating.

[0048] Step S103: Open the electrode window to be thickened on the chip surface through lithography technology, and cover the first metal layer on the entire wafer surface through the first thin gold sputtering; as Figure 4 shown, Figure 4 shows the schematic structural view of the chip after the first thin gold plating.

[0049] Step S104: Perform a second coating of metal stripping glue and photoresist on the first metal layer, with the distance between the edge of the coated colloid and the edge of the isolation trench being greater than that during the first coating; as Figure 5 shown, Figure 5 Figure 4 shows a schematic diagram of the chip structure after the second coating.

[0050] Step S105: Open the electrode window to be thickened on the chip surface through lithography technology, and cover the second metal layer on the wafer surface through the second thin gold sputtering; as Figure 6 shown, Figure 6 Figure 5 shows a schematic diagram of the chip structure after the second thin gold sputtering.

[0051] Step S106: Electroplate the wafer entirely covered with the second metal layer to thicken the chip metal layer in the window opening area and ensure the contact performance of the electrodes; as Figure 7 shown, Figure 7 Figure 6 shows a schematic diagram of the chip structure after electroplating.

[0052] Step S107: Place the electroplated chip in an organic solvent for gold layer stripping to retain the thickened area of the electrode metal layer and remove the metal layers formed in other functional areas after sputtering and electroplating; as Figure 8 shown, Figure 8 Figure 7 shows a schematic diagram of the chip structure finally completed with the thickened electrode metal layer.

[0053] In the method of this embodiment, first, the isolation trench is filled with benzocyclobutene resin to ensure the flatness of the wafer surface, making the coating of the metal stripping glue and photoresist more uniform and facilitating the stripping process. Secondly, the second thin gold ensures the connection between the bottom electrode and the first thin gold; finally, by coating the metal stripping glue and photoresist twice, it ensures the normal progress of the stripping process after electroplating.

[0054] As a specific embodiment, in step S101, the specific method of deposition treatment for the chip with an electrical isolation structure is the electrode sputtering process. After the electrode sputtering process, a thin metal film will be formed on the chip surface to ensure good electrical conductivity and stability of the circuit connection.

[0055] For chips with isolation trenches in the middle, such as traditional EML chips, EA, and DFB, the electroplating process cannot be used normally; on the basis of the completion of this structure, as a preferred embodiment, in step S101, first, the isolation trenches in the chip are preliminarily filled with benzocyclobutene resin, specifically including:

[0056] Coat the benzocyclobutene resin on the wafer surface through a spin coater;

[0057] After exposure under preset exposure parameter conditions, perform development and passivation operations.

[0058] Specifically, the detailed process of the filling process is as follows: Apply benzocyclobutene resin on the surface of the wafer through a spin coater with a rotation speed of 3000 - 4000 r, and perform exposure under an exposure parameter of 300 mj / cm 2 , develop for 120 s and passivate for 4 h.

[0059] Furthermore, the thickness of the benzocyclobutene resin is about 500 nm. An appropriate resin thickness helps to ensure the stability of the electrical isolation effect. Within the thickness range of 500 nm, the resin can be fully and smoothly filled into the isolation trench, improving the flatness of the isolation trench, thereby enhancing the overall quality of the chip and avoiding problems such as edge effects or insufficient filling caused by uneven thickness.

[0060] As a preferred embodiment, in step S102, the first coating of the metal stripping glue and photoresist on the surface of the wafer of the chip and in the isolation trench after preliminary filling includes:

[0061] Coat HMDS by spin coating and bake for the first duration under the first temperature condition;

[0062] Coat LOR glue and bake for the second duration under the second temperature condition;

[0063] Coat a layer of photoresist and then perform exposure and development;

[0064] Rinse with deionized water and then perform a drying operation.

[0065] In some embodiments, first coat a layer of HMDS (dimethylchlorosilane) on the surface of the wafer and bake at 120 degrees for 3 min, then coat LOR glue and bake at 170 degrees for 3 min, and finally coat a layer of 1 um positive photoresist and then perform exposure, development and cleaning processes. Sputter a thin gold layer with a thickness of 30 nm on the surface of the chip using a magnetron sputtering machine to complete the first thin gold operation.

[0066] As a specific embodiment, in step S103, open the electrode window to be thickened on the surface of the chip through lithography technology, specifically: develop for 60 seconds under an exposure dose of 150 - 300 mj / cm 2 . Cover the first metal layer on the surface of the entire wafer through the first thin gold sputtering.

[0067] Due to the undercut characteristic of LOR glue, it may cause the thin gold plating layer to be unable to be fully connected to the original electrode, affecting the electrical performance. Only performing one thin gold cannot ensure the connection with the original electrode. Therefore, in step S104, we perform secondary thin gold to ensure the connection between the bottom electrode and the first thin gold.

[0068] It should be noted that in step S104, since the window opening position of the second thin gold layer is different from that of the first thin gold layer, it is necessary to apply glue again.

[0069] As a specific embodiment, in step S105, the process details of the second thin gold layer are the same as those of the first thin gold layer, except for the position. The second thin gold layer is shorter than the first thin gold layer at the isolation table position, and the distance range is quantitatively limited within 5 microns, which can ensure electrode connection.

[0070] As a preferred embodiment, the thickness range of the metal layer formed after the first thin gold layer and the second thin gold layer is 10 - 50 nm. The metal layer must contain Au and may contain Ti - Pt. Gold (Au), as the main component of the metal layer, has very excellent electrical conductivity, corrosion resistance, and good solderability, enabling the metal layer to provide reliable electrical connections and being suitable for integrated circuits and microelectronic devices that require long - term stable operation. The addition of titanium (Ti) and platinum (Pt) can improve the adhesion and stability of the metal layer. Especially on certain substrates (such as silicon wafers or other semiconductor materials), the alloy layer of Ti - Pt can better react with the substrate surface to form a strong interfacial connection, thus preventing the peeling of the metal layer under high temperature or current stress.

[0071] As a preferred embodiment, in S106, the wafer covered with the second metal layer as a whole is electroplated to thicken the chip metal layer in the window opening area to ensure the contact performance of the electrodes. After placing the wafer in the electroplating equipment for electroplating, it is placed in an organic solvent for metal stripping to completely remove the gold sputtered and electroplated at other positions except the electrode area.

[0072] Electroplating to thicken the metal layer can ensure that the electrode area has sufficient electrical conductivity and corrosion resistance, enabling the electrode to withstand greater current and temperature changes during subsequent use, thereby extending the service life and reliability of the device.

[0073] Furthermore, the thickness of the thickened metal layer of the electrode is within 2 μm. A suitable metal layer thickness can not only provide sufficient electrical connection performance but also have no negative impact on the overall structure or subsequent process steps.

[0074] In summary, for the isolation electrode interconnection method provided by the present invention, filling the isolation trench with benzocyclobutene resin effectively improves the flatness of the chip surface; through two LOR glue coating operations, it ensures that the stripping process after electroplating can proceed normally; through two thin gold sputtering techniques, it not only ensures the connection between the bottom electrode and the first thin gold layer, but also guarantees the thickness of the electrode surface, making the electrode have better conductivity and reliability. The isolation electrode interconnection method provided by the present invention solves the technical problem that the electroplating process cannot cross the electrical isolation structure, can effectively ensure the reliability and conductivity of electrode connection, improve the chip performance, reduce the manufacturing cost, and promote the application of high-integration semiconductor lasers in a wider range of fields.

[0075] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A method for interconnecting isolated electrodes, characterized in that: include: Performing deposition processing on the chip with electrical isolation structure to form electrodes on the chip surface, and preliminarily filling the isolation groove in the chip with benzocyclobutene resin; The first coating of metal stripping glue and photoresist is performed on the wafer surface of the chip and in the isolation groove after preliminary filling, so that the coated glue surface is at the same level; The electrode window to be thickened is opened on the chip surface by photolithography technology, and the first metal layer is covered on the entire wafer surface by the first thin gold sputtering; Performing a second coating of metal stripping glue and photoresist on the first metal layer, wherein the distance between the edge of the coated glue and the edge of the isolation groove is greater than the distance during the first coating; The electrode window to be thickened on the chip surface is opened by photolithography technology, and the second metal layer is covered on the wafer surface by a second thin gold sputtering; Electroplating the wafer covered with the second metal layer as a whole to thicken the metal layer of the chip in the window area to ensure the contact performance of the electrode; The electroplated chip is placed in an organic solvent for gold layer stripping to retain the thickened metal layer area of ​​the electrode and remove the metal layer formed in other functional areas after sputtering and electroplating.

2. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The method of preliminarily filling the isolation trench in the chip with benzocyclobutene resin comprises: The benzocyclobutene resin is coated on the surface of the wafer through a coating device; After exposure under preset exposure parameter conditions, development and passivation operations are performed.

3. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The thickness of the benzocyclobutene resin is 500 nm.

4. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The first coating of metal stripping glue and photoresist on the wafer surface of the chip and in the isolation groove after preliminary filling includes: Applying HMDS by spin coating and baking at a first temperature for a first time; Apply LOR glue, and bake at a second temperature for a second time; After coating a layer of photoresist, exposure and development are performed; Rinse with deionized water and blow dry.

5. The method for interconnecting isolated electrodes according to claim 4, characterized in that: The first temperature condition is 120° C., and the first time duration is three minutes.

6. The method for interconnecting isolated electrodes according to claim 4, characterized in that: The second temperature condition is 170° C., and the second time period is three minutes.

7. The method for interconnecting isolated electrodes according to claim 4, characterized in that: The photoresist adopts a positive photoresist with a thickness of 1 um.

8. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The thickness of the metal layer generated after the first and second thin gold layers is in the range of 10-50 nm.

9. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The step of opening the electrode window to be thickened on the chip surface by photolithography technology comprises: At an exposure dose of 150-300 mj / cm 2 After exposure under the conditions, the development operation is performed.

10. The method for interconnecting isolated electrodes according to claim 1, characterized in that: The thickness of the thickened metal layer of the electrode is within 2 μm.

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