Method for manufacturing a semiconductor device having a channel-stopping region

Abstract

A channel stop region (191) is formed in an edge region of the component region (600) connected to the saw street region (800), which extends from the first main surface (701) into the component layer (710) of the first conductivity type. Thereafter, a doped region (120) is formed in the component region (600), which extends from the first main surface (701) into the component layer (710). The channel stop region (191) is formed by a photolithography method performed before a first photolithography method, which is used to introduce dopants into a section of the component region (600) outside the channel stop region (191).

Description

Technical Field

[0001] The present application relates to semiconductor devices having relatively high blocking capability, such as power semiconductor diodes and power semiconductor switches. Background Art

[0002] Vertical power semiconductor components are based on a semiconductor body having a first load electrode on the front side and a second load electrode on the back side. In the case of blocking, the electric field between the two load electrodes in the central active region of the semiconductor body is reduced in the vertical direction. The blocking capacity of the semiconductor body is significantly lower along the sides than in the bulk and is also more difficult to control. The purpose of the edge termination structure on the front side of the component is to reduce the electric field in the lateral direction so that the side surfaces of the semiconductor body remain field-free. The edge termination structure can, in particular, include a doped channel stopper region that typically extends from the front side into the semiconductor body near the outer edge of the semiconductor die. Summary of the Invention

[0003] The present disclosure aims to improve the reliability of edge termination structures.

[0004] The present disclosure relates to a method for manufacturing a semiconductor device. A trench stopper region is formed, which extends from a first main surface of a semiconductor substrate into a component layer of a first conductivity type in an edge termination region of the component region connected to a saw street region and is adjacent to or slightly spaced apart from the saw street region.

[0005] A component region corresponds to a section of a semiconductor substrate that a semiconductor device comprises at least. A saw street region denotes a portion of a semiconductor substrate from which material can be removed during the separation process of the semiconductor device from the semiconductor substrate composite without negatively affecting the component properties of the semiconductor device. For example, the sawing process removes material from a saw street within the saw street region, wherein the saw street region is wider than the actual saw street. Thus, in addition to the actual component region along the lateral sides, the semiconductor device may also have a residual section of the original saw street region.

[0006] Subsequently, a doped region of the first conductivity type or a complementary second conductivity type is formed in the component region at a first distance from the channel stopper region, the doped region extending from the first main surface into the component layer. The channel stopper region is formed by means of a photolithographic process, wherein the photolithographic process is performed before a first photolithographic process, wherein the first photolithographic process is used to introduce dopants into a section of the component region outside the channel stopper region.

[0007] In vertical components with a current flow between the component front and rear sides, a channel-stopping region prevents lateral diffusion of the space charge zone toward the component edge during blocking operation. The channel-stopping region can be the outermost region on the component front side, whose doping is higher than the base doping. The channel-stopping region can completely surround a central section of the component region.

[0008] The early formation of the channel stopper region at a point in time when no further laterally structured doped regions, such as the anode region of a semiconductor diode or the source or body region of a transistor cell, have yet been formed in the component region, allows a higher temperature budget to be used for forming the channel stopper region, since this temperature budget does not affect the other doped regions. The free temperature budget can be used, for example, for deep indiffusion of suitable dopants or for using only slowly diffusing dopants for the channel stopper region, making it possible to provide a channel stopper region with a relatively large vertical dimension.

[0009] If the vertical dimension of the channel stop region exceeds the vertical dimension of the doped region by at least a factor of two, for example, four or ten times, the space charge zone that expands from the inner component region toward the outer edge of the semiconductor body in a blocking situation will encounter the channel stop region in a section in which surfaces of equal dopant concentration have a relatively small curvature. Consequently, the field peak in the edge termination region is reduced, and the blocking capability of the semiconductor component is less affected by charges that accumulate at energetically favorable locations in the region of the edge termination structure or at the interface in the passivation layer above the edge termination structure and could negatively influence the electric field distribution. The robustness of the semiconductor component against corrosion caused by external charges and moisture is improved. During the production of semiconductor components, a sufficiently deep channel stop region can reduce clipping effects during separation from the wafer assembly.

[0010] According to one embodiment, constructing the channel stop region includes: constructing a first dopant mask on the first main surface and introducing a first dopant through a mask opening in the first dopant mask, wherein the mask opening exposes at least one section of the saw street region adjacent to or slightly spaced apart from the component region, so that the lateral width of the channel stop region is reduced while maintaining the same vertical dimension and the area efficiency of the semiconductor device can be improved.

[0011] The first dopant can be introduced, for example, through a section of the first main surface exposed by the mask opening of the first dopant mask. According to one embodiment, after the introduction of the first dopant, the following process sequence can be performed at least once more, the process sequence comprising: removing the first dopant mask; applying another component layer; forming another first dopant mask with a mask opening, wherein the mask opening exposes at least one section of the saw street region adjacent to the component region; and introducing the first dopant through the mask opening.

[0012] By means of this method, in which epitaxy and implantation (“Multi-Epi / Multi-Implant”) are alternated multiple times, the ratio of the vertical dimension to the lateral dimension of the channel stop region can be further improved.

[0013] According to another embodiment, a trench can be constructed before the introduction of the first dopant, the trench extending from the first main surface into the component layer so that the first dopant can be introduced into the component layer through the inner surface of the trench. With such a trench, the ratio of the vertical dimension to the lateral dimension of the channel interruption region can be further improved without increasing the required temperature budget. The trench can be constructed partially or completely in the saw street area and filled with a doped semiconductor material, wherein the doped semiconductor material can serve as a source of the first dopant. The trench can be constructed as an annular trench, which completely surrounds the active area in the laterally direction and shields the active area from fractures and clipping effects when the individual semiconductor bodies are separated from the semiconductor substrate along the saw streets in the saw street area.

[0014] The channel-stopping region can be formed at least partially by thermomigration. To this end, an n- or p-doped dopant source is applied to the semiconductor surface to be doped and then pressed into the lamella by creating a targeted vertical temperature gradient.

[0015] According to one embodiment, the first dopant contains phosphorus and / or selenium and / or sulfur. If, for example, the introduction of phosphorus and / or selenium and / or sulfur is followed by a high-temperature treatment at temperatures above 1000° C., the first dopant can be distributed over a relatively deep enough diffusion region, wherein a section of the diffusion region in the component region forms a channel stopper region, wherein the high-temperature treatment is performed before the doped region is formed in the inner component region.

[0016] The high-temperature treatment of the semiconductor substrate can be performed, for example, in an oxygen-containing atmosphere at temperatures exceeding 1000° C., with an oxide layer being formed on the first main surface. The formation of the channel stopper region can thus be effectively combined, for example, with the elimination of near-surface crystal defects caused by the growth of the oxide layer and the formation of a diffuse oxide, so that a deep channel stopper region can be provided with relatively little additional effort. According to one embodiment, the indiffusion is carried out at least temporarily in a wet oxidizing atmosphere, since under these conditions there is a very high concentration of interstitial silicon, which leads to a strongly accelerated diffusion of phosphorus or selenium atoms. The indiffusion is carried out immediately after the introduction of the dopant required for the channel stopper region, for example by ion implantation.

[0017] According to one embodiment, the formation of the channel stop region comprises plasma deposition of phosphorus, which can achieve a channel stop of greater than 1×10 17 cm -2 The resulting high density of implanted phosphorus facilitates phosphorus diffusion in the presence of a relatively strong doping gradient and enables the realization of such a deep trench stop region in a furnace process with a relatively small temperature / time budget.

[0018] Forming the channel stopper region may include forming hydrogen-related donors in the channel stopper region. Proton implantation with a relatively large range can generate hydrogen-related donors in the semiconductor substrate, thereby further increasing the net doping of the channel stopper region at a certain distance from the first main surface.

[0019] The channel-stopping region may completely surround an inner central region of the component region. In the component region, a vertical dimension of the channel-stopping region may decrease strictly monotonically with increasing distance from the saw street region, and a maximum vertical dimension of the channel-stopping region perpendicular to the first main surface may be greater than a lateral dimension parallel to the first main surface, such that a gain in depth of the channel-stopping region (Gewinn) hardly reduces the area efficiency of the semiconductor device.

[0020] A first dopant can be introduced into the edge termination region via the first main surface. According to another embodiment, a method for manufacturing a semiconductor device includes: introducing a first dopant into at least a section of a saw street region of a semiconductor substrate adjacent to or spaced apart from the component region, wherein a channel stop region is formed that extends laterally from the saw street region into the component region. A doped region is formed in the component region and spaced apart from the channel stop region, which forms a pn junction with the drift layer in the semiconductor substrate. The vertical dimension of the channel stop region in the component region can be greater than the lateral dimension, and in this case, the dopant concentration in the channel stop region in the component region decreases strictly monotonically with increasing distance from the saw street region.

[0021] The formation of the channel stop region by at least partially introducing dopants into a section of the saw street region adjacent to the component region or spaced apart from the component region makes it possible to achieve a relatively deep and narrow channel stop region in the component region, thereby increasing the robustness of the edge termination structure with respect to charges on the semiconductor surface without sacrificing active area.

[0022] The first dopant may include at least one of the dopants phosphorus, selenium, or sulfur. A high-temperature treatment can outdiffuse the first dopant, wherein the high-temperature treatment can be carried out in an oxidizing atmosphere, and according to one embodiment, in a wet oxidizing atmosphere, so that an oxide layer can be formed on the first main surface during the high-temperature treatment and the formation of the deep trench stop region can be effectively combined with the elimination of crystallographic errors, such as so-called crystal-origin particles (COPs).

[0023] Before introducing the first dopant, a trench can be formed that extends from the first main surface into the component layer, allowing the first dopant to be introduced into the component layer through the inner surface of the trench. With such a trench, the ratio of the vertical to the lateral dimensions of the channel-stopping region can be improved, even without high-temperature processing between the introduction of the first dopant and the formation of the doped region in the component region.

[0024] Additional features and advantages of the disclosed subject matter will become apparent to those skilled in the art from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings facilitate a deeper understanding of the present invention and are incorporated into and constitute a part of this disclosure. The drawings illustrate embodiments of the present invention and, together with the description, explain the principles of the present invention. Other embodiments and intended advantages of the present invention will become apparent from an understanding of the following detailed description.

[0026] Figure 1 is a simplified flow chart of a method for fabricating a semiconductor device having a deep trench stop region in accordance with one embodiment.

[0027] Figure 2A is a schematic vertical cross-sectional illustration of a semiconductor substrate section after formation of a trench stopper region, to illustrate a method for producing a semiconductor component according to one embodiment.

[0028] Figure 2B is based on Figure 2A Schematic vertical cross section of a semiconductor substrate section after the formation of a doped region at a distance from the channel interrupter region.

[0029] Figure 3A is a schematic vertical cross-section of a semiconductor device having a deep trench stop region used to illustrate the embodiments.

[0030] Figure 3B is used to illustrate these embodiments and to show the breakdown voltage and Figure 3A Schematic diagram of the vertical dimension of the deep channel cutoff region and its dependence on the external negative charge.

[0031] Figure 4A A first vertical doping profile for the channel-stopping region based on phosphorus implantation followed by high-temperature processing is shown for these illustrated embodiments.

[0032] Figure 4B A second vertical doping profile for the channel-stopping region based on phosphorus implantation followed by high-temperature processing is shown for these illustrated embodiments.

[0033] Figure 4C A third vertical doping profile of the channel-stopping region based on a phosphorus implantation and subsequent high-temperature treatment is shown for illustrating these embodiments.

[0034] Figure 4D A fourth vertical doping profile of the channel-stopping region based on a phosphorus implantation and subsequent high-temperature treatment is shown for illustrating these embodiments.

[0035] Figure 5A is a schematic vertical cross-sectional view of a semiconductor substrate section after phosphorus implantation, illustrating a method for producing a deeply n-doped channel stop region including a high-dose phosphorus implantation according to one embodiment.

[0036] Figure 5B is based on Figure 5A Schematic vertical cross section of a semiconductor substrate section after high temperature processing.

[0037] Figure 5C is based on Figure 5BSchematic vertical cross section through a semiconductor substrate section after the formation of a p-doped region at a distance from the channel interrupter region.

[0038] Figure 5D The semiconductor device is cut by sawing from the Figure 5C Schematic vertical cross section of a semiconductor body separated by semiconductor substrate segments.

[0039] Figure 6A is a schematic vertical cross section of a semiconductor substrate section having a first dopant mask with mask openings spaced apart from sawing regions in accordance with one embodiment.

[0040] Figure 6B is a schematic vertical cross section of a semiconductor substrate section having a first dopant mask with mask openings adjoining the sawing region according to one embodiment.

[0041] Figure 6C is a schematic vertical cross section of a semiconductor substrate section having a first dopant mask with mask openings overlapping sawing regions in accordance with one embodiment.

[0042] Figure 6D is a schematic vertical cross section of a semiconductor substrate section having a first dopant mask with mask openings formed only in the sawing region according to one embodiment.

[0043] Figure 7A is a schematic vertical cross-section of a semiconductor substrate segment having saw streets spaced apart from channel-stopping regions in accordance with one embodiment.

[0044] Figure 7B is a schematic vertical cross-section of a semiconductor substrate segment having a saw street adjoining a channel-stopping region in accordance with one embodiment.

[0045] Figure 7C is a schematic vertical cross-section of another semiconductor substrate segment having a saw street adjacent to a channel-stopping region in accordance with one embodiment.

[0046] Figure 7D is a schematic vertical cross section of a semiconductor substrate segment having a saw street adjoining a channel-stopping region according to another embodiment.

[0047] Figure 7E is a schematic vertical cross-section of a semiconductor substrate segment having a channel-stopping region spaced apart from a saw street region in accordance with one embodiment.

[0048] Figure 8Ais a schematic vertical cross-sectional illustration of a semiconductor substrate segment after trench formation to illustrate a method for producing a deep n-doped channel stopper region according to an embodiment including trench formation.

[0049] Figure 8B is based on Figure 8A Schematic vertical cross-sectional view of a semiconductor substrate section after high temperature processing.

[0050] Figure 8C is based on Figure 8B Schematic vertical cross-section of a semiconductor substrate section after the formation of a p-doped region at a distance from the channel interrupter region.

[0051] Figure 8D The semiconductor device is cut by sawing from the Figure 8C Schematic vertical cross section of a semiconductor body separated by semiconductor substrate segments.

[0052] Figure 9 is a simplified flow chart of a method for fabricating a semiconductor device having a deep trench stop region according to another embodiment.

[0053] Figure 10A is a schematic vertical cross-sectional illustration of a semiconductor substrate section after trench formation, illustrating a method for forming a deep trench stopper region according to an embodiment including trench formation.

[0054] Figure 10B is based on Figure 10B Schematic vertical cross section of a semiconductor substrate section after the formation of a doped region at a distance from the channel interrupter region.

[0055] Figure 10C The semiconductor device is cut by sawing from the Figure 10B Schematic vertical cross section of a semiconductor body separated by semiconductor substrate segments. DETAILED DESCRIPTION

[0056] In the following detailed description, reference is made to the accompanying drawings, which form part of the present disclosure and in which specific embodiments are shown for illustrative purposes. It goes without saying that further embodiments are possible and that structural or logical changes may be made to the embodiments without departing from the scope defined by the claims. In this respect, the description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of other described embodiments, unless the context indicates otherwise.

[0057] The terms "having", "comprising", "including", "having" and the like are open-ended terms which, on the one hand, specify the presence of the elements or features described, but do not exclude the presence of other elements or features. Unless otherwise clearly indicated by the context, the indefinite and definite articles include not only the plural but also the singular.

[0058] Some figures indicate relative dopant concentrations by specifying "-" or "+" next to the doping type. For example, "n-" means a lower dopant concentration than that of an "n"-doped region, while an "n+"-doped region has a higher dopant concentration than an "n"-doped region. Unless otherwise specified, the specification of relative dopant concentrations does not necessarily mean that doped regions with the same relative dopant concentration specification must have the same absolute dopant concentration. For example, two different "n"-doped regions can have the same or different absolute dopant concentrations.

[0059] Figure 1 The invention relates to a method for producing a semiconductor component, for example a vertical power semiconductor component such as a semiconductor diode, an IGBT (Insulated Gate Bipolar Transistor) or an HVMOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor).

[0060] A channel stop region extending from the first main surface into the component layer of the first conductivity type is formed in the component region connected to the saw street region, wherein the channel stop region can be adjacent to the saw street region (902). Thereafter, a doped region of the first conductivity type or a complementary second conductivity type is formed in the component region at a first distance from the channel stop region (904), extending from the first main surface into the component layer. The channel stop region is formed by means of a photolithography method performed before the first photolithography method, wherein the first photolithography method is used to introduce dopants into a section of the component region outside the channel stop region.

[0061] Figure 2A and 2B According to the cross section of the semiconductor substrate 700 Figure 1 method.

[0062] The semiconductor substrate 700 is based on a single crystal semiconductor material, such as silicon, germanium, silicon-germanium mixed crystal, silicon carbide or A III B V Compound semiconductors, such as GaN or GaAs.

[0063] The semiconductor substrate 700 has a first main surface 701 on the front side that is as planar as possible and a second main surface 702 on the back side that is substantially parallel to the first main surface 701. The direction perpendicular to the first main surface 701 defines a vertical direction. The direction parallel to the first main surface 701 is a lateral or horizontal direction.

[0064] The semiconductor substrate 700 includes at least one component layer 710 connected to the first main surface 701, wherein the component layer is unstructured in the lateral direction over its entire vertical and lateral dimensions, is uniformly doped at least in the lateral direction, and has no laterally separated doped regions. The component layer 710 is of a first conductivity type, for example, n-doped.

[0065] In the vertical direction, the dopant concentration in the component layer 710 may be constant or may vary depending on the distance from the first main surface 701 .

[0066] The semiconductor substrate 700 may further include a substrate segment 780, which may have a different conductivity type than the component layer 710. For example, the substrate segment 780 is a starting substrate sawn from a semiconductor crystal, and the component layer 710 is grown as an epitaxial layer on the starting substrate.

[0067] Semiconductor substrate 700 has component regions 600 arranged in columns and rows in a regular pattern. Adjacent component regions 600 are separated from each other by grid-like saw street regions 800. Each component region 600 includes a central active region 610 and an edge termination region 690 laterally surrounding active region 610 and separating active region 610 from saw street regions 800.

[0068] The actual saw street is located within saw street region 800 and does not necessarily coincide with the boundary line between component region 600 and saw street region 800. The boundary line can be defined such that deviations of the saw street beyond the boundary line into component region 600 result in a reduction in the breakdown voltage. In saw street region 800 below the channel-stopping region, the maximum field strength occurring when the breakdown voltage is applied is <100 V / cm.

[0069] In active region 610, semiconductor elements are subsequently formed that determine the nominal functionality of the semiconductor device, such as the anode region of a semiconductor diode, a switchable transistor cell of a MOSFET, MOS gated diode (MGD), IGBT, or thyristor, or the charge collection region of a radiation detector. In edge region 690, such semiconductor elements are absent. The edge region may have edge termination structures, such as field rings, JTE (junction termination extension) regions, or VLD (variation of lateral doping) regions, which ensure minimal blocking capability in the edge region.

[0070] A first mask layer is applied to the first main surface 701 and structured by photolithography. Thereafter, a first dopant 195 is introduced into predefined sections of the component layer 710 through mask openings 415 of a first dopant mask 410 emerging from the first mask layer, wherein the first dopant has the conductivity type of the component layer 710.

[0071] The first dopant 195 may contain phosphorus, selenium, and / or sulfur as well as hydrogen-related donors generated by implanted protons for a silicon semiconductor substrate 700 having an n-doped component layer 710 , and aluminum or boron for a semiconductor substrate 700 having a p-doped component layer 710 .

[0072] Figure 2A A first dopant mask 410 emerging from a first mask layer is shown, which has a mask opening 415, which can laterally completely surround the active region 610 and be spaced apart from the active region 610. The mask opening 415 can be completely within the edge termination region 690 and spaced apart from the saw street region 800, can adjoin the saw street region 800, can be formed only within the saw street region 800, or can overlap both the edge termination region 690 and the saw street region 800. The first dopant 195 is introduced into the section of the component layer 710 exposed by the mask opening 415.

[0073] During the subsequent high-temperature treatment, the first dopant 195 diffuses in the lateral and vertical directions. The first dopant mask 410 is removed. A second mask layer is applied and structured by photolithography. The second dopant is introduced into predefined sections of the component layer 710 through the mask openings 425 of the second dopant mask 420 emerging from the second mask layer.

[0074] Figure 2B A second dopant mask 420 with a mask opening 425 in the active region 610 and a doped region 120 containing the second dopant in the section of the component layer 710 exposed by the mask opening 425 are shown. Doped region 120 forms a first pn junction pn1 with a section of the component layer 710 that remains unaffected by the two implants, wherein the section that remains unaffected by the two implants constitutes a drift layer 731. Doped region 120 forms, for example, the anode region of a power semiconductor diode or a doped well forming the body region of a transistor cell for constructing a MOSFET or IGBT. For simplicity, only one coherent body region is shown here. In practice, multiple body regions are typically produced.

[0075] The doped region 120 is formed at a lateral distance from the channel stop region 191, which is formed by Figure 2A The channel stop region 191 is formed by vertical and lateral diffusion of the first dopant 195. The channel stop region 191 has the same conductivity type as the component layer 710 and forms a unipolar junction jn together with the drift layer 731, such as an n- / n+ junction or a p- / p+ junction, wherein the position of the unipolar junction jn is determined by the position of the maximum dopant concentration change on the line intersecting the unipolar junction jn.

[0076] Since no other doped regions have yet been formed in component layer 710 at the time of forming channel stopper region 191, a high temperature budget is available for forming channel stopper region 191, wherein this temperature budget can be used to provide channel stopper region 191 with a relatively large maximum vertical dimension v1 compared to the maximum vertical dimension v2 of doped region 120. For example, the maximum vertical dimension v1 or the depth of channel stopper region 191 is at least twice, for example, at least five times, or at least ten times, the maximum vertical dimension v2 of doped region 120.

[0077] If the mask openings 415 of the first dopant mask 410 at least partially overlap the saw street region 800, the lateral area requirement of the channel-stopping region 191 within the component region 600 can be further reduced. According to one embodiment, the maximum vertical dimension v1 of the channel-stopping region 191 is at least as large as the maximum lateral dimension w1, for example, at least twice or at least five times larger.

[0078] As a result, the unipolar junction jn between the drift layer 731 and the channel stop region 191, which is spaced apart from the first main surface 701 and corresponds to the maximum vertical dimension v2 of the doped region 120, has only a relatively small curvature, so that in the blocking case, the "collision" of the space charge region onto the channel stop region 191 does not produce a field peak, or only produces a field peak that is strongly reduced compared to the field peak when "colliding" with a section of the channel stop region with a strong curvature.

[0079] Figures 3A to 3B This relates to a semiconductor diode 500 manufactured using the described method and having a doped region 120 on the front side of the device, which forms the anode region. A JTE region 125 is connected to the doped region 120 in an edge termination region 690. An n+-doped channel-stopping region 191 extends from the first surface 101 into the semiconductor body 100 along the side surface 103 of the semiconductor body 100. The channel-stopping region 191 forms an n- / n+ junction with the n-doped drift zone 131, separating the p-doped regions 120, 125 on the front side from the more highly doped cathode layer on the rear side of the component and, in doing so, reducing the electric field in the vertical direction due to the barrier.

[0080] The maximum dopant concentration in the channel stop region 191 is approximately 5×10 18 cm -3 The maximum vertical dimension v1 of the channel stop region 191 is approximately twice the maximum lateral dimension w1 and approximately five times the maximum vertical dimension v2 of the doped regions 120 , 125 .

[0081] The first load electrode 310 contacts the doped region 120 on the component front side in the active region 610. In the edge termination region 690, the passivation layer 400 lies flat on the semiconductor body 100, laterally surrounds the first load electrode 310, and may cover a subsection of the first load electrode 310. Negative charges 250, such as OH, are schematically indicated in the passivation layer 400. - ions, fluoride ions or lithium ions, which can accumulate in the passivation layer 400 at locations that are energetically favorable to them.

[0082] exist Figure 3B In the example, the first line 921 is for 4 μm, Figure 3A The maximum vertical dimension v1 of the channel stop region 191 is shown in FIG. 1 , the second line 922 is for v1 = 20 μm, the third line 923 is for v1 = 40 μm, the fourth line 924 is for v1 = 100 μm, and the fifth curve 925 is for v1 = 200 μm to illustrate the breakdown voltage V of the edge termination region 690 PT The external integrated charge density Q in the volume of the passivation layer 400 F The deeper the channel stop region 191 is, the less the negative charge present in the passivation layer 400 has an influence on the breakdown voltage. From a vertical dimension or depth of 200 μm, no negative charge influence on the breakdown voltage that reduces the blocking capability can be detected any more.

[0083] Figures 4A to 4D The invention relates to a deep indiffusion of phosphorus for forming a channel-stopping region 191 in a silicon-based semiconductor substrate, wherein the indiffusion of phosphorus can be combined with diffusions of selenium and / or sulfur. In order to keep the maximum lateral dimension w1 of the channel-stopping region 191 small, the phosphorus can be introduced at least partially or only in the region of the saw streets, so that during sawing to separate the individual components from the semiconductor substrate, a large part of the diffusion region formed by the diffusion of phosphorus is removed, and only a relatively narrow range of lateral outdiffusion remains in the final semiconductor device.

[0084] Figure 4A The results show that for 5×10 15 cm -2The first vertical dopant profile 931 in the channel stop region is caused by the phosphorus implantation dose of 1.5 wt %. After high-temperature treatment at 1150°C for 20 hours, the channel stop region 191 has a depth of approximately 20 μm. If the high-temperature treatment is performed in an oxidizing atmosphere, a 20 nm thick oxide layer is grown in the same time period.

[0085] According to one embodiment, using more than 10 17 cm -2 Phosphorus is implanted by plasma deposition with an implantation dose of .

[0086] For example, Figure 4B For plasma deposition at an injection energy of 100 keV, the value is 2×10 17 cm -2 The phosphorus implantation dose of 930° C. shows a second vertical dopant profile 932 of the channel stop region after high temperature treatment at 1150° C. for 20 hours. The depth of the channel stop region is slightly less than 30 μm.

[0087] For example, with a nominal blocking voltage of 1.2 kV and a vertical drift region dimension of approximately 90 μm, in a silicon semiconductor device, a channel stop region having a vertical dimension of approximately 30 μm significantly reduces the dependence of the breakdown voltage on the negative charge in the passivation layer.

[0088] Figure 4C and 4D The third and fourth vertical dopant profiles 933, 934 are shown after 30 hours of high temperature treatment at 1106°C, with Figure 4A and 4B The achieved penetration depth was approximately 16 μm or slightly less than 30 μm.

[0089] The first dopant mask 410 is formed on the first main surface 701 of the semiconductor substrate 700 made of single-crystal silicon, wherein the semiconductor substrate has a component layer 710 connected to the first main surface 701. Through the grid-shaped mask openings 415 or a plurality of frame-shaped mask openings 415 in the first dopant mask 410, phosphorus is introduced at a rate of at least 10 15 cm -2 A dose of at least 10 16 cm -2 dose, or at least 10 17 cm -2 Phosphorus may be implanted into the component layer 710 at a dose of 100 keV. The implantation of phosphorus may include plasma deposition. The implantation energy may be in the range of 50 keV to 200 keV, for example, at about 100 keV.

[0090] Figure 5APhosphorus atoms of first dopant 195 are shown, introduced in a vertical projection of mask opening 415 in first dopant mask 410. In the illustrated embodiment, first dopant mask 410 completely covers component region 600 of semiconductor substrate 700, and mask opening 415 exposes at least a portion of saw street region 800. According to other embodiments, mask opening 415 can laterally overlap component region 600 or be formed only in the central region of saw street region 800. According to another embodiment, each component region is assigned a frame-shaped mask opening, which is respectively formed only within component region 600, only within saw street region 800, or overlapping within component region 600 and saw street region 800.

[0091] After the phosphorus implantation and removal of the first dopant mask 410, a high-temperature step follows at a temperature above 1000° C., and according to one embodiment, at a temperature above 1100° C. This high-temperature step can be used solely for phosphorus diffusion or for another purpose besides phosphorus diffusion, such as for forming an oxide layer on the first main surface 701. For example, in the high-temperature step, the semiconductor substrate 700 is held at a temperature of at least 1000° C. or at least 1100° C. in an oxidizing atmosphere for a duration of at least 1 hour, for example, at least 3 hours, wherein the oxide layer 210 is formed on the first main surface 701. According to one embodiment, the oxidation is performed in a humid atmosphere.

[0092] Figure 5B The oxide layer 210 on the first main surface 701 and the diffusion region 190 formed by the lateral and vertical diffusion of implanted phosphorus atoms are shown. The diffusion region 190 includes a first section forming a channel stop region 191 in the component region 600 and a second section 192 in the saw street region 800. The layer thickness of the oxide layer 210 is a few nanometers, for example, at least 5 nm or at least 10 nm, or even greater than 100 nm, or even greater than 1000 nm when wet oxidation is used. The oxide layer 210 can be a sacrificial oxide, the formation and subsequent removal of which removes near-surface crystal defects. The oxide layer 210 can also serve as a diffused oxide layer for subsequent implantation.

[0093] A second dopant mask 420 is formed on the oxide layer 210, or immediately after removing the oxide layer 210, on the first main surface 701. The second dopant mask 420 covers at least an outer section of the edge termination region 690 of the component region 600 and may completely cover the saw street region 800. Mask openings 425 in the second dopant mask 420 expose at least the central active region 610 of the component region 600. A second dopant of p-type conductivity is implanted through the mask openings 425.

[0094] Figure 5C A second doped region 120, formed by implanting a second dopant, is shown. It forms a first pn junction pn1 with a drift layer 731 near the substrate front side. The drift layer comprises a section of the component layer 710 outside the doped region 120 and outside the diffusion region 190. The doped region 120 is spaced apart from the diffusion region 190. One or more further implants can form further p-doped regions 125 or n-doped regions of an edge termination structure, such as field rings, JTE regions, or VLD regions, in the region between the doped region 120 and the diffusion region 190. The section of the drift layer 731 adjoining the first main surface 701 can separate the outermost doped region of such an edge termination structure, such as the p-doped region 125 of the JTE, from the diffusion region 190.

[0095] After further method steps, individual semiconductor bodies 100 are obtained from the semiconductor substrate 700 , for example by a sawing process. During the sawing process, the section of the semiconductor substrate 700 comprising the second section 192 of the diffusion region 190 is partially or completely consumed.

[0096] Figure 5D Shown by sawing process from Figure 5C A section of the semiconductor body 100 separated by the semiconductor substrate 700 .

[0097] The p-doped region 120 in the active region 610 is connected to the Figure 5C The drift region 131 formed by the section of the drift layer 731 forms a first pn junction pn1. For example, the p-doped region 120 forms the anode region of a semiconductor diode or the p-well of the body region of a transistor cell for a MOSFET. A further p-doped region 125 is formed in the edge termination region and can adjoin the p-doped region 120.

[0098] The channel stopper region 191 forms an n- / n+ junction jn with the drift zone 131, wherein a section of the drift zone 131 adjoining the first surface 101 of the semiconductor body 100 separates the channel stopper region 191 from the nearest p-doped region of complementary conductivity type. The position (Lage) of the n- / n+ junction jn is determined by the position of the maximum dopant concentration change on a line intersecting the n- / n+ junction. The channel stopper region 191 is formed in a lateral direction at a lateral distance d1 from the nearest p-doped region 120 , 125 , wherein, given a thickness D of the semiconductor body 100 between the first surface 101 and a second surface 101 opposite the first surface, the lateral distance d1 is at least D / 20 and at most 2×D.

[0099] The maximum vertical dimension v1 of the channel-stopping region 191 exceeds the maximum vertical dimension v2 of the p-doped region 120 by at least two times, for example, by at least five times or by at least ten times. The maximum vertical dimension v1 of the channel-stopping region 191 may be less than, equal to, or greater than the distance from the lower edge of the drift zone 131 to the first surface 101. For example, the maximum vertical dimension v1 of the channel-stopping region 191 is at least 20% and at most 100% of the distance d3.

[0100] In the channel-stopping region 191, the dopant concentration may decrease monotonically, for example, strictly monotonically, with increasing distance from the side 103. The maximum vertical dimension v1 may have the channel-stopping region 191 at the side 103. The vertical dimension may decrease monotonically, for example, strictly monotonically, with increasing distance from the side 103.

[0101] Figures 6A to 6D Different embodiments of a first dopant mask 410 for implanting a first dopant are shown.

[0102] exist Figure 6A In FIG. 4 , the first dopant mask 410 has a plurality of frame-shaped mask openings 415 , which each laterally surround the active region 610 of the component region 600 and space it apart from both the saw street region 800 and the active region 610 .

[0103] Figure 6B A frame-shaped mask opening 415 is shown directly adjacent to the saw street region 800 . Figure 6C Frame-shaped mask openings 415 are shown, which partially overlap respectively with the outermost sections of the edge termination region 690 of the component region 600 and with the sections of the saw street region 800 adjoining the component region 600 .

[0104] exist Figure 6D, the mask opening 415 is completely formed in the saw street region 800. Instead of a plurality of frame-shaped mask openings 415, the dopant mask 410 may include a single grid-shaped mask opening 415 that exposes at least a central section of the saw street region 800 and may expose the outermost section of the edge termination region 690 of the component region 600.

[0105] Figures 7A to 7E The various positions of saw streets 810 relative to component region 690 are shown. A separation process, such as sawing, laser dicing, or etching, removes sections 795 of semiconductor substrate 710 in saw streets 810, separating semiconductor substrate 710 into individual semiconductor bodies. The lateral width of saw streets 810 can be several tens of micrometers. Saw street region 800 corresponds to a tolerance window for permissible lateral position deviations of saw streets 810.

[0106] The boundary 681 between the saw street region 800 and the component region 600 can be defined in such a way that a lateral deviation of the saw street 810 into the component region 600 reduces the breakdown voltage of the component below a predetermined threshold value.

[0107] In the embodiments of Figures 7A to 7C, boundary line 681 runs through the lateral center of channel stop region 191 before the separation process.

[0108] exist Figure 7A In the embodiment shown in FIG. 1 , the saw street 810 extends at a distance d2 from the channel stop region 191. The semiconductor device obtained from the semiconductor substrate 700 includes the remaining section 699 of the saw street region 800 in addition to the component region 600. The distance d2 between the saw street 810 and the channel stop region 191 can be in the range of 0 μm to 200 μm, for example, in the range of 10 μm to 100 μm or in the range of 20 μm to 50 μm.

[0109] exist Figure 7B In FIG, the saw street 810 is adjacent to the channel stop region 191. Figure 7C , saw street 810 directly adjoins boundary line 681 .

[0110] exist Figure 7D In the embodiment shown in FIG. 1 , before the separation process, boundary line 681 is further shifted from the lateral center of channel-stopping region 191 in the direction of component region 600, so that channel-stopping region 191 formed in component region 600 includes less than 50% of the channel-stopping region before the separation process. If saw street 810 reaches boundary line 681 exactly, a narrow channel-stopping region 191 is obtained, whose vertical dimension decreases from the component edge.

[0111] exist Figure 7EIn the embodiment, the trench stopper region 191 is spaced apart from the saw street region 810 and is retained during the separation process. The distance d2 between the saw street 810 and the trench stopper region 191 can be in the range of 0 μm to 200 μm, for example, in the range of 10 μm to 100 μm or in the range of 20 μm to 50 μm.

[0112] Figures 8A to 8D This involves constructing the channel-stopping region 191 by introducing a first dopant through the inner surface of the trench 790 .

[0113] A trench etch mask 430 is formed on the first main surface 701, wherein mask openings 435 in the trench etch mask 430 are aligned with respect to the component region 600 and the saw street region 800. In the depicted embodiment, the trench etch mask 735 has a plurality of frame-shaped mask openings, which are each formed along the separation line between the component region 600 and the saw street region and overlap with the component region 600, the saw street region 800, or both.

[0114] In vertical projection of mask opening 435, trench 790 is introduced into component layer 710 of semiconductor substrate 700 by directional etching, for example by ion beam etching. Through the inner surface of trench 790, a first dopant, for example phosphorus, selenium or sulfur, is introduced.

[0115] The introduction of the first dopant can be performed by masked implantation or by masked in-diffusion by means of a first dopant mask, wherein the first dopant mask can be, for example, the trench etch mask 430. According to another embodiment, the trench 790 can be filled with a doped material, for example a doped semiconductor material, so that the introduction of the first dopant includes out-diffusion from the doping material.

[0116] Figure 8A The first dopant 195 introduced in the region of the trench 790 is shown for the case where the first dopant 195 is introduced by implantation or inward diffusion from the gas phase. The dopant mask is removed and the trench 790 is filled. The first dopant atoms diffuse vertically and laterally by a high-temperature process, for example, a high-temperature step for forming the oxide layer 210. To sufficiently dope the trench sidewalls, either an inclined implantation or plasma deposition can be used for implantation, which can result in a nearly uniform coverage of the sidewalls / trench bottom with the dopant.

[0117] Figure 8B The oxide layer 210 on the first main surface 701 and the diffusion region 190 with the nearly vertical n− / n+ junction jn over a long distance are shown.

[0118] Figure 8C and 8D Involving similar Figure 5C and 5D Process as described. Figure 8D The channel-stopping region 191 defined by the trench etching method has an almost vertical n- / n+ junction jn over a long distance. The region where the space charge zone impinges upon the channel-stopping region 191 during blocking has virtually no curvature. Consequently, the component's blocking capacity is relatively insensitive to charges in the passivation layer above the first surface.

[0119] Figure 9 A further method for producing a semiconductor device is disclosed. A first dopant is introduced (912) into at least a section of a saw street region of a semiconductor substrate adjacent to a component region, wherein a channel stop region is formed that extends laterally from the saw street region into the component region. A doped region is formed in the semiconductor substrate at a lateral distance from the channel stop region, the doped region forming a pn junction (914) with a drift layer, wherein a maximum vertical dimension of the channel stop region perpendicular to the first main surface is at least twice as large as a maximum vertical dimension of the doped region.

[0120] For the silicon carbide semiconductor substrate 700, the introduction of the first dopant can include: one or more implantations with an implantation energy higher than the implantation energy later used to construct the doped region in the active region, wherein each implantation can be implemented with the aid of an energy diffuser arranged in the optical path, which causes a more uniform vertical distribution of the first dopant 195.

[0121] Figures 10A to 10C Another method is involved for constructing the channel-stopping region 191 by introducing a first dopant through the inner surface of the trench 790 .

[0122] In a vertical projection of the mask opening 435 of the trench etch mask 730 , trenches 790 are introduced into the component layer 710 of the semiconductor substrate 700 . A first dopant, such as phosphorus, selenium, sulfur, or arsenic, is introduced into the component layer 710 through the inner surface of the trenches 790 .

[0123] Figure 10A The diffusion region 190 is shown formed by introducing a first dopant in the region of the trench 790. The formation of the diffusion region 190 may include a high temperature step. According to one embodiment, the formation of the diffusion region 190 is performed without a high temperature step.

[0124] Figure 10BP-doped regions 120 , 125 are shown, which are formed in a further process or already in the component region 600 before the diffusion region 190 and at a distance therefrom.

[0125] Figure 10C Shown by Figure 10B The channel stopper region 191 formed by the first section of the diffusion region 190 has almost no curvature over a large area of ​​its vertical dimension and its blocking capability is therefore as insensitive as possible to charges in the passivation layer of the semiconductor component above the first surface 101 of the semiconductor body 100.

[0126] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be replaced by numerous alternative configurations and / or equivalent configurations without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the present invention is limited only by the claims and their equivalents.

[0127] Reference Signs List

[0128] 100 semiconductor body

[0129] 101 First Surface

[0130] 103 Side

[0131] 120 Doped region

[0132] 125 Other doped areas

[0133] 131 Drift Zone

[0134] 190 diffusion area

[0135] 191 channel cutoff region

[0136] 192 Second Section

[0137] 195 First Dopant

[0138] 210 oxide layer

[0139] 250 Charge

[0140] 310 first load electrode

[0141] 400 passivation layer

[0142] 410 First dopant mask

[0143] 415 Mask opening of the first dopant mask

[0144] 420 Second dopant mask

[0145] 425 Mask opening of the second dopant mask

[0146] 430 Trench Etching Mask

[0147] 435 Mask opening of trench etch mask

[0148] 500 semiconductor diodes

[0149] 600 component area

[0150] 610 active area

[0151] 681 Boundary

[0152] 690 Edge Termination Area

[0153] 699 remaining segments

[0154] 700 semiconductor substrates

[0155] 701 first main surface

[0156] 702 second main surface

[0157] 710 Component Layer

[0158] 731 Drift Layer

[0159] 780 substrate segment

[0160] 790 Groove

[0161] 795 section

[0162] 800 Saw Road Area

[0163] 810 saw track

[0164] 902 Methods and Steps

[0165] 904 Methods and Steps

[0166] 912 Methods and Steps

[0167] 914 Methods and Steps

[0168] 921 First Line

[0169] 922 Second Line

[0170] 923 Third Line

[0171] 924 Fourth Line

[0172] 925 Fifth Line

[0173] 931 First Vertical Dopant Distribution

[0174] 932 Second vertical dopant distribution

[0175] 933 Third Vertical Dopant Distribution

[0176] 934 Fourth vertical dopant distribution

[0177] v1 Maximum vertical dimension of the channel-truncation region

[0178] v2 Maximum vertical dimension of the doped region

[0179] w1 Maximum lateral dimension of the channel-intercepting region

[0180] d1 horizontal spacing

[0181] d2 spacing

[0182] pn pn junction

[0183] jn unipolar junction

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Constructing a channel stop region (191) in an edge termination region (690) of the component region (600) connected to the saw street region (800), the channel stop region (191) extending from the first main surface (701) into the component layer (710) of the first conductivity type; as well as A doped region (120) is formed in the component region (600) and extends from the first main surface (701) into the component layer (710), wherein The channel stopper region (191) is formed by means of a photolithographic process carried out before a first photolithographic process, wherein the first photolithographic process is used to introduce dopants into a section of the component region (600) outside the channel stopper region (191), wherein constructing the channel stop region (191) comprises: constructing a first dopant mask (410) on the first main surface (701) and introducing a first dopant (195) through a mask opening (415) of the first dopant mask (410), wherein the mask opening (415) exposes at least a section of the saw street region (800), wherein the first dopant (195) is introduced through a section of the first main surface (701) exposed by the mask opening (415) of the first dopant mask (410), wherein, after introducing the first dopant (195), the following process sequence is carried out at least once more, the process sequence comprising: removing the first dopant mask (410); applying a further component layer to the first main surface (701); constructing a further first dopant mask (410) having a mask opening (415), the mask opening (415) of the further first dopant mask (410) exposing at least one section of the saw street region (800); and The first dopant (195) is introduced through the mask opening (415) in the further first dopant mask (410).

2. The method according to claim 1, wherein The channel-stopping region (191) is adjacent to the saw street region (800) or extends into the saw street region (800).

3. The method according to claim 1, wherein The channel stop region (191) is spaced apart from the saw street region (800).

4. The method according to claim 1, wherein Before the first dopant (195) is introduced, a trench (790) is formed, wherein the trench extends from the first main surface (701) into the component layer (710), and wherein the first dopant (195) is introduced into the component layer (710) through the inner surface of the trench (790).

5. The method according to claim 4, wherein The groove (790) is at least partially formed in the saw street region (800).

6. The method according to claim 4 or 5, wherein: The trench is filled (790) with a doped semiconductor material of a first conductivity type.

7. The method according to any one of claims 1 to 3, wherein The channel-stopping region (191) is at least partially structured by thermomigration.

8. The method according to any one of claims 1 to 3, wherein: The first dopant (195) contains at least selenium, sulfur or phosphorus.

9. The method according to any one of claims 1 to 3, wherein Constructing the channel stop region (191) includes: a high-temperature treatment at a temperature of at least 1000° C., the high-temperature treatment being performed after introducing the first dopant and before constructing the doped region (120), and distributing the first dopant (195) onto the diffusion region (190) by the high-temperature treatment, wherein the diffusion region (190) forms the channel stop region (191) in a first section in the component region (600).

10. The method according to claim 9, wherein: The high-temperature treatment is carried out at a temperature above 1000° C. in an oxygen-containing environment, wherein an oxide layer (210) is formed on the first main surface (701).

11. The method according to any one of claims 1 to 3, wherein Constructing the channel stop region (191) includes plasma deposition of phosphorus.

12. The method according to any one of claims 1 to 3, wherein Constructing the channel stop region (191) includes constructing hydrogen-related donors in the channel stop region (191).

13. The method according to any one of claims 1 to 3, wherein The channel stop region (191) completely surrounds the active region (610).

14. The method according to any one of claims 1 to 3, wherein The maximum vertical dimension (v1) of the channel stop region (191) perpendicular to the first main surface (701) is at least twice the maximum vertical dimension (v2) of the doped region (120).

15. The method according to any one of claims 1 to 3, wherein In the component region (600), the vertical dimension of the channel-stopping region (191) decreases strictly monotonically with increasing distance to the saw street region (800).

16. The method according to any one of claims 1 to 3, wherein In the component region (600), a maximum vertical dimension (v1) of the channel stop region (191) perpendicular to the first main surface (701) is greater than a maximum lateral dimension (w1) of the channel stop region (191) in the component region (600) parallel to the first main surface (701).

17. A method for manufacturing a semiconductor device, the method comprising: introducing a first dopant (195) through a mask opening (415) of a dopant mask (410) into at least a section of a saw street region (800) of a semiconductor substrate (700) adjacent to a component region (600), wherein the dopant mask (410) exposes at least one section of the saw street region (800), wherein a channel stop region (191) is formed extending laterally from the saw street region (800) into the component region (600); and A doped region (120, 125) is formed at a distance from the channel stop region (191), wherein the doped region (120, 125) in the semiconductor substrate (700) forms a pn junction with a drift layer (731) and wherein a maximum vertical dimension (v1) of the channel stop region (191) perpendicular to the first main surface (701) is at least twice as large as a maximum vertical dimension (v2) of the doped region (120, 125); wherein, after introducing the first dopant (195), the following process sequence is performed at least once more, the process sequence comprising: removing the dopant mask (410); applying a further component layer to the first main surface (701); constructing a further dopant mask (410) having a mask opening (415), the mask opening (415) of the further dopant mask (410) exposing at least one section of the saw street area (800); and introducing the first dopant (195) through the mask opening (415) in the further dopant mask (410).

18. The method according to claim 17, wherein The first dopant (195) comprises at least one of the dopants selenium, sulfur or phosphorus, and the diffusion of the first dopant (195) comprises: a high temperature treatment in an oxidizing atmosphere, and wherein an oxide layer (210) is formed on the first main surface (701) during the high temperature treatment.

19. The method according to claim 17 or 18, wherein Before the first dopant (195) is introduced, a trench (790) is formed, wherein the trench extends from the first main surface (701) into the semiconductor substrate (700), and wherein the first dopant (195) is introduced into the component layer (710) through the inner surface of the trench (790).

20. The method according to claim 17 or 18, wherein The drift layer (731) and the channel stop region (191) form a unipolar junction (jn).

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