Semiconductor memory package

Abstract

A semiconductor memory package is provided. The package includes: a base substrate and chip connection pads and external connection pads respectively arranged on the upper surface and the lower surface of the base substrate; and two semiconductor memory chips mounted on the base substrate, each semiconductor memory chip having a chip pad electrically connected to the chip connection pad. A first electrical path extends from the external connection pad to a first chip pad of one of the chips, and a second electrical path extends from the external connection pad to a second chip pad of another chip, the first electrical path and the second electrical path have a common line, and the first electrical path has a first branch line, and the second electrical path has a second branch line. The base substrate includes an open short stub extending from the common line, and the open short stub has an open end that is not connected to the other electrical path.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0000269 filed on January 2, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] The inventive concept relates to a semiconductor memory package, and more particularly, to a semiconductor memory package in which a plurality of semiconductor memory chips are connected to a memory interface of one channel.

[0004] With the rapid development of the electronics industry and user needs, electronic devices are required to be more compact and have higher capacity. However, the high capacity of semiconductor memory chips can no longer meet this demand. Therefore, multiple semiconductor memory chips connected to one channel storage interface are included in one semiconductor memory package to meet the demand for high capacity. Summary of the invention

[0005] The inventive concept provides a semiconductor memory package having a high-speed operation characteristic and having a plurality of semiconductor memory chips.

[0006] According to an aspect of an example embodiment, there is provided a semiconductor memory package, comprising: a package base substrate, the package base substrate comprising a base substrate and a plurality of chip connection pads and a plurality of external connection pads respectively arranged on an upper surface and a lower surface of the base substrate; and at least two semiconductor memory chips, the at least two semiconductor memory chips being mounted on the package base substrate and each semiconductor memory chip having a plurality of chip pads electrically connected to the plurality of chip connection pads, wherein a first electrical path extends from one of the plurality of external connection pads to a first chip pad of one of the at least two semiconductor memory chips, and a second electrical path extends from the one of the plurality of external connection pads to the at least two semiconductor memory chips. a second chip pad of another semiconductor storage chip in the package, the first electrical path and the second electrical path include a common line extending from a branch point of the first electrical path and the second electrical path to the one external connection pad among the plurality of external connection pads, a first branch line of the first electrical path extends from the branch point to the first chip pad, a second branch line of the second electrical path extends from the branch point to the second chip pad, and the package base substrate includes an open short-circuited stub extending from the common line, the open short-circuited stub having one end connected to the common line and the other end which is open and not connected to the other electrical path, and a stub extension length of the open short-circuited stub is greater than half of a branch extension length of a longer branch line among the first branch line and the second branch line and less than twice the branch extension length.

[0007] According to another aspect of an example embodiment, a semiconductor memory package is provided, comprising: a package base substrate, the package base substrate comprising: a substrate base, a plurality of chip connection pads arranged on an upper surface of the substrate base and a plurality of external connection pads arranged on a lower surface of the substrate base and electrically connected to the plurality of chip connection pads, and an open short-circuited line, the open short-circuited line comprising one end electrically connected to one of the plurality of external connection pads and another end extending from the one end and being open and not connected to another electrical path; at least two semiconductor memory chips, the at least two semiconductor memory chips being mounted on the package base substrate, each semiconductor memory chip having a chip connection terminal pad, a chip pad and a rewiring pattern connecting the chip connection terminal pad to the chip pad, and each semiconductor memory chip having at least one bonding wire connecting the chip connection terminal pad to one or more of the plurality of chip connection pads.

[0008] According to another aspect of an example embodiment, there is provided a semiconductor memory package, comprising: a package base substrate, the package base substrate comprising: a base substrate including a plurality of layers, a plurality of chip connection pads arranged on an upper surface of the base substrate and a plurality of external connection pads arranged on a lower surface of the base substrate and electrically connected to the plurality of chip connection pads, a ground plane layer formed between the plurality of layers included in the base substrate, and an open stub electrically connected to one of the plurality of external connection pads and extending between the plurality of layers away from the ground plane layer; a first semiconductor memory chip attached to the package base substrate and a first semiconductor memory chip stacked on the first semiconductor memory chip; A second semiconductor storage chip on a chip, the first semiconductor storage chip having a first chip connection terminal pad, a first chip pad and a first rewiring pattern connecting the first chip connection terminal pad to the first chip pad, the second semiconductor storage chip having a second chip connection terminal pad, a second chip pad and a second rewiring pattern connecting the second chip connection terminal pad to the second chip pad; and a first bonding wire connecting the first chip connection terminal pad to one or more chip connection pads among the multiple chip connection pads, and a second bonding wire connecting the second chip connection terminal pad to one or more chip connection pads among the multiple chip connection pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0011] Figure 2 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0012] Figure 3 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0013] Figure 4 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0014] Figure 5 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0015] Figure 6 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0016] Figure 7 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0017] Figure 8 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0018] Fig. 9 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0019] Fig.10 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0020] Fig.11 is a cross-sectional view of a semiconductor memory package according to an example embodiment;

[0021] Fig.12 is a schematic diagram of a channel of a semiconductor memory package according to an example embodiment;

[0022] FIG. 13A to FIG. 13E is a graph of a waveform arriving at a receiver in a channel of a semiconductor memory package according to an example embodiment;

[0023] Figures 14 to 18 is a layout of a wiring pattern of a package base substrate of a semiconductor memory package according to example embodiments; and

[0024] FIG. 19A to FIG. 19D is a signal eye diagram for comparing a semiconductor memory package according to example embodiments with a semiconductor memory package of a comparative example. DETAILED DESCRIPTION

[0025] Figure 1 is a cross-sectional view of a semiconductor memory package 1 according to example embodiments.

[0026] Reference Figure 1 , the semiconductor memory package 1 includes a package base substrate 100 and at least two semiconductor memory chips 200 .

[0027] In some exemplary embodiments, the package base substrate 100 may be a printed circuit board (PCB). For example, the package base substrate 100 may be a double-sided PCB or a multi-layer PCB. The package base substrate 100 may include a base substrate 110. The base substrate 110 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The base substrate 110 may include at least one material selected from, for example, flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxide / polyphenylene ether, bismaleimide triazine (BT), aramid paper, cyanate ester, polyimide, and liquid crystal polymer.

[0028] The package base substrate 100 may have wiring patterns 120 formed on the upper and lower surfaces of the base substrate 110. In some example embodiments, if the package base substrate 100 is a multi-layer substrate in which the base substrate 110 includes a plurality of layers, the wiring patterns 120 may be formed between each of the plurality of layers of the base substrate 110. The package base substrate 100 may include a conductive via 130 connected to the wiring pattern 120 in the base substrate 110. The conductive via 130 may penetrate all or a portion of the base substrate 110 to be electrically connected to the wiring pattern 120. The wiring pattern 120 and / or the conductive via 130 may include copper, nickel, stainless steel, or beryllium copper.

[0029] A solder resist layer (not shown) may be formed on the upper and lower surfaces of the package base substrate 100 to cover at least a portion of the wiring pattern 120 arranged on the upper and lower surfaces of the base substrate 110. Portions of the wiring pattern 120 arranged on the upper and lower surfaces of the base substrate 110 that are not covered by the solder resist layer may be a plurality of chip connection pads 122 electrically connected to at least two semiconductor memory chips 200 and a plurality of external connection pads 124 electrically connected to a plurality of external connection terminals 500.

[0030] When the external connection terminals 500 are solder balls, the external connection pads 124 may be referred to as a ball land pattern. When the external connection terminals 500 are pins, the external connection pads 124 may be referred to as a pin land pattern.

[0031] A portion of the wiring pattern 120 may be an open stub 126 extending from a portion connecting the chip connection pad 122 and the external connection pad 124 corresponding to the chip connection pad 122. In other words, the open stub 126 may extend from the chip connection pad 122, the external connection pad 124, and / or a portion between the chip connection pad 122 and the corresponding external connection pad 124. Fig.12 The open stub 126 is described in detail.

[0032] In some example embodiments, if the package base substrate 100 is a multi-layer substrate in which the base substrate 110 includes a plurality of layers, some of the wiring patterns 120 formed between the plurality of layers of the base substrate 110 may include a ground plane layer 128 provided with a ground signal. The ground plane layer 128 may be located at a level closer to the lower surface than the upper surface of the base substrate 110.

[0033] At least two semiconductor memory chips 200 may be mounted on the package base substrate 100. In some example embodiments, at least two semiconductor memory chips 200 may be vertically stacked on the package base substrate 100, but example embodiments are not limited thereto. At least two semiconductor memory chips 200 may include a plurality of chip connection terminal pads 212 and 222, a plurality of chip pads 214 and 224, and a plurality of rewiring patterns 216 and 226.

[0034] The at least two semiconductor memory chips 200 may include a first semiconductor memory chip 210 and a second semiconductor memory chip 220. In some example embodiments, the first semiconductor memory chip 210 may be mounted on the upper surface of the package base substrate 100 with a first die adhesive film 218 therebetween, and the second semiconductor memory chip 220 may be mounted on the first semiconductor memory chip 210 with a second die adhesive film 228 therebetween.

[0035] The first semiconductor memory chip 210 and the second semiconductor memory chip 220 may be the same kind of semiconductor memory chips having the same capacity. Unless otherwise specified, the description of the first semiconductor memory chip 210 may also be applied to the second semiconductor memory chip 220.

[0036] Each of the first semiconductor storage chip 210 and the second semiconductor storage chip 220 may include a semiconductor substrate. The semiconductor substrate may include, for example, silicon (Si). Alternatively, the semiconductor substrate may include semiconductor elements such as germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate may have an active surface and a passive surface relative to the active surface. The first semiconductor storage chip 210 and the second semiconductor storage chip 220 may be formed by semiconductor devices including a plurality of individual devices of various types on the active surface.

[0037] The first semiconductor memory chip 210 and the second semiconductor memory chip 220 may be, for example, volatile semiconductor memory chips such as dynamic random access memory (DRAM) or static random access memory (static RAM), or non-volatile semiconductor memory chips such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM) or resistive RAM (RRAM).

[0038] The first semiconductor memory chip 210 may include a plurality of first chip connection terminal pads 212 on an active surface, a plurality of first chip pads 214, and a first rewiring pattern 216 connecting each first chip connection terminal pad 212 to each first chip pad 214. Similarly, the second semiconductor memory chip 220 may include a plurality of second chip connection terminal pads 222 on an active surface, a plurality of second chip pads 224, and a second rewiring pattern 226 connecting each second chip connection terminal pad 222 to each second chip pad 224. The number of the plurality of first chip connection terminal pads 212 and the number of the plurality of first chip pads 214 may be the same, and the number of the plurality of second chip connection terminal pads 222 and the number of the plurality of second chip pads 224 may be the same.

[0039] A plurality of first chip pads 214 and a plurality of second chip pads 224 may be respectively arranged in a center pad manner at a center portion of an active surface of a corresponding one of the first semiconductor memory chip 210 and the second semiconductor memory chip 220. The plurality of first chip pads 214 may be electrically connected to a semiconductor device of the first semiconductor memory chip 210, and the plurality of second chip pads 224 may be electrically connected to a semiconductor device of the second semiconductor memory chip 220.

[0040] The first and second rewiring patterns 216 and 226 may extend on active surfaces of the first and second semiconductor memory chips 210 and 220 , respectively.

[0041] Each of the multiple first chip connection terminal pads 212 can be electrically connected to the semiconductor device of the first semiconductor storage chip 210 through the first rewiring pattern 216 and the first chip pad 214, and each of the multiple second chip connection terminal pads 222 can be electrically connected to the semiconductor device of the second semiconductor storage chip 220 through the second rewiring pattern 226 and the second chip pad 224.

[0042] In some example embodiments, a plurality of first chip pads 214 and a plurality of second chip pads 224 may be arranged in an edge pad manner at an edge portion of an active surface of a corresponding one of the first semiconductor memory chip 210 and the second semiconductor memory chip 220, respectively. Here, the first semiconductor memory chip 210 and the second semiconductor memory chip 220 may omit the first chip connection terminal pad 212 and the first rewiring pattern 216 and the second chip connection terminal pad 222 and the second rewiring pattern 226, respectively. The plurality of first chip pads 214 may perform the function of the first chip connection terminal pad 212 together, and the plurality of second chip pads 224 may perform the function of the second chip connection terminal pad 222 together.

[0043] In some example embodiments, even when a plurality of first chip pads 214 and a plurality of second chip pads 224 are respectively arranged in an edge pad manner at an edge portion of an active surface of a corresponding one of the first semiconductor storage chip 210 and the second semiconductor storage chip 220, the first semiconductor storage chip 210 and the second semiconductor storage chip 220 may also have a first chip connection terminal pad 212 and a first rewiring pattern 216 and a second chip connection terminal pad 222 and a second rewiring pattern 226, respectively.

[0044] At least two semiconductor memory chips 200 may be electrically connected to the package base substrate 100 through a plurality of bonding wires 300. In more detail, the at least two semiconductor memory chips 200 and the package base substrate 100 may be electrically connected to each other through a plurality of bonding wires 300 that respectively connect the plurality of chip connection terminal pads 212 and 222 to the plurality of chip connection pads 122. The plurality of bonding wires 300 may include a first bonding wire 310 that connects the chip connection pad 122 to the first chip connection terminal pad 212 of the first semiconductor memory chip 210, and a second bonding wire 320 that connects the chip connection pad 122 to the second chip connection terminal pad 222 of the second semiconductor memory chip 210.

[0045] A molding member 400 covering the at least two semiconductor memory chips 200 and the bonding wires 300 may be disposed on the package base substrate 100. The molding member 400 may include, for example, epoxy molding compound (EMC).

[0046] The plurality of external connection terminals 500 may be respectively attached to the plurality of external connection pads 124 of the package base substrate 100. The plurality of external connection terminals 500 may include first external connection terminals 502 for transmitting or receiving relatively high speed signals and second external connection terminals 504 for transmitting or receiving relatively low speed signals.

[0047] For example, among the plurality of external connection terminals 500, the first external connection terminal 502 may be used for data input / output (DQ) or a clock signal (CK), and the second external connection terminal 504 may be used for the rest of the signals except for those signals for which the first external connection terminal 502 is intended. For example, the second external connection terminal 504 may be used for command input (CMD), address input (A), chip select (CS), power supply DQ power supply (VDDQ), power supply DQ ground (VSSQ), power supply reference pin (ZQ) for ZQ calibration, etc. In some example embodiments, some of the plurality of external connection terminals 500 may be used for no connection (NC) having no internal electrical connection.

[0048] Although Figure 1The first external connection terminal 502 is shown on the left and the second external connection terminal 504 is shown on the right, but this is only for convenience of explanation. The positions and numbers of the first external connection terminal 502 and the second external connection terminal 504 are not limited thereto.

[0049] Each of the first external connection terminal 502 and the second external connection terminal 504 may be electrically connected to the chip connection pad 122 through the external connection pad 124, the wiring pattern 120 in the substrate base 110, and / or the conductive via 130. The wiring pattern 120 and / or the conductive via 130 in the substrate base 110 for electrically connecting the chip connection pad 122 and the external connection pad 124 corresponding to each other may be referred to as an internal wire.

[0050] The first and second bonding wires 310 and 320 may be commonly connected to one of the chip connection pads 122. The first and second bonding wires 310 and 320 may be connected to the first and second chip connection terminal pads 212 and 222 of the first and second semiconductor memory chips 210 and 220, respectively.

[0051] The external connection pad 124 to which the first external connection terminal 502 is attached may be referred to as a package terminal PKT. The electrical path between the external connection pad 124 formed by the wiring pattern 120 and / or the conductive via 130 in the substrate base 110 and the chip connection pad 122 may be referred to as a common line CML (in Figures 1 to 4 ), where the chip connection pad 122 may be referred to as a branch point BPT. The electrical path from the chip connection pad 122 to the first chip pad 214, including the chip connection pad 122, the first bonding wire 310, the first chip connection terminal pad 212, the first rewiring pattern 216, and the first chip pad 214, may be referred to as the first branch line BRL1. The electrical path from the chip connection pad 122 to the second chip pad 224, including the chip connection pad 122, the second bonding wire 320, the second chip connection terminal pad 222, the second rewiring pattern 226, and the second chip pad 224 may be referred to as the second branch line BRL2. The value of the length of the electrical path formed by the second branch line BRL2 may be greater than the value of the length of the electrical path formed by the first branch line BRL1. In the following, the length of the electrical path formed by the first branch line BRL1 and the second branch line BRL2 may be referred to as the extension length of the first branch line BRL1 and the second branch line BRL2, respectively.

[0052] Similar to the electrical path from the external connection pad 124 to which the first external connection terminal 502 is attached to the first chip pad 214 and the second chip pad 224, the electrical path from the external connection pad 124 to which the second external connection terminal 504 is attached to the first chip pad 214 and the second chip pad 224 may also include the package terminal PKT, the common line CML, the branch point BPT, and the first branch line BRL1 and the second branch line BRL2.

[0053] Therefore, the semiconductor memory package 1 can be connected from the first external connection terminal 502 and the second external connection terminal 504 to the first chip pad 214 of the first semiconductor memory chip 210 and the second chip pad 224 of the second semiconductor memory chip 220, and can be connected from the package terminal PKT to the branch point BPT through the common line CML as an electrical path. The branch point BPT and the first chip pad 214 and the second chip pad 224 can be connected to each other through the first branch line BRL1 and the second branch line BRL2, respectively, and the first branch line BRL1 and the second branch line BRL2 are independent electrical paths that branch from each other.

[0054] In some example embodiments, the open stub 126 may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126 may be connected to the external connection pad 124 to which the first external connection terminal 502 is attached, that is, the portion of the common line CML that serves as the package terminal PKT. The open stub 126 may be a portion of the wiring pattern 120 on the lower surface of the substrate base 110. One end of the open stub 126 may be connected to the external connection pad 124 to which the first external connection terminal 502 is attached, and the other end of the open stub 126 may be open without being connected to another electrical path.

[0055] The length extending from one end to the other end of the open stub 126 may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some example embodiments, the extension length of the open stub 126 may be substantially the same as the extension length of the second branch line BRL2.

[0056] In some example embodiments, the open stub 126 may not be connected to the common line CML connected to the second external connection terminal 504. That is, the open stub 126 may be connected to the common line CML connected to the first external connection terminal 502 for transmitting or receiving a relatively high-speed signal among the plurality of external connection terminals 500, and not connected to the common line CML connected to the second external connection terminal 504 for transmitting or receiving a relatively low-speed signal.

[0057] According to the prior art, a plurality of semiconductor memory chips included in a semiconductor memory package are connected to a storage interface of a channel through a plurality of branch lines constituting a plurality of branches without an open-circuited short-circuit line. In such a semiconductor memory package, when a semiconductor memory chip connected to a branch line having a relatively short extension length receives a signal, signal distortion may occur due to a signal reflected from an end of the branch line having a relatively long extension length.

[0058] However, the semiconductor memory package 1 according to the example embodiment includes an open stub 126 connected to a common line CML constituting a storage interface of one channel. Therefore, when the first semiconductor memory chip 210 connected to the first branch line BRL1 having a relatively short extension length receives a signal, the signal reflected by the one end of the open stub 126 can compensate for the signal distortion caused by the signal reflected by the end of the second branch line BRL2. Therefore, the signal characteristics of the semiconductor memory package operating at a high speed can be improved. Fig.12 13 to describe it in detail.

[0059] Figure 2 is a cross-sectional view of a semiconductor memory package 1a according to an example embodiment. Figure 2 In, with Figure 1 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0060] Reference Figure 2 , a semiconductor memory package 1 a includes a package base substrate 100 a and at least two semiconductor memory chips 200 .

[0061] The open stub 126a may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126a may be located between a plurality of layers formed by the substrate base 110. In more detail, the open stub 126a may be a portion of the wiring pattern 120 between a plurality of layers formed by the substrate base 110. One end of the open stub 126a may be connected to a portion of the central portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT, and the other end of the open stub 126a may be open without being connected to other electrical paths.

[0062] That is, when the package base substrate 100 is a multi-layer board, the layer where the open stub 126 a is arranged may be different from the layer where the plurality of chip connection pads 122 are arranged and from the layer where the plurality of external connection pads 124 are arranged.

[0063] The length extending from one end to the other end of the open stub 126a may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some example embodiments, the extension length of the open stub 126a may be substantially the same as the extension length of the second branch line BRL2.

[0064] Figure 3 is a cross-sectional view of a semiconductor memory package 1b according to an example embodiment. Figure 3 In, with Figure 1 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0065] Reference Figure 3 , the semiconductor memory package 1 b includes a package base substrate 100 b and at least two semiconductor memory chips 200 .

[0066] The common line CML may include a portion of the wiring pattern 120 extending along the lower surface of the substrate substrate 110. That is, the common line CML may have a portion extending from the external connection pad 124 along the lower surface of the substrate substrate 110.

[0067] The open stub 126b may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126b may be located between a plurality of layers formed by the substrate 110. In more detail, the open stub 126b may be a portion of the wiring pattern 120 between a plurality of layers formed by the substrate base 110. An auxiliary conductive via 130a that penetrates a portion of the substrate base 110 may be arranged on an external connection pad 124 to which the first external connection terminal 502 is attached. The open stub 126b may be electrically connected to the external connection pad 124 through the auxiliary conductive via 130a. The height of the auxiliary conductive via 130a may have a relatively small value compared to the value of the extended length of the open stub 126b. Therefore, the open stub 126b may function substantially as if the open stub 126b were connected to an external connection pad 124 to which the first external connection terminal 502 is attached.

[0068] The length extending from one end to the other end of the open stub 126b may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some example embodiments, the extension length of the open stub 126b may be substantially the same as the extension length of the second branch line BRL2.

[0069] Figure 4 is a cross-sectional view of a semiconductor memory package 1c according to an example embodiment. Figure 4 In, with Figure 1 and Figure 3 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0070] Reference Figure 4 , the semiconductor memory package 1 c includes a package base substrate 100 c and at least two semiconductor memory chips 200 .

[0071] The common line CML may include a portion 120a of the wiring pattern 120 extending along the lower surface of the substrate substrate 110. That is, the common line CML may have the portion 120a extending from the external connection pad 124 along the lower surface of the substrate substrate 110.

[0072] The open stub 126c may be connected to a portion 120a of the wiring pattern 120 that extends from the external connection pad 124 along the lower surface of the substrate base 110 and forms a portion of the common line CML. The open stub 126c may extend along the lower surface of the substrate base 110. In more detail, the open stub 126c may be a portion of the wiring pattern 120 on the lower surface of the substrate base 110.

[0073] The value of the extension length of the portion 120a of the wiring pattern 120 extending along the lower surface of the substrate base 110 in the common line CML may be smaller than the value of the extension length of the remaining portion of the common line CML. That is, the value of the extension length of the portion of the common line CML from the package terminal PKT to the position where the open stub 126c is connected to the common line CML may be smaller than the value of the extension length of the portion of the common line CML from the branch point BPT to the position where the open stub 126c is connected to the common line CML. That is, the open stub 126c may be connected to the portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT.

[0074] The length extending from one end to the other end of the open stub 126c may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some embodiments, the extension length of the open stub 126c may be substantially the same as the extension length of the second branch line BRL2.

[0075] Figure 5 is a cross-sectional view of a semiconductor memory package 2 according to an example embodiment. Figure 5 In, with Figure 1 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0076] Reference Figure 5 , the semiconductor memory package 2 includes a package base substrate 102 and at least two semiconductor memory chips 200. In some example embodiments, the package base substrate 102 may be a PCB.

[0077] At least two semiconductor memory chips 200 may be mounted on the package base substrate 102. In some example embodiments, the at least two semiconductor memory chips 200 may be spaced apart from each other in a horizontal direction on the package base substrate 102 and attached to each other. The at least two semiconductor memory chips 200 may include a first semiconductor memory chip 210 and a second semiconductor memory chip 220. In some example embodiments, the first semiconductor memory chip 210 may be mounted on the upper surface of the package base substrate 102 with a first die adhesive film 218 between it and the upper surface of the package base substrate 102, and the second semiconductor memory chip 220 may be spaced apart from the first semiconductor memory chip 210 and may be mounted on the package base substrate 102 with a second die adhesive film 228 between it and the package base substrate 102.

[0078] Figure 5 It is shown that a plurality of first chip pads 214 and a plurality of second chip pads 224 are arranged at the edge portion of the active surface of the corresponding one of the first semiconductor memory chip 210 and the second semiconductor memory chip 220 in an edge pad manner, but the concept of the present invention is not limited thereto. For example, the plurality of first chip pads 214 and the plurality of second chip pads 224 can be arranged at the center portion of the active surface of the corresponding one of the first semiconductor memory chip 210 and the second semiconductor memory chip 220 in a center pad manner, respectively. Although not shown, the first semiconductor memory chip 210 may further include a first chip connection terminal pad 212 and a first rewiring pattern 216, and the second semiconductor memory chip 220 may further include a second chip connection terminal pad 222 and a second rewiring pattern 226, as shown in FIG. Figure 1 shown.

[0079] The first external connection terminal 502 may be electrically connected to the chip connection pad 122 through the external connection pad 124, the wiring pattern 120 in the substrate base 110, and / or the conductive via 130. The first bonding wire 310 and the second bonding wire 320 may be connected to the corresponding chip connection pad 122. The first bonding wire 310 and the second bonding wire 320 may be connected to the first chip pad 214 of the first semiconductor memory chip 210 and the second chip pad 224 of the second semiconductor memory chip 220, respectively.

[0080] The chip connection pads 122 connected to the first bonding wire 310 and the second bonding wire 320, respectively, may form an electrical path through the wiring pattern 120 and the conductive via 130 on the upper surface of the substrate base 110 and / or in the substrate base 110. Thereafter, the chip connection pads 122 may be connected to each other at a branch point BPT, which is a part of the wiring pattern 120 or a part of the conductive via 130 in the substrate base 110. Therefore, the electrical path between the external connection pad 124 and the branch point BPT is a common line CML, and the electrical paths from the branch point BPT to the first chip pad 214 and the second chip pad 224 may be a first branch line BRL1 and a second branch line BRL2, respectively.

[0081] That is, the branch point BPT of the semiconductor memory package 2 may be a portion of the wiring pattern 120 or a portion of the conductive via 130 in the substrate base 110, and Figure 1 The branch point BPT of the semiconductor memory package 1 shown is the chip connection pad 122 .

[0082] Therefore, the first branch line BRL1 may include the wiring pattern 120 and / or the conductive via 130 in the substrate base 110, the chip connection pad 122, and the first bonding wire 310. In some example embodiments, the first branch line BRL1 may also include Figure 1 The first chip connection terminal pad 212 and the first rewiring pattern 216 are shown. Therefore, the second branch line BRL2 may include the wiring pattern 120 and / or the conductive via 130 in the substrate base 110, the chip connection pad 122 and the second bonding wire 320. In some example embodiments, the second branch line BRL2 may also include Figure 1 The second chip connection terminal pads 222 and the second rewiring pattern 226 are shown. The value of the extension length of the second branch line BRL2 may be greater than the value of the extension length of the first branch line BRL1.

[0083] The open stub 126 may be connected to the external connection pad 124 to which the first external connection terminal 502 is attached, that is, a portion of the common line CML serving as the package terminal PKT. The open stub 126 may be a portion of the wiring pattern 120 on the lower surface of the substrate base 110. One end of the open stub 126 may be connected to the external connection pad 124 to which the first external connection terminal 502 is attached, and the other end of the open stub 126 may be open without being connected to another electrical path.

[0084] The length extending from one end to the other end of the open stub 126 may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some example embodiments, the extension length of the open stub 126 may be substantially the same as the extension length of the second branch line BRL2.

[0085] Although for the sake of convenience, Figure 5 Omitted Figure 1 , but the semiconductor memory package 2 may include the second external connection terminal 504. In addition, the open stub 126 may not be connected to the common line CML connected to the second external connection terminal 504.

[0086] Figure 6 is a cross-sectional view of a semiconductor memory package 2a according to an example embodiment. Figure 6 In, with Figure 2 and Figure 5 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0087] Reference Figure 6 , the semiconductor memory package 2 a includes a package base substrate 102 a and at least two semiconductor memory chips 200 .

[0088] The open stub 126a may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126a may be located between a plurality of layers formed by the substrate 110. In more detail, the open stub 126a may be a portion of the wiring pattern 120 between a plurality of layers formed by the substrate substrate 110. One end of the open stub 126a may be connected to a portion of the central portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT, and the other end of the open stub 126a may be open without being connected to other electrical paths.

[0089] That is, when the package base substrate 100 is a multi-layer board, the layer where the open stub 126 a is arranged may be different from the layer where the plurality of chip connection pads 122 are located and from the layer where the plurality of external connection pads 124 are arranged.

[0090] The length extending from one end of the open stub 126a to the other end may be greater than half of the extension length of the second branch line BRL2, and the value of the length extending from one end of the open stub 126a to the other end is greater than the value of the extension length of the first branch line BRL1 and less than twice the extension length of the second branch line BRL2. In some example embodiments, the value of the extension length of the open stub 126a may be substantially the same as the value of the extension length of the second branch line BRL2.

[0091] Figure 7 is a cross-sectional view of a semiconductor memory package 2b according to an example embodiment. Figure 7 In, with Figure 3 and Figure 5 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0092] Reference Figure 7 , the semiconductor memory package 2 b includes a package base substrate 102 b and at least two semiconductor memory chips 200 .

[0093] The common line CML may include a portion of the wiring pattern 120 extending along the lower surface of the substrate substrate 110. That is, the common line CML may have a portion extending from the external connection pad 124 along the lower surface of the substrate substrate 110.

[0094] The open stub 126b may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126b may be between a plurality of layers formed by the substrate 110. In more detail, the open stub 126b may be a portion of the wiring pattern 120 between a plurality of layers formed by the substrate base 110. An auxiliary conductive via 130a that penetrates a portion of the substrate base 110 may be arranged on an external connection pad 124 to which the first external connection terminal 502 is attached. The open stub 126b may be electrically connected to the external connection pad 124 through the auxiliary conductive via 130a. The height of the auxiliary conductive via 130a may have a relatively small value compared to the value of the extended length of the open stub 126b. Therefore, the open stub 126b may function substantially like the open stub 126b being connected to the external connection pad 124 to which the first external connection terminal 502 is attached.

[0095] The length extending from one end to the other end of the open stub 126b may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some example embodiments, the extension length of the open stub 126b may be substantially the same as the extension length of the second branch line BRL2.

[0096] Figure 8 is a cross-sectional view of a semiconductor memory package 2c according to an example embodiment. Figure 8 In, with Figure 4 and Figure 5 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0097] Reference Figure 8 , the semiconductor memory package 2 c includes a package base substrate 102 c and at least two semiconductor memory chips 200 .

[0098] The common line CML may include a portion 120a of the wiring pattern 120 extending along the lower surface of the substrate substrate 110. That is, the common line CML may have the portion 120a extending from the external connection pad 124 along the lower surface of the substrate substrate 110.

[0099] The open stub 126c may be connected to a portion 120a of the wiring pattern 120 that extends from the external connection pad 124 along the lower surface of the substrate base 110 and forms a portion of the common line CML. The open stub 126c may extend along the lower surface of the substrate base 110. In more detail, the open stub 126c may be a portion of the wiring pattern 120 on the lower surface of the substrate base 110.

[0100] The value of the extension length of the portion 120a of the wiring pattern 120 extending along the lower surface of the substrate base 110 in the common line CML may be smaller than the value of the extension length of the remaining portion of the common line CML. That is, the value of the extension length of the portion of the common line CML from the package terminal PKT to the position where the open stub 126c is connected to the common line CML may be smaller than the value of the extension length of the portion of the common line CML from the branch point BPT to the position where the open stub 126c is connected to the common line CML. That is, the open stub 126c may be connected to the portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT.

[0101] The length extending from one end to the other end of the open stub 126c may be greater than half of the extension length of the second branch line BRL2 and less than twice the extension length of the second branch line BRL2, the extension length of which is greater than the extension length of the first branch line BRL1. In some embodiments, the extension length of the open stub 126c may be substantially the same as the extension length of the second branch line BRL2.

[0102] Fig. 9 is a cross-sectional view of a semiconductor memory package 3 according to an example embodiment. Fig. 9 In, with Figure 1 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0103] Reference Fig. 9 , the semiconductor memory package 3 includes a package base substrate 100 and a plurality of semiconductor memory chips 200a. The plurality of semiconductor memory chips 200a may be mounted on the package base substrate 100. In some example embodiments, the plurality of semiconductor memory chips 200a may be vertically stacked on the package base substrate 100, but is not limited thereto.

[0104] The plurality of semiconductor memory chips 200a may include a first semiconductor memory chip 210, a second semiconductor memory chip 220, a third semiconductor memory chip 230, and a fourth semiconductor memory chip 240. In some example embodiments, the first semiconductor memory chip 210 may be mounted on the upper surface of the package base substrate 100 via a first die adhesive film 218 between the first semiconductor memory chip 210 and the upper surface of the package base substrate 100, the second semiconductor memory chip 220 may be mounted on the first semiconductor memory chip 210 via a second die adhesive film 228 between the first semiconductor memory chip 210 and the first semiconductor memory chip 210, the third semiconductor memory chip 230 may be mounted on the second semiconductor memory chip 220 via a third die adhesive film 238 between the second semiconductor memory chip 220, and the fourth semiconductor memory chip 240 may be mounted on the third semiconductor memory chip 230 via a fourth die adhesive film 248 between the third semiconductor memory chip 230 and the third semiconductor memory chip 230. Since the configuration of each of the plurality of semiconductor memory chips 200a is similar to that of the semiconductor memory chip 200a, the semiconductor memory chip 200a may be mounted on the upper surface of the package base substrate 100, the second semiconductor memory chip 220 may be mounted on the first semiconductor memory chip 210 via a second die adhesive film 228 between the first semiconductor memory chip 210 and the first semiconductor memory chip 210, the third semiconductor memory chip 230 may be mounted on the second semiconductor memory chip 220 via a third die adhesive film 238 between the second semiconductor memory chip 220, and the fourth semiconductor memory chip 240 may be mounted on the third semiconductor memory chip 230 via a fourth die adhesive film 248 between the third semiconductor memory chip 230 and the third semiconductor memory chip 230. Figure 1 The configurations of the first semiconductor memory chip 210 and the second semiconductor memory chip 220 shown in FIG. 2 are similar, and thus a detailed description thereof will not be given here.

[0105] The plurality of semiconductor memory chips 200 a including the first to fourth semiconductor memory chips 210 , 220 , 230 , and 240 may be electrically connected to the chip connection pads 122 through the plurality of bonding wires 300 a including the plurality of bonding wires 310 , 320 , 330 , and 340 .

[0106] The respective electrical paths from the chip connection pad 122 to the chip pads 214, 224, 234, 244 of the first to fourth semiconductor memory chips 210, 220, 230, and 240 may be referred to as first to fourth branch lines BRL1, BRL2, BRL3, and BRL4, respectively. The value of the extension length of the fourth branch line BRL4 may be greater than the value of the extension length of each of the first to third branch lines BRL1, BRL2, and BRL3.

[0107] The open stub 126 may be connected to a portion of the common line CML connected to the first external connection terminal 502 that is closer to the package terminal PKT than the branch point BPT. For example, the open stub 126 may be connected to an external connection pad 124 to which the first external connection terminal 502 is attached, that is, a portion of the common line CML that serves as the package terminal PKT. The open stub 126 may be a portion of the wiring pattern 120 on the lower surface of the substrate base 110. One end of the open stub 126 may be connected to the external connection pad 124 to which the first external connection terminal 502 is attached, and the other end of the open stub 126 may be open without being connected to another electrical path.

[0108] The length extending from one end to the other end of the open stub 126 may be greater than half of the extension length of the fourth branch line BRL4 and less than twice the extension length of the fourth branch line BRL4. In some example embodiments, the extension length of the open stub 126 may have substantially the same value as the extension length of the fourth branch line BRL4.

[0109] according to Fig. 9 The semiconductor memory package 3 of the illustrated example embodiment includes an open stub 126 connected to a common line CML constituting a memory interface of one channel. Therefore, when any one of the first to third semiconductor memory chips 210, 220, and 230 respectively connected to the first to third branch lines BRL1, BRL2, and BRL3 having relatively short extension lengths receives a signal, the signal reflected by the end of the open stub 126 can compensate for the signal distortion caused by the signal reflected by the end of the fourth branch line BRL4. Therefore, the signal characteristics of the semiconductor memory package operating at a high speed can be improved.

[0110] Fig.10 is a cross-sectional view of a semiconductor memory package 4 according to an example embodiment. Fig.10 In, with Figure 1 The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0111] Reference Fig.10, the semiconductor memory package 4 includes a package base substrate 100 d and at least two semiconductor memory chips 200 .

[0112] The semiconductor memory package 4 includes a first common line CML1 connecting the first package terminal PKT1 to the first branch point BPT1 and a second common line CML2 connecting the second package terminal PKT2 to the second branch point BPT2. Figure 1 The first branch line BRL1 and the second branch line BRL2 are similar, and at least two branches connected to the second branch point BPT2 are respectively connected to Figure 1 The first branch line BRL1 and the second branch line BRL2 are shown to be similar, and therefore, a detailed description thereof will not be given here.

[0113] The bonding wires 302 include a first bonding wire 312 and a second bonding wire 322 .

[0114] The first bonding wires 312 respectively connecting the first branch point BPT1 and the second branch point BPT2 to the first semiconductor storage chip 210 may be respectively connected to the first chip connection terminal pads 212 of the first semiconductor storage chip 210. The second bonding wires 322 respectively connecting the first branch point BPT1 and the second branch point BPT2 to the second semiconductor storage chip 220 may be respectively connected to the second chip connection terminal pads 222 of the second semiconductor storage chip 220.

[0115] When the package base substrate 100 is a multi-layer substrate, the first open stub 126-1 connected to the first common line CML1 and the second open stub 126-2 connected to the second common line CML2 may be arranged on different layers. Figure 1 The open stub 126 shown, the first open stub 126-1 may be a part of the wiring pattern 120 arranged on the lower surface of the substrate 110, similar to Figure 2 The open stub 126a shown, the second open stub 126-2 may be a portion of the wiring pattern 120 arranged between a plurality of layers included in the substrate 110. The extension length of the first open stub 126-1 may be similar to that described above with respect to Figure 1 The extension length of the open stub 126 described above, the extension length of the second open stub 126-2 may be similar to the extension length of the second open stub 126-2 described above. Figure 2 The extended length of the open stub 126a is depicted.

[0116] Fig.11 is a cross-sectional view of a semiconductor memory package 5 according to an example embodiment. Fig.11 In, with Figure 1The same reference numerals in the drawings denote the same elements, and thus a detailed description thereof will not be given here.

[0117] Reference Fig.11 , the semiconductor memory package 5 includes a package base substrate 100 and at least two semiconductor memory chips 200. A plurality of external connection terminals 500a may be respectively attached to a plurality of external connection pads 124 of the package base substrate 100. The plurality of external connection terminals 500a may include a first external connection terminal 502a for transmitting or receiving a relatively high-speed signal and a second external connection terminal 504a for transmitting or receiving a relatively low-speed signal. The plurality of external connection terminals 500a may be, for example, pins.

[0118] Fig.12 is a schematic diagram of a channel of a semiconductor memory package 10 according to an example embodiment.

[0119] Reference Fig.12 , the semiconductor memory package 10 may be mounted on the system board B / D. The semiconductor memory package 10 may receive a signal from a transmitter STM of an external system through the system board B / D.

[0120] The semiconductor memory package 10 may be, for example, Figures 1 to 11 One of the semiconductor memory packages 1, 1a, 1b, 1c, 2, 2a, 2b, 2c, 3, 4 and 5 is shown.

[0121] The semiconductor memory package 10 can receive a signal from a transmitter STM of an external system through a package terminal PKT. The package terminal PKT can be electrically connected to a branch point BPT through a common line CML. An open stub OS can be connected between the package terminal PKT and the branch point BPT. One end of the open stub OS can be connected between the package terminal PKT and the branch point BPT, while the other end of the open stub OS can be open and not connected to other electrical paths. The open stub OS can be one of the open stubs 126, 126a, 126b and 126c, the first open stub 126-1 and the second open stub 126-2.

[0122] The branch point BPT and the receiver RCV1 of the first semiconductor storage chip may be connected through a first branch line BRL1. The branch point BPT and the receiver RCV2 of the second semiconductor storage chip may be connected through a second branch line BRL2. That is, the first branch line BRL1 and the second branch line BRL2 may branch from the branch point BPT and be connected to the receiver RCV1 of the first semiconductor storage chip and the receiver RCV2 of the second semiconductor storage chip.

[0123] The receiver RCV1 of the first semiconductor memory chip may have Figures 1 to 11The first chip connection terminal pad 212 is connected to the first semiconductor memory chip 210, and the receiver RCV2 of the second semiconductor memory chip may have the same Figures 1 to 11 The second chip connection terminal pads 222 are connected to the configuration inside the second semiconductor memory chip 220. Otherwise, the receiver RCV1 of the first semiconductor memory chip and the receiver RCV2 of the second semiconductor memory chip may have the configuration inside one of the first to fourth semiconductor memory chips 210, 220, 230 and 240.

[0124] In some example embodiments, the first extension length Lc1 may be smaller than the second extension length Lc2, the first extension length Lc1 being the distance between the location where the open stub OS is connected to the common line CML and the package terminal PKT, and the second extension length Lc2 being the distance between the location where the open stub OS is connected to the common line CML and the branch point BPT. In some example embodiments, the first extension length Lc1 may be zero.

[0125] The first branch extension length Lb1, which is the extension length of the first branch line BRL1, may be less than the second branch extension length Lb2, which is the extension length of the second branch line BRL2. The open stub extension length Los, which extends from one end of the open stub OS to the other end of the open stub OS, may be greater than half of the second branch extension length Lb2, and may be less than twice the second branch extension length Lb2. In some example embodiments, the value of the open stub extension length Los may be substantially the same as the value of the second branch extension length Lb2.

[0126] The sum of the first extension length Lc1 and the second extension length Lc2 may be the physical length of the common line CML or the impedance Z0 of the common line CML. Similarly, the first branch extension length Lb1 and the second branch extension length Lb2 may be the physical length of the first branch line BRL1 and the physical length of the second branch line BRL2, respectively, or the impedance Z1a of the first branch line BRL1 and the impedance Z1b of the second branch line BRL2, respectively. In addition, the open stub extension length Los may be the physical length of the open stub line OS or the impedance Z2 of the open stub line OS.

[0127] In the related art package without an open stub, when a signal S1 transmitted from a transmitter STM of an external system is received by a receiver RCV1 of a first semiconductor memory chip through a first branch line BRL1, a signal S2 reflected by an end of a second branch line BRL2 may cause signal distortion.

[0128] However, in the semiconductor memory package 1 according to the example embodiment, the signal reflected by the end of the open stub line OS can compensate for the signal distortion caused by the signal S2 reflected by the end of the second branch line BRL2. Therefore, the signal characteristics of the semiconductor memory package 10 performing high-speed operation can be improved.

[0129] Although Fig.12 A case where the receiver RCV1 of the first semiconductor memory chip and the receiver RCV2 of the second semiconductor memory chip receive signals from the transmitter STM of the external system is shown, but even when the receiver of the external system receives signals from the transmitter of the first semiconductor memory chip and the transmitter of the second semiconductor memory chip, the signal characteristics of the semiconductor memory package 10 can be improved by the open stub OS. In some example embodiments, the receiver RCV1 of the first semiconductor memory chip and the receiver RCV2 of the second semiconductor memory chip can be used as the transmitter of the first semiconductor memory chip and the transmitter of the second semiconductor memory chip, respectively, and the transmitter STM of the external system can be used as the receiver of the external system. Therefore, bidirectional communication is possible.

[0130] FIG. 13A to FIG. 13E is a graph of a waveform reaching a receiver in a channel of a semiconductor memory package according to example embodiments.

[0131] refer to Fig.12 and FIG. 13A to FIG. 13E , Fig.13A shows a first signal S1 transmitted from a transmitter STM of an external system and received by a receiver RCV1 of a first semiconductor memory chip, Fig. 13B The second signal S2 reflected by the end of the second branch line BRL2 and received by the receiver RCV1 of the first semiconductor memory chip is shown. Fig. 13C A third signal S3 reflected by the end of the open stub OS and received by the receiver RCV1 of the first semiconductor storage chip, and a fourth signal S4 reflected by the end of the open stub OS and then reflected back by the end of the second branch line BRL2 and received by the receiver RCV1 of the first semiconductor storage chip are shown.

[0132] "td" represents the signal transmission time from the transmitter STM of the external system to the receiver RCV1 of the first semiconductor memory chip, and "tr" represents the rise time of the signal. 1 " denotes a first time, which is the time taken for a signal emitted from the common line CML to the open stub line OS to reach the common line CML again after being reflected by the end of the open stub line OS, and "t 2" represents a second time, which is the time taken for the signal transmitted from the branch point BPT to the second branch line BRL2 to reach the branch point BPT again after being reflected by the end of the second branch line BRL2.

[0133] When the open stub line OS does not exist like the related art, the receiver RCV1 of the first semiconductor memory chip receives the first signal S1 and the second signal S2 together. Therefore, signal distortion may occur due to signal bending of the second signal S2.

[0134] Fig.13D and Fig.13E Compensation signals SC1 and SC2 in which the first to fourth signals S1 , S2 , S3 , and S4 are superimposed are shown. Fig.13D It shows that when the signal rise time tr is greater than the second time t 2 The compensation signal SC1 is Fig.13E It shows that when the signal rise time tr is less than the second time t 2 The compensation signal SC1 at this time.

[0135] Reference Fig.13D and Fig.13E In the compensation signals SC1 and SC2, the third signal S3 and the fourth signal S4 compensate for signal distortion that may occur due to signal bending of the second signal S2, so that the signal bending may be reduced or may not occur.

[0136] Figures 14 to 18 is a layout of wiring patterns of a package base substrate of a semiconductor memory package according to example embodiments.

[0137] Fig.14 A bottom layer LB on a lower surface of a substrate substrate 110 of the package substrate 100 and a top layer LT on an upper surface of the substrate substrate 110 are shown.

[0138] When space for arranging the open stub OS is gained in the portion of the bottom layer LB adjacent to the package terminal PKT, the open stub OS may be arranged on the bottom layer LB where the package terminal PKT is arranged. The open stub OS may extend from the package terminal PKT along the bottom layer LB. The open stub OS may be Figure 1 or Figure 5 The open stub 126 is shown. The branch point BPT may be arranged on the top layer LT. The package terminal PKT may be connected to the branch point BPT through the common line CML.

[0139] Fig.15 A bottom layer LB on a lower surface of the substrate substrate 110 of the package substrate 100 a and a middle layer LM between adjacent layers among a plurality of layers included in the substrate substrate 110 are shown.

[0140] When space for arranging the open stub OS is not secured in a portion of the bottom layer LB adjacent to the package terminal PKT due to other wiring patterns, the open stub OS may be arranged on the middle layer LM instead of the bottom layer LB where the package terminal PKT is arranged.

[0141] The open stub line OS may extend from the common line CML along the middle layer LM. The open stub line OS may be Figure 2 or Figure 6 An open circuit stub 126a is shown.

[0142] Fig.16 A bottom layer LB on the lower surface of the substrate substrate 110 of the package substrate 100 b and a middle layer LM between adjacent layers among a plurality of layers included in the substrate substrate 110 are shown.

[0143] When there is no space for arranging the open stub OS in the portion of the bottom layer LB adjacent to the package terminal PKT because the portion 120a of the wiring pattern 120 (which is a portion of the common line CML) is arranged on the portion of the bottom layer LB adjacent to the package terminal PKT, the open stub OS may be arranged on the middle layer LM instead of the bottom layer LB where the package terminal PKT is arranged. The open stub OS may be electrically connected to the package terminal PKT through the auxiliary conductive via 130a arranged on the package terminal PKT, and penetrate a portion of the substrate base 110, and may extend along the middle layer LM. The open stub OS may be Figure 3 or Figure 7 An open circuit stub 126b is shown.

[0144] Fig.17 A bottom layer LB on the lower surface of the substrate substrate 110 of the package substrate 100 c and a middle layer LM between adjacent layers among a plurality of layers included in the substrate substrate 110 are shown.

[0145] When there is no space for arranging the open short line OS in the portion of the underlying layer LB adjacent to the package terminal PKT because a portion 120a of the wiring pattern 120 (a portion of the common line CML) is arranged on the portion of the underlying layer LB adjacent to the package terminal PKT, the open short line OS can be arranged on the underlying layer LB to extend from the portion 120a of the wiring pattern 120 extending from the package terminal PKT. Fig.17 The diagram shows that one end of the portion 120a of the wiring pattern 120 is connected to the package terminal PKT, and the open stub OS is connected to the other end of the portion 120a of the wiring pattern 120 opposite to the one end, but the inventive concept is not limited thereto. The open stub OS may be connected to the middle portion of the wiring pattern 120. The open stub OS may be Figure 4 or Figure 8 An open circuit stub 126c is shown.

[0146] Fig.18 A bottom layer LB on a lower surface of the substrate substrate 110 of the package substrate 100 a and a middle layer LM between adjacent layers among a plurality of layers included in the substrate substrate 110 are shown.

[0147] When space for arranging the open stub OS is not secured in a portion of the bottom layer LB adjacent to the package terminal PKT due to other wiring patterns, the open stub OS may be arranged on the middle layer LM instead of the bottom layer LB where the package terminal PKT is arranged.

[0148] The middle layer LM may be a layer on which the ground plane layer 128 is arranged. The open stub OS may extend from the common line CML away from the ground plane layer 128 along a space between the ground plane layer 128 and the middle layer LM. The open stub OS may be Figure 2 or Figure 6 The open stub 126a is shown. The ground plane layer 128 may occupy most of the area of ​​the middle layer LM where the ground plane layer 128 is arranged. Therefore, even when a portion of the ground plane layer 128 is removed to form a slit (the slit is a space where the open stub OS is arranged), the function of the ground plane layer 128 is not affected.

[0149] 19A to 19D is a signal eye diagram for comparing a semiconductor memory package according to example embodiments with a comparative example.

[0150] Reference 19A to 19D , FIG. 19A to FIG. 19B 3 are respectively a signal eye diagram of a semiconductor memory package according to a comparative example and a signal eye diagram of a semiconductor memory package according to an example embodiment when a transmission rate is 4568 Mbps, FIG. 19C to FIG. 19D 1 and 2 are signal eye diagrams of a semiconductor memory package according to a comparative example and a semiconductor memory package according to example embodiments, respectively, when a transmission rate is 5600 Mbps.

[0151] Unlike the semiconductor memory package according to the example embodiment, the semiconductor memory package according to the comparative example does not have ( Figures 1 to 11 ) open circuited stubs 126, 126a, 126b and 126c.

[0152] and Fig.19A and Fig.19C Compared with the signal eye diagram of the semiconductor memory package according to the comparative example, Fig.19B and Fig.19DThe signal eye diagram of the semiconductor memory package according to example embodiments shown in shows a greater eye opening of the eye pattern. Therefore, it can be seen that the quality of the signal received by the semiconductor memory package according to example embodiments is excellent.

[0153] In addition, it can be seen that in the semiconductor memory package according to the example embodiment, when the transmission rate is 4266 Mbps Fig.19B Compared with the case of 5600Mbps, Fig.19D The degree of reduction in the eye opening size in the case of is less than that in the semiconductor memory package according to the comparative example and when the transmission rate is 4266 Mbps. Fig.19A Compared with the case of 5600Mbps, Fig.19C Therefore, it can be seen that the semiconductor memory package according to the example embodiment has excellent high-speed operation characteristics.

[0154] A semiconductor memory package according to example embodiments includes a plurality of semiconductor memory chips connected to each other through a plurality of branch lines constituting a plurality of branches connected to a common line in a single-channel memory interface, and further includes an open stub connected to the common line.

[0155] Therefore, the semiconductor memory package according to example embodiments may improve signal characteristics and may operate at high speed because a signal reflected by the open stub may compensate for signal distortion caused by a signal reflected by a branch line other than a branch line receiving a signal.

[0156] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory package, comprising: a package base substrate, the package base substrate comprising a base substrate and a plurality of chip connection pads and a plurality of external connection pads respectively arranged on an upper surface and a lower surface of the base substrate; as well as at least two semiconductor memory chips, the at least two semiconductor memory chips being mounted on the package base substrate and each semiconductor memory chip having a plurality of chip bonding pads electrically connected to the plurality of chip connection pads, wherein a first electrical path extends from one of the plurality of external connection pads to a first chip pad of one of the at least two semiconductor storage chips, and a second electrical path extends from the one of the plurality of external connection pads to a second chip pad of another of the at least two semiconductor storage chips, The first electrical path and the second electrical path include a common line extending from a branch point of the first electrical path and the second electrical path to the one of the plurality of external connection pads, A first branch of the first electrical path extends from the branch point to the first chip pad, a second branch of the second electrical path extends from the branch point to the second chip pad, and The package base substrate includes an open short stub extending from the common line, the open short stub having one end connected to the common line and the other end which is open and not connected to another electrical path, and the short stub extension length of the open short stub is greater than half of the branch extension length of the longer branch of the first branch line and the second branch line and less than twice the branch extension length.

2. The semiconductor memory package according to claim 1, wherein: The one end of the open stub is connected to a portion of the common line that is closer to the one of the plurality of external connection pads than to the branch point.

3. The semiconductor memory package according to claim 1, wherein: The one end of the open stub is connected to the one external connection pad among the plurality of external connection pads.

4. The semiconductor memory package according to claim 1, wherein: The open stub extends along a lower surface of the substrate base.

5. The semiconductor memory package according to claim 1, wherein: The substrate base comprises a plurality of layers, and The open stub is disposed on a middle layer of the plurality of layers.

6. The semiconductor memory package according to claim 5, wherein: The plurality of layers includes a ground plane layer.

7. The semiconductor memory package according to claim 6, wherein: The open circuit stub is disposed on the ground plane layer. 8 . The semiconductor memory package according to claim 6 , further comprising an auxiliary conductive via disposed on the one of the plurality of external connection pads and connected to the open stub through a portion of the substrate base.

9. The semiconductor memory package according to claim 1, wherein: The branch point is one chip connection pad among the plurality of chip connection pads.

10. The semiconductor memory package according to claim 9, wherein: The first leg and the second leg each include a bonding wire.

11. The semiconductor memory package according to claim 1, wherein: The branch point is a portion of a wiring pattern or a conductive via in the substrate base.

12. The semiconductor memory package according to claim 11, wherein: The first branch line and the second branch line each include a portion of the wiring pattern or the conductive via in the substrate base connected to one of the multiple chip connection pads, and a bonding wire connecting the one of the multiple chip connection pads to one of the multiple chip connection pads. 13 . The semiconductor memory package according to claim 1 , further comprising a plurality of solder balls or a plurality of pins attached to the plurality of external connection pads.

14. The semiconductor memory package according to claim 1, wherein: The one external connection pad among the plurality of external connection pads is used for data input / output or a clock signal.

15. A semiconductor memory package, comprising: A package base substrate, the package base substrate comprising: a base substrate, a plurality of chip connection pads arranged on an upper surface of the base substrate, a plurality of external connection pads arranged on a lower surface of the base substrate and electrically connected to the plurality of chip connection pads, and an open stub, the open stub comprising one end electrically connected to one of the plurality of external connection pads and another end extending from the one end and being open and not connected to another electrical path; At least two semiconductor memory chips are mounted on the package base substrate, each semiconductor memory chip has a chip connection terminal pad, a chip pad and a rewiring pattern connecting the chip connection terminal pad to the chip pad, and each semiconductor memory chip has at least one bonding wire connecting the chip connection terminal pad to one or more chip connection pads among the multiple chip connection pads.

16. The semiconductor memory package according to claim 15, wherein: The one end of the open stub extends along a lower surface of the substrate base.

17. The semiconductor memory package according to claim 15, wherein: The substrate base includes a plurality of layers, a ground plane layer is disposed on a middle layer of the plurality of layers, and The open circuit stub is disposed on the intermediate layer in a space between portions of the ground plane layer.

18. The semiconductor memory package according to claim 15, wherein: The one end of the open stub is connected to a portion of an electrical path formed between one of the plurality of chip connection pads and a corresponding one of the plurality of external connection pads.

19. A semiconductor memory package, comprising: A package base substrate, the package base substrate comprising: a base substrate including a plurality of layers, a plurality of chip connection pads arranged on an upper surface of the base substrate and a plurality of external connection pads arranged on a lower surface of the base substrate and electrically connected to the plurality of chip connection pads, a ground plane layer formed between the plurality of layers included in the base substrate, and an open stub extending between the plurality of layers away from the ground plane layer, the open stub comprising one end electrically connected to one of the plurality of external connection pads and another end extending from the one end and being open and not connected to another electrical path; a first semiconductor memory chip attached to the package base substrate and a second semiconductor memory chip stacked on the first semiconductor memory chip, the first semiconductor memory chip having a first chip connection terminal pad, a first chip pad, and a first rewiring pattern connecting the first chip connection terminal pad to the first chip pad, the second semiconductor memory chip having a second chip connection terminal pad, a second chip pad, and a second rewiring pattern connecting the second chip connection terminal pad to the second chip pad; and A first bonding wire connects the first chip connection terminal pad to one or more of the plurality of chip connection pads, and a second bonding wire connects the second chip connection terminal pad to one or more of the plurality of chip connection pads.

20. The semiconductor memory package according to claim 19, wherein: The ground plane layer is located at a level closer to the lower surface than the upper surface of the substrate base, and The stub extension length of the open stub is greater than half of a sum of a bonding wire extension length of the second bonding wire and a rewiring extension length of a second rewiring pattern of the second semiconductor memory chip and is less than twice the sum.

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