Read margin control circuit, memory controller and electronic device including the same

Abstract

A read margin control circuit is provided. The read margin control circuit includes: a delay circuit that delays a data input / output signal and generates delayed signals having different phases from each other; a sampler that samples the delayed signal based on a data strobe signal to generate a sampled value; and a determiner configured to determine a data valid window of the data input / output signal based on the sampled value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0003172 filed on January 10, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Apparatus, devices, and articles consistent with the present disclosure relate to a read margin control circuit, a memory controller including the read margin control circuit, and an electronic device, and more particularly, to a read margin control circuit that determines a data valid window, a memory controller including the read margin control circuit, and an electronic device. Background Art

[0004] The memory device may process commands sent from the memory controller based on a clock. The memory device may output a data input / output signal and a data strobe signal in response to a read command from the memory controller. After issuing a read command, the memory controller may sample the data input / output signal based on the data strobe signal.

[0005] The sampling point can be placed in the center of the data valid window of the data input / output signal through training between the memory controller and the memory device. However, if the operating conditions such as voltage and temperature change, the data input / output signal or the data strobe signal output from the memory device may be shifted, and therefore, the sampling point may not be placed in the center of the data valid window. When adjusting the sampling point, the memory controller cannot access the memory device. Therefore, it is necessary to shorten the time taken to adjust the sampling point. Summary of the invention

[0006] One aspect is to provide a read margin control circuit for determining a data valid window, a memory controller including the read margin control circuit, and an electronic device.

[0007] According to an aspect of an exemplary embodiment, a read margin control circuit may include: a delay circuit configured to delay a data input / output signal and generate a plurality of delayed signals having different phases from each other; a sampler configured to sample the plurality of delayed signals based on a data selection signal to generate a plurality of sampling values; and a determiner configured to determine a data valid window of the data input / output signal based on the plurality of sampling values.

[0008] According to another aspect of the exemplary embodiment, a memory controller may include: a delay circuit configured to delay a data input / output signal sent from a storage device to generate a first delayed signal, a plurality of second delayed signals whose delays are less than the first delayed signal, and a plurality of third delayed signals whose delays are more than the first delayed signal; a sampler configured to sample the first delayed signal, the plurality of second delayed signals, and the plurality of third delayed signals at a rising edge of a data selection signal sent from the storage device, and to sample the first delayed signal, the plurality of second delayed signals, and the plurality of third delayed signals at a falling edge of the data selection signal; and a determiner configured to determine a data valid window of the data input / output signal based on a first rising sampling value and a first falling sampling value of the first delayed signal sampled at a rising edge and a falling edge, respectively.

[0009] According to another aspect of the exemplary embodiment, an electronic device may include: a storage device configured to generate a data input / output signal and a data selection signal synchronized with the data input / output signal; and a memory controller configured to generate a plurality of delayed signals having different phases by delaying the data input / output signal, generate a plurality of sampling values ​​by sampling the plurality of delayed signals based on the data selection signal, and determine a data valid window of the data input / output signal based on the plurality of sampling values. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will become apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a read margin control circuit according to an exemplary embodiment;

[0012] Figure 2 It is shown Figure 1 A block diagram of a delay circuit of a read margin control circuit;

[0013] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 A block diagram of a delay stage of a delay circuit;

[0014] Figure 4 is a diagram showing a method according to another exemplary embodiment Figure 2 A block diagram of a delay stage of a delay circuit;

[0015] Figure 5 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a sampler for reading a margin control circuit;

[0016] Figure 6 is a diagram showing a method according to an exemplary embodiment Figure 1A block diagram of a determiner of a read margin control circuit;

[0017] Figures 7 to 9 It is shown Figure 2 The delay circuit delays the signal and Figure 6 a view of a left parity signal and a right parity signal of a determiner of;

[0018] Figure 10 to Figure 11 It is shown Figure 2 The delay circuit delays the signal and Figure 6 a view of a left parity signal and a right parity signal of a determiner of;

[0019] Fig.12 is a block diagram showing a read margin control circuit according to another exemplary embodiment;

[0020] Fig.13 and Fig.14 is a diagram showing a method of performing a Fig.12 A view of an example of a read margin control circuit sliding a data valid window of a data input / output signal;

[0021] Fig.15 is a flowchart illustrating an operation for controlling a read margin of a data input / output signal according to an exemplary embodiment;

[0022] Fig.16 is a block diagram showing a read margin control circuit according to another exemplary embodiment;

[0023] Fig.17 It is shown Fig.16 A block diagram of a sampler for reading a margin control circuit;

[0024] Fig.18 It is shown Fig.16 A block diagram of a first comparator and a second comparator of a read margin control circuit;

[0025] Fig.19 is a block diagram illustrating a storage system according to an exemplary embodiment;

[0026] Fig. 20 is a block diagram illustrating a computing device according to an exemplary embodiment; and

[0027] Fig.21 is a block diagram illustrating an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] Below, exemplary embodiments may be described in detail and clearly so that those having ordinary skill in the art can easily realize the inventive concept.

[0029] Figure 1 1 is a block diagram showing a read margin control circuit according to an exemplary embodiment. The read margin control circuit 100 may include a delay circuit 110, a sampler 120, and a determiner 130. The read margin control circuit 100 may receive a data input / output signal DQ and a data strobe signal DQS and may determine a data valid window.

[0030] The data input / output signal DQ may be generated in response to the read command by a storage device receiving the read command. The read data may be included in the data input / output signal DQ. The data strobe signal DQS may be generated by the storage device and may be used to sample the data input / output signal DQ. Since the read margin control circuit 100 receives the data input / output signal DQ and the data strobe signal DQS output from the storage device and determines the data valid window, the read margin control circuit 100 may be referred to as a "memory controller".

[0031] The data input / output signal DQ may be synchronized with the data selection signal DQS. The data valid window may indicate a period during which the data input / output signal DQ is effectively sampled based on the data selection signal DQS. For example, the data valid window may indicate whether the read margin is sufficient.

[0032] The delay circuit 110 may receive a data input / output signal DQ. The delay circuit 110 may delay the data input / output signal DQ and may generate a delayed signal. For example, the phases of the delayed signals delayed by the delay circuit 110 may be different from each other. The delay circuit 110 may be referred to as a "delay line".

[0033] The sampler 120 may sample the delayed signals output from the delay circuit 110 respectively based on the data strobe signal DQS. The sampler 120 may generate a sampled value of the delayed signal by sampling. Here, the sampled value may include a logic value of the delayed signal captured at a rising edge or a falling edge of the data strobe signal DQS. For example, the logic value of the delayed signal may be based on data stored in a storage device.

[0034] In some exemplary embodiments, the data select signal DQS is shown as being sent in a single-ended manner, but the data select signal DQS may be sent in a differential manner. That is, the sampler 120 may sample the delay signal based on the positive data select signal PDQS (not shown) and the negative data select signal NDQS (not shown), respectively. In addition, the storage device may send the data input / output signal DQ at a double data rate, and the data input / output signal DQ may be sampled at both the rising edge and the falling edge of the data select signal DQS.

[0035] The determiner 130 may determine the data valid window based on the sampled value sampled by the sampler 120. The determiner 130 may determine where the sampling point is placed in the data valid window. The determination result of the determiner 130 may be used to adjust the data input / output signal DQ or the data strobe signal DQS so that the sampling point is located at the center of the data valid window. Here, the sampling point may indicate a point where the edge of the data strobe signal DQS for sampling the data input / output signal DQ is placed.

[0036] In some exemplary embodiments, the determiner 130 may determine the data valid window based on a sampled value of a center delayed signal among the delayed signals of the delay circuit 110 sampled by the sampler 120. Here, the center delayed signal refers to a signal placed at the center when the delayed signals are arranged in order of delay amount.

[0037] Generally, before receiving read data output from the memory device in response to a read command, training may be performed on the data input / output signal DQ and the data strobe signal DQS output from the memory device. The sampling point may be placed at the center of the data valid window through training.

[0038] However, due to voltage or temperature variation, the data input / output signal DQ or the data strobe signal DQS may be shifted when accessing the memory device, and thus, the read margin or the data valid window may be reduced. Therefore, even after training, the memory controller for controlling the memory device may adjust the data input / output signal DQ or the data strobe signal DQS so that the sampling point is located at the center of the data valid window.

[0039] In order to determine the data valid window, the memory controller of the related art may, for example, repeatedly sample the data input / output signal DQ while changing the sampling point. That is, in order to change the sampling point, the memory controller of the related art may apply an offset to the data strobe signal DQS and may repeatedly issue a read command. However, due to the iterative read command, the time taken to determine the data valid window may increase.

[0040] According to an exemplary embodiment, the read margin control circuit 100 can determine the data valid window by sampling the delayed signal of the data input / output signal DQ based on the data strobe signal DQS through one read command. That is, the read margin control circuit 100 can determine the data valid window without repeatedly issuing the read command in an iterative manner (i.e., without using an iterative read command).

[0041] Figure 2 It is shown Figure 1The delay circuit 110 may include a first delay stage 111_1 to an n+1th delay stage 111_n+1 connected in series or cascade. The first delay stage 111_1 to the n+1th delay stage 111_n+1 may be implemented to be identical to each other. Here, "n" is an integer of 2 or more, and the number of the first delay stage 111_1 to the n+1th delay stage 111_n+1 is not limited to Figure 3 For example, when the number of the first delay stage 111_1 to the n+1th delay stage 111_n+1 increases, the size of the data valid window determined by the read margin control circuit 100 may increase.

[0042] The first delay stage 111_1 may delay the data input / output signal DQ based on the selection signal SEL and may delay a return signal of the second delay stage 111_2. The first delay stage 111_1 may return the data input / output signal DQ based on the selection signal SEL.

[0043] The second delay stage 111_2 may delay the signal delayed by the first delay stage 111_1, and may delay the return signal of the third delay stage 111_3 based on the selection signal SEL. The second delay stage 111_2 may return the signal delayed by the first delay stage 111_1 based on the selection signal SEL. Each of the third delay stage 111_3 to the n+1th delay stage 111_n+1 may operate substantially similarly to the second delay stage 111_2.

[0044] In some exemplary embodiments, the selection signal SEL may include n+1 bits, the same number as the number of the first delay stage 111_1 to the n+1th delay stage 111_n+1. Each of the n+1 bits may include a first logic value (e.g., logic "0") or a second logic value (e.g., logic "1"). For example, a delay stage receiving a first logic value may output a delayed signal sent from a previous delay stage to a next delay stage. Conversely, a delay stage receiving a second logic value may return a delayed signal sent from a previous delay stage to the previous delay stage. One of the first delay stage 111_1 to the n+1th delay stage to 111_n+1 may receive a bit of the selection signal SEL having a second logic value, and the remaining delay stages may receive bits of the selection signal SEL having a first logic value.

[0045] Figure 2 It is shown that the n+1th delay stage 111_n+1 returns the delayed signal transmitted from the seventh delay stage 111_7 to the seventh delay stage 111_7. However, any one of the first to seventh delay stages 111_1 to 111_7 except the n+1th delay stage 111_n+1 may return the delayed signal transmitted from the previous stage to the previous stage.

[0046] The signal returned from the n+1th delay stage 111_n+1 may sequentially pass through the seventh delay stage 111_7 to the first delay stage 111_1. The first to nth delayed signals DS[1:n] may be output from the second delay stage 111_2 to the n+1th delay stage 111_n+1, respectively. The sixth delayed signal DS[6] may be further delayed by ΔT relative to the nth delayed signal DS[n], and the fifth delayed signal DS[5] may be further delayed by ΔT relative to the sixth delayed signal DS[6]. That is, the delay difference between the first to nth delayed signals DS[1:n] may be ΔT. ΔT may indicate the propagation delay of the first delay stage 111_1 to the n+1th delay stage 111_n+1. The phase difference of the first to nth delayed signals DS[1:n] may be determined based on ΔT. When ΔT becomes smaller, the data valid window may be determined more accurately.

[0047] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 The delay stage 111 may be one of the first delay stage 111_1 to the n+1th delay stage 111_n+1. The delay stage 111 may include an inverter 112 and NAND gates 113 to 115.

[0048] The inverter 112 may invert the selection signal SEL. The NAND gate 113 may delay the input signal IN and may output the pass signal PASS to the next delay stage based on the inverted selection signal. The NAND gate 114 may output the input signal IN to the NAND gate 115 based on the selection signal SEL. Here, the input signal IN may be sent from the previous delay stage. For example, if the selection signal SEL includes a first logic value, the input signal IN may be delayed and output as the pass signal PASS. If the selection signal SEL includes a second logic value, the input signal IN may be returned.

[0049] The NAND gate 115 may receive the output of the NAND gate 114 and the return signal RETURN, and may output the output signal OUT. Here, the return signal RETURN may be sent from the next delay stage. For example, the propagation delay ( Figure 2 ΔT) may be the propagation delay of the NAND gate 115.

[0050] Figure 4 is a diagram showing a method according to another exemplary embodiment Figure 2 A block diagram of a delay stage of a delay circuit of FIG. Figure 3 describe Figure 4 . Figure 4 The delay stage 111 can be similar to Figure 3 The delay stage 111 operates with Figure 3The delay level 111 is different, Figure 4 The delay stage 111 of the embodiment of the present invention can be implemented by using a NOR gate instead of a NAND gate. Since the delay stage 111 is implemented with NOR gates 117 to 119 instead of a NAND gate, the output of the inverter 116 can be provided to the NOR gate 118. For example, the propagation delay of the delay stage 111 can be the propagation delay of the NOR gate 119. The propagation delay of the delay stage 111 can be the propagation delay of a logic gate such as a NAND gate or a NOR gate.

[0051] Figure 5 is a diagram showing a method according to an exemplary embodiment Figure 1 The block diagram of the sampler of the read margin control circuit is shown in FIG. Figure 1 and Figure 2 describe Figure 5 .exist Figure 5 In, assuming Figure 2 The delay circuit 110 includes first to eighth delay stages 111_1 to 111_8, and first to seventh delay signals DS[1:7] are output from second to eighth delay stages 111_2 to 111_8, respectively (ie, n is 7).

[0052] The sampler 120 includes first to seventh flip-flops 121_1 to 121_7 which may sample first to seventh delay signals DS[1:7] at a rising edge or a falling edge of a data strobe signal DQS and may output first to seventh sampled values ​​S[1:7].

[0053] In some exemplary embodiments, the number of the first to seventh triggers 121_1 to 121_7 included in the sampler 120 may be the same as the number of the first to seventh delay signals DS[1:7]. Of course, the number of the first to seventh triggers 121_1 to 121_7 is not limited to Figure 5 The quantity shown in .

[0054] In some exemplary embodiments, the first to seventh triggers 121_1 to 121_7 may be implemented to be identical to each other and may be arranged in the form of an array. Similar to the first delay stage 111_1 to the eighth delay stage 111_8 of the delay circuit 110, the first to seventh triggers 121_1 to 121_7 may be arranged in series. The first to seventh triggers 121_1 to 121_7 may be arranged adjacent to the delay circuit 110 so that the lengths of the transmission paths of the first to seventh delay signals DS[1:7] are identical to each other. Here, the transmission paths of the first to seventh delay signals DS[1:7] may be from the second delay stage 111_2 to the eighth delay stage 111_8 to the first to seventh triggers 121_1 to 121_7.

[0055] Figure 6 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a read margin control circuit is provided. Figure 1 , Figure 2 and Figure 5 describe Figure 6 .exist Figure 6 In, assuming Figure 2 The delay circuit 110 includes the first to eighth delay stages 111_1 to 111_8, and the first to seventh delay signals DS[1:7] are output from the second to eighth delay stages 111_2 to 111_8, respectively. The first to seventh sampling values ​​S[1:7] may be values ​​obtained by sampling the first to seventh delay signals DS[1:7].

[0056] The determiner 130 may compare the fourth sampling value S[4] with each of the first to third sampling values ​​S[1:3] and the fifth to seventh sampling values ​​S[5:7]. The fourth sampling value S[4] may be a value obtained by sampling the fourth delayed signal DS[4], and the fourth delayed signal DS[4] may be a central delayed signal of the first to seventh delayed signals DS[1:7]. That is, the delay circuit 110 may generate the fourth delayed signal DS[4], the fifth to seventh delayed signals DS[5:7] which are less delayed than the fourth delayed signal DS[4] (or whose total delay amount is less than the delay amount of the fourth delayed signal DS[4]), and the first to third delayed signals DS[1:3] which are more delayed than the fourth delayed signal DS[4] (or whose total delay amount is greater than the delay amount of the fourth delayed signal DS[4]). In other words, the fifth to seventh delayed signals DS[5:7] may be before the fourth delayed signal DS[4], and the first to third delayed signals DS[1:3] may be after the fourth delayed signal DS[4]. Here, in the case where the delay circuit 110 outputs odd-numbered delayed signals DS[1:n], the center delayed signal may be the (n+1) / 2th delayed signal DS[(n+1) / 2].

[0057] The determiner 130 may determine a data valid window based on the fourth sampling value S[4]. The determiner 130 may determine whether each of the first to third sampling values ​​S[1:3] matches the fourth sampling value S[4]. The determiner 130 may determine whether each of the fifth to seventh sampling values ​​S[5:7] matches the fourth sampling value S[4]. To this end, the determiner 130 may include first to third exclusive OR (XOR) gates 131_1 to 131_3 and fifth to seventh XOR gates 131_5 to 131_7.

[0058] The first XOR gate 131_1 may generate a first left parity check signal LP[1] indicating whether the first sampling value S[1] matches the fourth sampling value S[4]. Similar to the above description, the second XOR gate 131_2 and the third XOR gate 131_3 may respectively generate second and third left parity check signals LP[2:3] indicating whether the second and third sampling values ​​S[2:3] match the fourth sampling value S[4]. The first to third left parity check signals LP[1:3] obtained as a result of comparing the first to third sampling values ​​S[1:3] with the fourth sampling value S[4] may indicate a left valid window margin LeftVWM (Left VWM) of the data valid window.

[0059] The fifth XOR gate 131_5 may generate a first right parity check signal RP[1] indicating whether the fifth sampling value S[5] matches the fourth sampling value S[4]. Similar to the above description, the sixth XOR gate 131_6 and the seventh XOR gate 131_7 may respectively generate second and third right parity check signals RP[2:3] indicating whether the sixth and seventh sampling values ​​S[6:7] match the fourth sampling value S[4]. The first to third right parity check signals RP[1:3] obtained as a result of comparing the fifth to seventh sampling values ​​S[5:7] with the fourth sampling value S[4] may indicate a right valid window margin RightVWM (right VWM) of the data valid window.

[0060] In some exemplary embodiments, the case where the parity check signal is in the first logic state may indicate that the sampled values ​​match each other, and the case where the parity check signal is in the second logic state may indicate that the sampled values ​​do not match each other. However, in other exemplary embodiments, the opposite approach may be adopted, so that the case where the parity check signal is in the second logic state may indicate that the sampled values ​​match each other, and the case where the parity check signal is in the first logic state may indicate that the sampled values ​​do not match each other.

[0061] The determiner 130 may include a logic gate that performs an exclusive OR operation or an exclusive NOR operation on the first to seventh sampling values ​​S[1:7]. Figure 6 An example in which the logic gate is an XOR gate is shown, but in other exemplary embodiments, the logic gate may be implemented with an XNOR gate. The number of logic gates may be determined according to the number of sample values.

[0062] Figures 7 to 9 It is shown Figure 2 The delay circuit delays the signal and Figure 6 A view of the left parity signal and the right parity signal of the determiner. Figure 1 , Figure 2 and Figure 6 describe Figures 7 to 9 It is assumed that the first to seventh delayed signals DS[1:7] are output from the delay circuit 110 .

[0063] The data valid window of the seventh delayed signal DS[7] can be formed in any period. The data valid window of the sixth delayed signal DS[6] can be delayed by ΔT relative to the data valid window of the seventh delayed signal DS[7]. As described above, the data valid window of each of the first to fifth delayed signals DS[1:5] can be delayed by ΔT. As described above, ΔT can indicate the propagation delay of the delay stage.

[0064] The first to seventh delayed signals DS[1:7] may be sampled at a sampling point by the sampler 120. The first to third XOR gates 131_1 to 131_3 may generate first to third left parity signals LP[1:3]. The fifth to seventh XOR gates 131_5 to 131_7 may generate first to third right parity signals RP[1:3].

[0065] Figure 7 It can indicate the case where the sampling point is located at the center of the data valid window of the fourth delayed signal DS[4]. The left valid window margin Left VWM and the right valid window margin Right VWM can be the same as each other with respect to the fourth delayed signal DS[4]. For example, the sampling point can be within all data valid windows of the first to seventh delayed signals DS[1:7]. Each of the first to third sampling values ​​S[1:3] and the fifth to seventh sampling values ​​S[5:7] can match the fourth sampling value S[4]. Therefore, the first to third left parity check signals LP[1:3] can be "000", and the first to third right parity check signals RP[1:3] can be "000". Here, the logic values ​​of the parity check signals can be exemplary values.

[0066] Figure 8 It can indicate that the sampling point is located on the right side of the data valid window of the fourth delayed signal DS[4]. The right valid window margin Right VWM can be smaller than the left valid window margin Left VWM relative to the fourth delayed signal DS[4]. For example, the sampling point can be within the data valid window of the first to fifth delayed signals DS[1:5], and can be outside the data valid window of the sixth and seventh delayed signals DS[6:7]. Figure 8Different from the description given, the sampling point may be outside the data valid window of one or more of the fifth to seventh delayed signals DS[5:7]. For example, in some cases, the sampling point may be outside the data valid window of DS[7], but within the data valid windows of DS[6] and DS[5] (i.e., RP[1:3]=001), while in another example, the sampling point may be outside the data valid window of DS[5:7] (i.e., RP[1:3]=111).

[0067] exist Figure 8 In the example shown, each of the first to third sampling values ​​S[1:3] may match the fourth sampling value S[4]. The first to third left parity check signals LP[1:3] may be "000". The fifth sampling value S[5] may match the fourth sampling value S[4], but the sixth and seventh sampling values ​​S[6:7] may not match the fourth sampling value S[4]. The first to third right parity check signals RP[1:3] may be "011". Here, the logic values ​​of the parity check signals may be exemplary values. It may be determined by the first to third left parity check signals LP[1:3] and the first to third right parity check signals RP[1:3] that the sampling point is located on the right side of the data valid window.

[0068] Fig. 9 It can indicate the case where the sampling point is located on the left side of the data valid window of the fourth delayed signal DS[4]. The left valid window margin Left VWM can be smaller than the right valid window margin Right VWM relative to the fourth delayed signal DS[4]. For example, the sampling point can be within the data valid window of the third to seventh delayed signals DS[3:7] and can be outside the data valid window of the first and second delayed signals DS[1:2]. Fig. 9 Different from the description given, the sampling point may be outside the data valid window of one or more of the first to third delayed signals DS[1:3]. For example, in some cases, the sampling point may be outside the data valid window of DS[1], but within the data valid windows of DS[2] and DS[3] (i.e., LP[1:3]=100), while in another example, the sampling point may be outside the data valid window of DS[1:3] (i.e., LP[1:3]=111).

[0069] exist Fig. 9In the example shown, each of the fifth to seventh sampling values ​​S[5:7] may match the fourth sampling value S[4]. The first to third right parity check signals RP[1:3] may be "000". The third sampling value S[3] may match the fourth sampling value S[4], but the first and second sampling values ​​S[1:2] may not match the fourth sampling value S[4]. The first to third left parity check signals LP[1:3] may be "110". Here, the logic values ​​of the parity check signals may be exemplary values. It may be determined by the first to third left parity check signals LP[1:3] and the first to third right parity check signals RP[1:3] that the sampling point is located on the left side of the data valid window.

[0070] Figure 10 to Figure 11 It is shown Figure 2 The delay circuit delays the signal and Figure 6 The view of the left parity signal and the right parity signal of the determiner will refer to Figure 1 , Figure 2 , Figure 6 and Figure 7 describe Fig.10 and Fig.11 It is assumed that the first to seventh delayed signals DS[1:7] are output from the delay circuit 110 .

[0071] According to an exemplary embodiment, Figures 7 to 9 Various examples of placing sampling points in the data valid window are described. According to another exemplary embodiment, the size of the data valid window (ie, the absolute data valid window margin) may be determined.

[0072] Fig.10 Can indicate Figure 7 The size of the data valid window is reduced. For example, the sampling point may be within the data valid window of the third to fifth delayed signals DS[3:5], and may be outside the data valid window of the first delayed signal DS[1], the second delayed signal DS[2], the sixth delayed signal DS[6], and the seventh delayed signal DS[7]. Each of the third and fifth sampled values ​​S[3,5] may match the fourth sampled value S[4], but the first sampled value S[1], the second sampled value S[2], the sixth sampled value S[6], and the seventh sampled value S[7] may not match the fourth sampled value S[4].

[0073] Therefore, the first to third left parity signals LP[1:3] may be "110", and the first to third right parity signals RP[1:3] may be "011". It may be determined that the size of the data valid window is reduced by the first to third left parity signals LP[1:3] and the first to third right parity signals RP[1:3]. That is, since each of the left parity signal and the right parity signal has a bit indicating that the sampling point is outside the data valid window, it may be determined that the size of the data valid window is less than Figure 7 The data valid window.

[0074] Fig.11 Can indicate Figure 7 The size of the data valid window is further reduced. For example, the sampling point may be within the data valid window of the fourth delayed signal DS[4], and may be outside the data valid windows of the first delayed signal DS[1], the second delayed signal DS[2], the third delayed signal DS[3], the fifth delayed signal DS[5], the sixth delayed signal DS[6], and the seventh delayed signal DS[7]. Each of the first sampling value S[1], the second sampling value S[2], the third sampling value S[3], the fifth sampling value S[5], the sixth sampling value S[6], and the seventh sampling value S[7] may not match the fourth sampling value S[4].

[0075] Therefore, the first to third left parity signals LP[1:3] may be "111", and the first to third right parity signals RP[1:3] may be "111". The size of the data valid window may be further reduced by determining the first to third left parity signals LP[1:3] and the first to third right parity signals RP[1:3].

[0076] In some exemplary embodiments, the determiner 130 may determine the size of the data valid window based on at least one sampling value among the first sampling value S[1], the second sampling value S[2], the third sampling value S[3], the fifth sampling value S[5], the sixth sampling value S[6], and the seventh sampling value S[7] that matches the fourth sampling value S[4]. The determiner 130 may decode the first to third left parity check signals LP[1:3] and the first to third right parity check signals RP[1:3], and may determine the sampling value among the first sampling value S[1], the second sampling value S[2], the third sampling value S[3], the fifth sampling value S[5], the sixth sampling value S[6], and the seventh sampling value S[7] that matches the fourth sampling value S[4].

[0077] Fig.12 FIG. 2 is a block diagram showing a read margin control circuit according to another exemplary embodiment. Figure 1 and Figure 6 describe Fig.12 The read margin control circuit 200 may include a delay circuit 210 , a sampler 220 , a determiner 230 , a first delay cell Delay Cell 1 240 , a second delay cell Delay Cell 2 250 , and a code generator 290 .

[0078] Unlike the delay circuit 110, the delay circuit 210 may receive the output of the first delay unit 240 by which the data input / output signal DQ is delayed. Except for the above differences, the delay circuit 210 may operate similarly to the delay circuit 110. The delay circuit 210 may delay the output of the first delay unit 240, and may generate a delayed signal having a different phase.

[0079] Unlike the sampler 120, the sampler 220 may receive the output of the second delay unit 250 by which the data strobe signal DQS is delayed. Except for the above differences, the sampler 220 may operate similarly to the sampler 120. The sampler 220 may sample the delayed signal output from the delay circuit 210 based on the data strobe signal delayed by the second delay unit 250.

[0080] The determiner 230 may include a comparator 231 and an accumulator 236. The comparator 231 may compare the sampled values ​​of the sampler 220. The comparator 231 may include first to third XOR gates 131_1 to 131_3 and fifth to seventh XOR gates 131_5 to 131_7. Figure 6 That is, the determiner 230 may operate similarly to the determiner 130 .

[0081] The accumulator 236 can accumulate the comparison results from the comparator 231. For example, the data input / output signal can include various read data for determining the data valid window. One or more read commands can be sent to a storage device (not shown), and one or more data input / output signals can be sent from the storage device. The accumulator 236 can accumulate the comparison results of the comparator 231 for the data input / output signal.

[0082] The determiner 230 may determine the data valid window based on the comparison result of the comparator 231 and the accumulation result of the accumulator 236. The determiner 230 may send an increase signal INC or a decrease signal DEC to the code generator 290 for changing the first code Code1 or the second code Code2.

[0083] In some exemplary embodiments, the unit or amount of the delay of the first delay unit 240 adjusted according to the first code Code1 may correspond to the reference Figure 2The propagation delay of each of the first delay stage 111_1 to the n+1th delay stage 111_n+1 is described. The delay of the first delay unit 240 changed according to the least significant bit (LSB) of the first code Code1 may correspond to the propagation delay of the delay stage. Similar to the above description, the unit or amount of the delay of the second delay unit 250 adjusted according to the second code Code2 may correspond to the propagation delay of the delay stage. The delay of the second delay unit 250 changed according to the LSB of the second code Code2 may also correspond to the propagation delay of the delay stage.

[0084] and Figure 1 Compared with the read margin control circuit 100, the read margin control circuit 200 may further include a first delay unit 240 and a second delay unit 250. Fig.12 In the example shown, the read margin control circuit 200 includes both the first delay unit 240 and the second delay unit 250. However, in some example embodiments, the read margin control circuit 200 may include only one of the first delay unit 240 and the second delay unit 250.

[0085] The first delay unit 240 may receive the data input / output signal DQ. The first delay unit 240 may delay the data input / output signal DQ based on the first code Code1. The first delay unit 240 may be a variable delay unit in which the delay amount of the data input / output signal DQ is determined according to the first code Code1.

[0086] In some exemplary embodiments, the delay amount of the data input / output signal DQ of the first delay unit 240 may be changed in a digital manner based on the first code Code1. The first delay unit 240 may be implemented with at least one logic gate (e.g., inverter) that receives the first code Code1. Alternatively, the first delay unit 240 may be implemented similarly to the delay circuit 210. In another exemplary embodiment, the delay amount of the data input / output signal DQ of the first delay unit 240 may be changed in an analog manner based on a voltage or current corresponding to the first code Code1.

[0087] The second delay unit 250 may receive the data strobe signal DQS. The second delay unit 250 may delay the data strobe signal DQS based on the second code Code2. The second delay unit 250 may be a variable delay unit, wherein the delay amount of the data strobe signal DQS is determined according to the second code Code2. For example, the second delay unit 250 may be implemented similarly to the first delay unit 240. That is, the delay amount of the second delay unit 250 may be changed in a digital or analog manner.

[0088] The code generator 290 may generate a first code Code1 for adjusting the delay amount of the first delay unit 240 or a second code Code2 for adjusting the delay amount of the second delay unit 250 based on the determination result of the determiner 230. Through the code generator 290, the data input / output signal DQ may be further delayed with respect to the data strobe signal DQS, or conversely, the data strobe signal DQS may be further delayed with respect to the data input / output signal DQ.

[0089] In detail, the code generator 290 may generate the first code Code1 or the second code Code2 based on the left parity signal and the right parity signal. Figure 6 As described, the first to third XOR gates 131_1 to 131_3 may generate first to third left parity check signals LP[1:3]. The fifth to seventh XOR gates 131_5 to 131_7 may generate first to third right parity check signals RP[1:3]. The first to third left parity check signals LP[1:3] may indicate at least one sampled value among the first to third sampled values ​​S[1:3] that does not match the fourth sampled value S[4]. The first to third right parity check signals RP[1:3] may indicate at least one sampled value among the fifth to seventh sampled values ​​S[5:7] that does not match the fourth sampled value S[4].

[0090] For example, assuming that the sampling point is located on the left side of the data valid window and the left window margin of the data valid window is insufficient. In this case, at least one of the first to third sampling values ​​S[1:3] may not match the fourth sampling value S[4]. The code generator 290 may generate the first code Code1 or the second code Code2 based on at least one sampling value that does not match the fourth sampling value S[4], so that the data selection signal DQS is further delayed relative to the data input / output signal DQ.

[0091] On the contrary, in another example, it is assumed that the sampling point is located on the right side of the data valid window and the right window margin of the data valid window is insufficient. In this case, at least one of the fifth to seventh sampling values ​​S[5:7] may not match the fourth sampling value S[4]. The code generator 290 may generate the first code Code1 or the second code Code2 based on at least one sampling value that does not match the fourth sampling value S[4], so that the data input / output signal DQ is further delayed relative to the data selection signal DQS.

[0092] Fig.13 and Fig.14 is a diagram showing a method of performing a Fig.12 FIG. 1 is a diagram showing an example of a data valid window of a read margin control circuit sliding a data input / output signal. Figure 6 and Fig.12 describe Fig.13 and Fig.14 . Fig.13 This involves the case where the sampling point is shifted to the right. Fig.14 This involves the case where the sampling point is shifted to the left.

[0093] A signal (delayed signal) generated by delaying the data input / output signal DQ can be Fig.13 and Fig.14 The sampling point may be sampled at a point indicated by each arrow shown in . According to an exemplary embodiment, the sampling point may not be changed by applying an offset to the data strobe signal DQS. A delayed signal of the data input / output signal DQ may be generated, and the delayed signal may be sampled at the same time.

[0094] exist Fig.13 and Fig.14 In the example, "P" and "F" may represent "pass" and "fail", respectively. A pass may indicate that a value sampled at a point indicated by an arrow matches a value sampled in a data valid window. A fail may indicate that a value sampled at a point indicated by an arrow does not match a value sampled in a data valid window. For example, a pass and a fail may be generated based on the first to third left parity check signals LP[1:3] and the first to third right parity check signals RP[1:3], and may be referenced to Fig.12 The determination result of the determiner 230 is described.

[0095] exist Fig.13 In the example, at least one of the first to third left parity check signals LP[1:3] may be activated. The first to third left parity check signals LP[1:3] may indicate that the sampling point is on the left side of the data valid window. The code generator 290 may be configured according to Fig.13 The first code Code1 or the second code Code2 is generated by the pass and fail shown in , and the code generator 290 can delay the data strobe signal DQS more than the data input / output signal DQ. Based on the code generated in this way, the data strobe signal DQS can be further delayed relative to the data input / output signal DQ. Therefore, the sampling point can be shifted to the right.

[0096] exist Fig.14 In the example, at least one of the first to third right parity check signals RP[1:3] may be activated. The first to third right parity check signals RP[1:3] may indicate that the sampling point is located on the right side of the data valid window. The code generator 290 may be based on Fig.14The first code Code1 or the second code Code2 is generated by the pass and fail shown in , and the code generator 290 can delay the data input / output signal DQ more than the data strobe signal DQS. Based on the code generated in this way, the data input / output signal DQ can be further delayed relative to the data strobe signal DQS. Therefore, the sampling point can be shifted to the left.

[0097] exist Fig.13 and Fig.14 , each indicating a pass or a fail is shown in FIG. 1 , but the inventive concept is not limited thereto. The number of passes and the number of fails may be determined according to the number of delay signals generated by the delay circuit 210 .

[0098] Fig.15 is a flowchart illustrating an operation for controlling a read margin of a data input / output signal according to an exemplary embodiment. Figure 12 to Figure 14 describe Fig.15 .

[0099] In operation S110, the delay circuit 210 may delay the data input / output signal DQ and may generate a delayed signal. For example, the delay circuit 210 may include a digital circuit such as a logic gate for delaying the data input / output signal DQ. The phases of the delayed signals may be different from each other.

[0100] In operation S120, the sampler 220 may sample the delayed signal based on the data strobe signal DQS. The sampler 220 may generate a sample value including a logic value of the delayed signal at a rising edge or a falling edge of the data strobe signal DQS.

[0101] In operation S130, the determiner 230 may compare the sample values. The determiner 230 may compare the center delay signal (reference Figure 2 The sampled value of the fourth delayed signal DS[4]) sampled is compared with each of the remaining sampled values.

[0102] In operation S140, the determiner 230 may accumulate the comparison results and compare the right valid window margin and the left valid window margin. As described above, the comparison result may be generated by sampling the data input / output signal including various read data and comparing the sampling results. The determiner 230 may determine the data valid window based on the accumulated comparison results. In detail, the determiner 230 may determine whether the left valid window margin is insufficient, whether the right valid window margin is insufficient, or whether all left valid window margins and right valid window margins are insufficient.

[0103] In operation S150, the left valid window margin (Left VWM) of the data valid window may be insufficient (see Fig.13The code generator 290 may generate the first code Code1 or the second code Code2 so that the data strobe signal DQS is further delayed relative to the data input / output signal DQ. The code generator 290 may shift the sampling point of the data input / output signal DQ to the right.

[0104] In operation S160, the right valid window margin (Right VWM) of the data valid window may be insufficient (see Fig.14 The code generator 290 may generate the first code Code1 or the second code Code2 so that the data input / output signal DQ is further delayed relative to the data strobe signal DQS. The code generator 290 may shift the sampling point of the data input / output signal DQ to the left.

[0105] In operation S170, all Left VWM and Right VWM of the data valid window may be insufficient. In this case, the determiner 230 may determine that the absolute size of the data valid window is small. For example, the determiner 230 may shield the storage device that generates the data input / output signal DQ. In operation S180, both the Left VWM and the Right VWM of the data valid window may be sufficient. In this case, the determiner 230 may determine that no action is required.

[0106] Fig.16 FIG. 2 is a block diagram showing a read margin control circuit according to another exemplary embodiment. Fig.12 describe Fig.16 The read margin control circuit 300 may include a delay circuit 310, a sampler 320, a determiner 330, a first delay unit 340, a second delay unit 350, a third delay unit 360, and a code generator 390. The operations of the delay circuit 310 and the first delay unit 340 may be similar to the operations of the delay circuit 210 and the first delay unit 240.

[0107] The read margin control circuit 300 may receive a positive data strobe signal PDQS and a negative data strobe signal NDQS transmitted in a differential manner. The second delay unit 350 may delay the positive data strobe signal PDQS based on the second code Code2. The third delay unit 360 may delay the negative data strobe signal NDQS based on the third code Code3. The operation of each of the second delay unit 350 and the third delay unit 360 may be similar to the operation of the second delay unit 250.

[0108] The sampler 320 may sample the delayed signal output from the delay circuit 310 based on the positive data strobe signal PDQS and the negative data strobe signal NDQS, respectively. For example, the sampled value sampled based on the positive data strobe signal PDQS may correspond to the delay signal output from the delay circuit 310. Fig.12 The sampled value sampled based on the negative data strobe signal NDQS may correspond to the sampled value sampled on the rising edge of the data strobe signal DQS. Fig.12 The sampler 320 may be operated similarly to the sampler 220 .

[0109] The determiner 330 may determine the data valid window based on the sampled values ​​sampled based on the positive data strobe signal PDQS and the negative data strobe signal NDQS, respectively. For example, the determiner 330 may determine the data valid window based on the sampled values ​​sampled by the sampler 320 at the rising edge and the falling edge of the data strobe signal DQS, respectively. The determiner 330 may operate similarly to the determiner 230.

[0110] The determiner 330 may include a first comparator 331, a second comparator 332, and an accumulator 336. The first comparator 331 may compare a sampled value sampled synchronously with the positive data strobe signal PDQS. The second comparator 332 may compare a sampled value sampled synchronously with the negative data strobe signal NDQS. The operation of each of the first comparator 331 and the second comparator 332 may be similar to the operation of the comparator 231. The operation of the accumulator 336 may be similar to the operation of the accumulator 236.

[0111] The code generator 390 may generate a first code Code1 for adjusting the delay amount of the first delay unit 340, a second code Code2 for adjusting the delay amount of the second delay unit 350, or a third code Code3 for adjusting the delay amount of the third delay unit 360 based on the determination result of the determiner 330. Through the code generator 390, the data input / output signal DQ may be further delayed with respect to the positive data strobe signal PDQS and the negative data strobe signal NDQS, or conversely, the positive data strobe signal PDQS and the negative data strobe signal NDQS may be further delayed with respect to the data input / output signal DQ. The operation of the code generator 390 may be similar to the operation of the code generator 290.

[0112] Fig.17 It is shown Fig.16 The block diagram of the sampler of the read margin control circuit is shown in FIG. Figure 5 and Fig.16 describe Fig.17 .exist Fig.17 In, assuming Fig.16 The delay circuit 310 includes eight delay stages, and outputs first to seventh delay signals DS[1:7] from the delay stages.

[0113] The sampler 320 may include first to seventh positive flip-flops 321_1 to 321_7 and first to seventh negative flip-flops 322_1 to 322_7. The operations of the first to seventh positive flip-flops 321_1 to 321_7 and the first to seventh negative flip-flops 322_1 to 322_7 may be similar to those of the first to seventh flip-flops 121_1 to 121_7.

[0114] The first positive flip-flop 321_1 to the seventh positive flip-flop 321_7 may sample the first to seventh delayed signals DS[1:7] based on the positive data strobe signal PDQS, and may output the first to seventh up-sampled values ​​RS[1:7]. The first negative flip-flop 322_1 to the seventh negative flip-flop 322_7 may sample the first to seventh delayed signals DS[1:7] based on the negative data strobe signal NDQS, and may output the first to seventh down-sampled values ​​FS[1:7].

[0115] Fig.18 It is shown Fig.16 A block diagram of a first comparator and a second comparator of a read margin control circuit. Figure 6 , Fig.16 and Fig.17 describe Fig.18 .

[0116] The first comparator 331 may compare the fourth up-sampled value RS[4] with each of the first to third up-sampled values ​​RS[1:3] and the fifth to seventh up-sampled values ​​RS[5:7]. In some exemplary embodiments, the fourth up-sampled value RS[4] may be a center delayed signal (reference signal) of the delayed signal at the rising edge of the data strobe signal DQS. Figure 2 The first comparator 331 may include first to third XOR gates 331_1 to 331_3 and fifth to seventh XOR gates 331_5 to 331_7. The operations of the first to third XOR gates 331_1 to 331_3 and the fifth to seventh XOR gates 331_5 to 331_7 may be similar to Figure 6 The operations of the XOR gates 131_1 to 131_3 and 131_5 to 131_7 are similar.

[0117] The second comparator 332 may compare the fourth down-sampling value FS[4] with each of the first to third down-sampling values ​​FS[1:3] and the fifth to seventh down-sampling values ​​FS[5:7]. In some exemplary embodiments, the fourth down-sampling value FS[4] may be a center delayed signal (reference signal) of the delayed signal at the falling edge of the data strobe signal DQS. Figure 2The second comparator 332 may include first to third XOR gates 332_1 to 332_3 and fifth to seventh XOR gates 332_5 to 332_7. The operations of the first to third XOR gates 332_1 to 332_3 and the fifth to seventh XOR gates 332_5 to 332_7 may be similar to Figure 6 The operations of the XOR gates 131_1 to 131_3 and 131_5 to 131_7 are similar.

[0118] Fig.19 1 is a block diagram illustrating a memory system according to an exemplary embodiment. The memory system 1000 may include a memory controller 1100 and a memory device 1200. The memory system 1000 may be implemented in an electronic device.

[0119] The memory controller 1100 may control the memory device 1200. The memory controller 1100 may send a write command for writing data to the memory device 1200 and a read command for reading data from the memory device 1200. The memory controller 1100 may communicate with the reference Figures 1 to 18 The described read margin control circuits 100, 200, or 300 operate similarly. As in the read margin control circuits 100, 200, and 300, the memory controller 1100 may include a delay circuit 1110, a sampler 1120, a determiner 1130, and / or a code generator 1190, depending on which of the read margin control circuits 100, 200, and 300 is implemented. Although not described in Fig.19 Although shown in FIG. 1 , the memory controller 1100 may further include detailed components of the read margin control circuits 100 , 200 , and 300 .

[0120] According to an exemplary embodiment, the memory controller 1100 may respectively determine the data valid windows of the data input / output signals DQ[1:m] and may respectively control the read margins of the data input / output signals DQ[1:m]. Fig.19 As shown, the number of delay circuits 1110 may be the same as the number of data input / output signals DQ[1:m]. The sampler 1120 may sample the delayed signals of the delay circuits 1110 respectively based on the data strobe signal DQS. Here, all data input / output signals DQ[1:m] may be synchronized with the data strobe signal DQS.

[0121] The memory device 1200 may store data in response to a write command of the memory controller 1100, and may output data in response to a read command of the memory controller 1100. Fig.19, the memory device 1200 may transmit the data input / output signal DQ[1:m] and the data strobe signal DQS to the memory controller 1100 in response to the read command of the memory controller 1100. Here, “m” representing the number of the data input / output signals DQ[1:m] may be an integer of 1 or more and may be determined according to an interface defining a channel between the memory controller 1100 and the memory device 1200.

[0122] In some exemplary embodiments, the memory device 1200 may include a volatile memory device, such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device. In another embodiment, the memory device 1200 may include a non-volatile memory device, such as a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase change random access memory (PRAM) device, a thyristor random access memory (TRAM) device, or a magnetic random access memory (MRAM) device.

[0123] Fig. 20 is a block diagram illustrating a computing device according to an exemplary embodiment. Fig. 20 , the computing device 2000 may include a processor 2100 , a working memory 2200 , a memory controller 2300 , a storage device 2400 , a user interface 2500 , a communication circuit 2600 , and a bus 2700 .

[0124] The processor 2100 may control the overall operation of the computing device 2000. The processor 2100, which may be a central processing unit (CPU), may perform various operations. For example, the processor 2100 may include one or more processor cores.

[0125] The working memory 2200 may exchange data with the processor 2100. The working memory 2200 may temporarily store data used for the operation of the computing device 2000. For example, the working memory 2200 may include a high-speed memory such as a DRAM or an SRAM.

[0126] The memory controller 2300 may exchange data with the memory device 2400. In some exemplary embodiments, the operations of the memory controller 2300 and the memory device 2400 may be similar to those described in the reference Fig.19 The operations of the memory controller 1100 and the memory device 1200 are described to be similar.

[0127] The user interface 2500 may perform communication mediation between a user and the computing device 2000 under the control of the processor 2100. In some exemplary embodiments, the user interface 2500 may include input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, and a vibration sensor. In addition, the user interface 2500 may include output interfaces such as a liquid crystal display (LCD) device, a light emitting diode (LED) display device, an organic LED (OLED) display device, an active matrix OLED (AMOLED) display device, a speaker, and a motor.

[0128] The communication circuit 2600 may communicate with the outside of the computing device 2000 under the control of the processor 2100. The communication circuit 2600 may communicate with the outside of the computing device 2000 according to a wired communication protocol or a wireless communication protocol. For example, the communication circuit 2600 may communicate with the outside of the computing device 2000 in accordance with at least one of various wireless communication protocols (such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID)) (or at least one of various wired communication protocols (such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), and Universal Flash Storage (UFS)) to communicate with the outside of the computing device 2000.

[0129] The bus 2700 may provide a communication path between components of the computing device 2000. The components of the computing device 2000 may exchange data with each other according to a bus format. In some exemplary embodiments, the bus format may include a universal serial bus (USB), a small computer system interface (SCSI), a peripheral component interconnect express (PCIe), an advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), and integrated drive electronics (IDE).

[0130] Fig.21 3000 is a block diagram showing an electronic device according to an exemplary embodiment. The electronic device 3000 may be a data processing device that may use or support an interface proposed by the Mobile Industry Processor Interface (MIPI) Alliance. The electronic device 3000 may be a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device.

[0131] The electronic device 3000 may include a system on chip (SoC) 3100 and a memory device 3200. The SoC 3100, which may be an application processor, may control the overall operation of the electronic device 3000. Various circuits for controlling the electronic device 3000 may be integrated in the SoC 3100. For example, the SoC 3100 may include a memory controller 3110.

[0132] In some exemplary embodiments, the memory controller 3110 and the memory device 3200 may exchange data with each other. The data input / output signal DQ[1:m] and the data strobe signal DQS may be transmitted in both directions between the memory controller 3110 and the memory device 3200. The operations of the memory controller 3110 and the memory device 3200 may be similar to those of the reference Fig.19 The operations of the memory controller 1100 and the memory device 1200 are described to be similar.

[0133] The electronic device 3000 may include a display 3310 and an image sensor 3320. The SoC 3100 may communicate with a display serial interface (DSI) device 3315 of the display 3310 through a DSI. For example, an optical serializer SER may be implemented in the SoC 3100, and an optical deserializer DES may be implemented in the DSI device 3315.

[0134] The SoC 3100 may communicate with a camera serial interface (CSI) device 3325 of the image sensor 3320 through a CSI. For example, an optical deserializer DES may be implemented in the SoC 3100, and an optical serializer SER may be implemented in the CSI device 3325.

[0135] The electronic device 3000 may further include a radio frequency (RF) chip 3330 that communicates with the SoC 3100. The RF chip 3330 may include a physical layer 3331, a DigRF slave device 3332, and an antenna 3333. For example, the physical layer 3331 of the RF chip 3330 and the physical layer of the SoC 3100 may exchange data with each other through a DigRF interface proposed by the MIPI Alliance.

[0136] The electronic device 3000 may further include an embedded / card memory 3340. The embedded / card memory 3340 may exchange data with the SoC 3100. In some exemplary embodiments, the SoC 3100 may receive a data input / output signal and a data strobe signal output from the embedded / card memory 3340, may determine a data valid window of the data input / output signal, and may control a read margin of the data input / output signal.

[0137] The electronic device 3000 may communicate with an external system via Worldwide Interoperability for Microwave Access (WiMAX) 3350, Wireless Local Area Network (WLAN) 3360, Ultra Wideband (UWB) 3370, etc. In addition, the electronic device 3000 may further include a Global Positioning System (GPS) device for processing location information. The electronic device 3000 may further include a bridge chip for managing connections with peripheral devices.

[0138] The read margin control circuit according to an exemplary embodiment can avoid repeatedly sampling the data input / output signal DQ while changing the sampling point by applying an offset to the data strobe signal DQS and repeatedly issuing a read command. Therefore, the time required to determine the data valid window may be reduced.

[0139] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A read margin control circuit, comprising: A delay circuit configured to receive a data input / output signal and generate a plurality of delayed signals by delaying the data input / output signal, the plurality of delayed signals having phases different from each other; a sampler configured to sample a plurality of delayed signals of a data input / output signal based on a data strobe signal to generate a plurality of sampled values; as well as A determiner is configured to compare a first sampling value among the plurality of sampling values ​​with a plurality of second sampling values ​​and a plurality of third sampling values ​​excluding the first sampling value among the plurality of sampling values, and determine a data valid window of the data input / output signal based on a result of the comparison.

2. The read margin control circuit according to claim 1, wherein: The delay circuit includes a plurality of delay stages connected in series, wherein a plurality of delayed signals are outputted from a plurality of delay stages respectively, and Therein, a phase difference between the plurality of delayed signals is determined based on a propagation delay of each of the plurality of delay stages.

3. The read margin control circuit according to claim 1, wherein: The plurality of delayed signals include a first delayed signal, a plurality of second delayed signals having a delay less than that of the first delayed signal, and a plurality of third delayed signals having a delay greater than that of the first delayed signal, and Among them, the multiple sampling values ​​include a first sampling value, multiple second sampling values ​​and multiple third sampling values, the first sampling value is generated by sampling a first delayed signal, the multiple second sampling values ​​are generated by respectively sampling multiple second delayed signals, and the multiple third sampling values ​​are generated by respectively sampling multiple third delayed signals.

4. The read margin control circuit according to claim 1, wherein: The determiner includes a plurality of logic gates, each of which performs an exclusive OR operation on the first sampling value and one of the one or more third sampling values ​​among the plurality of second sampling values, or performs an exclusive NOR operation on the first sampling value and one of the one or more third sampling values ​​among the plurality of second sampling values.

5. The read margin control circuit according to claim 1, wherein: The determiner is further configured to determine a size of the data valid window based on at least one sampling value among the plurality of second sampling values ​​and the plurality of third sampling values ​​that matches the first sampling value.

6. The read margin control circuit according to claim 1, further comprising: a first delay unit configured to delay a data input / output signal; as well as A second delay unit is configured to delay the data strobe signal, The delay circuit is further configured to receive a first output of the first delay unit, and The sampler is further configured to receive the second output of the second delay unit.

7. The read margin control circuit according to claim 6, further comprising: The code generator is configured to generate a code for adjusting a first delay amount of the first delay unit or a second delay amount of the second delay unit based on the data valid window determined by the determiner.

8. The read margin control circuit according to claim 7, wherein: The code generator is further configured to generate a code based on at least one value of the plurality of second sample values ​​that does not match the first sample value so that the data input / output signal is more delayed relative to the data strobe signal.

9. The read margin control circuit according to claim 7, wherein: The code generator is further configured to generate a code based on at least one value of the plurality of third sampled values ​​that does not match the first sampled value so that the data strobe signal is more delayed relative to the data input / output signal.

10. A memory controller comprising: a delay circuit configured to receive a data input / output signal from a memory device, and to generate a first delayed signal, a plurality of second delayed signals having a delay less than the first delayed signal, and a plurality of third delayed signals having a delay greater than the first delayed signal by delaying the data input / output signal; a sampler configured to sample the first delayed signal, the plurality of second delayed signals, and the plurality of third delayed signals at a rising edge of a data strobe signal sent from a memory device, and to sample the first delayed signal, the plurality of second delayed signals, and the plurality of third delayed signals at a falling edge of the data strobe signal; as well as A determiner is configured to determine a data valid window of a data input / output signal based on a first up-sampled value and a first down-sampled value of a first delayed signal sampled at a rising edge and a falling edge, respectively.

11. The memory controller according to claim 10, wherein: The delay circuit includes a plurality of delay stages configured to delay a data input / output signal, and The first delayed signal, the plurality of second delayed signals and the plurality of third delayed signals are outputted from the plurality of delay stages respectively.

12. The memory controller according to claim 11, wherein: The determiner is also configured to compare the first up-sampling value with each of the multiple second up-sampling values ​​and the multiple third up-sampling values ​​of the multiple second delayed signals and the multiple third delayed signals sampled at the rising edge, and to compare the first down-sampling value with each of the multiple second down-sampling values ​​and the multiple third down-sampling values ​​of the multiple second delayed signals and the multiple third delayed signals sampled at the falling edge.

13. The memory controller according to claim 12, further comprising: a first delay unit configured to delay a data input / output signal; as well as A second delay unit is configured to delay the data strobe signal, The delay circuit is configured to receive a first output of the first delay unit, and The sampler is configured to receive the second output of the second delay unit.

14. The memory controller according to claim 13, further comprising: A code generator is configured to generate a code for adjusting a first delay amount of the first delay unit or a second delay amount of the second delay unit based on at least one first value among the plurality of second up-sampled values ​​and the plurality of third up-sampled values ​​that does not match the first up-sampled value, or at least one second value among the plurality of second down-sampled values ​​and the plurality of third down-sampled values ​​that does not match the first down-sampled value.

15. The memory controller according to claim 14, wherein: A unit of the first delay amount of the first delay unit or the second delay amount of the second delay unit adjusted according to the code corresponds to a propagation delay of each of the plurality of delay stages.

16. An electronic device comprising: a memory device configured to generate a data input / output signal and a data strobe signal synchronized with the data input / output signal; as well as A memory controller is configured to generate a plurality of delayed signals having different phases by delaying a data input / output signal, generate a plurality of sampled values ​​by sampling the delayed signals of the plurality of data input / output signals based on a data strobe signal, compare a first sampled value among the plurality of sampled values ​​with a plurality of second sampled values ​​and a plurality of third sampled values ​​among the plurality of sampled values ​​except the first sampled value, and determine a data valid window of the data input / output signal based on a result of the comparison.

17. The electronic device according to claim 16, wherein: generating a first sample value by sampling a first delayed signal among a plurality of delayed signals, wherein a plurality of second sampled values ​​are generated by sampling a plurality of second delayed signals among the plurality of delayed signals, wherein a plurality of third sampled values ​​are generated by sampling a plurality of third delayed signals among the plurality of delayed signals, and The first delayed signal is delayed more than the plurality of second delayed signals and is delayed less than the plurality of third delayed signals.

18. The electronic device according to claim 16, wherein: The memory controller is further configured to adjust a first delay of the data input / output signal or a second delay of the data strobe signal based on the determined data valid window.

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