ORing FET circuits and power supplies and multi-output power supplies

Abstract

The present application is applicable to the field of circuit technology, and provides an ORing FET circuit, power supply, and multi-channel output power supply, wherein the ORing FET circuit includes: a current sampling resistor, an ORing controller, and a first field effect tube; the positive end of the current sampling resistor is connected to the input pin of the ORing controller; the output pin of the ORing controller is connected to the drain of the first field effect tube. Since the input pin and the output pin of the ORing controller collect the voltage in series with the current sampling resistor and the first field effect tube, it is equivalent to increasing the internal resistance of the field effect tube in disguised form, so as to avoid the first field effect tube from being unable to start normally or alternating switching when lightly loaded due to too low a driving voltage.

Description

Technical Field

[0001] The present application belongs to the field of circuit technology, and in particular relates to an ORing FET circuit and power supply and a multi-channel output power supply. Background Art

[0002] Many modern devices and systems require power redundancy design, that is, multiple power supplies are connected in parallel to provide power supply current to the system at the same time. When one power supply fails, the other power supply works normally, and the system can also operate normally without crashing. In the process of multiple power supplies connected in parallel, there is a special situation that can also cause the system to crash, that is, a short circuit occurs in the output of a power supply. Since multiple power supplies are connected in parallel, their output sides are also connected in parallel. If one of the power supplies is short-circuited, the entire power supply is short-circuited, and the system still cannot work normally, which loses the meaning of redundant backup. Instead, the system reliability is reduced due to the increase in the number of parallel power supplies. To address this problem, the ORing FET circuit came into being.

[0003] Ordinary ORing FET circuits can work normally under full load, but under light load and low current conditions, they may fail to turn on properly or switch alternately, thus affecting the reliability and stability of the power supply. Summary of the invention

[0004] In view of this, the embodiments of the present application provide an ORing FET circuit and power supply and a multi-output power supply to solve the problem of poor turn-on or alternating switching of the current ORing FET circuit under light load and low current conditions.

[0005] According to a first aspect, an embodiment of the present application provides an ORing FET circuit, comprising: a current sampling resistor, an ORing controller, and a first field effect transistor; the positive end of the current sampling resistor is connected to the input pin of the ORing controller; the positive end of the current sampling resistor is also used to collect a high-voltage output signal of a power supply controlled by the ORing FET circuit; the reverse end of the current sampling resistor is connected to the source of the first field effect transistor; the output pin of the ORing controller is connected to the drain of the first field effect transistor.

[0006] In combination with the first aspect, in some embodiments of the present application, a field effect tube group is used to replace the first field effect tube; the field effect tube group includes at least two second field effect tubes connected in parallel, the drains of the at least two second field effect tubes connected in parallel are all connected and constitute the drain of the field effect tube group, and the sources of the at least two second field effect tubes connected in parallel are all connected and constitute the source of the field effect tube group; accordingly, the reverse end of the current sampling resistor is connected to the source of the field effect tube group, and the output pin of the ORing controller is connected to the drain of the field effect tube group.

[0007] In combination with the first aspect, in some embodiments of the present application, the ORing controller is a LM5050-1 type ORing controller.

[0008] According to a second aspect, an embodiment of the present application provides a power supply, which includes the ORing FET circuit as described in the first aspect or any implementation of the first aspect.

[0009] In combination with the second aspect, in some embodiments of the present application, the power supply further includes a power supply body, and a high-voltage output end of the power supply body is connected to the positive end of the current sampling resistor in the ORing FET circuit.

[0010] According to a third aspect, an embodiment of the present application provides a multi-output power supply, wherein the multi-output power supply includes at least two ORing FET circuits as described in the first aspect or any implementation of the first aspect.

[0011] In combination with the third aspect, in some embodiments of the present application, the multi-output power supply further includes at least two power supply bodies, and the number of the power supply bodies in the multi-output power supply is consistent with the number of the ORing FET circuits.

[0012] In combination with the third aspect, in some embodiments of the present application, the high voltage output end of any power supply body in the multi-output power supply is connected to the positive end of the current sampling resistor in the corresponding ORing FET circuit.

[0013] According to a fourth aspect, an embodiment of the present application provides an electrical device, characterized in that the electrical device includes a power supply as described in the second aspect or any embodiment of the second aspect.

[0014] According to the fifth aspect, an embodiment of the present application provides an electrical device, characterized in that the electrical device includes a multi-output power supply as described in the third aspect or any implementation manner of the third aspect.

[0015] The ORing FET circuit provided in the embodiment of the present application moves the current sampling resistor to the output high voltage side of the power supply, so that the ground wire of the power supply output can be directly connected together, avoiding the cross-intermodulation crosstalk caused by the existing ORing FET circuit setting the current sampling resistor on the ground wire. In addition, the input pin (IN) and the output pin (OUT) of the ORing controller collect the voltage of the current sampling resistor and the field effect tube in series, which is equivalent to increasing the internal resistance of the field effect tube in disguised form, so that the driving voltage output by the ORing controller for driving the field effect tube is increased when the load is light, thereby avoiding the field effect tube from being unable to start normally or alternating switches due to the low driving voltage when the load is light; it can also avoid the field effect tube from entering the amplification area due to the low driving voltage when the load is light, thereby increasing the loss of the field effect tube and causing the problem of overheating damage at high temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 It is an application diagram of the existing ORing FET circuit;

[0018] Figure 2 This is the circuit schematic diagram of the existing ORing controller;

[0019] Figure 3 It is the circuit schematic diagram of the existing ORing FET circuit;

[0020] Figure 4 is the on-state voltage curve of the MOSFET;

[0021] Figure 5 is a circuit schematic diagram of an ORing FET circuit provided in an embodiment of the present application;

[0022] Figure 6 It is the curve of MOSFET body resistance changing with temperature;

[0023] Figure 7 is a circuit schematic diagram of a power supply provided in an embodiment of the present application;

[0024] Figure 8 is a circuit schematic diagram of a multi-channel output power supply provided in an embodiment of the present application;

[0025] Fig. 9is a structural example diagram of an electrical device provided in an embodiment of the present application;

[0026] Fig.10 This is a structural example diagram of another electrical device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0028] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0029] Figure 1 This is the application diagram of the existing ORing FET circuit. Figure 1 As shown, through the cooperation between the control chip LM5050 and the corresponding MOSFET, the corresponding MOSFET is disconnected after a short circuit fault occurs in the power supply PS1 or the power supply PS2, so as to ensure the normal operation of the back-end electrical equipment. The basis for the control chip to turn on or off the MOSFET is the voltage difference between the drain and the source of the switch tube. Under full load, the MOSFET can work normally; but under light load or low current, due to the very small voltage difference between the drain and the source, it will cause the switch tube to open poorly or alternately switch, thereby further causing output oscillation problems. The ORing FET circuit proposed in this application focuses on solving the above problems under light load and low current conditions.

[0030] Figure 2 This is the circuit schematic of the existing ORing controller. The ORing controller controls the internal comparator to output high and low levels by checking the voltages of the IN and OUT pins, and then controls the pump-up circuit to send high and low levels at the GATE pin. During normal operation, the load current first flows through the body diode. When the voltage difference exceeds Vsd, the 30uA current source starts to charge the GATE pin. When the power output is short-circuited, the OUT pin voltage of the ORing controller is much higher than the IN pin voltage, the comparator output turns to a high level, the internal 2A switch tube is turned on, the GATE pin output is low, and the external ORing FET circuit is turned off, isolating the short-circuited power supply from the system to ensure the normal operation of the back-end electrical equipment. The actual application circuit is as follows Figure 3 shown.

[0031] like Figure 3As shown in the figure, in traditional multi-channel output power supplies, the current sampling resistor is placed on the ground line. This is convenient for the design of the current differential amplifier circuit in the subsequent stage. However, in the dynamic change of the load, the ripple noise generated by the first load is easily connected in series to the second output through the ground line, causing the ripple of the second output to increase; similarly, the second output will also affect the first output, resulting in the problem of cross-influence in multi-channel output power supplies. In addition, there is another problem. Under light load, the current flowing through the ORing FET is very small, and the voltage drop between the drain and source of the MOSFET is also reduced, resulting in the drive voltage V gs Very low; in actual testing, it will be lower than 1.5V, which is not conducive to the normal operation of MOSFET. Taking Infineon's MOSFET as an example, the normal turn-on voltage of this MOSFET is generally around 2V. If it is too low, it is easy for the tube to enter the amplification area, the loss will increase, and there is a risk of overheating loss at high temperature. Figure 4 The driving voltage and drain current curves of the MOSFET are shown. At room temperature, 2.2V is required to achieve normal turn-on, and it becomes higher at low temperatures.

[0032] In order to ensure the normal operation of MOSFET, efficiency is generally sacrificed to select devices with large body resistance. For example, change 2mR to 5mR; or, reduce the number of MOSFETs in parallel, for example, reduce the number of MOSFETs in parallel from six to three. This can effectively ensure the normal operation of MOSFET under light load, but it will introduce other heating problems, especially when working at high temperature and full load. Taking the output of 12V50A as an example, four 2mR switches are connected in parallel in the circuit. Under full load, the loss W = I*I*R = 50*50*(2 / 4) = 1.25W, and the voltage drop V = I*R = 25mV. In order to ensure normal opening under light load, in a specific example, the number of MOSFETs in parallel can be reduced from four to two, so that the loss W = 2.5W and the voltage drop V = 50mV. Doing so not only causes a reduction in efficiency, but also causes serious heat generation in the switch tube, requiring emphasis on heat dissipation design; at the same time, the MOSFET alone accounts for 50mV of the 120mV load regulation rate, and when coupled with connectors, PCB traces, output filter circuits, etc., it is easy to exceed the 120mV voltage drop range.

[0033] In response to the above problems, the embodiments of the present application provide an improved ORing FET circuit, which can ensure the normal operation of the MOSFET under light load without increasing additional losses and meet the requirements of load regulation rate. Figure 5 is a circuit schematic diagram of an ORing FET circuit provided in an embodiment of the present application. The ORing FET circuit 100 may include a current sampling resistor R6, an ORing controller IC2, and a first field effect transistor Q2. Figure 5In the ORing FET circuit 100 shown, the positive end of the current sampling resistor R6 is connected to the first voltage collection end of the ORing controller IC2; the positive end of the current sampling resistor R6 is also used to collect the high-voltage output signal of the power supply M2 controlled by the ORing FET circuit 100; the reverse end of the current sampling resistor R6 is connected to the source of the first field effect transistor Q2; the second voltage collection end of the ORing controller IC2 is connected to the drain of the first field effect transistor Q2. Specifically, the ORing controller IC2 can be a LM5050 chip, and its first voltage collection end is the input pin (port IN) of the LM5050 chip, and its second voltage collection end is the output pin (port OUT) of the LM5050 chip.

[0034] contrast Figure 3 and Figure 5 There are two main differences between the two ORing FET circuits shown. The first is that the current sampling resistor is moved from the ground line to the output high voltage side; the second is that the 4-pin voltage sampling IN of the chip LM5050 is moved from the S pole of the switch tube to the positive pole of the sampling resistor. Moving the current sampling resistor and directly connecting the ground of each output together can effectively reduce the crosstalk caused by cross-modulation, making the ground line very clean and improving the anti-interference and reliability of the entire power supply system. Changing the voltage sampling position of the 4-pin of the chip LM5050 is equivalent to increasing the internal resistance of the switch tube in disguise, achieving the same electrical effect as reducing the number of parallel tubes and replacing devices with large body resistance. Since the sampling resistor is external and the resistance of the sampling resistor hardly changes with temperature, good parameter consistency can be achieved in high and low temperature experiments. Compared with the internal body resistance of the MOSFET, the resistance value also fluctuates greatly with temperature changes, which is not conducive to the adjustment of the parameters of the whole machine. The change curve is shown. Figure 6 .

[0035] In a specific real-time mode, a field effect transistor group can also be used instead of Figure 5 Specifically, the field effect tube group includes at least two second field effect tubes connected in parallel, the drains of the at least two second field effect tubes connected in parallel are connected to form the drain of the field effect tube group, and the sources of the at least two second field effect tubes connected in parallel are connected to form the source of the field effect tube group.

[0036] Correspondingly, the reverse end of the current sampling resistor R6 is connected to the source of the field effect tube group, and the second voltage collection end of the ORing controller IC2 is connected to the drain of the field effect tube group.

[0037] In a specific implementation, the ORing controller may be a LM5050-1 type ORing controller.

[0038] Figure 7 is a circuit diagram of a power supply provided in an embodiment of the present application. Figure 7 As shown, the power supply 200 includes a power supply body 101 and Figure 5 The ORing FET circuit 100 shown in FIG. 1 is a circuit diagram of an embodiment of the present invention. Specifically, the high voltage output terminal of the power source body 101 is connected to the positive terminal of the current sampling resistor R6 in the ORing FET circuit 100 .

[0039] Figure 8 is a circuit diagram of a multi-channel output power supply provided in an embodiment of the present application. Figure 8 As shown, the multi-output power supply 300 includes at least two power supply bodies 101 and Figure 5 The ORing FET circuit 100 shown. Specifically, in the multi-output power supply 300, the number of the ORing FET circuits 100 is the same as the number of the power supply bodies 101 therein. The high voltage output end of any power supply body 101 in the multi-output power supply 300 is connected to the positive end of the current sampling resistor R6 in the corresponding ORing FET circuit 100. Figure 8 In the embodiment, a multi-channel output power supply 300 including two power supply bodies 101 and two ORing FET circuits 100 is taken as an example to illustrate the composition of the multi-channel output power supply 300. In practical applications, users can select the number of power supply bodies 101 and ORing FET circuits 100 in a specific multi-channel output power supply 300 as needed, and the embodiment of the present application does not limit this.

[0040] Fig. 9 is a structural example diagram of an electrical device provided in an embodiment of the present application. Fig. 9 As shown, the electrical equipment 400 includes Figure 7 A power supply 200 is shown.

[0041] Fig.10 FIG. 1 is another structural example diagram of an electrical device provided in an embodiment of the present application. Fig.10 As shown, the electrical equipment 500 includes Figure 8 A multiple output power supply 300 is shown.

[0042] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An ORing FET circuit, characterized in that: include: Current sampling resistor, ORing controller, and first field effect transistor; The positive end of the current sampling resistor is connected to the input pin of the ORing controller; the positive end of the current sampling resistor is also used to collect the high-voltage output signal of the power supply controlled by the ORing FET circuit; The reverse end of the current sampling resistor is connected to the source of the first field effect transistor; The output pin of the ORing controller is connected to the drain of the first field effect transistor; wherein the ground lines of each output of the ORing FET circuit are connected together, and the current sampling resistor is not provided on the ground line.

2. The ORing FET circuit according to claim 1, wherein: Using a field effect tube group to replace the first field effect tube; The field effect tube group includes at least two second field effect tubes connected in parallel, the drains of the at least two second field effect tubes connected in parallel are connected to form the drain of the field effect tube group, and the sources of the at least two second field effect tubes connected in parallel are connected to form the source of the field effect tube group; Correspondingly, the reverse end of the current sampling resistor is connected to the source of the field effect tube group, and the output pin of the ORing controller is connected to the drain of the field effect tube group.

3. The ORing FET circuit according to claim 1 or 2, characterized in that: The ORing controller is a LM5050-1 ORing controller.

4. A power supply, characterized in that: The power supply comprises an ORing FET circuit as claimed in any one of claims 1 to 3.

5. The power supply according to claim 4, characterized in that The power supply further comprises a power supply body, and a high voltage output end of the power supply body is connected to a positive end of the current sampling resistor in the ORing FET circuit.

6. A multi-output power supply, characterized in that: The multi-output power supply comprises at least two ORing FET circuits as claimed in any one of claims 1 to 3.

7. The multi-output power supply according to claim 6, characterized in that: The multi-channel output power supply further includes at least two power supply bodies, and the number of the power supply bodies in the multi-channel output power supply is consistent with the number of the ORing FET circuits.

8. The multi-output power supply according to claim 7, characterized in that: The high-voltage output end of any power source body in the multi-output power source is connected to the positive end of the current sampling resistor in the corresponding ORing FET circuit.

9. An electrical device, characterized in that: The electrical equipment comprises the power supply as claimed in claim 4 or 5.

10. An electrical device, characterized in that: The electrical equipment comprises a multi-output power supply as claimed in any one of claims 6 to 8.

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