Integrated circuit and method of manufacturing integrated circuit

Abstract

Embodiments of the present disclosure relate to the co-integration of tensile silicon and compressive silicon germanium. Disclosed herein is an integrated circuit in which the strain characteristics of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressively strained SiGe on a silicon substrate, and the nFETs include tensile strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type fin FETs and p-type fin FETs are separated by multiple electrically insulating regions formed by a damascene process. During the formation of these insulating regions, the SiGe substrate supporting the n-type devices is allowed to relax elastically, thereby limiting the formation of defects in the lattice of the SiGe substrate.

Description

[0001] This application is a divisional application of the Chinese invention patent application filed on November 25, 2015, with application number 201510834395.X and invention name “Integrated Circuit and Method for Manufacturing Integrated Circuit”. Technical Field

[0002] The present disclosure relates generally to techniques for fabricating high performance fin field effect transistors (FinFETs), and in particular, to techniques for reducing defects in strained silicon transistors. Background Art

[0003] Advanced integrated circuits often feature strained channel transistors, silicon-on-insulator (SOI) substrates, fin-FET structures, or a combination thereof, in order to continue scaling transistor gate lengths below 20 nm. Such techniques allow transistor channel lengths to be made smaller while minimizing deleterious consequences such as current leakage and other short channel effects.

[0004] FinFETs are electronic switching devices characterized by a conductive channel in the form of a semiconductor fin extending outward from the substrate surface. In such devices, the gate that controls the current flow in the fin wraps around three sides of the fin to affect the current flow from three surfaces instead of one surface. The improved control achieved with the FinFET design results in faster switching performance in the "on" state and less current leakage in the "off" state compared to conventional planar devices. FinFETs are described in further detail in U.S. Patent 8,759,874 and U.S. Patent Application Publication US2014 / 0175554.

[0005] Strained silicon transistors have been developed to increase the mobility of carriers (i.e., electrons or holes) through the semiconductor lattice. Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing the carrier mobility in the channel, thereby making the device a more responsive switch. Introducing compressive strain into a pFET transistor tends to increase the hole mobility in the channel, resulting in a faster switching response to changes in the voltage applied to the transistor gate. Similarly, introducing tensile strain into an nFET tends to increase the electron mobility in the channel, also resulting in a faster switching response.

[0006] For both planar devices and fin FETs, there are many ways to introduce tensile strain or compressive strain into transistors. Typically, such techniques require multiple epitaxial layers of one or more materials to be incorporated into the device, and these materials have a crystal lattice size or geometry that is slightly different from the silicon substrate. The strain and mobility effects in the epitaxially grown crystal are adjusted by controlling the elemental composition of the crystal. Such epitaxial layers can be incorporated into the source and gate regions, incorporated into the transistor gate used to modulate the current flow in the channel, or incorporated into the channel itself as part of the fin. For example, one way to introduce strain is to replace the bulk silicon from the source and drain regions or from the channel with a silicon compound such as silicon germanium (SiGe). Because Si-Ge bonding is longer than Si-Si bonding, there is more open space in the SiGe lattice. There is a tensile lattice of germanium atoms with longer bonding, resulting in internal strain. Electrons can move more freely through a lattice containing long and narrow Si-Ge bonds and Ge-Ge bonds than through a lattice containing shorter Si-Si bonds. In a controlled process of epitaxial crystal growth, in which a new SiGe crystal layer grows from the surface of a bulk silicon crystal, replacement of silicon atoms with SiGe atoms can be accomplished while maintaining the same crystal structure of the underlying bulk silicon crystal. It has been determined that epitaxial SiGe films containing high concentrations of germanium (e.g., in the range of 25%-40%) provide enhanced electron mobility compared to lower concentration SiGe films. Therefore, increasing the percentage concentration of germanium atoms in the fins of a fin FET is generally advantageous from a device performance perspective.

[0007] Alternatively, strain can be induced in the fin below the slave device by using various types of silicon-on-insulator (SOI) substrates. The SOI substrate is characterized by a buried insulator, typically a buried oxide layer (BOX) below the active area. SOI fin FET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. Patent Application No. 14 / 231,466 entitled "SOI FinFET Transistor with Strained Channel", U.S. Patent Application No. 14 / 588,116 entitled "Silicon Germanium-on-insulator FinFET", and U.S. Patent Application No. 14 / 588,221 entitled "Defect-Free Strain-Relaxed Buffer Layer".

[0008] Although strained silicon lattices are beneficial, creating strain by combining germanium atoms using existing methods tends to damage the crystal lattice. As a result, the lattice structure of the germanium-rich film tends to be mechanically unstable, especially if it contains a high number of structural defects, such as faults or dislocations. In addition, the mechanically unstable SiGe fins can be structurally limited with respect to their aspect ratio or height-to-width ratio. This limitation is undesirable because one advantage of the FinFET is that the vertically structured fins have a small footprint. Summary of the invention

[0009] Dislocation defects that cause mechanical instability in fin FETs can be avoided by creating a relaxed germanium-rich layer as an alternative to the strained film. The self-aligned SiGe fin FET device disclosed herein is characterized by a strain-relaxed substrate with a high germanium concentration. An integrated circuit is disclosed in which the strain characteristics of the pFET and nFET are independently adjustable. The pFET includes compressively strained SiGe on a silicon substrate, while the nFET includes tensile strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type fin FETs and p-type fin FETs are separated by insulating regions formed using a damascene process. During the formation of the insulating region, the SiGe substrate supporting the n-type device is allowed to relax elastically, thereby limiting the formation of defects in the lattice of the SiGe substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, identical reference numerals identify similar elements or operations. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale.

[0011] Figure 1 is a flow chart illustrating steps in a first method of fabricating an integrated circuit including a compressively strained SiGe pFET and a tensile silicon nFET according to one embodiment as described herein.

[0012] Figure 2A is a top plan view of a SiGe active layer on a silicon substrate according to one embodiment as described herein.

[0013] Figure 2B is corresponding to Figure 2A Cross-sectional view of .

[0014] Figure 3A is a top plan view of a large trench formed in an nFET region of a silicon substrate according to one embodiment as described herein.

[0015] Figure 3B yes Figure 3A Cross-sectional view of the large trench shown in .

[0016] Figure 4Ais a top plan view of an active layer of silicon indicating the orientation of fins formed below an oxide surface according to one embodiment as described herein.

[0017] Figure 4B According to one embodiment as described herein Figure 4A 4B-4B is a cross-sectional view of the active layer of silicon shown in FIG.

[0018] Figure 4C is a cross-sectional view of an active layer of silicon along a cut line 4C-4C across a fin according to one embodiment as described herein.

[0019] Figure 5A is a top plan view of an active layer of silicon after forming isolation trenches between nFET and pFET regions according to one embodiment as described herein.

[0020] Figure 5B , Figure 5C is corresponding to Figure 5A Cross-sectional view of .

[0021] Fig. 6A is a top plan view of an active layer of silicon after filling isolation trenches and inter-fin regions with oxide according to one embodiment as described herein.

[0022] Figure 6B , Figure 6C is corresponding to Fig. 6A Cross-sectional view of .

[0023] Fig. 7A is a top plan view of an nFET and a pFET after forming a polysilicon gate according to one embodiment as described herein.

[0024] Figure 7B , Figure 7C is corresponding to Fig. 7A Cross-sectional view of .

[0025] Figure 8 is a flow chart illustrating steps in a second method of fabricating an integrated circuit including a compressively strained SiGe pFET and a tensile silicon nFET according to an alternative embodiment as described herein.

[0026] Fig. 9 It shows that according to Figure 8 A cross-sectional view of the isolation region between the nFET device and the pFET device before fin formation in the second manufacturing method shown in FIG.

[0027] Fig.10is a cross-sectional view showing an isolation region between an nFET device and a pFET device that is shallower than an intervening strain-relaxed SiGe substrate according to one embodiment as described herein. DETAILED DESCRIPTION

[0028] In the following description, certain specific details are set forth in order to provide a comprehensive understanding of the various aspects of the disclosed subject matter. However, the disclosed subject matter can be implemented without these specific details. In some instances, known structures and semiconductor processing methods have not yet been specifically described in order to avoid obscuring the description of other aspects of the disclosure.

[0029] Unless the context requires otherwise, throughout the specification and the appended claims, the word "comprise" and its various variations (such as, "comprises" and "comprising") are to be interpreted in an open and inclusive sense, that is, as "including, but not limited to."

[0030] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0031] References to integrated circuits throughout this specification are generally intended to include integrated circuit components built on a semiconductor substrate, whether or not the components are coupled together into a circuit or are capable of being interconnected. Throughout this specification, the term "layer" is used in the broadest sense to include films, caps, etc., and a layer may be composed of multiple sub-layers.

[0032] References to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals or similar materials throughout the specification include processes such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, etc. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and references to certain deposition techniques should not be limited to those described. For example, in some circumstances, PVD can be used alternatively to complete the description of the referenced CVD, or electroless plating can be used alternatively to achieve the description of the specified electroplating. In addition, references to conventional techniques for thin film formation can include in-situ growth films. For example, in some embodiments, controlling oxide growth to a desired thickness can be achieved by exposing the silicon surface to oxygen or moisture in a heated chamber.

[0033] References throughout this specification to conventional photolithography techniques known in the semiconductor fabrication art for patterning various thin films include a spin-on-exposure-development process sequence, typically followed by an etching process. Alternatively or additionally, photoresists may also be used to pattern hard masks (e.g., silicon nitride hard masks), which in turn may be used to pattern underlying films.

[0034] Throughout this specification, quotations of conventional etching techniques for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials known in the semiconductor manufacturing field include such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical planarization (CMP) etc. Specific embodiments are described herein with reference to the examples of such processes. However, this disclosure and quotations to some deposition techniques should not be limited to described these. In some instances, two such techniques can be interchangeable. For example, stripping the photoresist may require dipping the sample in a wet chemical bath or alternatively directly spraying a wet chemical agent on the sample.

[0035] Certain embodiments are described herein with reference to co-integrated tensile nFETs and compressive pFETs that have been produced. However, the present disclosure and references to certain materials, dimensions, and details and order of processing steps are exemplary and should not be limited to those shown.

[0036] Now turning to the attached figure, Figure 12 shows steps in a method 200 of fabricating a compressively strained p-type fin FET or pFET co-integrated with a tensilely strained n-type fin FET or nFET according to one embodiment. Steps 202 to 219 in method 200 are FIG. 2A to FIG. 7C 1 and described below. In each figure, A is a top plan view of a co-integrated finFET at this step in the fabrication process, indicating the cut line of the cross-sectional view; B is a cross-sectional view along a cut line parallel to the fin of the finFET; and C is a cross-sectional view along a cut line transverse to the fin. An exemplary nFET and two exemplary pFETs are shown in each cross-sectional view.

[0037] At 202, a blanket epitaxial SiGe film with compressive strain is grown on a silicon substrate 220 to form a compressive SiGe active layer 222. The compressive SiGe active layer 222 (cSiGe) is desirably in the range of about 10 nm thick to 100 nm thick, with a target thickness of 40 nm, and has a Ge concentration in the range of about 15% to 50%, with a target concentration of 25% germanium. The compressive SiGe active layer 222 is a fully compressively strained film that will include at least one source and one drain of a p-type fin FET and a fin channel coupling the source to the drain.

[0038] At 204, according to Figure 2A , Figure 2B , Figure 3A and Figure 3B In one embodiment shown in FIG. 1 , a compressive SiGe active layer 222 and a silicon substrate 220 are patterned together to open an nFET region and cover a pFET region. First, a blanket hard mask 224 is deposited on the compressive SiGe active layer 222 and patterned in the usual manner using a photoresist 226 and (optionally) an optical planarization layer (OPL). The hard mask 224 and subsequent hard masks described below can be made of SiN, SiO2, or a SiO2 / SiN bilayer. The hard mask 224 can be deposited according to any conventional method (e.g., plasma enhanced CVD (PE-CVD), low pressure CVD (LP-CVD), rapid thermal CD (RT-CVD), atomic layer deposition (ALD), etc.). Then, the SiN hard mask 224 is used to etch an opening 228 in the underlying epitaxial SiGe layer, which further extends into the silicon substrate 220 to form a damascene trench having a width "a" and a depth "d". The width may be anywhere in the range of 10 nm to 100 um. The depth is desirably in the range of approximately 50 nm to 400 nm. For example, dimensions a and d may depend on whether a logic or SRAM device is being fabricated.

[0039] At 206, according to Figure 4B , Figure 4C In one embodiment shown in FIG. 2 , a thick SiGe layer 230 is formed to fill the opening 228. Filling the opening 228 completes the damascene process of forming a strained SiGe layer in the silicon substrate 220 below the active layer where the nFET will be formed later. The thick SiGe layer 230 effectively serves as a substrate that replaces the silicon substrate 220. In one embodiment, the thick SiGe layer 230 is formed by selective epitaxial growth from the silicon substrate 220 below. Only in the nFET region, the selective epitaxial process proceeds from the bottom to the top and stops at the surface of the silicon substrate 220. During the selective epitaxial process, the hard mask 224 remains in place. For example, methyl chloride-based chemistry or silane-based chemistry can be used to suppress the growth from the sidewalls of the silicon substrate 220, thereby achieving directional deposition. Such techniques for directional epitaxy are known to those skilled in the art of epitaxial crystal growth. The thickness of the thick SiGe layer 230 can be maximized without forming crystal defects by adjusting the germanium concentration. Further optimization to maximize the mechanical stress in the fin channel may require forming a thick SiGe layer 230 with a vertical germanium concentration gradient, which can be achieved by varying the amount of germanium during the directional deposition step. Alternatively, other techniques for directional epitaxy may also be used to grow the thick SiGe layer 230. The resulting embedded thick SiGe layer 230 in the nFET region has a compressive strain.

[0040] At 208, according to Figure 4B and Figure 4C In one embodiment shown in FIG. 2 , an epitaxial silicon active layer 232 is formed. In one embodiment, the epitaxial silicon active layer 232 is also directionally grown upward from the surface of the thick SiGe layer 230, while suppressing the growth from the sidewalls of the SiGe active layer 222. The epitaxial silicon active layer 232 has a thickness target that is approximately equal to the thickness target of the surrounding compressive SiGe layer 222. The epitaxial silicon active layer 232 is thereby formed in the active region, which will include the source and drain of the n-type fin FET and the fin channel that couples the source to the drain. The epitaxial silicon active layer 232 can be grown as an added step in the same process as the thick SiGe layer 230, wherein the flow of the germanium gas is disconnected at the transition between silicon germanium and silicon. A timed epitaxial process can be used, wherein the time for each step is based on the desired mask opening a and the known growth rate of each of the epitaxial SiGe and epitaxial silicon. The source and drain regions of the epitaxial silicon active layer 232 can be in-situ doped during epitaxial growth. The epitaxial silicon active layer 232 thus formed is a relaxed layer having a crystal structure similar to that of the substrate 220 .

[0041] At 210 , after the directional epitaxy step, the hard mask 224 is removed, for example, by any suitable method.

[0042] At 212, according to Figure 4A and Figure 4C In one embodiment shown in FIG. 2 , the fin 240 is formed in the compressive SiGe active layer 222 and in the tensile Si active layer 232 . Figure 4A A top view of the nFET and pFET is shown after forming the fins 240 and inter-fin oxide 244. Although the surface is covered with pad oxide 242, the underlying fins 240 are indicated by dashed lines, as are the epitaxial silicon active layer 232 that delineates the boundaries of the thick SiGe layer 230.

[0043] In a fin FET device, the fin embodies a conductive channel that couples the source region and the drain region to each other. Figure 4C As shown in , a first pad oxide 242 is deposited, and on top of the pad oxide 242, a pad nitride (SiN) layer is used as a fin hard mask (not shown) to define the fin 240 by conventional photolithography methods. Alternatively, the fin 240 can be defined using a sidewall image transfer (SIT) method, which is capable of producing very narrow features, as known in the art. In one embodiment, the fin 240 has a fin width in the range of about 5nm to 20nm. In the pFET region, the fin 240 extends vertically into the silicon substrate 220 below the compressive SiGe active layer 222. In the nFET region, the fin 240 extends vertically through the tensile silicon active layer 232 and into the thick SiGe layer 230. After the fins are formed, the pad oxide 242 and the fin hard mask, each with a fin pattern, are removed. In preparation for the next process step, the space between the fins 240 is filled with an inter-fin oxide 244. The inter-fin oxide 244 is then planarized to re-establish the pad oxide 242 : slightly above the fin 240 and the inter-fin oxide 244 .

[0044] At 214, according to FIG. 5A to FIG. 5C In one embodiment shown in FIG. 1 , parallel cuts 252 substantially parallel to the fin 240 and vertical cuts 254 transverse to the fin 240 are made between the pFET active area and the nFET active area. First, a SiN cut hard mask 250 is formed on top of the pad oxide 242. Then, the parallel cuts 252 are patterned in the SiN cut hard mask 250, as shown in FIG. Figure 5A , Figure 5C Then, by etching Figure 5A The pattern of parallel cuts 252 shown in FIG. 2 is transferred to substrate 220 such that parallel cuts 252 extend down between thick SiGe layer 230 and silicon substrate 220 to a cut depth 245. Figure 5B , Figure 5C, the notch depth 245 is shown as being slightly less than the SiGe depth d. However, in general, the notch depth 245 can be less than, equal to, or greater than the depth d of the thick SiGe layer 230, although it can be advantageous for the notch depth 245 to be greater than the depth d of the thick SiGe layer 230.

[0045] Next, in a subsequent photolithography step, vertical cuts 254 are patterned in the cut hard mask 250, such as Figure 5A , Figure 5B Then, by etching Figure 5A The pattern of vertical cuts 254 shown in FIG. 2 is transferred to substrate 220 such that vertical cuts 254 extend downward between thick SiGe layer 230 and silicon substrate 220 to approximately the same cut depth 245 as parallel cuts 252, as shown in FIG. Figure 5B Each of the cuts 252, 254 thus creates three free surfaces 253 adjacent to the lower portion of the thick SiGe layer 230. The depth of the vertical cuts 254 can be less than, equal to, or greater than the depth of the parallel cuts 252.

[0046] Due to the parallel cuts 252, the thick SiGe layer 230 partially or completely elastically relaxes (rSiGe) in the horizontal direction parallel to the active layers 222 and 232. Such elastic relaxation transforms the thick SiGe layer 230 from a compressive strain layer into a strain-relaxed SiGe region 258 embedded in the silicon substrate 220. The elastic relaxation occurs without defects, which would otherwise occur in conventional processes that rely on plastic relaxation. Similarly, due to the vertical cuts 254, the strain-relaxed SiGe region 258 undergoes biaxial elastic relaxation, in which the SiGe completely elastically relaxes in all directions, also without defects. At the same time that the cuts 252, 254 are made, the overlying epitaxial silicon active layer 232 is separated from the compressive SiGe active layer 222 and transformed into a biaxial tensile strained film. The resulting tensile silicon active layer 243 provides excellent electron mobility within the nFET fin. At the same time, the compressive SiGe active layer 222 on either side of the tensile silicon active layer 243 remains fully compressively strained to provide excellent hole mobility within the pFET fin. In this way, the compressive strain in the pFET and the tensile strain in the nFET are independently tuned.

[0047] At 216, according to FIG. 6A to FIG. 6CIn one embodiment shown in FIG. 1 , the photoresist is stripped from the cut hard mask 250 and the cuts 252, 254 are filled with oxide, thereby creating insulating regions 262, 264, respectively. The insulating regions 262, 264 electrically insulate the nFET and the pFET from each other. In contrast to the usual sloped sides, the insulating regions 262, 264 have substantially straight vertical sides. The oxide within the insulating regions 262, 264 is then planarized to stop on the cut hard mask 250 before the cut hard mask 250 is removed. The oxide is then further recessed to remove the pad oxide 242 from the fin 240. The insulating regions 262, 264 may extend beyond the top of the fin 240, as shown in FIG. Figure 6B , Figure 6C as shown in .

[0048] At 218, according to FIG. 7A to FIG. 7C In one embodiment shown in FIG. 2 , a gate structure 255 is formed transversely to the fin 240. The gate structure 255 of the fin FET device surrounds three sides of each fin to more accurately control the current flow therein than in a conventional planar device. The gate structure 255 includes a gate dielectric 266 and a gate 268, which can be made of polysilicon, for example. Alternatively, the gate 268 can be made of metal, or it can be initially made of polysilicon and later replaced by metal using a replacement metal gate process as known in the art. First, the oxide within the insulating regions 262 and 264 is partially removed, down to the surface of the substrate 220. Next, a gate dielectric 266, such as a thin layer of SiO2, HfO2, etc., is formed over the fin 240. Finally, a thick polysilicon gate 268 is formed on top of the gate dielectric 266, and the gate dielectric 266 and the polysilicon gate 268 are patterned in a usual manner with features transverse to the fin.

[0049] At 219, according to one embodiment, the source and drain regions are doped. The source and drain regions of the p-type compressive SiGe active layer 222 and the n-type tensile silicon active layer 232 may be doped by ion implantation or plasma implantation or a combination thereof using the existing gate structure 255 as a mask. Alternatively, elevated source and drain regions may be epitaxially grown from the source and drain regions and doped in situ. Using either technique, the self-aligned doping step completes the formation of the co-integrated nFET device and pFET device.

[0050] Figure 8 A series of steps in a method 300 of fabricating a compressively strained p-type fin FET or pFET co-integrated with a tensilely strained n-type fin FET or nFET according to an alternative embodiment is shown. In the method 300, some steps occur in a different order, for example, forming the fin 240 after the insulating regions 262, 264.

[0051] Fig. 9 and Fig.10 An exemplary cross-sectional view of structures 320a, 320b formed according to method 300 including steps 302 to 320 is shown. Structures 320a, 320b show the nFET and pFET after step 314, which is after completion of the isolation region 264, but before the formation of the fin 240 at 316. Fig. 9 In FIG. 2 , the insulating region 264a extends to a depth 245a below the depth d of the strain-relaxed SiGe region 258. Fig.10 , insulating region 264b extends to a depth 245b that is greater than the depth d of strain-relaxed SiGe region 258. The sequence of steps in exemplary method 300 is otherwise similar to the sequence of steps in method 200. As in method 200, insulating regions 262 and 264 fabricated by method 300 may extend to a depth that is less than, equal to, or greater than the depth of the trench that defines the boundary of strain-relaxed SiGe region 258, while still inducing relaxation of the SiGe and tensile strain in silicon active layer 232.

[0052] It will be understood that, although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not to be restricted, except in the context of the appended claims.

[0053] In light of the above detailed description, these and other changes can be made to the embodiments. In summary, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments, along with the entire range of equivalents to which the claims are entitled. Therefore, the claims are not limited to the scope of the present disclosure.

[0054] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If necessary, various aspects of the embodiments can be modified to provide further embodiments using the concepts of the various patents, applications, and disclosures.

Claims

1. A method of manufacturing an integrated circuit, include: forming a compressive SiGe active layer on a silicon substrate; forming a p-type fin FET in the compressive SiGe active layer; forming a strain-relaxed SiGe region embedded in the silicon substrate; forming a tensile silicon active layer on the strain-relaxed SiGe region and adjacent to the compressive SiGe active layer; forming an n-type fin FET in the tensile silicon active layer; as well as A plurality of electrically insulating regions are formed, the plurality of electrically insulating regions being positioned between the p-type fin FET and the n-type fin FET and between the strain-relaxed SiGe region and the silicon substrate.

2. The method according to claim 1, in, Forming the tensile silicon active layer includes forming the tensile silicon active layer surrounded by the compressive SiGe active layer.

3. The method according to claim 1, forming the tensile silicon active layer include: The tensile silicon active layer is vertically aligned with the strain-relaxed SiGe region.

4. The method according to claim 1, in, The plurality of insulating regions have substantially straight vertical sides and a width in the range of 50 nm to 100 nm.

5. The method according to claim 1, in, Forming the plurality of electrically insulating regions includes extending the plurality of electrically insulating regions above a top surface of the active layer.

6. The method according to claim 1, in, The compressive SiGe active layer and the tensile Si active layer have a thickness in the range of 10 nm to 100 nm.

7. The method according to claim 1, in, The compressive SiGe active layer has a germanium concentration in the range of 15% and 50%.

8. The method according to claim 1, in, Forming the strain-relaxed SiGe region: Partially replacing the portion of the silicon substrate in the nFET region with a SiGe substrate; as well as A plurality of trenches are formed along at least two sides of the nFET region separating at least a portion of the SiGe substrate portion from the silicon substrate, thereby relieving strain in the SiGe substrate portion and inducing tensile strain in the silicon active layer.

9. The method according to claim 8, in, Forming the plurality of electrically insulating regions includes forming an electrically insulating material in the plurality of trenches.

10. The method according to claim 8, in, Forming the plurality of trenches includes forming the plurality of trenches along four sides of the nFET region to generate biaxial elastic relaxation in the SiGe substrate portion and biaxial tensile strain in the silicon active layer.

11. An integrated circuit, include: Silicon substrate; A first compressive SiGe active region and a second compressive SiGe active region are on the silicon substrate; A strain-relaxed SiGe region embedded in the silicon substrate; a tensile silicon active layer on the strain-relaxed SiGe region and between the first compressive SiGe active region and the second compressive SiGe active region; a plurality of transistors formed in the first compressive SiGe active region and the second compressive SiGe active region and in the tensile silicon active layer; a first electrically insulating region extending into the silicon substrate along a first sidewall of the strain-relaxed SiGe region; as well as A second electrically insulating region extends into the silicon substrate along a second sidewall of the strain-relaxed SiGe region.

12. The integrated circuit according to claim 11, in, The first electrically insulating region extends between the first compressive SiGe active region and the tensile silicon active layer, and the second electrically insulating region extends between the second compressive SiGe active region and the tensile silicon active layer.

13. The integrated circuit according to claim 11, in, The tensile silicon active layer is vertically aligned with the strain-relaxed SiGe region.

14. The integrated circuit according to claim 11, in, The strain-relaxed SiGe region has a first depth into the silicon substrate, and the first electrically insulating region and the second electrically insulating region have a second depth greater than the first depth.

15. The integrated circuit according to claim 11, in, The plurality of transistors include: a plurality of p-type fin FETs formed in the first compressive SiGe active region and the second compressive SiGe active region; and A plurality of n-type fin FETs are formed in the tensile silicon active layer.

16. A method of manufacturing an integrated circuit, include: forming a first compressive SiGe active region and a second compressive SiGe active region on a silicon substrate; forming a strain-relaxed SiGe region embedded in the silicon substrate; forming a tensile silicon active layer on the strain-relaxed SiGe region and between the first compressive SiGe active region and the second compressive SiGe active region; forming a plurality of transistors in the first compressive SiGe active region and the second compressive SiGe active region and in the tensile silicon active layer; forming a first electrically insulating region extending into the silicon substrate along a first sidewall of the strain-relaxed SiGe region; as well as A second electrically insulating region is formed, extending into the silicon substrate along a second sidewall of the strain-relaxed SiGe region.

17. The method according to claim 16, in, Forming the first electrically insulating region includes extending the first electrically insulating region between the first compressive SiGe active region and the tensile silicon active layer, and forming the second electrically insulating region includes extending the second electrically insulating region between the second compressive SiGe active region and the tensile silicon active layer.

18. The method according to claim 16, in, Forming the tensile silicon active layer includes vertically aligning the tensile silicon active layer with the strain-relaxed SiGe region.

19. The method according to claim 16, in, The strain-relaxed SiGe region has a first depth into the silicon substrate, and the first electrically insulating region and the second electrically insulating region have a second depth greater than the first depth.

20. The method according to claim 16, in, Forming the plurality of transistors includes: forming a plurality of p-type fin FETs in the first compressive SiGe active region and the second compressive SiGe active region; and A plurality of n-type fin FETs are formed in the tensile silicon active layer.

21. An integrated circuit, include: Semiconductor substrate; A strain-relaxed SiGe region embedded in the semiconductor substrate; A tensile silicon active layer on the strain-relaxed SiGe region; a first fin FET formed in the tensile silicon active layer; as well as A plurality of electrically insulating regions are positioned between the strain-relaxed SiGe region and the semiconductor substrate.

22. The integrated circuit of claim 21, further comprising a compressive semiconductor active layer on the semiconductor substrate, in, The tensile silicon active layer is laterally surrounded by the compressive semiconductor active layer.

23. The integrated circuit according to claim 21, in, The tensile silicon active layer is vertically aligned with the strain-relaxed SiGe region.

24. The integrated circuit according to claim 21, in, The plurality of insulating regions have substantially straight vertical sides and a width in the range of 50 nm to 100 nm.

25. The integrated circuit of claim 21, further comprising: include: a compressive semiconductor active layer on the semiconductor substrate, wherein the tensile silicon active layer is laterally surrounded by the compressive semiconductor active layer; and A second fin FET is formed in the compressive semiconductor active layer.

26. The integrated circuit of claim 21, further comprising a compressive semiconductor active layer on the semiconductor substrate, in, The plurality of electrically insulating regions extend between the compressive semiconductor active layer and the tensile silicon active layer.

27. The integrated circuit of claim 21, further comprising a compressive semiconductor active layer on the semiconductor substrate, in, The compressive semiconductor active layer is a compressive SiGe active layer.

28. The integrated circuit according to claim 21, in, The tensile silicon active layer includes a plurality of tensile semiconductor fins extending parallel to each other along a first direction on the strain-relaxed SiGe region, and the integrated circuit also includes a plurality of conductive gates extending parallel to each other in a second direction transverse to the first direction.

29. The integrated circuit according to claim 21, in, The strain-relaxed SiGe region extends into the semiconductor substrate to a first depth, and the plurality of electrically insulating regions extend into the semiconductor substrate to a second depth that is less than the first depth.

30. The integrated circuit of claim 21, further comprising a compressive semiconductor active layer on the semiconductor substrate, in, The tensile silicon active layer has a similar thickness to the compressive semiconductor active layer.

31. A fin FET device, include: Semiconductor substrate; A strain-relaxed SiGe region is formed in the semiconductor substrate; a tensile semiconductor fin on top of the strain-relaxed SiGe region; a source region formed in the tensile semiconductor fin; a drain region formed in the tensile semiconductor fin; a channel region formed in the tensile semiconductor fin and coupling the source region to the drain region; as well as A gate structure surrounds three sides of the tensile semiconductor fin.

32. The device according to claim 31, in, The gate structure includes a gate dielectric and a conductive gate.

33. The device of claim 31 further comprising a plurality of electrically insulating regions extending into the semiconductor substrate and laterally surrounding the strain-relaxed SiGe region.

34. The device of claim 31 further comprising a compressive semiconductor active layer on the semiconductor substrate, in, The tensile silicon active layer is laterally surrounded by the compressive semiconductor active layer.

35. The device according to claim 34, in, The compressive semiconductor active layer is a compressive SiGe active layer.

36. An integrated circuit, include: Semiconductor substrate; A strain-relaxed SiGe region embedded in the semiconductor substrate; a plurality of first compressive semiconductor active fins on the semiconductor substrate; a plurality of second compressive semiconductor active fins on the semiconductor substrate; a plurality of tensile semiconductor active fins on the strain-relaxed SiGe region and between the first plurality of compressive semiconductor active fins and the second plurality of compressive semiconductor active fins; as well as A plurality of transistors are formed in the plurality of first compressive semiconductor active fins and the plurality of second compressive semiconductor active fins and in the plurality of tensile semiconductor active fins.

37. The integrated circuit of claim 36, further comprising: include: a first electrically insulating region extending into the semiconductor substrate along a first sidewall of the strain-relaxed SiGe region; as well as A second electrically insulating region extends into the semiconductor substrate along a second sidewall of the strain-relaxed SiGe region.

38. The integrated circuit according to claim 37, in, The first electrically insulating region extends between the first plurality of compressive semiconductor active fins and the plurality of tensile semiconductor active fins, and the second electrically insulating region extends between the second plurality of compressive semiconductor active fins and the plurality of tensile semiconductor active fins.

39. The integrated circuit according to claim 37, in, The strain-relaxed SiGe region has a first depth into the semiconductor substrate, and the first electrically insulating region and the second electrically insulating region have a second depth greater than the first depth.

40. The integrated circuit of claim 36, in, The plurality of transistors include: a plurality of p-type fin FETs formed in the plurality of first compressive semiconductor active fins and the plurality of second compressive semiconductor active fins; and A plurality of n-type fin FETs are formed in the plurality of tensile semiconductor active fins.

41. A semiconductor device, include: A substrate having a first surface and a second surface opposite to the first surface, the substrate comprising a first material, wherein the first material is silicon; a strain relaxation region on a third surface of the substrate, the third surface being between the first surface and the second surface, the strain relaxation region comprising a second material different from the first material, wherein the second material is SiGe; a plurality of first fins on the strain relaxation region; as well as A plurality of first inter-fin insulation regions extend between adjacent first fins among the plurality of first fins and into the strain relaxation region.

42. The device according to claim 41, in, The first fin is a strain-stretched fin comprising the first material. 43 . The device of claim 41 , further comprising a first gate structure on the plurality of first fins, the first gate structure contacting at least three sides of each of the first fins.

44. The device according to claim 43, in, The first gate structure contacts the plurality of first inter-fin insulation regions between adjacent first fins among the plurality of first fins.

45. The device according to claim 44, in, The plurality of first fins are spaced apart from each other along a first direction, and the first gate structure extends between adjacent first fins among the plurality of first fins along the first direction.

46. ​​The device according to claim 45, further comprising: include: a first insulating region, between a first sidewall of the strain relaxation region and the substrate; as well as A second insulating region is between a second sidewall of the strain relaxation region and the substrate, wherein the second sidewall is spaced apart from the first sidewall along the first direction.

47. The device according to claim 46, further comprising: include: A plurality of second fins are on the first surface of the substrate, the second fins comprising the second material.

48. The device according to claim 47, further comprising: include: A plurality of second inter-fin insulation regions extend into the substrate between adjacent second fins of the plurality of second fins.

49. The device according to claim 41, in, The first material is silicon and the second material is germanium.

50. A semiconductor device, include: A substrate having a first surface and a second surface opposite to the first surface, the substrate comprising a first material, wherein the first material is silicon; a strain relaxation region on a third surface of the substrate, the third surface being between the first surface and the second surface, the strain relaxation region comprising a second material different from the first material, wherein the second material is SiGe; an insulating material surrounding a side surface of the strain relaxation region and extending between the substrate and the side surface of the strain relaxation region; a plurality of first fins on the strain relaxation region, the first fins comprising the first material; as well as A plurality of second fins are on the first surface of the substrate, the second fins comprising the second material.

51. The device according to claim 50, in, Each first fin of the plurality of first fins is a strained tensile fin, and each second fin of the plurality of second fins is a strained compressive fin.

52. The device according to claim 50, further comprising: include: a plurality of first inter-fin insulation regions extending between adjacent first fins among the plurality of first fins into the strain relaxation region; as well as A plurality of second inter-fin insulation regions extend into the substrate between adjacent second fins of the plurality of second fins.

53. The device according to claim 52, further comprising: include: A gate structure is on the plurality of first fins and the plurality of second fins, the gate structure contacting at least three sides of each of the plurality of first fins and the plurality of second fins. 54 . The device of claim 53 , wherein the gate structure contacts each of the plurality of first inter-fin insulation regions and each of the plurality of second inter-fin insulation regions.

55. A method of manufacturing an integrated circuit, include: forming a strain relaxation region on a first surface of a substrate, the first surface being located between a second surface and a third surface opposite to the second surface, the substrate comprising a first material, the strain relaxation region comprising a second material different from the first material, wherein the first material is silicon and the second material is SiGe; forming a plurality of first fins on the strain relaxation region, wherein the first fins include the first material; as well as A plurality of first inter-fin insulation regions are formed between adjacent first fins among the plurality of first fins and extend into the strain relaxation region.

56. The method according to claim 55, further comprising: include: A first gate structure is formed on the plurality of first fins, the first gate structure contacting at least three sides of each of the first fins.

57. The method according to claim 56, further comprising: include: An insulating region is formed that surrounds a side surface of the strain relaxation region and extends between the substrate and the side surface of the strain relaxation region.

58. The method according to claim 57, further comprising: include: A plurality of second fins are formed on the second surface of the substrate, the second fins comprising the second material.

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