Storage device with improved data reliability and method of operating the same

Abstract

A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate a string selection line based on control of the control logic circuit. A programming interval is formed between a first programming operation and a second programming operation. The control logic circuit includes a reprogramming controller configured to control the row decoder so that the programming intervals in memory cells connected to different string selection lines are different among memory cells connected to a first word line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0037763 filed in the Korean Intellectual Property Office on March 30, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a storage device and more particularly to a storage device with improved data reliability and an operating method thereof. Background Art

[0004] A nonvolatile memory device is a semiconductor memory device that includes a plurality of memory cells that store a plurality of pieces of data in a nonvolatile manner. Flash memory systems are examples of nonvolatile memory devices, and have been widely used in Universal Serial Bus (USB) drives, digital cameras, mobile phones, smart phones, tablet computers, personal computers (PCs), memory cards, and solid-state drives (SSDs). In a memory system such as a nonvolatile memory device, there is a significant need to achieve large-capacity storage and improve the reliability of programmed data. Summary of the invention

[0005] According to aspects of the present disclosure, a memory device and an operating method thereof provide improved data reliability, whereby an order of program operations to be performed can be controlled according to string selection lines.

[0006] According to one aspect of the present disclosure, a memory cell array includes a plurality of string selection lines, a plurality of cell strings respectively connected to the plurality of string selection lines and including a plurality of memory cells, and a plurality of word lines connected to the plurality of memory cells. A control logic circuit is configured to control a plurality of data programming steps with respect to the plurality of memory cells. A row decoder is configured to activate the plurality of string selection lines based on control of the control logic circuit. The data programming step includes a first programming operation and a second programming operation, and a programming interval is formed between the first programming operation and the second programming operation. The control logic circuit includes a reprogramming controller configured to control the row decoder so that the programming intervals are different in the memory cells connected to different string selection lines in the memory cells connected to the first word line.

[0007] According to another aspect of the present disclosure, a memory cell array includes a plurality of string selection lines, a plurality of cell strings respectively connected to the plurality of string selection lines and including a plurality of memory cells, and a plurality of word lines connected to the plurality of memory cells. A method of operating a memory device including a memory cell array includes: performing a first programming operation on a memory cell connected to a first word line among the plurality of word lines; performing a first programming operation on a memory cell connected to a second word line among the plurality of word lines; and performing a second programming operation on a memory cell connected to the first word line. In memory cells included in cell strings connected to different string selection lines among the memory cells connected to the first word line, a first interval between the first programming operation and the second programming operation is different.

[0008] According to another aspect of the present disclosure, a memory cell array includes a plurality of string selection lines, a plurality of cell strings connected to the string selection lines and including a plurality of memory cells, respectively, and a plurality of word lines connected to the memory cells. A method of operating a memory device including a memory cell array includes: performing a first programming operation on a memory cell included in a cell string connected to a first string selection line among memory cells connected to a first word line; performing a first programming operation on a memory cell included in a cell string connected to a string selection line other than the first string selection line among memory cells connected to the first word line; performing a first programming operation on a memory cell connected to a second word line; performing a second programming operation on a memory cell included in a cell string connected to a string selection line other than the first string selection line among memory cells connected to the first word line; and performing a second programming operation on a memory cell included in a cell string connected to the first string selection line among memory cells connected to the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A block diagram showing a storage system according to an exemplary embodiment of the present disclosure;

[0011] Figure 2 A block diagram showing a storage device according to an exemplary embodiment of the present disclosure;

[0012] Figure 3A and Figure 3B is a graph showing distribution of threshold voltages of memory cells to be formed when a program operation is performed according to an exemplary embodiment of the present disclosure;

[0013] Figure 4 Show Figure 2 A perspective view of an implementation example of a first storage block in the storage blocks of;

[0014] Figure 5 Show Figure 2A circuit diagram of an equivalent circuit of a first storage block in the storage blocks;

[0015] Figure 6 Show Figure 4 A portion of a cross section of a storage block shown in;

[0016] Fig. 7A and Figure 7B is a diagram for explaining a programming operation according to an exemplary embodiment of the present disclosure;

[0017] Figure 8 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure;

[0018] Fig. 9 is a flowchart illustrating a method of operating a storage device according to another exemplary embodiment of the present disclosure;

[0019] Fig.10 is a diagram for explaining a level of a voltage applied to a memory cell when a program operation is performed according to an exemplary embodiment of the present disclosure;

[0020] Fig.11A and Fig. 11B is a diagram for explaining a programming operation according to an exemplary embodiment of the present disclosure;

[0021] Fig. 12A and Fig. 12B is a diagram for explaining a programming operation according to another exemplary embodiment of the present disclosure;

[0022] Fig.13A and Fig. 13B is a diagram for explaining a programming operation according to another exemplary embodiment of the present disclosure;

[0023] Fig.14 A conceptual diagram showing a memory block according to another exemplary embodiment of the present disclosure; and

[0024] Fig.15 A block diagram illustrating an example in which a storage device according to an exemplary embodiment of the present disclosure is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 FIG. 1 shows a block diagram of a storage system according to an exemplary embodiment of the present disclosure. Figure 1, the memory system 1 may include a memory controller 10 and a memory device 100 . The memory controller 10 may include a buffer memory 12 , and the memory device 100 may include a memory cell array 110 , a voltage generator 120 , and a reprogramming controller 132 .

[0027] In the figure, this includes Figure 1 , circuits may be shown as, for example, "controllers," "devices," "logic," "circuits," "generators," "decoders," "blocks," and "units." As is conventional in the art of the inventive concepts described herein, examples may be described and illustrated in terms of blocks that perform one or more functions described. These blocks (which may be referred to herein as controllers, devices, logic, circuits, generators, decoders, blocks, and units, etc.) are physically implemented by analog and / or digital circuits (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.) and may optionally be driven by firmware and / or software. For example, the circuits may be embodied in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuits constituting the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the blocks and a processor that performs other functions of the blocks. Each block of the examples may be physically divided into two or more interacting and discrete blocks without departing from the scope of the inventive concepts. Likewise, the illustrated blocks may be physically combined into more complex blocks without departing from the scope of the inventive concept.

[0028] In some embodiments, the storage system 1 may be implemented with an internal memory embedded in an electronic device, and may be, for example, a universal flash storage (UFS) storage device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). In some embodiments, the storage system 1 may be implemented with an external memory detachably attached to an electronic device, and may be a UFS memory card, a compact flash (CF) memory, a secure digital (SD) memory, a micro SD memory, a mini-SD memory, an xD memory, or a memory stick.

[0029] The memory controller 10 may control the memory device 100 to read data stored in the memory device 100 or program data into the memory device 100 in response to a write / read request from the host HOST. In detail, the memory controller 10 may provide an address ADDR, a command CMD, and a control signal CTRL to the memory device 100, thereby controlling programming, reading, and erasing operations to be performed on the memory device 100. In addition, data DATA to be programmed and data DATA to be read may be received from the memory device 100 and may be sent to the memory controller 10.

[0030] The buffer memory 12 provided in the memory controller 10 can temporarily store data sent from the host HOST, and can store data read from the memory device 100. For example, the data sent from the host HOST is data to be programmed into the memory cell array 110, and can be written into the memory cell array 110 through multiple data programming steps.

[0031] In an exemplary embodiment, a first programming operation may be performed on a memory cell of a first word line connected to the memory cell array 110 based on first data stored in the buffer memory 12. Subsequently, a first programming operation may be performed on a memory cell of a second word line connected to the memory cell array 110 based on second data stored in the buffer memory 12. Then, a second programming operation may be performed on the memory cell connected to the first word line based on the first data. For example, the first programming operation may be referred to as a pre-programming operation. In addition, the second programming operation may also be referred to as a reprogramming operation with respect to the first programming operation.

[0032] In an exemplary embodiment, the second programming operation may be performed in a different order from the order of the first programming operation. The reprogramming controller 132 may control the voltage generator 120 to generate various types of voltage signals used in memory operations such as programming and erasing operations, thereby adjusting the order of the second programming operation. A detailed description thereof will be described later.

[0033] For example, the storage device 100 may include a single memory chip. In another example, the storage device 100 may also include multiple memory chips. A memory chip may include a single die or multiple die. A die may include a single plane or multiple planes. A plane may include multiple memory blocks, and each memory block may include multiple pages, and each page may include multiple sectors.

[0034] The memory cell array 110 may include a plurality of memory cells. For example, the memory cells may be flash memory cells. The memory cell array 110 may include a plurality of cell strings (or NAND strings) connected to points where a plurality of string selection lines and a plurality of bit lines intersect each other. Each cell string may include a plurality of memory cells. For example, each cell string may be implemented to extend in a direction perpendicular to the semiconductor substrate. Therefore, each cell string may include a plurality of memory cells arranged perpendicular to the semiconductor substrate. The memory cells included in the cell string may be connected to a plurality of word lines. That is, different memory cells in a single cell string may be connected to different word lines, and this may be achieved, for example, by Figure 5 The cell strings NS11 to NS33 and the word lines WL1 to WL8 are shown.

[0035] In an exemplary embodiment, the degradation information 112 may be stored in the memory cell array 110. The degradation information 112 may include degradation information about the string selection line. In detail, the degradation information 112 may include information about the degree of degradation of the memory cells included in the cell string connected to the string selection line. For example, the degradation information 112 may include information about the string selection line with poor degradation durability and / or the string selection line with excellent degradation durability. The degradation information 112 may be sorted or classified to reflect when the string selection line deteriorates, or to reflect when the string selection line has the highest degradation durability or the lowest degradation durability of two or more degradation durability. The degradation information may reflect the usage of the memory cells included in the cell string connected to the string selection line. The usage may be a usage duration, a number of uses, or other types of information reflecting how much the memory cell may have deteriorated from a starting time point.

[0036] In an example, the deterioration information 112 may be information predicted by test statistics before mass production of the storage device 100. In the present embodiment, a plurality of pieces of deterioration information 112 are stored in the storage cell array 110. However, this is only an example, and the embodiments of the present disclosure are not limited thereto. That is, an additional memory for storing the deterioration information 112 may also or alternatively be provided in the storage device 100.

[0037] In an exemplary embodiment, one of the string selection lines may be set to a string selection line with poor degradation durability, such as the lowest degradation durability of a plurality of degradation durability among the string selection lines. The string selection line with poor degradation durability may be a string selection line for predicting that the distribution of cells of the memory cells included in the cell string connected to the corresponding string selection line deteriorates under a specific criterion or a higher criterion. The distribution may mean the distribution of the threshold voltage of the memory cell. For example, the prediction may be statistically performed by testing before mass production of the memory device 100. The degradation of the string selection line may be based on various reasons, and the string selection line with poor degradation durability may be predicted by various types of test methods.

[0038] In an exemplary embodiment, the interval between the first programming operation and the second programming operation in the memory cell connected to the first word line in the word line can be changed according to the string selection line to which each memory cell is connected. For example, the interval can represent the time interval between the first programming operation and the second programming operation. Hereinafter, in the present specification, the interval between the first programming operation and the second programming operation for any memory cell will be referred to as a "programming interval".

[0039] In an example, when the first string selection line is predicted to be a deteriorated string selection line (i.e., having poor deterioration durability), the programming interval in the memory cells included in the cell string connected to the first string selection line in the memory cells connected to the first word line may be a first interval. The first interval may be longer than the programming interval in the memory cells connected to the first word line in the memory cells included in the cell string connected to the string selection line other than the first string selection line. In other words, the order of the first programming operation and the order of the second programming operation on the memory cells connected to one word line may be changed. The order of the programming operations may vary according to the string selection line, such as to which cell string the string selection line is connected. Since the cell string includes a group of memory cells, the order of the programming operations on the memory cells included in the cell string may vary according to which string selection line is connected to which cell string.

[0040] In an exemplary embodiment, one of the string selection lines may also be set as a string selection line having excellent degradation durability, wherein the excellent degradation durability may be the highest degradation durability of two or more degradation durability. For example, a string selection line having excellent degradation durability may be statistically predicted by testing before mass production of the memory device 100.

[0041] In an example, when the second string selection line is predicted to be a string selection line having excellent deterioration durability, a programming interval in a memory cell included in a cell string connected to the second string selection line among memory cells connected to the first word line may be a second interval. The second interval may be shorter than a programming interval in a memory cell included in a cell string connected to a string selection line other than the second string selection line among memory cells connected to the first word line.

[0042] In an exemplary embodiment of the present disclosure, the order of the first program operation and the order of the second program operation can be adaptively controlled according to the string selection line. Therefore, a relatively long program interval is allocated to the string selection line with poor degradation durability, so that the stability and reliability of data can be further improved.

[0043] Figure 2 A block diagram of a storage device according to an exemplary embodiment of the present disclosure is shown. For example, Figure 2 It can be shown Figure 1 An implementation example of the storage device 100 is provided.

[0044] Reference Figure 2 , the memory device 100 may include a memory cell array 110, a voltage generator 120, a control logic 130 (eg, a control logic circuit), a row decoder 140, and a page buffer 150. Figure 2 Although not shown in the figure, the memory device 100 may further include other various components related to memory operations, such as a data input / output circuit or an input / output interface.

[0045] The memory cell array 110 may include a plurality of memory cells and may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array 110 may be connected to a row decoder 140 via word lines WL, string selection lines SSL, and ground selection lines GSL, and may be connected to a page buffer 150 via bit lines BL.

[0046] For example, the memory cells included in the memory cell array 110 may be nonvolatile memory cells for maintaining stored data even if the power supplied to the memory cells is cut off. In detail, when the memory cells are nonvolatile memory cells, the memory device 100 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM). Hereinafter, the embodiments of the present disclosure will be described in the context of a memory cell being a NAND flash memory cell. However, the embodiments of the present disclosure are not limited thereto.

[0047] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKZ. Each of the memory blocks BLK1 to BLKZ may have a planar structure or a three-dimensional (3D) structure. The memory cell array 110 may include at least one of a single-level cell (SLC) block including a single-level cell (SLC), an MLC block including a multi-level cell (MLC), a TLC block including a triple-level cell (TLC), and a QLC block including a quad-level cell (QLC). For example, some of the memory blocks BLK1 to BLKz may be SLC blocks, and the other memory blocks may be MLC blocks, TLC blocks, or QLC blocks.

[0048] The voltage generator 120 may generate various voltages used in the memory device 100. In an example, the voltage generator 120 may generate a program voltage V_PGM supplied to a selected word line for a program operation and a pass voltage V_PASS supplied to an unselected word line. Figure 2 , but the voltage generator 120 may also generate a string selection voltage and a ground selection voltage (or more, not shown) supplied to a string selection line SSL and a ground selection line GSL.

[0049] The control logic 130 (control logic circuit) may output various internal control signals for programming data into the memory cell array 110 or reading data from the memory cell array 110 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 10. For example, the control logic 130 (control logic circuit) may output a voltage control signal CTRL_vol for controlling the levels of various voltages generated by the voltage generator 120.

[0050] The control logic 130 (control logic circuit) may provide a row address X-ADDR to the row decoder 140, and may provide a column address Y-ADDR to the page buffer 150. The row decoder 140 may select at least one from the word lines of the memory block selected in response to the row address X-ADDR. When performing a programming operation, the row decoder 140 may provide a programming voltage V_PGM to the word line of the selected memory cell in response to the row address X-ADDR, and may provide a pass voltage V_PASS to the word line of the unselected memory cell. The page buffer 150 may be used as a write driver or a sense amplifier. When performing a programming operation, the page buffer 150 may operate as a write driver, and may apply a voltage caused by the data DATA to be stored in the memory cell array to the bit line BL. At the same time, when performing a read operation, the page buffer 150 may operate as a sense amplifier, and may detect the data DATA stored in the memory cell array 110.

[0051] The control logic 130 (control logic circuit) may include a reprogramming controller 132. However, the embodiments of the present disclosure are not limited thereto. The reprogramming controller 132 may be provided outside the control logic 130 (control logic circuit).

[0052] The control logic 130 (control logic circuit) and the reprogramming controller 132 may control the voltage generator 120, the row decoder 140, and the page buffer 150 so that a data programming step may be performed on the memory cell array 110. For example, the control logic 130 (control logic circuit) and the reprogramming controller 132 may control a first programming operation and a second programming operation on the memory cell array 110. However, this is only an example, and the programming step may include a first programming operation, a second programming operation, a third programming operation, or more. In an exemplary embodiment, the control logic 130 (control logic circuit) and the reprogramming controller 132 may control the row decoder 140 based on the deterioration information 112 so that a data programming step may be performed.

[0053] A first programming operation may be performed on the memory cells connected to the first word line based on the control of the control logic 130 (control logic circuit). In an exemplary embodiment, in the first programming operation, a primary coarse distribution may be formed on the memory cells connected to the first word line. For example, when the coarse distribution is formed, the distribution in each programming state may overlap with other adjacent distributions.

[0054] In an exemplary embodiment, a first programming operation may be performed on a memory cell included in a cell string connected to a first string selection line among memory cells connected to a first word line. Then, a first programming operation may be performed on a memory cell included in a cell string connected to a string selection line other than the first string selection line. In other words, a first programming operation may be performed on a memory cell included in a cell string connected to a first string selection line among memory cells connected to a first word line.

[0055] Next, a first programming operation may be performed on a memory cell connected to the second word line based on the control of the control logic 130 (control logic circuit), and a second programming operation may be performed on a memory cell connected to the first word line based on the control of the reprogramming controller 132. For example, the second word line may be a word line adjacent to the first word line. In the second programming operation, a secondary fine distribution may be formed on the memory cell connected to the first word line that forms the primary coarse distribution. For example, when forming the fine distribution, the distribution in each programming state may not overlap with other adjacent distributions, but a predetermined interval may be formed between programming operations that are adjacent in time.

[0056] When performing the first programming operation, a pulse voltage of a first level may be applied to a word line connected to a memory cell to be programmed. In addition, when performing the second programming operation, a pulse voltage of a second level may be applied to a word line connected to a memory cell to be programmed. In an exemplary embodiment, the second level may be higher than the first level. In another exemplary embodiment, the time for applying the pulse voltage of the second level to the word line connected to the memory cell to be programmed may be longer than the time for applying the pulse voltage of the first level to the word line connected to the memory cell to be programmed.

[0057] In an exemplary embodiment, a second programming operation may be performed on a memory cell included in a cell string connected to a string selection line other than a first string selection line among the memory cells connected to the first word line. Then, a second programming operation may be performed on a memory cell included in a cell string connected to the first string selection line among the memory cells connected to the first word line. In other words, a second programming operation may be performed on a memory cell included in a cell string connected to the first string selection line among the memory cells connected to the first word line.

[0058] For example, the first string selection line may be a string selection line predicted to be a deteriorated string selection line (i.e., having poor deterioration durability). Due to the control of the reprogramming controller 132 according to an embodiment of the present invention, the programming interval in the memory cell connected to the first string selection line may be longer than the programming interval in the memory cell connected to the other string selection lines. Therefore, the deteriorated string selection line may have a relatively long programming interval, so that the reliability of the data may be further improved.

[0059] Figure 3A and Figure 3B is a graph showing the distribution of threshold voltages of memory cells to be formed when a program operation is performed according to an exemplary embodiment of the present disclosure. Figure 3A and Figure 3B In the embodiment of the present invention, the memory cell is programmed by a three-level cell method (TLC method). However, this is only an example, and the embodiments of the present disclosure are not limited thereto.

[0060] Figure 3AThe distribution of memory cells connected to the first word line after performing the first programming operation 1 PGM is shown. When the first programming operation 1 PGM is performed, the memory cell may have eight threshold voltage distributions. In an example, the memory cell may include a distribution of threshold voltages in the first programming state P1 to the seventh programming state P7 and a distribution of threshold voltages in the erase state E. The memory cell on which the first programming operation 1 PGM is performed may have a coarse threshold voltage distribution. For example, the distribution in each programming state may overlap with other adjacent distributions. Although not shown, when the first programming operation 1 PGM is performed on the first word line, the overlapping area between the threshold voltage distributions of the memory cells connected to the first word line may be further increased.

[0061] Figure 3B The distribution of the threshold voltages of the memory cells connected to the first word line after performing the second programming operation second PGM is shown. When the second programming operation second PGM is performed, the memory cells may have independent final threshold voltage distributions without overlapping areas. In an exemplary embodiment of the present disclosure, the programming interval in the memory cells connected to the string selection line with poor deterioration durability may be longer than the programming interval in the memory cells connected to other string selection lines. Therefore, the memory cells form a further improved threshold voltage distribution, and the reliability of the data stored in the storage device 100 may be improved.

[0062] In the current embodiment, the programming operation is performed in two steps including a first programming operation first PGM and a second programming operation second PGM. However, this is only an example, and the embodiments of the present disclosure are not limited thereto. For example, the programming operation may also be performed in three or more steps. In addition, when a programming operation is performed on a multi-bit memory cell such as an MLC or TLC, a step-by-step programming operation may also be performed in units of bits.

[0063] Figure 4 Show Figure 2 2 is a perspective view of an implementation example of a first memory block among the memory blocks BLK1 to BLKz.

[0064] Reference Figure 4 , the first memory block BLK1 may be formed perpendicular to the substrate SUB. Figure 4, the first memory block BLK1 includes a ground selection line GSL and a string selection line SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3. The marked string selection line SSL represents three string selection lines present in the first memory block BLK1. However, in practice, the first memory block BLK1 may include a greater or lesser number of marked elements than the above number. In addition, in another example, the first memory block BLK1 may further include one or more dummy word lines between the first word line WL1 and the ground selection line GSL and / or between the eighth word line WL8 and the string selection line SSL. As shown in FIG. Figure 4 As shown, one side of the cell string is connected to a common source line CSL or more than one such common source line. The other side of the cell string is connected to bit lines BL1 to BL3.

[0065] The substrate SUB may be a polysilicon layer doped with a first conductivity type (e.g., p-type). The substrate SUB may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial thin layer obtained by selectively performing epitaxial growth (SEG). The substrate SUB may be formed of a semiconductor material and may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and a mixture thereof.

[0066] A common source line CSL extending in a first direction and doped with impurities having a second conductivity type (e.g., n-type) may be provided to the substrate SUB. A plurality of insulating layers IL extending in the first direction may be sequentially provided in a third direction to a region of the substrate SUB between two adjacent common source lines CSL. The insulating layers IL may be spaced apart from each other by a predetermined distance in the third direction. For example, the insulating layer IL may include an insulating material such as silicon oxide.

[0067] A plurality of pillars P may be provided for a region of the substrate SUB between two adjacent common source lines CSL, the plurality of pillars P being sequentially located in the first direction and passing through the insulating layer IL in the third direction. For example, the pillars P may pass through the insulating layer IL and may contact the substrate SUB. In detail, the surface layer S of each pillar P may include a silicon material doped with a first conductivity type and may be used as a channel region. At the same time, the inner layer I of each pillar P may include an insulating material or an air gap, such as silicon oxide.

[0068] A charge storage layer (CS) may be provided along the exposed surface of the insulating layer IL, the pillar P, and the substrate SUB in the region between two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (or "tunnel insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE (such as select lines GSL and SSL and word lines WL1 to WL8) may be provided on the exposed surface of the charge storage layer CS in the region between two adjacent common source lines CSL.

[0069] A drain or drain contact DR may be provided to the pillar P. For example, the drain or drain contact DR may include a silicon material doped with impurities of the second conductivity type. The drain or drain contact DR may be provided with bit lines BL1 to BL3 extending in the second direction and spaced apart from each other by a predetermined distance in the first direction.

[0070] Figure 5 Show Figure 2 A circuit diagram of an equivalent circuit of a first storage block among storage blocks.

[0071] Reference Figure 5 , the first memory block BLK1 may be a NAND flash memory having a vertical structure, and Figure 1 Each of the memory blocks BLK1 to BLKz shown in FIG. 1 may be implemented as follows: Figure 5 As shown. The first memory block BLK1 may include a plurality of NAND cell strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be changed in various ways without departing from the scope and spirit of the teachings herein. Figure 5 As shown, one side of the NAND cell string is connected to a common source line CSL or more than one such common source line. The other side of the NAND cell string is connected to bit lines BL1 to BL3.

[0072] NAND cell strings NS11, NS21, and NS31 may be provided between a first bit line BL1 and a common source line CSL. NAND cell strings NS12, NS22, and NS32 may be provided between a second bit line BL2 and a common source line CSL. NAND cell strings NS13, NS23, and NS33 may be provided between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST connected in series.

[0073] The NAND cell strings commonly connected to one bit line may constitute a column. For example, the NAND cell strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to the first column. The NAND cell strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to the second column. The NAND cell strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0074] The NAND cell strings connected to one string selection line may constitute a row. For example, the NAND cell strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may correspond to the first row. The NAND cell strings NS21, NS22, and NS23 connected to the second string selection line SSL2 may correspond to the second row. The NAND cell strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to the third row.

[0075] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8. The ground selection transistor GST may be connected to the corresponding ground selection line GSL1, and the string selection transistor SST may be connected to the corresponding bit line BL1. The ground selection transistor GST may be connected to the common source line CSL.

[0076] In the current embodiment, word lines (e.g., WL) having the same height are connected in common, string selection lines SSL1 to SSL3 are separated from each other, and ground selection lines GSL1 to GSL3 are separated from each other. For example, when programming a memory cell connected to the first word line WL1 and included in the NAND cell strings NS11, NS12, and NS13 corresponding to the first column, the first word line WL1 and the first string selection line SSL1 are selected. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the ground selection lines GSL1 to GSL3 may be connected in common.

[0077] Figure 6 Show Figure 4 A portion of a cross section of a storage block is shown. Figure 6 Show for example Figure 4 Part A.

[0078] Reference Figure 6, showing multiple programming directions for a cell string connected to an arbitrary string selection line. In the example, a programming operation can be performed on a memory cell included in a cell string connected to a second string selection line SSL2 in a direction from a common source line CSL (①) along a third bit line BL3. In other words, each of the first programming operation and the second programming operation can be performed in a direction from the common source line CSL to the third bit line BL3.

[0079] In another example, a program operation may be performed on a memory cell included in a cell string connected to a second string selection line SSL2 in a direction from the third bit line BL3 (②) along the common source line CSL. In other words, each of the first program operation and the second program operation may be performed in a direction from the bit line BL3 in the common source line CSL.

[0080] Fig. 7A and Figure 7B is a diagram for explaining a programming operation according to an exemplary embodiment of the present disclosure. Fig. 7A and Figure 7B In FIG. 1 , four string selection lines are included in a programming unit. However, this is only for convenience of explanation, and in practice, the number of string selection lines included in a programming unit may be more or less than four. For example, the programming unit may be a page unit or a block unit. Fig. 7A and Figure 7B The numbers marked in the table may indicate the order of programming operations.

[0081] Reference Fig. 7A , a first program operation first PGM may be performed in a direction ① of the bit line BL from the common source line CSL. In addition, a first program operation first PGM may be performed in the same word line in a direction from the first string selection line SSL[1] to the fourth string selection line SSL[4].

[0082] In an exemplary embodiment, the first string selection line SSL[1] may be a string selection line set as a deteriorated string selection line DET_SSL (i.e., a string selection line with poor degradation durability). For example, the deteriorated string selection line DET_SSL may be statistically predicted based on various tests of the storage device 100 or a category or type of storage devices similar to or the same as the storage device 100. Alternatively, the deteriorated string selection line DET_SSL may also be an option selected before performing mass production of the storage device 100. Furthermore, in an exemplary embodiment, the fourth string selection line SSL[4] may be a string selection line set as a string selection line with excellent degradation durability, so as to reflect that the fourth string selection line SSL[4] has the highest degradation durability of two or more degradation durability.

[0083] In detail, the first programming operation first PGM may be performed on memory cells included in a cell string connected to a first string selection line SSL[1] among memory cells connected to the first word line WL[1]. Then, the first programming operation first PGM may be performed on memory cells included in a cell string connected to each string selection line among memory cells connected to the first word line WL[1] in the order from the second string selection line SSL[2] to the fourth string selection line SSL[4]. Optionally, in a modifiable embodiment, the first programming operation first PGM may also be performed on memory cells included in a cell string connected to each string selection line among memory cells connected to the first word line WL[1] in the order of the third string selection line SSL[3], the second string selection line SSL[2], and the fourth string selection line SSL[4].

[0084] Next, the first programming operation first PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the second word line WL[2] in the order from the first string selection line SSL[1] to the fourth string selection line SSL[4]. Alternatively, in a modifiable embodiment, the first programming operation first PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the second word line WL[2] in the order of the first string selection line SSL[1], the third string selection line SSL[3], the fourth string selection line SSL[2], and the second string selection line SSL[4].

[0085] In the current embodiment, Figure 4 and Figure 5 , the second word line WL[2] may be located on (above, above) the first word line WL[1]. In other words, the second word line WL[2] may be located farther from the substrate SUB in the vertical direction than the first word line WL[1]. That is, if the substrate SUB is mainly arranged on Figure 4 In the plane in the first direction and the second direction, the first word line WL[1] is located in the third direction above the substrate SUB and is arranged in the plane in the first direction and the second direction, and the second word line WL[2] is located on the first word line WL[1] along the third direction and is arranged in the plane in the first direction and the second direction.

[0086] Further references Fig. 7A , after performing the first programming operation 1 PGM on the memory cells connected to the second word line WL[2], the second programming operation 2 PGM may be performed on the memory cells connected to the first word line WL[1]. In an exemplary embodiment, the second programming operation 2 PGM may be performed on the memory cells included in the string selection lines other than the first string selection line SSL[1] among the memory cells connected to the first word line WL[1].

[0087] In the example, the second programming operation second PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order from the fourth string selection line SSL[4] to the first string selection line SSL[1]. Alternatively, in a modifiable embodiment, the second programming operation second PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order of the fourth string selection line SSL[4], the second string selection line SSL[2], the third string selection line SSL[3], and the first string selection line SSL[1].

[0088] Then, the first programming operation first PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the third word line WL[3] in the order from the first string selection line SSL[1] to the fourth string selection line SSL[4]. Alternatively, in a modifiable embodiment, the first programming operation first PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the third word line WL[3] in the order of the first string selection line SSL[1], the third string selection line SSL[3], the second string selection line SSL[2], and the fourth string selection line SSL[4].

[0089] Then, a second program operation 2 PGM may be performed on memory cells connected to the second word line WL[2]. In an exemplary embodiment, the second program operation 2 PGM may be performed on memory cells included in string selection lines other than the first string selection line SSL[1] among the memory cells connected to the second word line WL[2].

[0090] In the example, the second programming operation second PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the second word line WL[2] in the order from the fourth string selection line SSL[4] to the first string selection line SSL[1]. Alternatively, in a modifiable embodiment, the second programming operation second PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the second word line WL[2] in the order of the fourth string selection line SSL[4], the second string selection line SSL[2], the third string selection line SSL[3], and the first string selection line SSL[1]. Although not shown, the first programming operation and the second programming operation may be performed in the same mode from the third word line WL[3] to the last word line.

[0091] Due to the program operation according to the exemplary embodiment of the present disclosure, the program interval between memory cells connected to the same word line can be changed according to the string selection line. Figure 7B, a programming interval between memory cells included in a cell string connected to a first string selection line SSL[1] among memory cells connected to a first word line WL[1] may be represented as "11(12-1)". In addition, in the order from a second string selection line SSL[2] to a fourth string selection line SSL[4], a programming interval between memory cells included in a cell string connected to each string selection line among memory cells connected to a first word line WL[1] may be represented as "9(11-2)", "7(10-3)", and "5(9-4)", respectively. That is, the programming interval is asymmetrically controlled based on the degree of deterioration of the string selection line, so that the reliability of the data can be further improved.

[0092] Figure 8 1 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure. The memory device may include a plurality of string selection lines, a plurality of cell strings connected to the string selection lines and including a plurality of memory cells, and a memory cell array including a plurality of word lines connected to the memory cells.

[0093] Reference Figure 8 , when a data programming operation having a plurality of steps is performed on a memory cell array, deterioration information about a string selection line may be checked (S100). For example, the deterioration information may be stored in a Figure 2 10 and can be provided to the control logic circuit (see Figure 2 In an exemplary embodiment, the corruption information may be a basis for performing a data programming operation.

[0094] Next, a first program operation may be performed on memory cells connected to the first word line (S200). By performing the first program operation, memory cells connected to the first word line may form a coarse distribution.

[0095] Next, a first programming operation (S300) may be performed on a memory cell connected to a second word line. The second word line may be a word line adjacent to the first word line. In an example, when the direction of the programming operation is in the direction of the bit line in the common source line, the second word line may be a word line located on (above, above) the first word line. In another example, when the direction of the programming operation is in the direction of the common source line in the bit line, the second word line may be a word line located below the first word line.

[0096] Next, a second program operation may be performed on the memory cells connected to the first word line (S400). In an exemplary embodiment, a program interval in the memory cells connected to the first word line may be changed according to a string selection line.

[0097] Fig. 9is a flow chart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. For example, Fig. 9 Can be Figure 8 A specific example of the flowchart shown.

[0098] Reference Fig. 9 When operation S200 is performed, a variable i may be initialized (S210). In the current embodiment, i is initialized to 1. However, this is only an example, and the embodiments of the present disclosure are not limited thereto. For example, the variable i may be set according to the deterioration information.

[0099] Next, a first programming operation (S220) may be performed on a memory cell included in a cell string connected to the i-th string selection line. Then, it is determined whether the i-th string selection line on which operation S220 is performed is the N-th string selection line (S230). For example, N may be a constant, meaning the string selection line on which the first programming operation will be last performed in the first word line, and may be a predetermined value. When it is determined that the i-th string selection line is not the N-th string selection line (S230=No), 1 is added to the variable i (S240), and operation S220 may be performed again. Otherwise, when it is determined that the i-th string selection line is the N-th string selection line (S230=Yes), the execution of the first programming operation in the first word line may be completed, and the first programming operation (S300) may be performed on the memory cell connected to the second word line.

[0100] Next, when operation S400 is performed, a second programming operation (S410) may be performed on a memory cell included in a cell string connected to the i-th string selection line. Then, it is determined whether the i-th string selection line is the first string selection line (S420). When it is determined that the i-th string selection line is not the first string selection line (S420=No), 1 is subtracted from the variable i (S430), and operation S410 may be performed again. Otherwise, when it is determined that the i-th string selection line is the first string selection line (S420=Yes), execution of the second programming operation in the first word line may be performed, and Fig. 9 The processing is finished.

[0101] Fig.10 is a diagram for explaining a level of a voltage applied to a memory cell when a program operation is performed according to an exemplary embodiment of the present disclosure. Fig.10 An example of a voltage level applied to each row of a memory cell array when, for example, a first or second program operation is performed is shown.

[0102] Reference Fig.10 , when performing the first or second program operation, the program voltage V_PGM may be applied to the selected word line WL_SEL, and the pass voltage V_PASS may be applied to the unselected word line WL_UNSEL. For example, the level of the pass voltage V_PASS may be lower than that of the program voltage V_PGM.

[0103] In addition, a ground voltage GND may be applied to the selected bit line BL_SEL, and an inhibit voltage V_INH may be applied to the unselected bit line BL_UNSEL. In addition, a predetermined common source line voltage V_CSL may be applied to the common source line CSL. For example, the levels of the inhibit voltage V_INH and the common source line voltage V_CSL may be the same as or lower than the level of the power supply voltage.

[0104] Fig.11A and Fig. 11B is a diagram for explaining a program operation according to an exemplary embodiment of the present disclosure. Fig.11A and Fig. 11B The programming operation shown is similar to that shown in Fig. 7A and Figure 7B The programming operation described. However, according to the present embodiment, a first programming operation first PGM and a second programming operation second PGM may be performed from the bit line BL in the direction ② of the common source line CSL. That is, after performing the first programming operation first PGM on the memory cell connected to the Mth word line (where M is a natural number) WL[M], the first programming operation first PGM may be performed on the memory cell connected to the M-1th word line WL[M-1]. Then, the second programming operation second PGM may be performed on the memory cell connected to the Mth word line WL[M]. For example, M may be a natural number indicating the topmost word line. However, the embodiments of the present disclosure are not limited thereto.

[0105] In the current embodiment, the M-1th word line WL[M-1] may be located below the M-th word line WL[M]. In other words, the M-1th word line WL[M-1] may be closer to the substrate SUB than the M-th word line WL[M] in the vertical direction.

[0106] Fig. 12A and Fig. 12B is a diagram for explaining a programming operation according to another exemplary embodiment of the present disclosure. Fig. 7A and Figure 7B Compared with Fig. 12A and Fig. 12B Redundant description about the programming operation shown.

[0107] Reference Fig. 12A , the data programming operation on the memory cell may include a first programming operation, a second programming operation, and a third programming operation. First, the first programming operation first PGM may be performed on the memory cell connected to the first word line WL[1], and the first programming operation first PGM may be performed on the memory cell connected to the second word line WL[2].

[0108] Next, a second programming operation 2 PGM may be performed on memory cells connected to the first word line WL[1], and a first programming operation 1 PGM may be performed on memory cells connected to the third word line WL[3]. In an exemplary embodiment, the second programming operation 2 PGM may be performed on memory cells included in a cell string connected to each string selection line among memory cells connected to the first word line WL[1] in a sequence from a first string selection line SSL[1] to a fourth string selection line SSL.

[0109] Further references Fig. 12B , a second programming operation second PGM may be performed on the memory cells connected to the second word line WL[2], and a third programming operation third PGM may be performed on the memory cells connected to the first word line WL[1]. In an exemplary embodiment, the third programming operation third PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order from the fourth string selection line SSL[4] to the first string selection line SSL[1]. Optionally, in a modifiable embodiment, the third programming operation third PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order of the fourth string selection line SSL[4], the second string selection line SSL[2], the third string selection line SSL[3], and the first string selection line SSL[1].

[0110] Due to the programming operation according to the exemplary embodiment of the present disclosure, the interval between the second programming operation and the third programming operation in the memory cell connected to the same word line can be changed according to the string selection line. That is, even in a programming operation including three or more steps, the interval between the programming operations can be asymmetrically controlled, so that the reliability of the data can be further improved.

[0111] Fig.13A and Fig. 13B is a diagram for explaining a programming operation according to another exemplary embodiment of the present disclosure. Fig.13A and Fig. 13B In the Fig. 7A and Figure 7B Compared with Fig.13A and Fig. 13B Redundant description about the programming operation shown.

[0112] Reference Fig.13A, the first programming operation first PGM may be performed in the direction ① of the bit line BL from the common source line CSL within the cell string connected to the same string selection line. However, the embodiments of the present disclosure are not limited thereto, and the first programming operation first PGM may also be performed in the direction ② of the bit line BL along the common source line CSL within the cell string connected to the same string selection line. In addition, the first programming operation first PGM may be performed in the direction from the first string selection line SSL[1] to the fourth string selection line SSL[4] within the same word line.

[0113] In an exemplary embodiment, the first programming operation first PGM may be alternately performed on the first word line WL[1] and the second word line WL[2]. In detail, the first programming operation first PGM may be performed on the memory cells connected to each word line among the memory cells included in the cell string connected to the first string selection line SSL[1] in the order from the first word line WL[1] to the second word line WL[2]. Then, the first programming operation first PGM may be performed on the memory cells connected to each word line among the memory cells included in the cell string connected to the second string selection line SSL[2] in the order from the first word line WL[1] to the second word line WL[2]. Then, the first programming operation first PGM may be performed on the memory cells connected to each word line among the memory cells included in the cell string connected to the third string selection line SSL[3] in the order from the first word line WL[1] to the second word line WL[2]. Then, a first program operation 1 PGM may be performed on memory cells connected to each word line among memory cells included in the cell string connected to the fourth string selection line SSL[4] in order from the first word line WL[1] to the second word line WL[2].

[0114] Further references Fig. 13B , after completing the execution of the first program operation 1 PGM on the memory cells connected to the first word line WL[1] and the second word line WL[2], the second program operation 2 PGM may be performed. In an exemplary embodiment, the second program operation 2 PGM may be performed on the memory cells included in the cell string first connected to the string selection line other than the first string selection line SSL[1] within the same word line.

[0115] In the example, the second programming operation second PGM may be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order from the fourth string selection line SSL[4] to the first string selection line SSL[1]. Alternatively, in a modifiable embodiment, the second programming operation second PGM may also be performed on the memory cells included in the cell string connected to each string selection line among the memory cells connected to the first word line WL[1] in the order of the fourth string selection line SSL[4], the second string selection line SSL[2], the third string selection line SSL[3], and the first string selection line SSL[1].

[0116] In an exemplary embodiment, a second programming operation 2 PGM on the first word line WL[1] and a first programming operation 1 PGM on the third word line WL[3] may be alternately performed. For example, after performing the second programming operation 2 PGM on the memory cells connected to the first word line WL[1] among the memory cells included in the cell string connected to the fourth string selection line SSL[4], the first programming operation 1 PGM may be performed on the memory cells connected to the third word line WL[3] among the memory cells included in the cell string connected to the first string selection line SSL[1]. Then, the second programming operation 2 PGM may be performed on the memory cells connected to the first word line WL[1] among the memory cells included in the cell string connected to the third string selection line SSL[3], and then, the first programming operation 1 PGM may be performed on the memory cells connected to the third word line WL[3] among the memory cells included in the cell string connected to the second string selection line SSL[2].

[0117] Fig.14 is a conceptual diagram of a storage block according to another exemplary embodiment of the present disclosure. For example, Fig.14 A schematic cross-sectional view of a bit line BLa, multiple string selection lines Global_SSLa and SSL1a to SSL4a, multiple word lines WL1 to WLm (where m is a positive integer), multiple ground selection lines GSL1a to GSL4a and a common source line CSLa in an element of a memory block BLK1a.

[0118] Reference Fig.14, a storage operation may be performed according to each string selection line based on a voltage applied to the first to fourth string selection lines SSL1a to SSL4a. For example, a transistor formed by the first column P1a and the first string selection line SSL1a may have a threshold voltage of a first level, and a transistor formed by the first column P1a and the second to fourth string selection lines SSL2a to SSL4a may have a threshold voltage of a second level lower than the first level. In addition, a transistor formed by the second column P2a and the second string selection line SSL2a may have a threshold voltage of a first level, and a transistor formed by the second column P2a and the first string selection line SSL1a, the third string selection SSL3a, and the fourth string selection SSL4a may have a threshold voltage of a second level. In addition, a transistor formed by the third column P3a and the third string selection line SSL3a may have a threshold voltage of a first level, and a transistor formed by the third column P3a and the first string selection line SSL1a, the second string selection line SSL2a, and the fourth string selection line SSL4a may have a threshold voltage of a second level. Furthermore, transistors formed by the fourth pillar P4a and the fourth string selection line SSL4a may have a threshold voltage at a first level, and transistors formed by the fourth pillar P4a and the first to third string selection lines SSL1a to SSL3a may have a threshold voltage at a second level.

[0119] For example, when a selection voltage of a first level or higher is applied to the first string selection line SSL1a, a storage operation of a memory cell formed by the first pillar P1a and the word lines WL1 to WLm may be performed. In this case, a voltage equal to or higher than the second level or lower than the first level may be applied to the second to fourth string selection lines SSL2a to SSL4a. Therefore, other pillars except the first pillar P1a may not be selected.

[0120] In other words, in the current embodiment, instead of Figure 4 In addition to the physical separation in the string selection lines SSL1a to SSL4a, logical separation between the string selection lines SSL1a to SSL4a can be performed. After the string selection lines extending in the horizontal direction are stacked on the bit line BLa and the common source line CSLa, a programming operation can be performed on the transistors formed by the string selection lines so that the string selection lines can be logically separated from each other.

[0121] Fig.15 is a block diagram of an example in which a storage device according to an exemplary embodiment of the present disclosure is applied to a solid state drive (SSD) system.

[0122] Reference Fig.15, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may send / receive signals to / from the host 1100 via a signal connector, and may receive power through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and storage devices 1230, 1240, and 1250. In this case, the SSD 1200 may use a reference Figure 1 and Fig. 13B The above-described embodiments are implemented. Therefore, each of the storage devices 1230, 1240, and 1250 can perform a data programming operation including multiple steps. Each of the storage devices 1230, 1240, and 1250 may include a reprogramming controller 1232. Therefore, the programming interval can be asymmetrically controlled based on the degree of deterioration of the string selection line. Therefore, the reliability of the data of the SSD system 1000 can be improved.

[0123] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: A memory cell array comprising a plurality of string selection lines, a plurality of cell strings respectively connected to the plurality of string selection lines and including a plurality of memory cells, and a plurality of word lines connected to the plurality of memory cells; a control logic circuit configured to control a plurality of data programming steps with respect to the plurality of memory cells; as well as a row decoder configured to activate the plurality of string selection lines based on control of the control logic circuit, wherein the plurality of data programming steps include a first programming operation and a second programming operation, a programming interval is formed between the first programming operation and the second programming operation, and The control logic circuit includes a reprogramming controller configured to control the row decoder so that the programming intervals in memory cells connected to different string selection lines among the memory cells connected to the first word line are different, The second programming operation on the memory cells connected to the first word line is performed after the first programming operation on the memory cells connected to the second word line.

2. The storage device according to claim 1, wherein: The multiple string selection lines include a first string selection line, a second string selection line, and a third string selection line, and the control logic circuit controls the row decoder so that the programming interval of the storage cells connected to the first word line in the storage cells included in the cell string connected to the first string selection line is longer than the programming interval of the storage cells connected to the first word line in the storage cells included in the cell string connected to the second string selection line and the third string selection line.

3. The storage device according to claim 1, wherein: The control logic circuit controls the row decoder to first perform the first programming operation on the memory cells included in the cell string connected to the first string selection line among the memory cells connected to the first word line, and controls the row decoder to finally perform the second programming operation on the memory cells included in the cell string connected to the first string selection line among the memory cells connected to the first word line.

4. The storage device according to claim 1, wherein: The control logic circuit controls the row decoder to finally perform the first programming operation on the memory cells included in the cell string connected to the second string selection line among the memory cells connected to the first word line, and controls the row decoder to first perform the second programming operation on the memory cells included in the cell string connected to the second string selection line among the memory cells connected to the first word line.

5. The storage device according to claim 4, wherein: The second string selection line is set as a string selection line having the highest degradation durability among the plurality of string selection lines.

6. The storage device according to claim 1, in, The control logic circuit is configured to control the plurality of data programming steps with respect to the plurality of memory cells based on the deterioration information of the plurality of string selection lines, wherein the programming interval is controlled based on the degradation information, and The degradation information includes prediction information of each of the plurality of string selection lines.

7. The storage device according to claim 6, in, The control logic circuit is configured to control the program interval between the first program operation and the second program operation to be different in the memory cells connected to different string selection lines based on the deterioration information.

8. A method of operating a memory device including a memory cell array, the memory cell array including a plurality of string selection lines, a plurality of cell strings respectively connected to the plurality of string selection lines and including a plurality of memory cells, and a plurality of word lines connected to the plurality of memory cells, the method comprising: performing a first programming operation on the memory cells connected to a first word line among the plurality of word lines; performing the first programming operation on the memory cells connected to a second word line among the plurality of word lines; as well as performing a second programming operation on the memory cell connected to the first word line, wherein, in the memory cells included in the cell string connected to different string selection lines among the plurality of string selection lines among the memory cells connected to the first word line, intervals between the first programming operation and the second programming operation are different, The second programming operation on the memory cells connected to the first word line is performed after the first programming operation on the memory cells connected to the second word line.

9. The method according to claim 8, wherein: A first string selection line among the multiple string selection lines is a string selection line set to be a string selection line having the lowest degradation durability, and the intervals among the memory cells included in the cell string connected to the first string selection line are longer than the intervals among the memory cells included in the cell string connected to string selection lines other than the first string selection line among the multiple string selection lines.

10. The method according to claim 8, wherein: Performing the first programming operation on the memory cell connected to the first word line includes: performing the first program operation on the memory cells included in the cell string connected to a first string selection line among the plurality of string selection lines among the memory cells connected to the first word line; and The first program operation is performed on the memory cells included in the cell strings connected to a string selection line other than the first string selection line among the plurality of string selection lines among the memory cells connected to the first word line.

11. The method according to claim 10, wherein: Performing the second programming operation on the memory cell connected to the first word line includes: performing the second program operation on the memory cells included in the cell strings connected to the string selection line other than the first string selection line among the memory cells connected to the first word line; and The second program operation is performed on the memory cells included in the cell string connected to the first string selection line among the memory cells connected to the first word line.

12. The method according to claim 8, wherein: A first interval between the first programming operation and the second programming operation in the memory cells included in the cell string connected to the first string selection line among the memory cells connected to the first word line is different from a second interval between the first programming operation and the second programming operation in the memory cells included in the cell string connected to the second string selection line among the memory cells connected to the first word line.

13. The method according to claim 12, wherein: The second string selection line is set as a string selection line having the highest degradation durability among the plurality of string selection lines.

14. The method according to claim 8, wherein: The first word line and the second word line are located adjacent to each other.

15. The method according to claim 14, wherein: One side of the multiple cell strings is connected to one or more common source lines, and the other side of the multiple cell strings is connected to multiple bit lines, and the first programming operation and the second programming operation in each cell string are performed from the one or more common source lines along the direction of the multiple bit lines, and the second word line is located offset from the first word line.

16. The method according to claim 14, wherein: One side of the multiple cell strings is connected to one or more common source lines, and the other side of the multiple cell strings is connected to multiple bit lines, and the first programming operation and the second programming operation in each cell string are performed from the multiple bit lines along the direction of the one or more common source lines, and the first word line is located offset from the second word line.

17. The method according to claim 8, in, controlling a plurality of data programming steps with respect to the plurality of memory cells based on the deterioration information of the plurality of string selection lines, the plurality of data programming steps including the first programming operation and the second programming operation, forming a programming interval between the first programming operation and the second programming operation, wherein the programming interval is controlled based on the degradation information, and The degradation information includes prediction information of each of the plurality of string selection lines.

18. The method according to claim 17, in, The program interval between the first program operation and the second program operation is controlled to be different in the memory cells connected to different string selection lines based on the deterioration information.

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