Semiconductor packaging

Abstract

A semiconductor package includes a dielectric layer and a conductive column. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive column is disposed in the dielectric layer. The conductive column includes a first portion and a second portion disposed above the first portion. The second portion of the conductive column is recessed from the second surface of the dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package and a method for manufacturing a semiconductor package. Background Art

[0002] A semiconductor package may include a conductive post encapsulated by an encapsulation material. To provide electrical connections, the conductive post encapsulated by the encapsulation material is exposed by removing the encapsulation material (e.g., by a grinding technique), and a circuit layer may be formed on the conductive post. However, a relatively small roughness of the conductive post (which may result from the use of a grinding technique) may cause cracks or delamination between the circuit layer and the conductive post.

[0003] Furthermore, particles of the conductive posts may remain on the encapsulation material after the grinding operation, and particles of the encapsulation material may remain on the conductive posts after the grinding operation. Summary of the invention

[0004] In one or more embodiments, a semiconductor package includes a first dielectric layer and a conductive column. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive column is disposed in the first dielectric layer. The conductive column includes a first portion and a second portion disposed above the first portion. The second portion of the conductive column is recessed from the second surface of the first dielectric layer.

[0005] In one or more embodiments, a method for manufacturing a semiconductor package includes: providing a conductive column; forming a sacrificial element on the conductive column; encapsulating the sacrificial element and the conductive column by an encapsulant; and removing a top portion of the encapsulant and the sacrificial element to expose the conductive column, so that the upper surface of the remaining portion of the encapsulant is rough. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0007] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M , Figure 2N , Fig.2O , Figure 2P and Figure 2QDescription of methods for manufacturing according to some embodiments Figure 1 A method of packaging a portion of a semiconductor is shown in FIG.

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J and Figure 3K Description of methods for manufacturing according to some embodiments Figure 1 A method of semiconductor packaging is shown in FIG.

[0009] Figure 4 Schematic diagram illustrating a sandblasting apparatus according to some embodiments of the present disclosure.

[0010] Figure 5 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0011] Figure 6 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0012] Fig. 7A , Figure 7B , Figure 7C and Fig.7D is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0013] Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0014] Fig.9A , Fig. 9B and Fig. 9C is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0015] Fig. 10A and Fig. 10B is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0016] Fig.11 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0017] Fig. 12A and Fig. 12B is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0018] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0019] Fig.14A and Fig. 14B Different types of semiconductor packages according to some embodiments of the present disclosure are described.

[0020] Fig.15 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0021] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar elements. Embodiments of the present disclosure will be readily understood from the following detailed description made in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0022] Unless otherwise specified, spatial descriptions such as "above", "below", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "above", "lower", "upper", "above", "below", etc. are indicated relative to the orientation shown in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes, and actual implementations of the structures described herein may be spatially arranged in any orientation or manner, with the limitation that the advantages of the embodiments of the present disclosure will not deviate from such arrangements.

[0023] Figure 1 1 is a cross-sectional view of a semiconductor package 1 according to some embodiments of the present disclosure. The semiconductor package 1 includes dielectric layers 11 and 12, electrical components 20 and 22, insulating layers (or passivation layers) 40 and 44, patterned conductive layers 60, 62, 64 and 68, conductive pillars 80 and 82, and solder 94.

[0024] In one or more embodiments, the electronic components 20 and 22 may be chips or dies. The dielectric layer 11 has a surface 111u and a surface 111b opposite to the surface 111u. The dielectric layer 12 has a surface 121u and a surface 121b opposite to the surface 121u. The conductive pillar 80 is disposed in the dielectric layer 11. In some embodiments, the material of the conductive pillar 80 may include, for example, copper (Cu), another metal, an alloy, or other suitable conductive materials. In some embodiments, the solder 94 may be a solder bump.

[0025] The conductive pillar 80 includes a first portion 801 and a second portion 802 below the first portion 801. The second portion 802 of the conductive pillar 80 is recessed from the surface 111b of the dielectric layer 11. The dielectric layer 11 defines a wedge-shaped opening 111o adjacent to the second portion 802 of the conductive pillar 80. In one or more embodiments, the thickness of one or more of the dielectric layers 11 and 12 is in a range of about 120 micrometers (μm) to about 150 μm.

[0026] The patterned conductive layer 60 extends into the wedge-shaped opening 111o and contacts the second portion 802 of the conductive pillar 80. The patterned conductive layer 62 is electrically connected to the second portion 801 of the conductive pillar 80. The height of the conductive pillar 80 is in the range from about 20 μm to about 70 μm. In some embodiments, the semiconductor package 1 includes a plurality of conductive pillars 80, and the conductive pillars 80 have a line width / line space (L / S) of less than about 5 μm / about 5 μm (e.g., about 4 μm / about 4 μm or less, or about 3 μm / about 3 μm or less).

[0027] The patterned conductive layer 60 includes a sublayer 601 and a sublayer 602. In some embodiments, the sublayer 601 may be a seed layer. In one or more embodiments, the material of the sublayer 601 may include, for example, Cu, titanium (Ti), titanium copper alloy (Ti / Cu), another metal, another alloy, or other suitable conductive materials. In some embodiments, the material of the sublayer 602 may include, for example, Cu, another metal, alloy, or other suitable conductive materials.

[0028] The sublayer 601 is disposed between the sublayer 602 and the second portion 802 of the conductive pillar 80. The patterned conductive layer 62 includes a sublayer 621. The sublayer 621 of the patterned conductive layer 62 includes Ti. In one or more embodiments, the material of the sublayer 621 may include, for example, Cu, Ti, a titanium copper alloy (Ti / Cu), another metal, another alloy, or other suitable conductive materials.

[0029] The electrical component 20 is embedded in the dielectric layer 11 and disposed between the patterned conductive layer 60 and the patterned conductive layer 62. The dielectric layers 11 and 12 include one or more molding materials. The molding material / encapsulation material / molding compound of the dielectric layers 11 and 12 includes, for example, resin and / or filler / particles.

[0030] The surface 111b of the dielectric layer 11 has an arithmetic mean surface roughness (Ra) value. In one or more embodiments, the Ra value is at least or greater than about 450 nanometers (nm). In one or more embodiments, the Ra value is at most or less than about 12 μm. The dielectric layer 11 has a sidewall 111s. The sidewall 111s defines a wedge-shaped opening 111o adjacent to the second portion 802 of the conductive pillar 80. The surface roughness of the sidewall 111s of the dielectric layer 11 is substantially the same as the surface roughness of the surface 111b of the dielectric layer 11. In one or more embodiments, the Ra value of the surface 111b of the dielectric layer 11 is in the range from about 3 μm to about 10 μm. In one or more embodiments, the Ra value of the surface 111b of the dielectric layer 11 is in the range from about 0.5 μm to about 12 μm. The maximum height difference between the portions of the surface 111b of the dielectric layer 11 is in the range from about 10 μm to about 20 μm. The surface roughness of the surface 111b of the dielectric layer 11 (e.g., greater than 450nm) may have sufficient bonding force to avoid cracks at the interface between the circuit layer and the surface of the conductive pillar 80 (e.g., the surface 80u of the conductive pillar 80 described below). Due to the increased surface area, the surface roughness of the surface 111b of the dielectric layer 11 (e.g., it may be in the range of from about 3μm to about 10μm) may provide improved adhesion. The surface 111b of the dielectric layer 11 may be roughened by dry sandblasting or wet sandblasting. Using a sacrificial metal including tin (Sn) that becomes brittle at a temperature in the range of from about -30 degrees Celsius (°C) to about 13°C, the surface 111b of the dielectric layer 11 may be roughened by low-temperature sandblasting. After thinning the dielectric layer 11 and roughening the surface 111b of the dielectric layer 11, the surface roughness of the surface of the conductive pillar 80 may be in the range of from about 0.1μm to about 0.4μm.

[0031] Figure 2A to Figure 2Q Describe the method for manufacturing the Figure 1 The method of the semiconductor package 1 shown in the part 1 '. Figure 2A , a carrier 70 including a release layer 72 is provided. A sublayer 641 and a patterned conductive layer 64' are formed or disposed on an upper surface of the release layer 72. In some embodiments, the carrier 70 may include an organic material (e.g., a molding compound, bismaleimide triazine (BT), polyimide (PI), polybenzoxazole (PBO), a solder resist, Ajinomoto build-up film (ABF), polypropylene (PP), or an epoxy material) and / or an inorganic material (e.g., silicon, glass, ceramic, or quartz).

[0032] refer to Figure 2B The passivation layer 40 is formed on the patterned conductive layer 64'. In some embodiments, the passivation layer 40 includes a suitable insulating material. For example, the passivation layer 40 may include silicon nitride (SiN x ) film; however, other suitable materials may be used in addition or alternatively. In one or more embodiments, the thickness of the passivation layer 40 is in the range of about 10 μm to about 20 μm.

[0033] refer to Figure 2C , removing a portion of the passivation layer 40 by etching. The sublayer 621' and the patterned conductive layer 62' are formed on the patterned conductive layer 64' and the passivation layer 40. In some embodiments, the material of the patterned conductive layer 62' may include, for example, Cu, another metal, an alloy, or other suitable conductive materials. In some embodiments, the material of the sublayer 621' may include, for example, Cu, Ti, a titanium copper alloy (Ti / Cu), another metal, another alloy, or other suitable conductive materials.

[0034] refer to Figure 2D The photoresist layer 46' is formed by coating. In one or more embodiments, the material of the photoresist layer 46' may include, for example, a photosensitive material, positive polyimide, positive or negative photoresist, or other suitable materials.

[0035] refer to Figure 2E A photolithography etching operation is used (eg, to pattern the photoresist layer 46') to form the patterned photoresist layer 46. A portion of the patterned conductive layer 62' is exposed. The thickness of the exposed portion of the patterned conductive layer 62' is increased by plating.

[0036] refer to Figure 2F The photoresist layer 48' is formed by coating. In one or more embodiments, the material of the photoresist layer 48' may include, for example, a photosensitive material, positive polyimide, positive or negative photoresist, or other suitable materials.

[0037] refer to Figure 2G , a photolithography etching operation is used to form a portion of the patterned photoresist layer 48. The conductive pillar 80 is formed in the patterned photoresist layer 48. The conductive pillar 80 has an upper surface 80u (the upper surface 80u can be Figure 1 ). The conductive pillar 80 has a first portion 801 and a second portion 802 disposed above the first portion 801. The second portion 802 of the conductive pillar 80 is recessed from the upper surface of the patterned photoresist layer 48. In some embodiments, the conductive pillar 80 is a single-body structure, and the first portion 801 and the second portion 802 are integrally formed with each other without a detectable interface therebetween.

[0038] refer to Figure 2H, the sacrificial element 90 is formed on the upper surface 80u of the conductive pillar 80. The sacrificial element 90 may include Sn.

[0039] refer to Fig.2I , patterned photoresist layers 46 and 48 are removed by etching. Portions of patterned conductive layer 62' and sublayer 621' are removed by etching. After etching, patterned conductive layer 62 and sublayer 621 are formed. A heating operation is performed to reflow sacrificial element 90. Sacrificial element 90 contains Sn in an amount greater than about 90 weight percent (wt%), for example, about 92 wt% or greater, or about 94 wt% or greater. The melting point of sacrificial element 90 is lower than the melting point of conductive pillar 80 (for example, lower by about 10°C or greater, about 30°C or greater, or about 50°C or greater).

[0040] refer to Figure 2J , the electrical component 20 is bonded to the patterned conductive layer 62. The electrical component 20 may be bonded to the patterned conductive layer 62 by a bonding component 96 such as an adhesive or a solder element.

[0041] refer to Figure 2K , a dielectric layer 11 is formed to encapsulate the electrical component 20, the conductive pillar 80 and the sacrificial element 90. The dielectric layer 11 may include a molding material, an encapsulating material or a molding compound. The molding material / encapsulating material / molding compound may include a resin and / or a filler / particle.

[0042] refer to Figure 2L , a portion of the dielectric layer 11 is removed using compressed nitrogen at a temperature equal to or lower than about 13° C. (e.g., equal to or lower than about 8° C., equal to or lower than about 3° C., or equal to or lower than about −2° C.) to perform a sandblasting process using a powder including particles having a corresponding width between about 2 μm and about 10 μm. The powder includes one or more of a ceramic (e.g., silicon carbide, an oxide such as aluminum oxide contained in corundum, or glass), steel, iron, or a resin (e.g., plastic). In some embodiments, the portion of the dielectric layer 11 is removed by sandblasting the powder onto the dielectric layer 11 using high pressure nitrogen at a temperature equal to or lower than about −20° C. (e.g., equal to or lower than about −25° C., equal to or lower than about −30° C., or equal to or lower than about −35° C.). In some embodiments, the pressure of the nitrogen is between about 2 kilograms per square centimeter (kg / cm 2 ) to about 10kg / cm 2. Sandblasting may form a rough surface 111b having a surface profile having peaks and having indentations having a size comparable to the size of the particles used for sandblasting. In some embodiments, removing a portion of the dielectric layer 11 may include a grinding operation, dry sandblasting, and / or wet sandblasting. After grinding, the surface roughness of the surface 111b of the dielectric layer 11 may be at least or greater than about 450nm (e.g., may be about 500nm or greater, about 550nm or greater, or about 600nm or greater). The sacrificial element 90 may be removed to expose the conductive pillar 80. Removing the sacrificial element 90 and exposing the conductive pillar 80 includes melting the sacrificial element 90 by a heating operation. Removing the sacrificial element 90 may expose a wedge-shaped opening 111o of the upper surface 80u of the exposed conductive pillar 80 defined by the dielectric layer 111. The surface roughness of the rough surface 111b of the dielectric layer 11 may be substantially the same as the surface roughness of the sidewalls of the wedge-shaped opening 111o. In some embodiments, the surface roughness of the upper surface 80u of the conductive pillar 80 is in a range from about 0.1 μm to about 0.4 μm. The sacrificial element 90 may be removed by performing a heating operation to melt the sacrificial element 90. The conductive pillar 80 may include a highly ductile conductive material such as Cu, and low temperature sandblasting may not substantially damage or deform the conductive pillar 80.

[0043] refer to Figure 2M , the sub-layer 601 and the conductive layer 602' are formed on the upper surface of the dielectric layer 11. Next, a photoresist layer 49' is formed by coating. In one or more embodiments, the material of the photoresist layer 49' may include, for example, a photosensitive material, positive polyimide, a positive or negative photoresist, or other suitable materials.

[0044] refer to Figure 2N , a portion of the photoresist layer 49' is removed by photolithography and etching to form a patterned photoresist layer 49. A portion of the conductive layer 602' is exposed.

[0045] refer to Fig.2O , the patterned photoresist layer 49 is removed. The upper surface of the dielectric layer 11 is exposed. Thus, a patterned conductive layer 60 including a sub-layer 601 and a conductive layer 602' (hereinafter referred to as sub-layer 602') is formed.

[0046] refer to Figure 2P , a passivation layer 44 is formed on the patterned conductive layer 60 and the dielectric layer 11. In some embodiments, the passivation layer 44 comprises a suitable insulating material. For example, the passivation layer 44 may comprise SiN x however, other suitable materials may additionally or alternatively be used. In one or more embodiments, the thickness of the passivation layer 44 is in a range from about 10 μm to about 20 μm.

[0047] refer to Figure 2Q, solder 94 is formed in passivation layer 44. Solder 94 may be a solder bump. Thus, portion 1 ′ of semiconductor package 1 is formed.

[0048] Figures 3A to 3K Describe the method for manufacturing the Figure 1 The method of semiconductor packaging 1 shown in FIG. Figure 3A , the carrier 70 and the release layer 72 are removed.

[0049] refer to Figure 3B , sublayer 641 is removed using etching.

[0050] refer to Figure 3C The photoresist layer 47' is formed by coating. In one or more embodiments, the material of the photoresist layer 47' may include, for example, a photosensitive material, positive polyimide, positive or negative photoresist, or other suitable materials.

[0051] refer to Figure 3D The photoresist layer 47' is patterned using a photolithography etching operation to form a patterned photoresist layer 47. A portion of the patterned conductive layer 64' is exposed. The thickness of the exposed portion of the patterned conductive layer 64' is increased by plating.

[0052] refer to Figure 3E The photoresist layer 45' is formed by coating. In one or more embodiments, the material of the photoresist layer 45' may include, for example, a photosensitive material, positive polyimide, positive or negative photoresist, or other suitable materials.

[0053] refer to Figure 3F , a photolithography etching operation is used to pattern the photoresist layer 45' to form a patterned photoresist layer 45. A conductive pillar 82 is formed in the patterned photoresist layer 45. The conductive pillar 82 has an upper surface 82u. The conductive pillar 82 has a first portion 821 and a second portion 822 disposed above the first portion 821. The second portion 822 of the conductive pillar 82 is recessed from the upper surface of the patterned photoresist layer 45. In some embodiments, the conductive pillar 82 is a single body structure, and the first portion 821 and the second portion 822 are integrally formed with each other without a detectable interface therebetween.

[0054] refer to Figure 3G , the sacrificial element 92 is formed on the upper surface 82u of the conductive pillar 82. The sacrificial element 92 may include Sn.

[0055] refer to Figure 3H, patterned photoresist layers 45 and 47 are removed by etching. A portion of patterned conductive layer 64' is removed by etching, thereby forming patterned conductive layer 64. A heating operation is performed to reflow sacrificial element 92. Sacrificial element 92 contains Sn in an amount greater than about 90 wt%, such as about 92 wt% or greater, or about 94 wt% or greater. The melting point of sacrificial element 92 is lower than the melting point of conductive pillar 82 (e.g., lower by about 10°C or greater, about 30°C or greater, or about 50°C or greater).

[0056] refer to Fig. 3I , the electrical component 22 is bonded to the patterned conductive layer 64 .

[0057] refer to Figure 3J , a dielectric layer 12 is formed to encapsulate the electrical components 22, the conductive pillars 82 and the sacrificial elements 92. The dielectric layer 12 may include a molding material, an encapsulating material or a molding compound. The molding material / encapsulating material / molding compound may include a resin and / or a filler / particle.

[0058] refer to Figure 3K , using compressed nitrogen at a temperature equal to or lower than about 13° C. (e.g., equal to or lower than about 8° C., equal to or lower than about 3° C., or equal to or lower than about -2° C.) to remove a portion of the dielectric layer 12 by sandblasting a powder containing particles having a corresponding width between about 2 μm and about 10 μm. The powder includes one or more of a ceramic (e.g., silicon carbide, an oxide such as aluminum oxide contained in corundum, or glass), steel, iron, or a resin (e.g., plastic). Sandblasting may form a rough surface 121u having a surface profile having peaks and having indentations having a size comparable to the size of the particles used for sandblasting. The surface roughness of the surface 121u may be similar to or different from the surface roughness explained for the surface 111b. The portion of the dielectric layer 12 is removed by performing the following operations: using high pressure nitrogen at a temperature equal to or lower than about -20° C. (e.g., equal to or lower than about -25° C., equal to or lower than about -30° C., or equal to or lower than about -35° C.) to sandblast the powder onto the dielectric layer 12. The pressure of nitrogen is about 2kg / cm 2 About 10kg / cm 2 Next, a patterned conductive layer 68 including a sub-layer 681 and a sub-layer 682 is formed. After forming the patterned conductive layer 68, a Figure 1 The semiconductor package 1 shown in FIG.

[0059] Figure 4A schematic diagram illustrating a sandblasting apparatus according to some embodiments. Powder is input into the upper opening. Compressed nitrogen is input from the side opening. The sandblasting apparatus uses compressed nitrogen at a temperature equal to or lower than about 13°C (e.g., equal to or lower than about 8°C, equal to or lower than about 3°C, or equal to or lower than about -2°C) to sandblast powders containing particles having corresponding widths between about 2 μm and about 10 μm. In some embodiments, the temperature of the nitrogen is controlled to be equal to or lower than about -20°C (e.g., equal to or lower than about -25°C, equal to or lower than about -30°C, or equal to or lower than about -35°C). The powder comprises one or more of ceramics (e.g., silicon carbide, oxides such as aluminum oxide contained in corundum, or glass), steel, iron, or resins (e.g., plastics). As Figure 4 The powder shown in the image (a) may be a ceramic powder, and the corresponding width of its particles is between about 5 μm and about 10 μm. Figure 4 The powder shown in the image (b) may be a resin powder, and the corresponding width of its particles is between about 2 μm and about 4 μm. Figure 4 The powder shown in image (c) of FIG. 5 may be a glass powder, and the corresponding width of its particles is between about 3 μm and about 6 μm.

[0060] Figure 5 is a cross-sectional view of a semiconductor package 2 according to some embodiments of the present disclosure. The semiconductor package 2 includes dielectric layers 11 and 12, electrical components 20 and 22, insulating layers 40 and 44, patterned conductive layers 60, 62 and 64, one or more conductive pillars 80, and solder 94. The semiconductor package 2 is similar in some aspects to Figure 1 semiconductor package 1, and no longer about Figure 5 Certain details of like numbered components are described. Surface 121u of dielectric layer 12 is not roughened by sandblasting. Surface 121u of dielectric layer 12 is smoother than surface 111b of dielectric layer 11.

[0061] Figure 6 is a cross-sectional view of a semiconductor package 3 according to some embodiments of the present disclosure. The semiconductor package 3 includes dielectric layers 11 and 12, electrical components 20 and 22, insulating layers 40 and 44, patterned conductive layers 60, 62, 64 and 68, conductive pillars 80 and 82, under-bump metallization 95, and solder 94. The semiconductor package 3 is similar in some aspects to Figure 1 semiconductor package 1, and no longer about Figure 6 In some embodiments, insulating layers 40 and 44 include organic materials (e.g., PI, ABF, PP, or epoxy-based materials). In some embodiments, dielectric layers 11 and 12 include organic materials (e.g., molding compounds) and / or other suitable materials. In some embodiments, insulating layers 40 and 44 include inorganic materials (e.g., SiOx 、SiN x 、TaO x , glass, silicon or ceramic). Solder 94 is connected to the internal components of package 3 through under bump metallization 95.

[0062] Figures 7A to 7D 4a to 4d are cross-sectional views of semiconductor packages 4a to 4d according to some embodiments of the present disclosure. The semiconductor packages 4a to 4d are similar in some respects to Figure 1 semiconductor package 1, and no longer about Figures 7A to 7D Describes some details of components with the same number. Fig. 7A The electrical component 22 is attached to the insulating layer 40 using a capillary underfill (CUF) operation. The electrical component 22 is attached to the insulating layer 40 using an adhesive layer 77. Figure 7B , the electrical component 22 is attached to the insulating layer 40 using a molded underfill (MUF) operation. The electrical component 22 is encapsulated by the dielectric layer 12, and the adhesive layer may be omitted. Figure 7C , the electrical component 22 is attached to the insulating layer 40 using a CUF operation. The electrical component 22 and the adhesive layer 77 are encapsulated by the dielectric layer 12. Fig.7D , the electrical component 22 is attached to the insulating layer 40 using the adhesive layer 78. The upper surface of the electrical component 22 is electrically connected to the patterned conductive layer 64 using the wire 33 in a wire bonding process.

[0063] Figures 8A to 8C is a cross-sectional view of semiconductor packages 5a to 5c according to some embodiments of the present disclosure. The semiconductor packages 5a to 5c are similar in some respects to Figure 1 semiconductor package 1, and no longer about Figures 8A to 8C Describes some details of components with the same number. Fig. 8A , the electrical component 20 is attached to the insulating layer 40 using a CUF operation. The electrical component 20 is attached to the insulating layer 40 using an adhesive layer 77. The electrical component 20 and the adhesive layer 77 are encapsulated by the dielectric layer 11. Figure 8B , the electrical component 20 is attached to the insulating layer 40 using a MUF operation. The electrical component 20 is encapsulated by the dielectric layer 11, and the adhesive layer may be omitted. Figure 8C , the electrical component 20 is attached to the insulating layer 40 using the adhesive layer 78. The upper surface of the electrical component 20 is electrically connected to the patterned conductive layer 62 using the wire 33 in a wire bonding process.

[0064] Figures 9A to 9C 6a to 6c are cross-sectional views of semiconductor packages 6a to 6c according to some embodiments of the present disclosure. The semiconductor packages 6a to 6c are similar in some respects to Figure 1semiconductor package 1, and no longer about Figures 9A to 9C Describes some details of components with the same number. Fig.9A , the thickness of dielectric layer 12 is greater than the thickness of dielectric layer 11 (e.g., about 1.5 times or greater, about 2.5 times or greater, or about 3.5 times or greater). Fig. 9B , the thickness of the dielectric layer 12 is substantially the same as the thickness of the dielectric layer 11. Fig. 9C , the thickness of dielectric layer 12 is smaller than the thickness of dielectric layer 11 (eg, smaller by about 0.8 times or less, about 0.5 times or less, or about 0.3 times or less).

[0065] Fig. 10A and Fig. 10B is a cross-sectional view of semiconductor packages 7a and 7c according to some embodiments of the present disclosure. Semiconductor packages 7a and 7c are similar in some respects to Figure 1 semiconductor package 1, and no longer about Fig. 10A and Fig. 10B Describes some details of components with the same number. Fig. 10A , layer 100 is disposed on the upper surface of electrical component 22. Layer 100 may be a metal layer (e.g., comprising an alloy, comprising Cu, Ni, Ti, W, or Pt). Layer 100 may be a non-metal layer (e.g., PI, epoxy, oxide (SiO x 、SiN x 、TaO x ), glass, silicon or ceramic). Reference Fig. 10B , layer 100 may be omitted. The electrical components 22 are encapsulated by the dielectric layer 12 .

[0066] Fig.11 is a cross-sectional view of a semiconductor package 8a according to some embodiments of the present disclosure. The semiconductor package 8a is similar in some respects to Figure 1 semiconductor package 1, and no longer about Fig.11 Some details of like numbered components are described. The insulating layer 40 has a surface 401 and a surface 402 opposite to the surface 401. The surfaces 401 and 402 are smooth. O2 gas plasma dry etching and / or H2SO4 liquid wet etching are used to form a fine roughness interface between the dielectric layer 12 and the insulating layer 40.

[0067] FIG. 12A to FIG. 12B is a cross-sectional view of semiconductor packages 9a and 9b according to some embodiments of the present disclosure. Semiconductor packages 9a and 9b are similar in some respects to Figure 1 semiconductor package 1, and no longer about Figures 12A to 12B Describes some details of components with the same number. Fig. 12A , the upper electrical component 22 is attached to the insulating layer 40. Fig. 12B, the two upper electrical components are attached to the insulating layer 40 .

[0068] Figures 13A to 13D 1 is a cross-sectional view of semiconductor packages 10a to 10d according to some embodiments of the present disclosure. Semiconductor packages 10a and 10d are similar in some respects to Figure 1 semiconductor package 1, and no longer about Figures 13A to 13D Describes some details of components with the same number. Fig.13A , the upper electrical component is omitted. The electrical component 20 is attached to the insulating layer 40. Fig. 13B , the lower electrical component is omitted. The electrical component 22 is attached to the insulating layer 40. Fig. 13C , the two electrical components 20 and 22 are attached to the insulating layer 40. Fig.13D , no electrical components are attached to the insulating layer 40 .

[0069] Fig.14A and Fig. 14B Different types of semiconductor packages according to some embodiments of the present disclosure are described.

[0070] like Fig.14A , a plurality of chips 51 or dies are placed on a generally square carrier 52 (e.g., according to one or more embodiments described herein). In some embodiments, the carrier 52 may include an organic material (e.g., mold compound, BT, PI, PBO, solder resist, ABF, PP, or epoxy-based material) and / or an inorganic material (e.g., silicon, glass, ceramic, or quartz).

[0071] like Fig. 14B , a plurality of chips 51 or dies are placed on a generally circular carrier 53 (e.g., according to one or more embodiments described herein). In some embodiments, the carrier 53 may include an organic material (e.g., mold compound, BT, PI, PBO, solder resist, ABF, PP, or epoxy-based material) and / or an inorganic material (e.g., silicon, glass, ceramic, or quartz).

[0072] Fig.15 1a is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. In some embodiments, a difference D between the highest point of the upper surface of the dielectric layer 11 and the lowest point of the upper surface of the dielectric layer 11 is between about 10 μm and about 20 μm.

[0073] As used herein, the terms "substantially," "generally," "approximately," and "about" are used to describe and take into account small variations. When used in conjunction with an event or circumstance, the terms may refer to instances in which the event or circumstance clearly occurred as well as instances in which the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, when a first value is within a variation range of less than or equal to ±10% of a second value (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), the first value may be considered to be substantially, approximately, or approximately the same as the second value.

[0074] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transfer an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Typically, a conductive material is a material having a conductivity greater than about 104 S / m (e.g., at least 105 S / m or at least 106 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0075] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise.

[0076] In addition, amounts, ratios and other numerical values ​​are sometimes presented in this article in a range format. It should be understood that such a range format is for convenience and brevity, and should be flexibly understood to include not only the values ​​explicitly specified as range limits, but also all individual values ​​or sub-ranges contained within the range, as if each value and sub-range were explicitly specified.

[0077] If the displacement between two surfaces or sides is no greater than 0.5 μm, no greater than 1 μm, no greater than 5 μm, no greater than 10 μm, or no greater than 15 μm, then the two surfaces may be considered to be substantially aligned or coplanar. In the description of some embodiments, a component provided "on" or "over" another component may include the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

[0078] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The description may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the goals, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A method for manufacturing a semiconductor package, comprising: Providing a conductive column; forming a sacrificial element on the conductive pillar; encapsulating the sacrificial element and the conductive pillar by an encapsulant; as well as Removing a top portion of the packaging material and the sacrificial element to expose the conductive post so that an upper surface of a remaining portion of the packaging material is rough, wherein removing the top portion of the packaging material includes one or more of grinding, dry sandblasting, or wet sandblasting, and wherein removing the sacrificial element and exposing the conductive post includes using a heating operation to melt the sacrificial element. 2 . The method of claim 1 , wherein the melting point of the sacrificial element is lower than the melting point of the conductive pillar. 3 . The method of claim 2 , wherein the sacrificial element comprises tin (Sn) and the conductive pillar comprises copper (Cu).

4. The method of claim 3, wherein removing the top portion of the packaging material comprises blasting powder onto the packaging material using high pressure nitrogen gas having a temperature equal to or lower than 13° C., wherein the pressure of the nitrogen gas is between 2 kg / cm 2 Up to 10kg / cm 2 in the range between.

5. The method of claim 3, wherein removing the top portion of the packaging material comprises using compressed nitrogen having a temperature equal to or lower than -20°C to blast powder onto the packaging material, wherein the powder comprises particles and respective widths of the particles are between 2 μm and 10 μm, wherein the powder comprises one or more of ceramic, steel, iron or resin. The method according to claim 5 , wherein the temperature of the nitrogen gas is less than -30° C. 7 . 7 . The method of claim 3 , wherein after removing the top portion of the encapsulation material, the surface roughness of the upper surface of the conductive pillar ranges from 0.1 μm to 0.4 μm.

8. The method of claim 3, wherein the sacrificial element comprises Sn in an amount greater than 90 weight percent.

9. The method of claim 1 , wherein removing the top portion of the packaging material comprises forming a wedge-shaped opening having sidewalls and exposing an upper surface of the conductive pillar, and further comprises causing a surface roughness of the upper surface of the remaining portion of the packaging material to be substantially the same as a surface roughness of the sidewalls of the wedge-shaped opening.

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