Semiconductor substrate, semiconductor packaging structure, and method for manufacturing semiconductor device

Abstract

A semiconductor substrate comprises a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer comprises at least one conductive segment. The conductive segment comprises a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor substrates, semiconductor packaging structures and manufacturing processes, and more particularly, to an embedded trace substrate (ETS), a semiconductor packaging structure including the ETS and a manufacturing process for manufacturing the same semiconductor packaging structure and / or the same ETS. Background Art

[0002] With the rapid development of the electronics industry and the progress of semiconductor processing technology, semiconductor chips are integrated with more and more electronic components to achieve better electrical performance and more functions. Therefore, semiconductor chips have more input / output (I / O) connectors. In order to manufacture a semiconductor package containing a semiconductor chip with a large number of I / O connectors, the size of the semiconductor chip and the semiconductor package can be correspondingly increased. Therefore, the manufacturing cost may increase accordingly. In addition, in order to minimize the size of the semiconductor package containing a semiconductor chip with a large number of I / O connectors, the bonding pad density of the semiconductor substrate for carrying the semiconductor chip can be correspondingly increased. Therefore, the line width / line space (L / S) of the circuit layer of the semiconductor substrate can be reduced. Summary of the invention

[0003] In some embodiments, according to one aspect, a semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. The width of the first portion of the conductive segment is different from the width of the second portion of the conductive segment. The angle between the sidewall of the conductive segment and the first surface of the first dielectric structure may be greater than 90 degrees.

[0004] In some embodiments, according to one aspect, a semiconductor package structure includes a semiconductor substrate and a semiconductor die. The semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. The width of the first portion of the conductive segment is different from the width of the second portion of the conductive segment. The angle between the sidewall of the conductive segment and the first surface of the first dielectric structure may be greater than 90 degrees. The line width / line spacing (L / S) of the first circuit layer is less than or equal to about 2μm / 2μm. The semiconductor die is attached to the semiconductor substrate and electrically connected to the first circuit layer.

[0005] In some embodiments, according to another aspect, a method for manufacturing a semiconductor device includes: (a) providing a stacked structure, wherein the stacked structure includes a first outermost layer, at least one intermediate layer and a second outermost layer, the second outermost layer is opposite to the first outermost layer, the refractive index of the stacked structure gradually increases from the first outermost layer through the at least one intermediate layer to the second outermost layer, and the second outermost layer is a photoresist layer; (b) emitting a light beam near the first outermost layer to pass through the first outermost layer and the intermediate layer to irradiate the second outermost layer; (c) developing the second outermost layer to form a plurality of openings; and (d) sputtering a metal structure in the opening of the second outermost layer to form a first circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features of some embodiments of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various structures may not be drawn to scale, and that the dimensions of various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A top view illustrating an example of a portion of a semiconductor substrate according to some embodiments of the present disclosure.

[0008] Figure 2 Instructions along the Figure 1 A cross-sectional view of an example of a portion of a semiconductor substrate taken along line II.

[0009] Figure 3 illustrate Figure 2 Magnified view of area "A".

[0010] Figure 4 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer according to some embodiments of the present disclosure.

[0011] Figure 5 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer according to some embodiments of the present disclosure.

[0012] Figure 6 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer according to some embodiments of the present disclosure.

[0013] Figure 7 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer according to some embodiments of the present disclosure.

[0014] Figure 8 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0015] Fig. 9 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0016] Fig.10 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0017] Fig.11 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0018] Fig.12 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0019] Fig.13 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0020] Fig.14 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0021] Fig.15 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0022] Fig.16 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0023] Fig.17 illustrate Fig.16 A magnified view of .

[0024] Fig.18 Simulation results of example scenarios according to some embodiments of the present disclosure are illustrated.

[0025] Fig.19 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0026] Fig. 20 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0027] Fig.21 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0028] Fig. 22 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0029] Fig.23 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0030] Fig.24 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0031] Fig.25 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0032] Fig.26 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0033] Fig. 27 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0034] Fig.28 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0035] Fig.29 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0036] Fig.30 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0037] Fig.31 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0038] Fig.32One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0039] Fig.33 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0040] Fig.34 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0041] Fig.35 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0042] Fig.36 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0043] Fig.37 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0044] Fig.38 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described.

[0045] Fig.39 One or more stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described. DETAILED DESCRIPTION

[0046] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar elements. Embodiments of the present disclosure will be readily understood from the following detailed description made in conjunction with the accompanying drawings.

[0047] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed or arranged in direct contact, and may also include an embodiment in which an additional feature may be formed or arranged between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0048] At least some embodiments of the present disclosure are directed to a semiconductor substrate including conductive segments that do not have a uniform width. A first portion of the conductive segment has a width that is different from a second portion of the conductive segment that is opposite the first portion. At least some embodiments of the present disclosure are directed to a technique for manufacturing a semiconductor substrate.

[0049] In a comparative fan-out ETS, the line width / line spacing (L / S) of the fine-line circuit layer can be about 2 microns (μm) / about 2 μm, or about 3 μm / about 3 μm. A comparative process for manufacturing this ETS may include the following steps. A seed layer (e.g., a copper (Cu) layer and / or a titanium (Ti) layer) is disposed on a release layer of a carrier (e.g., a silicon (Si) carrier or a glass carrier). A photoresist layer is disposed on the seed layer and is patterned by, for example, exposure and development to form a plurality of openings to expose one or more portions of the seed layer. It should be noted that during the exposure process, a light beam directly irradiates the photoresist layer through air close to the photoresist layer. A conductive metal (e.g., Cu) is plated on the exposed portion of the seed layer in the opening of the photoresist layer. The photoresist layer is removed. The portion of the seed layer not covered by the conductive metal is removed by etching to form a fine-line circuit layer.

[0050] However, during the manufacturing process, warping may occur due to a mismatch in the coefficient of thermal expansion (CTE) between the carrier, the seed layer, and the photoresist layer. That is, before the exposure step, the carrier, the seed layer, and the photoresist layer may undergo at least one thermal process, and the deformation of the carrier, the seed layer, and the photoresist layer caused by the thermal process is different. For example, the deformation of the photoresist layer may be greater than the deformation of the seed layer. Therefore, due to the warping, it is difficult to accurately control the size of the opening of the photoresist layer during the exposure and development processes. Therefore, it is difficult to accurately control the size of the fine line circuit layer. Therefore, the yield of the fine line circuit layer will be less than 100%. The yield loss of the fine line circuit layer will produce a defective final packaging structure and increase the cost of this fan-out process. In addition, wet processes, such as plating and etching, can further increase the cost of this fan-out process. In addition, although a laser directing image (LDI) technique may be used in the exposure process, the L / S of the fine line circuit layer cannot be effectively reduced due to the resolution limitation of the photoresist layer.

[0051] The present disclosure at least solves the above problems and provides an improved semiconductor substrate, and an improved technology for manufacturing a semiconductor substrate and / or an ETS. In the manufacturing process, a stacked structure including a first outermost layer, at least one intermediate layer and a second outermost layer is arranged, wherein the second outermost layer is opposite to the first outermost layer. The refractive index of the stacked structure gradually increases from the first outermost layer to the second outermost layer. A light beam approaching the first outermost layer passes through the first outermost layer and the intermediate layer and irradiates the second outermost layer. The second outermost layer is developed to form a plurality of openings. A fine-line circuit layer is formed in the opening of the second outermost layer. Due to the gradually increasing refractive index of the stacked structure, the exposure area of ​​the light beam decreases as the light beam travels through the stacked structure and is refracted at the boundary between the layers. Therefore, the second outermost layer can be accurately exposed and developed by a light beam with a small exposure area, and there is no need to use materials with different CTEs in the layers of the stacked structure. The features on the second outermost layer (including, for example, a photoresist) after exposure and development can be small in size due to the reduced exposure area of ​​the light beam. Therefore, the CTE mismatch problem is reduced or eliminated, and the manufacturing process can accurately control the size of the opening of the second outermost layer. Therefore, it is easy to accurately control the size of the fine line circuit layer. Therefore, the yield of the fine line circuit layer is efficiently improved. In addition, no wet process such as plating and etching is performed, which further reduces the cost of this fan-out process. In addition, laser alignment image (LDI) can be used in the exposure process.

[0052] Figure 1 A top view illustrating an example of a portion of a semiconductor substrate 1 according to some embodiments of the present disclosure. Figure 2 Instructions along the Figure 1 FIG. 1 is a cross-sectional view of an example of a portion of a semiconductor substrate 1 taken along line II of FIG. The semiconductor substrate 1 may be a fan-out ETS and include a first dielectric structure 12, a first circuit layer 2, a barrier layer 3, a second circuit layer 14, a plurality of second vias 143, a second dielectric structure 16, a third circuit layer 18, a plurality of third vias 183, and a third dielectric structure 19.

[0053] The first dielectric structure 12 may be a passivation layer, and may include a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as polyamide (PA), Ajinomoto build-up film (ABF), bismaleimide-triazine (BT), polyimide (PI), epoxy resin, or polybenzoxazole (PBO), or a combination of two or more thereof, or may be formed of the foregoing. In one or more embodiments, the first dielectric structure 12 may include a dry film type material including a resin and a plurality of fillers, or may be formed of the material. In another embodiment, the first dielectric structure 12 may include a liquid type material including a homogeneous resin without a filler, or may be formed of the material. In some embodiments, the material of the first dielectric structure 12 may include an inorganic material (e.g., SiO x 、SiN x 、TaO x ), glass, silicon, ceramic, or a combination of two or more thereof. Figure 1 As shown in FIG. 1 , the first dielectric structure 12 may have a first surface 121 and a second surface 122 opposite to the first surface 121. Figure 2 , the first dielectric structure 12 may define a plurality of recessed portions 123 and a plurality of openings 124. The recessed portions 123 are recessed from the first surface 121 of the first dielectric structure 12 and do not extend through (or through) the first dielectric structure 12. The openings 124 are recessed from the second surface 122 of the first dielectric structure 12 and do not extend through the first dielectric structure 12. The positions of the openings 124 correspond to the positions of at least some of the recessed portions 123. For example, the openings 124 may be disposed below at least some of the recessed portions 123. In one embodiment, the thickness of the first dielectric structure 12 may be in a range of about 5 μm to about 10 μm, about 2 μm to about 20 μm, about 1 μm to about 50 μm, or about 0.5 μm to about 100 μm.

[0054] The first circuit layer 2 is embedded in the first dielectric structure 12 and includes a first surface 21 and a second surface 22 opposite to the first surface 21. The first circuit layer 2 is disposed in the groove portion 123 of the first dielectric structure 12 and does not protrude from the first surface 121 of the first dielectric structure 12. A portion of the first circuit layer 2 (e.g., the first surface 21) is exposed from the first surface 121 of the first dielectric structure 12. For example, the first dielectric structure 12 does not cover the first surface 21 of the first circuit layer 2. In addition, a portion of the first circuit layer 2 (e.g., the second surface 22) may be exposed from the opening 124 of the first dielectric structure 12. Figure 2 As shown in FIG. 1 , the first surface 21 of the first circuit layer 2 is substantially coplanar with the first surface 121 of the first dielectric structure 12 . However, in some embodiments, the first surface 21 of the first circuit layer 2 may be recessed from the first surface 121 of the first dielectric structure 12 .

[0055] The first circuit layer 2 may include at least one conductive segment. Figure 1 and Figure 2 As shown in

[0056] The first circuit layer 2 may include a plurality of conductive segments. The conductive segments may include, for example, a plurality of conductive traces 23 and / or a plurality of bonding pads 24. In one or more embodiments, the line width / line spacing (L / S) of the first circuit layer 2 may be equal to or less than about 2 μm / about 2 μm (e.g., about 1.8 μm / about 1.8 μm or less, about 1.6 μm / about 1.6 μm or less, or about 1.4 μm / about 1.4 μm or less), equal to or less than about 1 μm / about 1 μm, or equal to or less than about 0.5 μm / about 0.5 μm. In addition, the surface roughness value of the first surface 21 of the first circuit layer 2 (e.g., according to the root mean square surface roughness) may be in the range of from about 5 nanometers (nm) to about 55 nm, from about 2 nm to about 80 nm, or from about 1 nm to about 100 nm.

[0057] like Figure 2 , each or at least one conductive segment of the first circuit layer 2 (e.g., conductive trace 23 or bonding pad 24) includes a first metal structure 27 and a second metal structure 28. The second metal structure 28 is disposed on the first metal structure 27. In some embodiments, the material of the first metal structure 27 is titanium (Ti), and the material of the second metal structure 28 is copper (Cu). The thickness of the first metal structure 27 may be greater than or equal to about 0.1 μm, and the thickness of the second metal structure 28 may be greater than or equal to about 0.2 μm. In some embodiments, the thickness of the first metal structure 27 may be in a range of about 0.1 μm to about 0.2 μm, about 0.05 μm to about 0.25 μm, or about 0.02 μm to about 0.28 μm; and the thickness of the second metal structure 28 may be in a range of about 0.2 μm to about 0.3 μm, about 0.15 μm to about 0.35 μm, or about 0.12 μm to about 0.38 μm.

[0058] The barrier layer 3 is disposed on one or more conductive segments (e.g., conductive traces 23 and / or bonding pads 24) of the first circuit layer 2. In some embodiments, the barrier layer 3 includes a nickel layer 31 and a gold layer 32. The nickel layer 31 is disposed on the conductive segments (e.g., conductive traces 23 and / or bonding pads 24), and the gold layer 32 is disposed on the nickel layer 31. Therefore, the nickel layer 31 is disposed between the gold layer 32 and the conductive segments (e.g., conductive traces 23 and / or bonding pads 24). In some embodiments, the surface roughness value of the first surface 311 of the nickel layer 31 is in the range of about 200 nm to about 300 nm, and the surface roughness value of the first surface 321 of the gold layer 32 is in the range of about 50 nm to about 200 nm. In some other embodiments, the materials of the layers 31 and 32 may include conductive materials other than nickel or gold.

[0059] The second circuit layer 14 is disposed on the conductive trace 23 of the first circuit layer 2 in the opening 124 of the first dielectric structure 12, and is disposed on the second surface 122 of the first dielectric structure 12. In some embodiments, a portion of the second circuit layer 14 is disposed in the opening 124 of the first dielectric structure 12 to form at least one second via 143, and the other portion of the second circuit layer 14 is disposed on the second surface 122 of the first dielectric structure 12 to form a second patterned layer 144 that may include at least one conductive trace and / or at least one bonding pad. The second via 143 is electrically connected to and in contact with the conductive trace 23 of the first circuit layer 2. Therefore, the second circuit layer 14 is electrically connected to the first circuit layer 2 through the second via 143.

[0060] The second guide hole 143 may be a tapered structure tapered from the second surface 122 of the first dielectric structure 12 toward the first surface 121 of the first dielectric structure 12. The second guide hole 143 may define a central hole 1431. The second guide hole 143 and the second patterned layer 144 may be integrally formed and formed simultaneously. The L / S of the second circuit layer 14 may be less than, for example, about 7 μm / about 7 μm, about 5 μm / about 5 μm, or about 2 μm / about 2 μm. The L / S of the second circuit layer 14 may be greater than the L / S of the first circuit layer 2.

[0061] like Figure 2, the second circuit layer 14 includes a second seed layer 15 and a second metal layer 141. The second seed layer 15 is disposed on and in contact with the conductive trace 23 of the first circuit layer 2 in the opening 124 of the first dielectric structure 12, and is disposed on and in contact with the second surface 122 of the first dielectric structure 12. The second metal layer 141 is disposed on the second seed layer 15. In some embodiments, the second seed layer 15 may have a double-layer structure (or a multi-layer structure), and may include a first layer 151 and a second layer 152. The material of the first layer 151 may be titanium (Ti), the material of the second layer 152 may be copper (Cu), and the material of the second metal layer 141 may be copper (Cu). It should be noted that the second guide hole 143 may include at least a portion of the second seed layer 15 and the second metal layer 141, and the second patterned layer 144 may include at least a portion of the second seed layer 15 and the second metal layer 141.

[0062] The second dielectric structure 16 may be a dielectric layer, which may include, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, other suitable materials or combinations thereof. The second dielectric structure 16 may be or may include, for example, a thin sheet made of pre-impregnated composite fibers. For example, the second dielectric structure 16 may include a cured fiber reinforced resin. It should be noted that the second dielectric structure 16 may include or be formed of a cured PID material such as an epoxy resin or a PI containing a photoinitiator. The material of the second dielectric structure 16 may be the same as or different from the material of the first dielectric structure 12. The thickness of the second dielectric structure 16 may be, for example, about 50 μm to about 100 μm, about 30 μm to about 120 μm, or about 10 μm to about 150 μm.

[0063] The second dielectric structure 16 includes a first surface 161 and a second surface 162 opposite to the first surface 161. The second dielectric structure 16 covers the second circuit layer 14 and the second surface 122 of the first dielectric structure 12. Therefore, the first surface 161 of the second dielectric structure 16 contacts the second surface 122 of the first dielectric structure 12, and at least a portion of the second dielectric structure 16 extends into the central hole 1431 of the second guide hole 143 of the second circuit layer 14. In addition, the second dielectric structure 16 defines a plurality of openings 163 to expose portions of the second circuit layer 14 (e.g., portions corresponding to the second metal layer 141). The openings 163 of the second dielectric structure 16 may extend through the second dielectric structure 16.

[0064] The third circuit layer 18 is disposed on the exposed portion of the second circuit layer 14 in the opening 163 of the second dielectric structure 16, and is disposed on the second surface 162 of the second dielectric structure 16. In some embodiments, a portion of the third circuit layer 18 is disposed in the opening 163 of the second dielectric structure 16 to form at least one third via 183, and the other portion of the third circuit layer 18 is disposed on the second surface 162 of the second dielectric structure 16 to form a second patterned layer 184 that may include at least one conductive trace and / or at least one bonding pad. The third via 183 is electrically connected to and in contact with the second circuit layer 14. Therefore, the third circuit layer 18 is electrically connected to the second circuit layer 14 through the third via 183.

[0065] The third guide hole 183 may be a wedge-shaped structure that tapers from the second surface 162 of the second dielectric structure 16 toward the first surface 161 of the second dielectric structure 16. The third guide hole 183 may define a concave portion 1831 at its bottom end. The third guide hole 183 and the third patterned layer 184 may be integrally formed and formed simultaneously. The L / S of the third circuit layer 18 may be greater than, for example, about 5 μm / about 5 μm, about 7 μm / about 7 μm, or about 10 μm / about 10 μm. The L / S of the third circuit layer 18 may be greater than the L / S of the second circuit layer 14.

[0066] like Figure 2 , the third circuit layer 18 may include a third seed layer 17 and a third metal layer 181. The third seed layer 17 is disposed on and in contact with the exposed portion of the second circuit layer 14 in the opening 163 of the second dielectric structure 16, and is disposed on and in contact with the second surface 162 of the second dielectric structure 16. The third metal layer 181 is disposed on the third seed layer 17. In some embodiments, the third seed layer 17 may be a single-layer structure or a double-layer structure (or a multi-layer structure). For example, the third seed layer 17 may include a titanium (Ti) layer and a copper (Cu) layer. It should be noted that the third guide hole 183 may include at least a portion of the third seed layer 17 and the third metal layer 181, and the third patterned layer 184 may include at least a portion of the third seed layer 17 and the third metal layer 181. In some other embodiments, the material of layer 17 may include a conductive material other than titanium or copper.

[0067] The third dielectric structure 19 may be a passivation layer, and may include a photoresist layer, a cured photosensitive material, a cured PID material such as PA, ABF, BT, PI, epoxy resin, or PBO, or a combination of two or more thereof, or may be formed of the foregoing. In one or more embodiments, the third dielectric structure 19 may include a dry film type material including a resin and a plurality of fillers, or may be formed of the material. In another embodiment, the third dielectric structure 19 may include a liquid type material including a homogeneous resin without a filler, or may be formed of the material. In some embodiments, the material of the third dielectric structure 19 may include an inorganic material (e.g., SiO x 、SiN x 、TaO x ), glass, silicon, ceramic, or a combination of two or more thereof. The material of the third dielectric structure 19 may be the same as or different from the material of the first dielectric structure 12. The thickness of the third dielectric structure 19 may be, for example, about 5 μm to about 10 μm, about 3 μm to about 12 μm, or about 1 μm to about 15 μm.

[0068] The third dielectric structure 19 includes a first surface 191 and a second surface 192 opposite to the first surface 191. The third dielectric structure 19 covers the third circuit layer 18 and the second surface 162 of the second dielectric structure 16. Therefore, the first surface 191 of the third dielectric structure 19 contacts the second surface 162 of the second dielectric structure 16. A portion of the third dielectric structure 19 extends into the recessed portion 1831 of the third via 183 of the third circuit layer 18. In addition, the third dielectric structure 19 defines a plurality of openings 193 to expose portions of the third circuit layer 18 (e.g., portions corresponding to the third metal layer 181).

[0069] In some embodiments, the barrier layer 3 may be formed in the opening 193 ( Figure 2 The nickel layer 31 is disposed on the exposed portion of the third circuit layer 18, and the gold layer 32 is disposed on the nickel layer 31. Therefore, the nickel layer 31 is disposed between the gold layer 32 and the third circuit layer 18.

[0070] Figure 3 illustrate Figure 2. The conductive segment (e.g., conductive trace 23 or bonding pad 24) includes a first portion 25 (e.g., a first end) and a second portion 26 (e.g., a second end). The first portion 25 is disposed proximate to or adjacent to the first surface 121 of the first dielectric structure 12, and the second portion 26 is opposite to the first portion 25. That is, the second portion 26 is further away from the first surface 121 of the first dielectric structure 12 than the first portion 25. The width of the first portion 25 of the conductive segment (e.g., conductive trace 23 and / or bonding pad 24) may be different from the width of the second portion 26 of the conductive segment (e.g., conductive trace 23 and / or bonding pad 24).

[0071] like Figure 3 , the width of the first portion 25 of the conductive segment adjacent to the first surface 21 (e.g., the conductive trace 23 or the bonding pad 24) may be greater than the width of the second portion 26 of the conductive segment adjacent to the second surface 22 (e.g., the conductive trace 23 or the bonding pad 24) by about 1.05 times or more, about 1.1 times or more, or about 1.2 times or more. The conductive segment (e.g., the conductive trace 23 or the bonding pad 24) tapers from the first surface 21 to the second surface 22. The conductive segment (e.g., the conductive trace 23 or the bonding pad 24) may be in an inverted trapezoidal shape. In other words, the conductive segment (e.g., the conductive trace 23 or the bonding pad 24) tapers from the first surface 121 of the first dielectric structure 12 toward the second surface 122 of the first dielectric structure 12. The angle between the sidewall of the conductive segment (e.g., the conductive trace 23 or the bonding pad 24) and the first surface 121 of the first dielectric structure 12 may be greater than about 90 degrees, about 95 degrees or more, or about 100 degrees or more.

[0072] like Figure 2 and Figure 3 , the second via 143 tapers in a direction opposite to the direction in which the conductive segments (e.g., conductive traces 23 and bonding pads 24) of the first circuit layer 2 taper. For example, the second via 143 is an upward tapered structure (e.g., tapered from the second surface 122 of the first dielectric structure 12 toward the first surface 121 of the first dielectric structure 12), and the conductive segments (e.g., conductive traces 23 and bonding pads 24) of the first circuit layer 2 are downward tapered structures (e.g., tapered from the first surface 121 of the first dielectric structure 12 toward the second surface 122 of the first dielectric structure 12).

[0073] In addition, the first metal structure 27 may be in an inverted trapezoidal shape. That is, the width of the upper portion of the first metal structure 27 is greater than the width of the lower portion of the first metal structure 27. The first metal structure 27 tapers from its top surface to its bottom surface. In addition, the second metal structure 28 further extends to cover and contact at least a portion of the side surface of the first metal structure 27. Therefore, the second metal structure 28 defines a cavity corresponding to the first metal structure 27, and the second metal structure 28 is, for example, in a bowl shape or an inverted hat shape. The width of the second surface 22 is defined as "W", and the leftmost point of the second surface 22 is defined as "B", and the leftmost point of the first surface 21 is defined as "C". The gap between point B and point C is defined as "G", and G is between 0% to about 5% of W, between 0% to about 10% of W, or between 0% to about 15% of W. Therefore, the difference between the width W of the first surface 21 and the width W of the second surface 22 is between 0% and about 10% of W, between 0% and about 20% of W, or between 0% and about 30% of W.

[0074] exist Figures 1 to 3 In the embodiment described in, the shape and size of the conductive segments (e.g., conductive traces 23 and / or bonding pads 24) of the first circuit layer 2 are specified by the manufacturing process as described below. In the manufacturing process, a light beam is provided to pass through a stacked structure with a gradually increasing refractive index. Therefore, the CTE mismatch problem is reduced or eliminated, and the technology can be used to accurately control the size of the opening of the photoresist layer in the exposure step and / or the development step. Therefore, the technology can be used to accurately control the size of the first circuit layer 2 formed in the opening of the photoresist layer. Therefore, the L / S of the first circuit layer 2 can be reduced, and the yield of the first circuit layer 2 can be efficiently improved.

[0075] Figure 4 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer 2a according to some embodiments of the present disclosure. Figure 4 The first circuit layer 2a is similar to Figures 1 to 3 The first circuit layer 2 shown in FIG. 1 is a single-layer structure instead of a double-layer structure except that the conductive segments (eg, conductive traces 23a and / or bonding pads) of the first circuit layer 2a are single-layer structures.

[0076] Figure 4 As shown in FIG. 1 , the conductive segments (e.g., conductive traces 23a and / or bonding pads) of the first circuit layer 2a include a second metal structure 28a, which may be, for example, copper (Cu) (or another suitable conductive material). That is, the second metal structure 28a may be a single layer and may substantially fill the recessed portion 123 of the first dielectric structure 12.

[0077] The conductive segment (e.g., conductive trace 23a and / or bonding pad 24) may include a first portion 25a and a second portion 26a. The first portion 25a is disposed close to or adjacent to the first surface 121 of the first dielectric structure 12, and the second portion 26a is opposite to the first portion 25a. Because the first circuit layer 2a is a single body structure, the first portion 25a and the second portion 26a may be formed of the same material (e.g., Cu), and may be integrally formed and formed simultaneously. The width of the first portion 25a of the conductive segment (e.g., conductive trace 23a and / or bonding pad) is greater than the width of the second portion 26a of the conductive segment (e.g., conductive trace 23a and / or bonding pad). Therefore, the width of the first portion 25a of the second metal structure 28a is greater than the width of the second portion 26a of the second metal structure 28a. The top surface of the second metal structure 28a is the first surface 21 of the conductive segment (e.g., conductive trace 23a or bonding pad). The surface roughness value of the first surface 21 of the first circuit layer 2a (eg, the top surface of the second metal structure 28a) ranges from about 5 nanometers (nm) to about 55 nm, from about 2 nm to about 80 nm, or from about 1 nm to about 100 nm.

[0078] Figure 5 An enlarged view of a region of a cross-sectional view illustrating an example of portion 2b of a first circuit layer according to some embodiments of the present disclosure. Figure 5 The first circuit layer 2b is similar to Figures 1 to 3 The first circuit layer 2 shown in FIG. 1 is a single-layer structure instead of a double-layer structure except that the conductive segments (eg, conductive traces 23b and / or bonding pads) of the first circuit layer 2b are single-layer structures. Figure 5 As shown in the figure, it can be omitted Figure 3 Thus, the conductive segments (e.g., conductive traces 23b and / or bonding pads) of the first circuit layer 2b may include a second metal structure 28b, which may be, for example, copper (Cu) (or another suitable conductive material). In some embodiments, the second metal structure 28b of the first circuit layer 2b may be connected to the conductive segments 23b and / or bonding pads. Figure 3 The second metal structure 28 of the first circuit layer 2 is similar or identical. Figure 5 In the embodiment, the second metal structure 28b may be a single layer and may not fill or may fill a portion of the recessed portion 123 of the first dielectric structure 12. The width of the first portion 25b of the conductive segment (e.g., conductive trace 23b and / or bonding pad) is greater than the width of the second portion 26b of the conductive segment (e.g., conductive trace 23b and / or bonding pad). Therefore, the width of the first portion 25b of the second metal structure 28b is greater than the width of the second portion 26b of the second metal structure 28b.

[0079] like Figure 5As shown in FIG. 1 , the first portion 25b of the conductive segment (e.g., conductive trace 23b or bonding pad) defines a cavity 233 that is recessed from the first surface 121 of the first dielectric structure 12. Therefore, the first surface 21 of the first circuit layer 2b is recessed from the first surface 121 of the first dielectric structure 12. The first surface 21 of the first circuit layer 2b defines the cavity 233. The cavity 233 has a first portion 2331 close to the first surface 121 of the first dielectric structure 12 and a second portion 2332 opposite to the first portion 2331. The width of the first portion 2331 of the cavity 233 is greater than the width of the second portion 2332 of the cavity 233. In addition, the barrier layer 3 is disposed in the cavity 233 of the conductive segment (e.g., conductive trace 23b and / or bonding pad) of the first circuit layer 2b. In some embodiments, the barrier layer 3 includes a nickel layer 31 and a gold layer 32. The nickel layer 31 is disposed in the cavity 233 of the conductive segment (e.g., conductive trace 23b and / or bonding pad) of the first circuit layer 2b, and the gold layer 32 is disposed on the nickel layer 31. Therefore, the nickel layer 31 is disposed between the gold layer 32 and the conductive segment (e.g., conductive trace 23b and / or bonding pad) of the first circuit layer 2b.

[0080] Figure 6 An enlarged view of a region of a cross-sectional view illustrating an example of a portion of a first circuit layer 2c according to some embodiments of the present disclosure. Figure 6 The first circuit layer 2c is similar to Figures 1 to 3 The first circuit layer 2 shown in FIG. 1 is shaped like an inverted triangle except that the conductive segments (eg, conductive traces 23c and / or bonding pads) of the first circuit layer 2c are shaped like an inverted triangle. Figure 6 As shown in FIG. 1 , the conductive segment (e.g., conductive trace 23c and / or bonding pad 24) of the first circuit layer 2c may include a first metal structure 27c and a second metal structure 28c. The second metal structure 28c is disposed on the first metal structure 27c. In some embodiments, the material of the first metal structure 27c is titanium (Ti), and the material of the second metal structure 28c is copper (Cu). In addition, the conductive segment (e.g., conductive trace 23c and / or bonding pad) may include a first portion 25c and a second portion 26c. The first portion 25c is disposed close to or adjacent to the first surface 121 of the first dielectric structure 12, and the second portion 26c is opposite to the first portion 25c. The width of the first portion 25c of the conductive segment (e.g., conductive trace 23c and / or bonding pad) is greater than the width of the second portion 26c of the conductive segment (e.g., conductive trace 23c and / or bonding pad).

[0081] Figure 7 A cross-sectional view illustrating an example of a portion of a semiconductor substrate 1 a according to some embodiments of the present disclosure. Figure 7 The semiconductor substrate 1a is similar to Figures 1 to 3 The semiconductor substrate 1 shown in FIG. 1 is formed in a columnar shape except that the third guide hole 183a of the third circuit layer 18 is formed in a columnar shape. Figure 7 As shown in , the third guide hole 183a can have a substantially uniform width.

[0082] Figure 8 1 is a cross-sectional view illustrating an example of a semiconductor package structure 4 according to some embodiments of the present disclosure. The semiconductor package structure 4 includes a semiconductor substrate 1, a semiconductor die 42, an encapsulant 44, and a plurality of external connectors 46. The semiconductor substrate 1 may be connected to a semiconductor die 42, such as a semiconductor die 42, and a semiconductor die 42. Figures 1 to 3 is similar or identical to the semiconductor substrate 1 shown in . Alternatively or additionally, Figure 8 The semiconductor substrate 1 may be, for example, a first circuit layer 2a ( Figure 4 ) of a semiconductor substrate, comprising a first circuit layer 2b ( Figure 5 ) of a semiconductor substrate, comprising a first circuit layer 2c ( Figure 6 ) of a semiconductor substrate, or Figure 7 The semiconductor substrate 1a is replaced.

[0083] The semiconductor die 42 is attached to the semiconductor substrate 1 and is electrically connected to the first circuit layer 2. Figure 8 As shown in FIG. 4 , the semiconductor die 42 has an active surface 421, a backside surface 422, a lateral surface 423, and a plurality of conductive bumps 424. The backside surface 422 is opposite to the active surface 421. The lateral surface 423 extends between the active surface 421 and the backside surface 422. The conductive bumps 424 are disposed adjacent to the active surface 421. Each or at least one of the conductive bumps 424 contacts the nickel layer 31 of the barrier layer 3 on a conductive segment (e.g., bonding pad 24) of the first circuit layer 2. Therefore, the semiconductor die 42 is attached to the semiconductor substrate 1 by flip chip bonding, and the semiconductor die 42 is electrically connected to the first circuit layer 2 of the semiconductor substrate 1 through the conductive bumps 424 and the barrier layer 3. In addition, a plurality of solders 45 cover the lower ends of the conductive bumps 424 and the barrier layer 3 to ensure bonding between the conductive bumps 424 and the barrier layer 3.

[0084] The package body 44, such as a molding compound, covers the semiconductor die 42 and the semiconductor substrate 1. In some embodiments, the package body 44 covers the first surface 121 of the first dielectric structure 12, a portion (e.g., an upper end) of the conductive bump 424, an active surface 421 of the semiconductor die 42, and a side surface 423 of the semiconductor die 42. The first surface 441 of the package body 44 may be substantially coplanar with the back surface 422 of the semiconductor die 42. Therefore, the back surface 422 of the semiconductor die 42 is exposed from the first surface 441 of the package body 44. External connectors 46 (e.g., solder bumps or solder balls) may be disposed in corresponding openings in the openings 193 of the third dielectric structure 19 to contact the barrier layer 3 on the third circuit layer 18 for external connection.

[0085] Fig. 9 A cross-sectional view illustrating an example of a semiconductor package structure 4a according to some embodiments of the present disclosure. Fig. 9 The semiconductor package structure 4a is similar to Figure 8 , except that the underfill material 47 is disposed in the space between the active surface 421 of the semiconductor die 42 and the first surface 121 of the first dielectric structure 12 to cover the upper end of the conductive bump 424 and the solder 45. The package body 44 covers the underfill material 47, the first surface 121 of the first dielectric structure 12 and the side surface 423 of the semiconductor die 42.

[0086] Fig.10 A cross-sectional view illustrating an example of a semiconductor package structure 4b according to some embodiments of the present disclosure. Fig.10 The semiconductor package structure 4b is similar to Fig. 9 The semiconductor package structure 4a shown in FIG. Fig.10 The package 44b is other than a gel type.

[0087] Fig.11 A cross-sectional view illustrating an example of a semiconductor package structure 4c according to some embodiments of the present disclosure. Fig.11 The semiconductor package structure 4c is similar to Figure 8 The semiconductor package structure 4 shown in Fig.11 The semiconductor substrate 1c is omitted Figure 8The third dielectric structure 19 covers the second circuit layer 14 and the second surface 122 of the first dielectric structure 12. The first surface 191 of the third dielectric structure 19 contacts the second surface 122 of the first dielectric structure 12, and a portion of the third dielectric structure 19 extends into the central hole 1431 of the second guide hole 143 of the second circuit layer 14. In addition, the opening 193 of the third dielectric structure 19 exposes a portion of the second circuit layer 14 (e.g., a portion corresponding to the second metal layer 141). The barrier layer 3 may be disposed on the exposed portion of the second circuit layer 14 (e.g., a portion corresponding to the second metal layer 141) in the opening 193 of the third dielectric structure 19. An external connector 46 (e.g., a solder bump or a solder ball) may be disposed in a corresponding opening in the opening 193 of the third dielectric structure 19 to contact the barrier layer 3 on the second circuit layer 14 for external connection.

[0088] Fig.12 A cross-sectional view illustrating an example of a semiconductor package structure 4d according to some embodiments of the present disclosure. Fig.12 The semiconductor package structure 4d is similar to Figure 8 The semiconductor package structure 4 shown in FIG. 4 differs in the location of the external connector 46 (eg, solder bump or solder ball). In contrast, Figure 8 The semiconductor package structure 4 is a fan-in package structure, and Fig.12 The semiconductor package structure 4d is a fan-out package structure. In addition, the package body 44 further covers the back surface 422 of the semiconductor die 42. Therefore, the first surface 441 of the package body 44 may be higher than the back surface 422 of the semiconductor die 42.

[0089] Fig.13 A cross-sectional view illustrating an example of a semiconductor package structure 4e according to some embodiments of the present disclosure. Fig.13 The semiconductor package structure 4e is similar to Figure 8 The semiconductor package structure 4 shown in FIG. Fig.13 The first circuit layer 2e of the semiconductor substrate 1e of the semiconductor package structure 4e further includes at least one additional portion 29. The additional portion 29 has a large area and is used to control the warpage of the semiconductor substrate 1e and the semiconductor package structure 4. In some embodiments, the area of ​​the additional portion 29 may be larger than the area of ​​the bonding pad 24, and the additional portion 29 may not have an electrical function (for example, it is not electrically connected to other conductive components of the semiconductor package structure 4). For example, the additional portion 29 may have a first metal structure 27 and a second metal structure 28. That is, the additional portion 29, the conductive trace 23, and the bonding pad 24 may be formed at the same time.

[0090] Fig.14 A cross-sectional view illustrating an example of a semiconductor package structure 4f according to some embodiments of the present disclosure. Fig.14 The semiconductor package structure 4f is similar to Figure 8 The semiconductor package structure 4 shown in FIG. 4 is different in the structure of the external connector 46f. Fig.14 As shown in FIG. 4 , external connector 46 f may be a rectangular solid solder bump.

[0091] Figures 15 to 39 The various stages of some embodiments of a method for manufacturing a semiconductor device according to aspects of the present disclosure are described. In some embodiments, the method is used to manufacture a semiconductor package structure, such as Figure 8 The semiconductor package structure 4 shown in FIG. In addition, the method can be used to manufacture a semiconductor substrate, such as Figure 1 The semiconductor substrate 1 is shown in FIG.

[0092] refer to Fig.15 , providing a stacking structure 5. The stacking structure 5 includes a first outermost layer 51, at least one intermediate layer 52, and a second outermost layer 53. The second outermost layer 53 is opposite to the first outermost layer 51. The intermediate layer 52 is located between the second outermost layer 53 and the first outermost layer 51. The refractive index of the stacking structure 5 gradually increases from the first outermost layer 51 to the second outermost layer 52. For example, the refractive index of the second outermost layer 52 is greater than the refractive index of the intermediate layer 52, and the refractive index of the intermediate layer 52 is greater than the refractive index of the first outermost layer 51. In some embodiments, the first outermost layer 51 is the top layer and can be a carrier. The first outermost layer 51 can be, for example, a metal material, a ceramic material, a glass material, a substrate, a semiconductor wafer, or a combination of two or more thereof. The shape of the first outermost layer 51 can be, for example, substantially rectangular or square. Alternatively or in addition, the shape of the first outermost layer 51 can be, for example, substantially circular or elliptical. The intermediate layer 52 is attached to the surface of the first outermost layer 51 and can include a release layer or two or more suitable layers. The second outermost layer 53 is attached to the surface of the intermediate layer 52. Therefore, the second outermost layer 53 may be the bottommost layer. The second outermost layer 53 may be a light blocking layer.

[0093] refer to Fig.16 , an exposure step is performed. A light beam 54 is provided close to or above the first outermost layer 51 to pass through the first outermost layer 51 and the intermediate layer 52 to irradiate the second outermost layer 53. It should be noted that a laser alignment image (LDI) can be used in the exposure step. That is, the photolithography patterning process is performed from one side of the first outermost layer 51 (e.g., a glass carrier) rather than from one side of the second outermost layer 53 (e.g., a photoresist layer).

[0094] See also Fig.17 , Fig.17 yes Fig.16Magnified view. The light beam 54 enters the first outermost layer 51 (with thickness t1 and refractive index n1) from air (with refractive index n0) via the first surface 511 of the first outermost layer 51. On the first surface 511 of the first outermost layer 51, the width of the exposure area (i.e., the pattern width) is defined as "D". The outermost part of the light beam 54 is defined as the incident light 541 that contacts the first surface 511 at point P1. The normal line at point P1 is defined as the first normal line L1, which is orthogonal to the first surface 511. The angle θ0 between the first normal line L1 and the incident light 541 is the incident angle. After entering the first outermost layer 51, the incident light 541 becomes the first light 542. At point P1, the first light 542 is the refracted light, and the angle θ1 between the first normal line L1 and the first light 542 is the refraction angle. According to Snell's law, n0×sinθ0 = n1×sinθ1; if n1>n0, then sinθ1<sinθ0, so θ1<θ0.

[0095] The first light 542 enters the intermediate layer 52 (with thickness t2 and refractive index n2) from the first outermost layer 51 via the first surface 521 of the intermediate layer 52. On the first surface 521 of the intermediate layer 52, the width of the exposure area is defined as "D1". As Fig.17 shown, D1<D. The first light 542 is defined as the incident light that contacts the first surface 521 at point P2. The normal line at point P2 is defined as the second normal line L2, which is orthogonal to the first surface 521. The angle θ1 between the second normal line L2 and the first light 542 is the incident angle because the second normal line L2 is parallel to the first normal line L1. After entering the intermediate layer 52, the first light 542 becomes the second light 543. At point P2, the second light 543 is the refracted light, and the angle θ2 between the second normal line L2 and the second light 543 is the refraction angle. According to Snell's law, n1×sinθ1 = n2×sinθ2. As Fig.17 shown, the reduced distance "x1" is defined as (D - D1) / 2. That is, the reduced distance "x1" is defined as the gap between the first normal line L1 and the second normal line L2. Alternatively or additionally, x1 = t1×tanθ1.

[0096] The second light 543 enters the second outermost layer 53 (with thickness t3 and refractive index n3) from the intermediate layer 52 via the first surface 531 of the second outermost layer 53. On the first surface 531 of the second outermost layer 53, the width of the exposure area is defined as "D2". As Fig.17As shown, D2 < D1. The second light 543 is defined as the incident light that contacts the first surface 531 at point P3. The normal line at point P3 is defined as the third normal line L3, which is orthogonal to the first surface 531. The angle θ2 between the third normal line L3 and the second light 543 is the incident angle because the third normal line L3 is parallel to the second normal line L2. After entering the second outermost layer 53, the second light 543 becomes the third light 544. At point P3, the third light 544 is the refracted light, and the angle θ3 between the third normal line L3 and the third light 544 is the refraction angle. According to Snell's law, n 2× sinθ2 = n 3× sinθ3. As Fig.17 shown, the reduced distance "x2" is defined as (D1 - D2) / 2. That is, the reduced distance "x2" is defined as the gap between the second normal line L2 and the third normal line L3. Alternatively or additionally, x2 = t2×tanθ2.

[0097] The third light 544 enters the air (with refractive index n0) from the second outermost layer 53 (with refractive index n3) via the second surface 532 of the second outermost layer 53. On the second surface 532 of the second outermost layer 53, the width of the exposure area is defined as "d". The third light 544 is defined as the incident light that contacts the second surface 532 at point P4. As Fig.17 shown, the reduced distance "x3" is defined as (D2 - d) / 2, that is, the reduced distance x3 = t3×tanθ3. Additionally, d < D2.

[0098] As stated above, for the general case, in the topmost layer (with thickness t1 and refractive index n1):

[0099] n0sinθ0 = n1sinθ1,

[0100] θ1 = sin -1 (n0sinθ0 / n1),

[0101] x1 = t1tanθ1 = t1tan[sin -1 (n0sinθ0 / n1)].

[0102] In the bottommost layer (with thickness t m and refractive index n m ) :

[0103] n m-1 sinθ m-1 = n m sinθ m ,

[0104] θ m = sin -1(n m-1 sinθ m-1 / n m ),

[0105] x m =t m tanθ m =t m tan[sin -1 (n m-1 sinθ m-1 / n m )].

[0106] On the bottom surface of the lowest layer, the width d of the exposed area is:

[0107]

[0108] Therefore, the reduction in the beam opening (d / D) is:

[0109]

[0110] In some embodiments, the air above the stacked structure 5 can be regarded as a first layer having a refractive index n0 of 1. The first outermost layer 51 (e.g., a glass carrier) can be regarded as a second layer having a thickness t1 of about 500 μm to about 1500 μm and a refractive index n1 of about 1.3 to about 2.2. The intermediate layer 52 (e.g., a release layer) can be regarded as a third layer having a thickness t2 of about 0.5 μm to about 2 μm and a refractive index n2 of about 1.5 to about 2.5. The second outermost layer 53 (e.g., a photoresist layer) can be regarded as a fourth layer having a thickness t3 of about 3 μm to about 10 μm and a refractive index n3 of about 1.6 to about 2.7. Table 1 below illustrates simulation results for Case A and Case B according to some embodiments of the present disclosure, wherein in Case A, θ0 is equal to about 0.05° and D is equal to about 2 μm; and in Case B, θ0 is equal to about 0.1° and D is equal to about 5 μm.

[0111] Table 1: Simulation results of Case A and Case B

[0112]

[0113]

[0114] As shown in Table 1 above, in Case A, D can be reduced from 2 μm to 0.75 μm, and in Case B, D can be reduced from 5 μm to 1.83 μm. Therefore, after the development step, the openings in the second outermost layer 53 (e.g., photoresist layer) can have a small width and / or small size. Additionally, laser direct imaging (LDI) can be used in the exposure step. The second outermost layer 53 (e.g., photoresist layer) can be patterned by the light beam 54 more than twice, and the positions where the light beam 54 contacts the first outermost layer 51 (e.g., glass carrier) at different patterning times can be extremely close. Therefore, after the development step, the openings in the second outermost layer 53 (e.g., photoresist layer) can have a small gap.

[0115] Fig.18 Describe the simulation results for Case C and Case D according to some embodiments of the present disclosure. The domain factors affecting the exposure width d can be: the thickness t1 of the first outermost layer 51 (e.g., glass carrier), the incident angle θ0 of the light beam 54, and the pattern width D. Fig.18 The relationship between G, θ0, and D values is shown in. In Case C, the first outermost layer 51 (e.g., glass carrier) has a thickness t1 of about 500 μm and a refractive index n1 of about 2.2. The intermediate layer 52 (e.g., release layer) has a refractive index n2 of about 2.5. The second outermost layer 53 (e.g., photoresist layer) has a refractive index n3 of about 2.7. Other factors are: about 0.5 μm < d < about 2 μm, about 2 μm < D < about 25 μm, and 0 < θ0 < about 3°. In Case D, the first outermost layer 51 (e.g., glass carrier) has a thickness t1 of about 1500 μm and a refractive index n1 of about 2.2. The intermediate layer 52 (e.g., release layer) has a refractive index n2 of about 2.5. The second outermost layer 53 (e.g., photoresist layer) has a refractive index n3 of about 2.7. Other factors are: about 0.5 μm < d < about 2 μm, about 2 μm < D < about 25 μm, and 0 < θ0 < about 1°. Therefore, if t1 and d are predetermined, then θ0 and D can be specified based on Fig.18 thereof.

[0116] Refer to Fig.19 , and perform a development step on the second outermost layer 53. That is, develop the second outermost layer 53 to form a plurality of openings 533. The openings 533 extend through the second outermost layer 53 to expose a portion of the intermediate layer 52. The angle θ between the sidewall 5331 of the opening 533 in the second outermost layer 53 and the outermost surface of the second outermost layer 53 (i.e., the second surface 532) can be less than about 90 degrees. The size and position of the opening 533 correspond to Fig.17 the third light 544, and thus, the opening 533 tapers from the first surface 531 of the second outermost layer 53 to the second surface 532 of the second outermost layer 53. As Fig.19As shown in , the sidewall 5331 of the opening 533 intersects the outermost surface of the second outermost layer 53 (eg, the second surface 532 ) at a point “D”.

[0117] A metal structure 55 is formed or disposed on the second surface 532 of the second outermost layer 53 and on the exposed portion of the intermediate layer 52 in the opening 533 of the second outermost layer 53 by sputtering such as physical vapor deposition (PVD). The metal structure 55 includes a first portion 551 and a second portion 552. The first portion 551 is not connected to the second portion 552, and there is a gap between the first portion 551 and the second portion 552. The first portion 551 is disposed in the opening 533 of the second outermost layer 53 and forms the first circuit layer 2. The second portion 552 is disposed on the second surface 532 of the second outermost layer 53 and can be removed.

[0118] In some embodiments, the metal structure 55 may be a double-layer structure (or a multi-layer structure) and may include a base metal layer (e.g., the first metal structure 27) and an outer metal layer (e.g., the second metal structure 28). The outer metal layer (the second metal structure 28) is disposed on the base metal layer (the first metal structure 27). During the manufacturing process, the base metal layer (the first metal structure 27) is formed or disposed on the second surface 532 of the second outermost layer 53 and in the opening 533 of the second outermost layer 53 by sputtering such as physical vapor deposition (PVD). The bonding force between the base metal layer (the first metal structure 27) and the non-metal layer (e.g., the second outermost layer 53) may be greater than the bonding force between the copper layer and the non-metal layer.

[0119] In some embodiments, the material of the first metal structure 27 is titanium (Ti). An outer metal layer (second metal structure 28) is formed or disposed on the base metal layer (first metal structure 27) by sputtering, such as physical vapor deposition (PVD). In some embodiments, the material of the second metal structure 28 is copper (Cu). The thickness of the first metal structure 27 may be greater than or equal to about 0.1 μm, and the thickness of the second metal structure 28 may be greater than or equal to about 0.2 μm. In some embodiments, the thickness of the first metal structure 27 may be in a range of about 0.1 μm to about 0.2 μm, about 0.05 μm to about 0.25 μm, or about 0.02 μm to about 0.28 μm, and the thickness of the second metal structure 28 may be in a range of about 0.2 μm to about 0.3 μm, about 0.15 μm to about 0.35 μm, or about 0.12 μm to about 0.38 μm. In addition, after the sputtering process, point “C” of the first metal structure 27 and point “B” of the second metal structure 28 may be aligned with point “D” of the second outermost layer 53 due to Brownian motion.

[0120] refer to Fig. 20 , the second outermost layer 53 and the second portion 552 of the metal structure 55 disposed on the second surface 532 of the second outermost layer 53 are removed by, for example, stripping. At the same time, the first portion 551 of the metal structure 55 becomes the first circuit layer 2. The first circuit layer 2 includes a first surface 21 and a second surface 22 opposite to the first surface 21. The first circuit layer 2 may include a plurality of conductive segments, such as a plurality of conductive traces 23 and / or a plurality of bonding pads 24. The conductive segments of the first circuit layer 2 (e.g., conductive traces 23 or bonding pads 24) include a first metal structure 27 and a second metal structure 28.

[0121] In one or more embodiments, the line width / line spacing (L / S) of the first circuit layer 2 may be equal to or less than about 2 μm / about 2 μm (e.g., about 1.8 μm / about 1.8 μm or less, about 1.6 μm / about 1.6 μm or less, or about 1.4 μm / about 1.4 μm or less), equal to or less than about 1 μm / about 1 μm, or equal to or less than about 0.5 μm / about 0.5 μm. In addition, the surface roughness value (e.g., according to the root mean square surface roughness) of the first surface 21 of the first circuit layer 2 may be in the range of from about 5 nanometers (nm) to about 55 nm, from about 2 nm to about 80 nm, or from about 1 nm to about 100 nm.

[0122] refer to Fig.21 , a first dielectric structure 12 is formed or disposed by, for example, coating to cover the first circuit layer 2 and the intermediate layer 52. Therefore, the first circuit layer 2 is embedded in the first dielectric structure 12. The first dielectric structure 12 may have a first surface 121 and a second surface 122 opposite to the first surface 121. The first dielectric structure 12 may define a plurality of groove portions 123. The groove portions 123 are recessed from the first surface 121 of the first dielectric structure 12 and do not extend through the first dielectric structure 12. The first circuit layer 2 is disposed in the groove portions 123 of the first dielectric structure 12 and does not protrude from the first surface 121 of the first dielectric structure 12.

[0123] refer to Fig. 22 , a plurality of openings 124 are formed from the second surface 122 of the first dielectric structure 12 by, for example, a lithographic patterning process. The openings 124 are recessed from the second surface 122 of the first dielectric structure 12 and do not extend through the first dielectric structure 12. Positions of the openings 124 correspond to some of the groove portions 123. Therefore, some portions of the first circuit layer 2 (e.g., the second surface 22) may be exposed from the openings 124 of the first dielectric structure 12.

[0124] The second seed layer 15 is formed or disposed on and in contact with the conductive trace 23 of the first circuit layer 2 in the opening 124 of the first dielectric structure 12, and is formed or disposed on and in contact with the second surface 122 of the first dielectric structure 12 by, for example, PVD. In some embodiments, the second seed layer 15 may be a double-layer structure (or a multi-layer structure), and may include a first layer 151 and a second layer 152. The material of the first layer 151 may be titanium (Ti), and the material of the second layer 152 may be copper (Cu).

[0125] refer to Fig.23 , a photoresist layer 56 is formed or disposed to cover the second seed layer 15 .

[0126] refer to Fig.24 A plurality of openings 561 are formed in the photoresist layer 56 by, for example, a photolithography patterning process to expose portions of the second seed layer 15. A second metal layer 141 is disposed on the exposed portions of the second seed layer 15 in the openings 561 by, for example, plating. The material of the second metal layer 141 may be copper (Cu).

[0127] refer to Fig.25 , the photoresist layer 56 is removed by, for example, stripping. Next, the portion of the second seed layer 15 not covered by the second metal layer 141 is removed by, for example, etching. At the same time, the second circuit layer 14 is formed or disposed on the first dielectric structure 12. The second circuit layer 14 includes the second seed layer 15 and the second metal layer 141. In some embodiments, a portion of the second circuit layer 14 is disposed in the opening 124 of the first dielectric structure 12 to form a second via 143, and the other portion of the second circuit layer 14 is disposed on the second surface 122 of the first dielectric structure 12 to form a second patterned layer 144 that may include at least one conductive trace and / or at least one bonding pad.

[0128] The second via 143 is electrically connected to and in contact with the conductive trace 23 of the first circuit layer 2. Therefore, the second circuit layer 14 is electrically connected to the first circuit layer 2 through the second via 143. The second via 143 may be a wedge-shaped structure that tapers from the second surface 122 of the first dielectric structure 12 toward the first surface 121 of the first dielectric structure 12. The second via 143 may define a central hole 1431. It should be noted that the second via 143 may include at least a portion of the second seed layer 15 and the second metal layer 141, and the second patterned layer 144 may include at least a portion of the second seed layer 15 and the second metal layer 141. The second via 143 and the second patterned layer 144 may be integrally formed and formed simultaneously. The L / S of the second circuit layer 14 may be less than, for example, about 7 μm / about 7 μm, about 5 μm / about 5 μm, or about 2 μm / about 2 μm. The L / S of the second circuit layer 14 may be greater than the L / S of the first circuit layer 2.

[0129] refer to Fig.26 , a second dielectric structure 16 is formed to cover the second circuit layer 14 and the second surface 122 of the first dielectric structure 12. The second dielectric structure 16 includes a first surface 161 and a second surface 162 opposite to the first surface 161. The first surface 161 of the second dielectric structure 16 contacts the second surface 122 of the first dielectric structure 12, and a portion of the second dielectric structure 16 extends into the central hole 1431 of the second guide hole 143 of the second circuit layer 14. Next, a plurality of openings 163 are formed in the second dielectric structure 16 by, for example, laser drilling to expose a portion of the second circuit layer 14 (e.g., a portion corresponding to the second metal layer 141). The openings 163 of the second dielectric structure 16 may extend through the second dielectric structure 16.

[0130] refer to Fig. 27 The third seed layer 17 is formed in the opening 163 of the second dielectric structure 16 or disposed on the exposed portion of the second circuit layer 14 and in contact therewith, and is formed or disposed on the second surface 162 of the second dielectric structure 16 by, for example, electroless plating and in contact therewith. In some embodiments, the third seed layer 17 may be a single-layer structure or a double-layer structure (or a multi-layer structure). For example, the third seed layer 17 may include a titanium (Ti) layer and a copper (Cu) layer.

[0131] refer to Fig.28 The third metal layer 181 is formed or disposed on the third seed layer 17 by, for example, overall plating.

[0132] refer to Fig.29 , a photoresist layer 58 is formed or disposed on the third metal layer 181 by, for example, lamination.

[0133] refer to Fig.30 , a plurality of openings 581 are formed in the photoresist layer 58 by, for example, a photolithography patterning process to expose portions of the third metal layer 181 .

[0134] refer to Fig.31, the portions of the third seed layer 17 and the third metal layer 181 exposed in the opening 581 are removed by, for example, etching. The photoresist layer 58 is removed by, for example, stripping. At the same time, the third circuit layer 18 is formed or disposed on the second dielectric structure 16. In some embodiments, a portion of the third circuit layer 18 is formed or disposed in the opening 163 of the second dielectric structure 16 to form at least one third guide hole 183, and the other portion of the third circuit layer 18 is disposed on the second surface 162 of the second dielectric structure 16 to form a second patterned layer 184 that may include at least one conductive trace and / or at least one bonding pad. The third guide hole 183 is electrically connected to the second circuit layer 14 and contacts it. Therefore, the third circuit layer 18 is electrically connected to the second circuit layer 14 through the third guide hole 183.

[0135] The third guide hole 183 may be a wedge-shaped structure that tapers from the second surface 162 of the second dielectric structure 16 toward the first surface 161 of the second dielectric structure 16. The third guide hole 183 may define a recessed portion 1831 at its bottom end. The third guide hole 183 and the third patterned layer 184 may be integrally formed and formed simultaneously. The L / S of the third circuit layer 18 may be greater than, for example, about 5 μm / about 5 μm, about 7 μm / about 7 μm, or about 10 μm / about 10 μm. The L / S of the third circuit layer 18 may be greater than the L / S of the second circuit layer 14. Fig.31 As shown in FIG. 1 , the third circuit layer 18 includes a third seed layer 17 and a third metal layer 181. It should be noted that the third via 183 may include at least a portion of the third seed layer 17 and the third metal layer 181, and the third patterned layer 184 may also include at least a portion of the third seed layer 17 and the third metal layer 181.

[0136] refer to Fig.32 , a third dielectric structure 19 is formed or disposed by, for example, coating to cover the third circuit layer 18 and the second surface 162 of the second dielectric structure 16. The third dielectric structure 19 includes a first surface 191 and a second surface 192 opposite to the first surface 191. The first surface 191 of the third dielectric structure 19 contacts the second surface 162 of the second dielectric structure 16. A portion of the third dielectric structure 19 extends into the concave portion 1831 of the third guide hole 183 of the third circuit layer 18.

[0137] refer to Fig.33 , a plurality of openings 193 are formed in the third dielectric structure 19 to expose a portion of the third circuit layer 18 (eg, a portion corresponding to the third metal layer 181). Next, the first outermost layer 51 and the intermediate layer 52 are removed to expose the first circuit layer 2. At the same time, Figures 1 to 3 A semiconductor substrate 1.

[0138] refer to Fig.34In some embodiments, the first metal structure 27 may be further removed to obtain the semiconductor substrate 1b. Figure 5 1 shows a portion of a first circuit layer 2b of a semiconductor substrate 1b. The conductive segments (eg, conductive traces 23b and / or bonding pads) of the first circuit layer 2b include a second metal structure 28b which may be copper (Cu). Figure 5 In the embodiment, the second metal structure 28 b may be a single layer and may not fill or may fill a portion of the groove portion 123 of the first dielectric structure 12 .

[0139] refer to Fig.35 ,exist Fig.33 The barrier layer 3 is formed or disposed on the conductive segments (e.g., conductive traces 23 and / or bonding pads 24) of the first circuit layer 2. In some embodiments, the barrier layer 3 includes a nickel layer 31 and a gold layer 32. The nickel layer 31 is disposed on the conductive segments (e.g., conductive traces 23 and bonding pads 24), and the gold layer 32 is disposed on the nickel layer 31. In some embodiments, the barrier layer 3 may be further disposed on the exposed portion of the third circuit layer 18 (e.g., a portion corresponding to the third metal layer 181) in the opening 193 of the third dielectric structure 19.

[0140] refer to Fig.36 , the semiconductor grain 42 is attached to the semiconductor substrate 1 and electrically connected to the first circuit layer 2. The semiconductor grain 42 has an active surface 421, a back surface 422, a side surface 423 and a plurality of conductive bumps 424. The back surface 422 is opposite to the active surface 421. The side surface 423 extends between the active surface 421 and the back surface 422. The conductive bump 424 is disposed adjacent to the active surface 421. The conductive bump 424 contacts the nickel layer 31 of the barrier layer 3 on the conductive segment (e.g., bonding pad 24) of the first circuit layer 2. Therefore, the semiconductor grain 42 is attached to the semiconductor substrate 1 by flip chip bonding. The semiconductor grain 42 is electrically connected to the first circuit layer 2 of the semiconductor substrate 1 through the conductive bump 424 and the barrier layer 3. In addition, a plurality of solders 45 are formed to cover the lower ends of the conductive bump 424 and the barrier layer 3 to ensure the bonding between the conductive bump 424 and the barrier layer 3.

[0141] refer to Fig.37 , a package body 44 , such as a molding compound, is formed or disposed to cover the semiconductor die 42 and the semiconductor substrate 1 . Fig.37 The structure shown in may include Figure 8. In some embodiments, the package body 44 covers the first surface 121 of the first dielectric structure 12, a portion (e.g., an upper end) of the conductive bump 424, an active surface 421 of the semiconductor die 42, and a side surface 423 of the semiconductor die 42. The first surface 441 of the package body 44 may be substantially coplanar with the back surface 422 of the semiconductor die 42. Therefore, the back surface 422 of the semiconductor die 42 is exposed from the first surface 441 of the package body 44.

[0142] refer to Fig.38 , the shape of the semiconductor substrate 1 may be substantially rectangular or square.

[0143] refer to Fig.39 , the shape of the semiconductor substrate 1 may be substantially circular or elliptical.

[0144] A plurality of external connectors 46 (such as solder bumps or solder balls) may be disposed in corresponding openings in the openings 193 of the third dielectric structure 19 to contact the barrier layer 3 on the third circuit layer 18 for external connection. The package body 44 may be singulated on the semiconductor substrate 1 to form Figure 8 . The multiple semiconductor package structures 4 shown in FIG.

[0145] Unless otherwise indicated, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "on", "below", etc. are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual implementations of the structures described herein may be spatially arranged in any orientation or manner, with the limitation that the advantages of the embodiments of the present disclosure are not deviated from such arrangements.

[0146] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms may refer to instances in which the event or circumstance clearly occurred as well as instances in which the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same or equal if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0147] As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may include a situation where the former component is directly on (e.g., physically in contact with) the latter component, as well as a situation where one or more intermediate components are located between the former component and the latter component.

[0148] If the displacement between two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, no more than 0.5 μm, or no more than 0.1 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the difference between the highest point and the lowest point of the surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, no more than 0.5 μm, or no more than 0.1 μm, then the surface can be considered planar or substantially planar.

[0149] In addition, sometimes amounts, ratios and other numerical values ​​are presented in range format herein. It should be understood that such range format is for the sake of convenience and brevity, and should be flexibly understood to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0150] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The description may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor substrate, comprising: a first dielectric structure comprising a first surface and a second surface opposite the first surface; a first circuit layer embedded in the first dielectric structure, wherein the first circuit layer does not protrude from the first surface of the first dielectric structure, the first circuit layer includes at least one conductive segment, the conductive segment includes a conductive trace, the conductive trace includes a first end adjacent to the first surface of the first dielectric structure and a second end opposite the first end, and the first end of the conductive trace has a width different from a width of the second end of the conductive trace; as well as a second circuit layer, a portion of the second circuit layer being disposed in the opening of the first dielectric structure to form a second via, the second via being electrically connected to and in contact with the conductive trace of the first circuit layer; The conductive trace tapers from the first surface of the first dielectric structure to the second surface of the first dielectric structure, and the second via of the second circuit layer tapers from the second surface of the first dielectric structure toward the first surface of the first dielectric structure. 2 . The semiconductor substrate of claim 1 , wherein an angle between a sidewall of the conductive trace and the first surface of the first dielectric structure is greater than 90 degrees. 3 . The semiconductor substrate of claim 1 , wherein the width of the first end of the conductive trace is greater than the width of the second end of the conductive trace. 4 . The semiconductor substrate according to claim 1 , wherein a line width / line spacing of the first circuit layer is less than or equal to 2 micrometers (μm) / 2 μm. 5 . The semiconductor substrate of claim 1 , wherein a first surface of the first circuit layer is substantially coplanar with the first surface of the first dielectric structure. 6 . The semiconductor substrate according to claim 1 , wherein the conductive segments of the first circuit layer are of a single structure, and a surface roughness value of a first surface of the first circuit layer is in a range from 5 nanometers (nm) to 55 nm.

7. The semiconductor substrate of claim 1, wherein the conductive trace of the first circuit layer comprises a first metal structure and a second metal structure, the second metal structure being disposed on the first metal structure and further extending to cover and contact at least a portion of a side surface of the first metal structure. 8 . The semiconductor substrate according to claim 7 , wherein a material of the first metal structure is titanium, and a material of the second metal structure is copper. 9 . The semiconductor substrate according to claim 7 , wherein a thickness of the first metal structure is greater than or equal to 0.1 μm, and a thickness of the second metal structure is greater than or equal to 0.2 μm.

10. The semiconductor substrate of claim 1, further comprising a barrier layer disposed on the conductive trace, wherein the barrier layer comprises a nickel layer and a gold layer, and the nickel layer is disposed between the gold layer and the conductive trace. 11 . The semiconductor substrate according to claim 10 , wherein the surface roughness value of the first surface of the nickel layer is in the range from 200 nm to 300 nm, and the surface roughness value of the first surface of the gold layer is in the range from 50 nm to 200 nm. 12 . The semiconductor substrate of claim 1 , wherein the first end of the conductive trace defines a cavity and a first surface of the first circuit layer is recessed from the first surface of the first dielectric structure. 13 . The semiconductor substrate of claim 12 , wherein the cavity has a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion, and a width of the first portion of the cavity is greater than a width of the second portion of the cavity.

14. The semiconductor substrate of claim 12, further comprising a barrier layer disposed in the cavity of the conductive trace, wherein the barrier layer comprises a nickel layer and a gold layer, and the nickel layer is disposed between the gold layer and the conductive trace. 15 . The semiconductor substrate according to claim 1 , wherein a line width / line spacing of the first circuit layer is less than or equal to 1 μm / 1 μm. 16 . The semiconductor substrate according to claim 1 , wherein a line width / line spacing of the second circuit layer is greater than a line width / line spacing of the first circuit layer.

17. The semiconductor substrate of claim 1, wherein the second circuit layer comprises a second seed layer and a second metal layer, the second seed layer disposed on and in contact with the conductive traces of the first circuit layer in the openings of the first dielectric structure.

18. The semiconductor substrate of claim 1, wherein the conductive segment further comprises a bonding pad, the bonding pad comprising a first end adjacent to the first surface of the first dielectric structure and a second end opposite to the first end, and a width of the first end of the bonding pad is different from a width of the second end of the bonding pad.

19. The semiconductor substrate of claim 1, wherein the conductive traces and bonding pads are formed simultaneously.

20. The semiconductor substrate according to claim 1, further comprising a second dielectric structure, wherein the second dielectric structure covers the second circuit layer and the second surface of the first dielectric structure, and at least a portion of the second dielectric structure extends into a central hole of the second via of the second circuit layer. The semiconductor substrate of claim 20 , wherein a material of the second dielectric structure is different from a material of the first dielectric structure.

22. The semiconductor substrate of claim 21, wherein the material of the second dielectric structure comprises a cured fiber-reinforced resin.

23. A semiconductor substrate according to claim 20, wherein the second dielectric structure defines an opening to expose a portion of the second circuit layer, and wherein the semiconductor substrate further includes a third circuit layer, the third circuit layer is disposed on the exposed portion of the second circuit layer in the opening of the second dielectric structure to form a third via, the third via being electrically connected to and in contact with the second circuit layer.

24. The semiconductor substrate according to claim 23, wherein the second dielectric structure comprises a first surface and a second surface opposite to the first surface, the first surface of the second dielectric structure contacts the second surface of the first dielectric structure, and the third via tapers from the second surface of the second dielectric structure toward the first surface of the second dielectric structure. 25 . The semiconductor substrate according to claim 1 , wherein the first circuit layer further comprises an additional portion, the additional portion having no electrical function, for controlling warpage of the semiconductor substrate. 26 . The semiconductor substrate of claim 25 , wherein the conductive segment further comprises a bonding pad, and an area of ​​the additional portion is larger than an area of ​​the bonding pad.

27. The semiconductor substrate of claim 26, wherein the additional portion has a first metal structure and a second metal structure.

28. The semiconductor substrate of claim 27, wherein the additional portion, the conductive trace, and the bond pad are formed simultaneously.

29. A semiconductor packaging structure, comprising: A semiconductor substrate comprising: a first dielectric structure comprising a first surface and a second surface opposite the first surface; a first circuit layer embedded in the first dielectric structure, wherein the first circuit layer does not protrude from the first surface of the first dielectric structure, the first circuit layer comprises at least one conductive segment, the conductive segment comprises a conductive trace, the conductive trace comprises a first end adjacent to the first surface of the first dielectric structure and a second end opposite to the first end, and a width of the first end of the conductive trace is different from a width of the second end of the conductive trace, wherein a line width / line spacing of the first circuit layer is less than or equal to 2 μm / 2 μm; and a second circuit layer, a portion of the second circuit layer disposed in the opening of the first dielectric structure to form a second via, the second via being electrically connected to and in contact with the conductive trace of the first circuit layer; and a semiconductor die attached to the semiconductor substrate and electrically connected to the first circuit layer; The conductive trace tapers from the first surface of the first dielectric structure to the second surface of the first dielectric structure, and the second via of the second circuit layer tapers from the second surface of the first dielectric structure toward the first surface of the first dielectric structure. 30 . The semiconductor package structure of claim 29 , wherein an angle between a sidewall of the conductive trace and the first surface of the first dielectric structure is greater than 90 degrees. 31 . The semiconductor package structure according to claim 29 , further comprising a package body covering the semiconductor die and the semiconductor substrate. 32 . The semiconductor package structure of claim 29 , wherein the width of the first end of the conductive trace is greater than the width of the second end of the conductive trace. 33 . The semiconductor package structure according to claim 29 , wherein a first surface of the first circuit layer is substantially coplanar with the first surface of the first dielectric structure.

34. The semiconductor package structure of claim 29, wherein the first end of the conductive trace defines a cavity, and a first surface of the first circuit layer is recessed from the first surface of the first dielectric structure. 35 . The semiconductor package structure according to claim 29 , wherein a surface roughness value of the first surface of the first circuit layer is in a range from 5 nm to 55 nm.

36. The semiconductor substrate of claim 29, wherein the conductive segment further comprises a bonding pad, the bonding pad comprising a first end adjacent to the first surface of the first dielectric structure and a second end opposite to the first end, and a width of the first end of the bonding pad is different from a width of the second end of the bonding pad. 37 . The semiconductor substrate of claim 36 , further comprising a barrier layer disposed on the bonding pad, the barrier layer comprising a nickel layer and a gold layer, and the nickel layer is disposed between the gold layer and the bonding pad. 38 . The semiconductor substrate according to claim 37 , wherein the semiconductor grain has a conductive bump, and the conductive bump contacts the nickel layer of the barrier layer at a bonding pad of the first circuit layer. 39 . The semiconductor substrate of claim 38 , further comprising a plurality of solders formed to cover the conductive bumps and lower ends of the barrier layer to ensure bonding between the conductive bumps and the barrier layer. 40 . The semiconductor substrate of claim 39 , further comprising a package, wherein the package covers the first surface of the first dielectric structure, upper ends of the conductive bumps, an active surface of the semiconductor die, and side surfaces of the semiconductor die. The semiconductor substrate of claim 40 , wherein the first surface of the package body is coplanar with the back surface of the semiconductor die.

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