A CC pin circuit for USB Type-C

Abstract

The present invention provides a CC pin circuit for a USB Type-C. In the Type-C interface circuit, a high-voltage NMOS is introduced for voltage isolation to generate a first low-voltage region. The pull-up resistor circuit, the CC connection detection circuit, the PD communication circuit, etc. are placed in the first low-voltage region to achieve high-voltage protection. The pull-down resistor circuit is directly connected to the CC pin, so that when the Type-C interface is in the dead battery state of the DRP or SNK mode, connecting to an SRC or other DRP can achieve normal CC connection. The resistor in the pull-down resistor circuit is divided into two parts, a first resistor and a second resistor, which are connected in series, and a voltage clamp is made at the intermediate series node to generate a second low-voltage region. The enable control switch of the pull-down resistor circuit and the second resistor are placed in the second low-voltage region to achieve high-voltage protection. The first resistor is placed in the high-voltage region and plays a current-limiting role when the voltage clamp circuit works. The voltage withstand design method and circuit structure of the present invention can be applied to all modes of Type-C interface circuits to solve the voltage withstand problem of the CC pin.

Description

Technical Field

[0001] The present invention relates to the technical field of USB Type-C interface circuits, and specifically relates to a CC pin circuit of USB Type-C. Background Art

[0002] With the rapid development of electronic technology, portable electronic products represented by mobile phones, tablets and laptops have widely affected people's daily lives. The new USB Type-C interface supports plugging in either side, solving the world problem of "USB is always difficult to plug in correctly". In addition, compared with traditional USB interfaces, the Type-C interface also has characteristics such as lighter weight, thinner design, smaller size, and stronger expandable functionality, which is very suitable for application to portable electronic products. Since the Type-C interface came out, it has been widely popularized in just a few years.

[0003] With the rise of USB fast charging technology, the voltage transmitted by VBUS in the USB interface is no longer a fixed 5V, but can cover a voltage range from 3V to 20V. Therefore, both chargers and charging devices face many reliability problems brought by high voltage. The CC pin of the Type-C interface is close to the VBUS pin, and the distance between them is very small. During the process of cable plugging and unplugging or when the connected cable shakes, the CC pin is very likely to be short-circuited with the VBUS pin, so that the voltage of VBUS is directly applied to the CC pin. Therefore, it is very necessary to design the CC pin of the Type-C interface circuit to be high-voltage resistant.

[0004] According to the power supply or power reception situation of the USB port, the Type-C of USB divides the port into power working modes such as SRC (only power supply), SNK (only power reception), DRP (can supply or receive power), etc. Among them, DRP can be divided into SRC connection state (power supply) and SNK connection state (power reception). Currently, the existing high-voltage resistant design circuit for the CC pin of Type-C simply connects a high-voltage NMOS in series on the CC pin as voltage isolation, and then places all the circuits on the CC pin in the low-voltage area generated by the high-voltage NMOS isolation. This method can be well applied to the SRC mode such as an adapter. However, when this method is applied to the DRP or SNK mode, as Figure 1 shown Figure 1It is a schematic diagram of the existing CC pin circuit of Type-C in the SNK connection state. The CC pin Ⅳ is connected in series with the high-voltage NMOS Ⅲ for voltage isolation, forming a high-voltage area Ⅰ and a low-voltage area Ⅱ. The CC pin Ⅳ and the high-voltage NMOS Ⅲ are in the high-voltage area Ⅰ. The pull-up resistor circuit composed of the pull-up resistor Ⅵ and the switch Ⅶ in series, the pull-down resistor circuit composed of the pull-down resistor Ⅹ and the switch Ⅸ in series, the CC connection detection circuit Ⅷ and the PD communication circuit Ⅸ are all placed in the low-voltage area Ⅱ. After the Type-C interface enters the Dead Battery state, the internal power supply VDD is 0 and the high-voltage NMOS Ⅲ is turned off. At this time, when connecting the SRC or other DRP, a pull-down path for connecting the CC pin cannot be formed. When the Rp_SRC resistor Ⅴ of the other end Type-C interface appears, it will pull up the voltage of the CC pin Ⅳ to the power supply VDDSRC of the other end Type-C interface, so the CC connection cannot be achieved, and the other end Type-C interface will not output VBUS, resulting in the Dead Battery state that cannot be activated all the time. This situation is often unacceptable in practical applications. Summary of the Invention

[0005] The purpose of the present invention is to provide a CC pin circuit for USB Type-C, which can be applied to all types of Type-C interface circuits and solve the voltage withstand problem of the CC pin.

[0006] To achieve the above purpose, the CC pin circuit for USB Type-C provided by the present invention includes a high-voltage NMOS, a pull-up resistor circuit, a CC connection detection circuit, a PD communication circuit, a pull-down resistor circuit and a voltage clamping circuit. The gate of the high-voltage NMOS is connected to the internal power supply VDD. One ends of the pull-up resistor circuit, the CC connection detection circuit and the PD communication circuit are all connected to the source of the high-voltage NMOS. The drain of the high-voltage NMOS is connected to the pull-down resistor circuit, and the drain of the high-voltage NMOS is connected to the first end of the CC pin. The pull-down resistor circuit includes a first resistor circuit and a second resistor circuit. The voltage clamping circuit is connected between the series node of the first resistor circuit and the second resistor circuit and the ground.

[0007] As can be seen from the above solution, through the design of the high-voltage NMOS and the pull-down resistor circuit, the overall circuit structure is divided into three regions: a high-voltage region, a first low-voltage region, and a second low-voltage region. The high-voltage NMOS, the first resistor circuit, and the CC pin are in the high-voltage region. The pull-up resistor circuit, the CC connection detection circuit, and the PD communication circuit are in the first low-voltage region. The second resistor circuit and the voltage clamping circuit are in the second low-voltage region. Among them, the high-voltage NMOS can play the role of isolating high voltage. When the Type-C is normally connected, the high-voltage NMOS acts as a transmission switch with a low resistance value, enabling the voltage signal to be transmitted without loss between the source node of the high-voltage NMOS and the CC pin. The CC connection detection circuit can identify and judge the connection state of Type-C. The PD communication circuit can realize the communication of the USB power transmission protocol. The voltage clamping circuit can achieve voltage withstand protection through voltage clamping. This circuit structure can be applied to all types of Type-C interface circuits. Even in the dead battery state of the DRP or SNK mode, when connecting to an SRC or other DRP, the CC connection can be achieved normally. At the same time, the high-voltage protection of the CC pin is realized, and the voltage withstand problem of the CC pin is solved.

[0008] A further solution is that the high-voltage NMOS is an NMOS with a breakdown voltage greater than the highest voltage of the VBUS of the Type-C interface.

[0009] As can be seen from the above, when the CC pin and the VBUS pin are short-circuited together, the high-voltage NMOS in the CC pin circuit of this USB Type-C can work normally and avoid being broken down.

[0010] A further solution is that the pull-up resistor circuit includes an impedance device and a first enable control switch. The impedance device and the first enable control switch are connected in series. One end of the pull-up resistor circuit far from the source of the high-voltage NMOS is connected to the internal power supply VDD.

[0011] A further solution is that the impedance device is a resistor or a current source.

[0012] A further solution is that the first enable control switch is a PMOS, NMOS, PNP, or NPN device.

[0013] As can be seen from the above, the pull-up resistor circuit of the CC pin circuit of this USB Type-C can pull up the signal of the source node of the high-voltage NMOS.

[0014] A further solution is that the first resistor circuit includes a first resistor.

[0015] A further solution is that the second resistor circuit includes a second resistor and a second enable control switch. The second enable control switch is connected in series between the first resistor and the second resistor, and the other end of the second resistor is grounded.

[0016] A further solution is that the second enabling control switch is a PMOS or PNP device.

[0017] As can be seen from the above, by connecting the second enabling control switch in series between the first resistor and the second resistor, it is possible to prevent the second enabling control switch from being broken down when a high voltage appears on the CC pin. In addition, compared with the connection method of connecting the second enabling control switch in series between the second resistor and the ground, the conduction threshold loss can be reduced. When a high voltage appears on the CC pin 13, the first resistor 12 can play a current limiting role. At the same time, when in the dead battery state of the DRP or SNK mode, the voltage of the CC pin can be made to be within the voltage range of the connected state by the conduction of the second enabling control switch, and the dead battery state can be activated. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the existing CC pin circuit of Type-C in the SNK connected state.

[0019] Figure 2 It is a schematic diagram of the circuit structure of a CC pin circuit of a USB Type-C according to the present invention.

[0020] Figure 3 It is a schematic diagram of the circuit structure of an embodiment of the present invention applied to the Type-C DRP mode.

[0021] Figure 4 It is a schematic diagram of the Type-C DRP embodiment of the present invention in the SRC connected state.

[0022] Figure 5 It is a schematic diagram of the Type-C DRP embodiment of the present invention in the SNK connected state.

[0023] Figure 6 It is a schematic diagram of the circuit structure of an embodiment of the present invention applied to the Type-C SRC mode.

[0024] Figure 7 It is a schematic diagram of the circuit structure of an embodiment of the present invention applied to the first embodiment of the Type-C SNK mode.

[0025] Figure 8 It is a schematic diagram of the circuit structure of an embodiment of the present invention applied to the second embodiment of the Type-C SNK mode. Detailed Embodiments

[0026] See Figure 2 , Figure 2Schematic diagram of a CC pin circuit structure of a USB Type-C according to the present invention. The CC pin circuit includes a high-voltage NMOS 11, a pull-up resistor circuit, a CC connection detection circuit 23, a PD communication circuit 24, a pull-down resistor circuit, and a voltage clamping circuit. The gate of the high-voltage NMOS 11 is connected to an internal power supply VDD. One ends of the pull-up resistor circuit, the CC connection detection circuit 23, and the PD communication circuit 24 are all connected to the source of the high-voltage NMOS. The drain of the high-voltage NMOS 11 is connected to the pull-down resistor circuit, and the drain of the high-voltage NMOS 11 is connected to the first end of the CC pin. The pull-down resistor circuit includes a first resistor circuit and a second resistor circuit. The voltage clamping circuit is connected between the series node of the first resistor circuit and the second resistor circuit and the ground. Among them, the pull-up resistor circuit includes an impedance device 21 and a first enable control switch 22. The impedance device 21 and the first enable control switch 22 are connected in series. The end of the pull-up resistor circuit far from the source of the high-voltage NMOS 11 is connected to the internal power supply VDD. The first resistor circuit includes a first resistor 12. The second resistor circuit includes a second resistor 32 and a second enable control switch 31. The second enable control switch 31 is connected in series between the first resistor 12 and the second resistor 32. The other end of the second resistor 32 is grounded.

[0027] Specifically, the overall circuit structure is divided into three regions: a high-voltage region 1, a first low-voltage region 2, and a second low-voltage region 3. The high-voltage NMOS 11, the first resistor circuit, and the CC pin 13 are located in the high-voltage region 1. The pull-up resistor circuit, the CC connection detection circuit 23, and the PD communication circuit 24 are located in the first low-voltage region 2. The second resistor circuit and the voltage clamping circuit are located in the second low-voltage region 3. Among them, the internal power supply VDD generally does not exceed 5.5V, and the high-voltage NMOS can withstand the highest voltage of VBUS of the Type-C interface. Since the gate of the high-voltage NMOS 11 is connected to the internal power supply VDD, and there is a threshold loss when the NMOS 11 transmits high voltage, when a high voltage appears on the CC pin, the voltage poured into the source node of the high-voltage NMOS 11 will not be higher than the internal power supply VDD. Therefore, the high-voltage NMOS 11 can achieve the function of isolating high voltage. When the Type-C is normally connected, the voltages of the source node of the high-voltage NMOS 11 and the CC pin 13 are much lower than the internal power supply VDD. Therefore, the high-voltage NMOS 11 behaves as a transmission switch with a low resistance value, enabling the voltage signal to be transmitted between the source node of the high-voltage NMOS 11 and the CC pin 13 without loss. The CC connection detection circuit 23 realizes the identification and judgment of the Type-C connection state, and may include a comparator, a reference voltage, a logic circuit, etc. The PD communication circuit 24 realizes the communication of the USB power transmission protocol and may include circuits such as TX and RX. In the pull-down resistor circuit, the first resistor 12 is connected to one end of the CC pin 13, and the second enable control switch 31 is connected in series between the first resistor 12 and the second resistor 32, which can prevent the second enable control switch 31 from being broken down when a high voltage appears on the CC pin 13. In addition, compared with the connection method of connecting the second enable control switch in series between the second resistor and the ground, the conduction threshold loss can be reduced. At the same time, the clamping voltage of the voltage clamping circuit is lower than the safety voltage. When a high voltage appears on the CC pin 13, the voltage of the series node of the first resistor circuit and the second resistor circuit is higher than the clamping voltage, and the voltage clamping circuit will conduct and drain the current. The voltage of the series node of the first resistor circuit and the second resistor circuit is not allowed to exceed the safety voltage by reducing the voltage through the IR drop of the first resistor 12. Based on the structural design of the pull-down resistor circuit, the voltage withstand problem of the CC pin 13 can be solved.

[0028] In the following specific embodiments, the impedance device 21 is a current source, the first enable control switch 22 is a PMOS (P1), the second enable control switch 31 is a PMOS (P2), and the voltage clamping circuit is implemented by using a Zener diode 33.

[0029] See Figure 3 , Figure 3Schematic diagram of the circuit structure of the embodiment of the present invention applied to the Type-C DRP mode. In this embodiment, the Type-C DRP defaults to switch between two non-connected states of SRC and SNK. When switching to the SRC mode, the first enable control switch 22 (P1) is turned on, and the second enable control switch 31 (P2) is turned off. The source node of the high-voltage NMOS 11 is pulled up to the internal power supply VDD. Since the gate of the high-voltage NMOS 11 is connected to the internal power supply VDD, there is a threshold loss when the high-voltage NMOS 11 transmits the VDD voltage. Therefore, the voltage on the CC pin 13 at this time is the internal power supply VDD minus the threshold voltage of the high-voltage NMOS 11. The CC connection detection circuit 23 detects the voltage of the source node of the high-voltage NMOS 11, so it can accurately identify the non-connected state of the SRC. When switching to the SNK mode, the first enable control switch 22 (P1) is turned off, and the second enable control switch 31 (P2) is turned on. The CC pin 13 is pulled down to the ground through the pull-down resistor circuit. At this time, the high-voltage NMOS 11 can transmit the low voltage of the CC pin 13 to the source node of the high-voltage NMOS 11 without loss, and the CC connection detection circuit 23 can accurately identify the non-connected state of the SNK.

[0030] See Figure 4 , Figure 4 Schematic diagram of the Type-C DRP embodiment of the present invention in the SRC connected state. In this state, the first enable control switch 22 (P1) is turned on, and the second enable control switch 31 (P2) is turned off, that is, the gate of the first enable control switch 22 (P1) is grounded, and the gate of the second enable control switch 31 (P2) is connected to the internal power supply VDD. The current Ip provided by the current source 21 flows through the first enable control switch 22 (P1), the high-voltage NMOS 11, the CC pin 13, the cable 14, and the Rd_SNK resistor 15 of the other end Type-C interface to the ground. When in the connected state, the voltage on the CC pin 13 is Ip×Rd_SNK, generally lower than 2.6V; when the PD communication circuit 24 works normally, the voltage of the CC pin 13 is generally lower than 1.2V. Therefore, the high-voltage NMOS 11 can transmit the voltage signal between the source node of the high-voltage NMOS 11 and the CC pin 13 without loss. When a high voltage appears on the CC pin 13, the high-voltage NMOS can control the voltage of the source node of the high-voltage NMOS 11 to be lower than the internal power supply VDD by a threshold voltage, which can protect the withstand voltage safety of the first low-voltage area 2; the Zener diode 33 is reversely broken down and conducts, and the current flows away, and then the voltage of the series node of the first resistor circuit and the second resistor circuit is controlled below the clamping voltage of the Zener diode 33 through the IR drop (IRdrop) of the current flowing through the first resistor 12, so as to ensure the withstand voltage safety of the second low-voltage area 3.

[0031] See Figure 5 , Figure 5Schematic diagram of the Type-C DRP embodiment of the present invention in the SNK connection state. In this state, the first enable control switch 22 (P1) is turned off, and the second enable control switch 31 (P2) is turned on, that is, the gate of the first enable control switch 22 (P1) is connected to the internal power supply VDD, and the gate of the second enable control switch 31 (P2) is grounded. The voltage of the CC pin 13 is generated by the voltage division of the Rp_SRC resistor 16 at the other end of the Type-C interface, the first resistor 12 (R1) and the second resistor 32 (R2) of this Type-C interface, that is, (VDDSRC×(R1 + R2)) / ((Rp_SRC + R1 + R2)), generally lower than 2.6V; when the PD communication circuit 24 is working properly, the voltage of the CC pin 13 is generally lower than 1.2V. Therefore, the high-voltage NMOS 11 can transfer the voltage signal between the source node of the high-voltage NMOS 11 and the CC pin 13 without loss. At the same time, when a high voltage appears on the CC pin 13, the high-voltage NMOS 11 and the Zener diode 33 can also ensure the breakdown voltage safety of the first low-voltage area 2 and the second low-voltage area 3.

[0032] When the Type-C DRP embodiment is in the Dead Battery state, the voltage of the corresponding internal power supply VDD is 0, and the gate voltages of the first enable control switch 22 (P1), the second enable control switch 31 (P2) and the high-voltage NMOS 11 are defaulted to low potential, and the high-voltage NMOS 11 remains off. At this time, when the Rp_SRC resistor 16 at the other end of the Type-C interface appears, it will pull up the voltage of the CC pin 13. At the same time, when the voltage of the series node of the first resistor circuit and the second resistor circuit is higher than the threshold voltage of the second enable control switch 31 (P2), the second enable control switch 31 (P2) will turn on and make the voltage of the CC pin 13 within the voltage range of the connection state. Then, after the other end of the Type-C interface recognizes the voltage of the CC pin 13, it enters the SRC connection state and sends VBUS over to activate the Dead Battery state of this Type-C interface. Different from Figure 1 , Figure 1 Schematic diagram of the CC pin circuit of the existing Type-C in the SNK connection state. When this circuit is applied to the DRP or SNK mode, after the Type-C interface enters the Dead Battery state, the internal power supply VDD is 0 and the high-voltage NMOS is turned off. At this time, when connecting to the SRC or other DRP, a pull-down path for connecting the CC pin 13 cannot be formed, and the voltage of the CC pin 13 is pulled up to the power supply VDDSRC of the other end of the Type-C interface, so CC connection cannot be achieved, and the other end of the Type-C interface will not output VBUS, resulting in the Dead Battery state that cannot be activated all the time.

[0033] SeeFigure 6 , Figure 6 This is a schematic diagram of the circuit structure of an embodiment in which the present invention is applied to the Type-C SRC mode. In this embodiment, the overall circuit structure is divided into a high-voltage region 1 and a first low-voltage region 2. The high-voltage NMOS 11 and the CC pin 13 are in the high-voltage region 1, and the pull-up resistor circuit, the CC connection detection circuit 23, and the PD communication circuit 24 are in the first low-voltage region 2. Specifically, if the on-off control of the pull-up resistor circuit is not supported, the first enable control switch 22 (P1) may not be adopted. The working process of this embodiment is the same as that of the SRC non-connected state and the SRC connected state of the Type-C DRP mode embodiment, and will not be described again here.

[0034] See Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of the first embodiment in which the present invention is applied to the Type-C SNK mode. In this embodiment, the overall circuit structure is divided into a high-voltage region 1, a first low-voltage region 2, and a second low-voltage region 3. The high-voltage NMOS 11, the first resistor circuit, and the CC pin 13 are in the high-voltage region 1, the CC connection detection circuit 23 and the PD communication circuit 24 are in the first low-voltage region 2. The second resistor circuit and the voltage clamping circuit are in the second low-voltage region 3. If the on-off control of the pull-down resistor circuit is not supported, the second enable control switch 31 (P2) and the Zener diode 33 may not be adopted, and then the first resistor 12 and the second resistor 32 can be combined into a pull-down resistor of about 5.1 kΩ and placed in the high-voltage region 1, specifically as Figure 8 shown. The working process of this embodiment is the same as that of the SNK non-connected state and the SNK connected state of the Type-C DRP mode embodiment, and will not be described again here.

[0035] In summary, a CC pin circuit of a USB Type-C of the present invention divides the overall circuit structure into three regions: a high-voltage region, a first low-voltage region, and a second low-voltage region through a delicate circuit structure design, which can solve the voltage withstand problem of the CC pin. At the same time, by directly connecting the pull-down resistor circuit to the CC pin, a pull-down path can be formed when the Type-C interface is in the dead battery state of the DRP or SNK mode, and the connection of the CC can be normally realized when accessing the SRC or other DRPs, thereby activating the dead battery state and realizing the effective transmission of the voltage signal of the CC pin.

[0036] Finally, it should be emphasized that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A CC pin circuit for USB Type-C, comprising a high-voltage NMOS, a pull-up resistor circuit, a CC connection detection circuit, a PD communication circuit, a pull-down resistor circuit, and a voltage clamping circuit. The gate of the high-voltage NMOS is connected to the internal power supply VDD. One ends of the pull-up resistor circuit, the CC connection detection circuit, and the PD communication circuit are all connected to the source of the high-voltage NMOS. The drain of the high-voltage NMOS is connected to the pull-down resistor circuit and the first end of the CC pin; Characterized in that: The pull-down resistor circuit includes a first resistor circuit and a second resistor circuit connected in series. The voltage clamping circuit is connected between the series node of the first resistor circuit and the second resistor circuit and the ground; The first resistor circuit includes a first resistor. The second resistor circuit includes a second resistor and a second enable control switch. The second enable control switch is connected in series between the first resistor and the second resistor. The other end of the second resistor is grounded; The CC pin circuit is divided into a high-voltage region, a first low-voltage region, and a second low-voltage region. The high-voltage NMOS, the first resistor circuit, and the CC pin are in the high-voltage region. The pull-up resistor circuit, the CC connection detection circuit, and the PD communication circuit are in the first low-voltage region. The second resistor circuit and the voltage clamping circuit are in the second low-voltage region.

2. The CC pin circuit of the USB Type-C according to claim 1, wherein: The high-voltage NMOS is an NMOS with a breakdown voltage greater than the highest voltage of VBUS of the Type-C interface.

3. The CC pin circuit of the USB Type-C according to claim 1, wherein: The pull-up resistor circuit includes an impedance device and a first enable control switch connected in series. The end of the pull-up resistor circuit far from the source of the high-voltage NMOS is connected to the internal power supply VDD.

4. The CC pin circuit of the USB Type-C according to claim 3, characterized in that: The impedance device is a resistor or a current source.

5. The CC pin circuit of the USB Type-C according to any one of claims 3 to 4, characterized in that: The first enable control switch is a PMOS, NMOS, PNP, or NPN device.

6. The CC pin circuit of the USB Type-C according to any one of claims 1 to 4, characterized in that: The second enable control switch is a PMOS or PNP device.

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