Semiconductor device with stress relief structure

Abstract

The present invention relates to a semiconductor device with a stress relief structure. The semiconductor device includes: a semiconductor body; a stress relief layer or layer stack disposed on at least a portion of the semiconductor body, the stress relief layer or layer stack including a plurality of openings that produce a patterned surface topography for the stress relief layer or layer stack; and a metal layer or layer stack formed on the stress relief layer or layer stack and occupying the plurality of openings in the stress relief layer or layer stack. The patterned surface topography of the stress relief layer or layer stack is transferred to a surface of the metal layer or layer stack that faces away from the semiconductor body. The stress relief layer or layer stack has an elastic modulus different from that of the metal layer or layer stack within a certain temperature range.

Description

Background Art

[0001] The demand for power semiconductor devices with lower on-state resistance (RdsON) values, smaller die (chip) areas, and smaller packages is increasing. In addition to technological advances in semiconductor processing and conceptual unit design, improvements in die metallization and package-to-die interaction are required to meet this increased demand. Recent advances in die metallization and package-to-die interaction include the use of copper metallization on the die and copper clips in the package.

[0002] The introduction of copper metallization introduces new challenges to the die-to-package interaction compared to standard aluminum metallization. Increased bow / warping and higher residual stresses within the die after the soldering process are two examples of the challenges introduced by incorporating copper into the die and packaging technology. Die bow / warping and residual stresses can significantly impact the die and clip attach process, resulting in the formation of voids in the solder and a tilted die relative to the lead frame or other substrate to which the die is attached.

[0003] The formation of voids within the conductive connections, such as between the die and the die attach substrate or between the die and the clip, may hamper the electrical and thermal performance of the packaged device to such an extent that early failure may occur. Moreover, packaged devices having such voids cannot always be screened out.

[0004] If the die is tilted relative to the substrate it is attached to, there may be an unusually small amount of solder under one corner or edge of the die compared to the other corners / edges. During temperature cycling, the unusually small amount of solder may degrade, causing early failure of the device.

[0005] Therefore, more robust techniques are needed to reduce die bending / warping and higher residual stresses within the die. Summary of the invention

[0006] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor body; a stress relief layer or layer stack disposed on at least a portion of the semiconductor body, the stress relief layer or layer stack including a plurality of openings that produce a patterned surface topography for the stress relief layer or layer stack; and a metal layer or layer stack formed on the stress relief layer or layer stack and occupying the plurality of openings in the stress relief layer or layer stack. The patterned surface topography of the stress relief layer or layer stack is transferred to a surface of the metal layer or layer stack that faces away from the semiconductor body. The stress relief layer or layer stack has an elastic modulus different from that of the metal layer or layer stack over a temperature range. In one embodiment, the stress relief layer or layer stack has an elastic modulus smaller than that of the metal layer or layer stack over a temperature range. In another embodiment, the stress relief layer or layer stack has an elastic modulus higher than that of the metal layer or layer stack over a temperature range.

[0007] In an embodiment, the stress mitigating layer or layer stack may include a material selected from the group consisting of polymers, imides, alloys of aluminum and copper, oxides, nitrides, silicon nitrides, oxynitrides, nitride-based ceramics, and SiCOH.

[0008] Alternatively or in combination, the semiconductor device may further include a wiring layer on which a stress relief layer or layer stack is formed, wherein the metal layer or layer stack may be in electrical contact with the wiring layer through a plurality of openings in the stress relief layer or layer stack. The plurality of openings in the stress relief layer or layer stack may be arranged independently of the layout of the wiring layer.

[0009] Alone or in combination, the metal layer or layer stack may be the uppermost metal layer of the semiconductor device. Portions of the stress mitigation layer or layer stack may be free of openings or have large openings to provide a generally flat surface topography, above which the metal layer or layer stack may include one or more contact pads.

[0010] Alone or in combination, the plurality of openings in the stress mitigating layer or layer stack may be arranged in a regular pattern, such that the patterned surface topography of the stress mitigating layer or layer stack may have a regular pattern.

[0011] Alone or in combination, the plurality of openings in the stress mitigating layer or layer stack may be arranged in a checkerboard pattern, a honeycomb pattern, or stripes, such that the patterned surface topography of the stress mitigating layer or layer stack may have a checkerboard pattern, a honeycomb pattern, or a stripe pattern, respectively.

[0012] Either alone or in combination, the stress mitigating layer or layer stack may have a corrugated profile with alternating ridges and grooves in a cross-section through any row of the plurality of openings.

[0013] Either alone or in combination, the plurality of openings in the stress mitigation layer or layer stack may comprise an arrangement of regularly spaced openings having the same or substantially the same shape. For example, the shape of the regularly spaced openings may be selected from the group consisting of square, rectangular, hexagonal, elliptical, and polygonal.

[0014] Either alone or in combination, the plurality of openings in the stress mitigating layer or layer stack may comprise rows of regularly spaced openings of the same shape.

[0015] Individually or in combination, the stress mitigation layer or layer stack may cover between 10% and 100% of the entire main surface of the semiconductor body on which the stress mitigation layer or layer stack is arranged. For example, the stress mitigation layer or layer stack may cover the entire main surface of the semiconductor body on which the stress mitigation layer or layer stack is arranged.

[0016] Alone or in combination, a plurality of openings may be formed in the stress mitigation layer or layer stack over a first portion of the semiconductor body, and the stress mitigation layer or layer stack may have no openings or have large openings over a second portion of the semiconductor body adjacent to the first portion to provide a substantially flat surface topography. For example, the first portion of the semiconductor body may be a central portion of the semiconductor body, and the second portion of the semiconductor body may be a peripheral region of the semiconductor body laterally surrounding the central portion.

[0017] Alone or in combination, the metal layer or layer stack may include: a barrier metal layer covering a top major surface of the stress mitigating layer or layer stack and sidewalls of an opening in the stress mitigating layer or layer stack; and a copper layer covering the barrier metal layer.

[0018] Either alone or in combination, in the same row of openings in a stress mitigation layer or layer stack, the spacing between adjacent ones of the openings may be approximately equal to the width of the openings.

[0019] Alone or in combination, the metal layer or layer stack may comprise copper.

[0020] Alone or in combination, a stress mitigation layer or layer stack may be formed on the AlCu layer, and the metal layer or layer stack may be in electrical contact with the AlCu layer through a plurality of openings or through a large opening in the stress mitigation layer or layer stack.

[0021] Alone or in combination, the stress mitigation layer or layer stack may include doped regions and / or polysilicon at a rear main surface of a semiconductor body structured with grooves, and the metal layer or layer stack may include a barrier layer covering the structured rear main surface of the semiconductor body, and a copper layer formed on the barrier layer and filling the grooves in the structured rear main surface of the semiconductor body.

[0022] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming one or more devices in a semiconductor body; forming a stress relief layer or layer stack over at least a portion of the semiconductor body; forming a plurality of openings in the stress relief layer or layer stack, and which produces a patterned surface topography for the stress relief layer or layer stack; and forming a metal layer or layer stack on the stress relief layer or layer stack, so that the metal layer or layer stack occupies the plurality of openings in the stress relief layer or layer stack, and the patterned surface topography of the stress relief layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body, and the metal layer or layer stack has an elastic modulus different from that of the stress relief layer or layer stack over a certain temperature range. In one embodiment, the metal layer or layer stack has an elastic modulus higher than that of the stress relief layer or layer stack over a certain temperature range. In another embodiment, the metal layer or layer stack has an elastic modulus lower than that of the stress relief layer or layer stack over a certain temperature range. Alone or in combination, forming a stress relief layer or layer stack over at least a portion of the semiconductor body may include forming a doped region and / or polysilicon at a rear main surface of the semiconductor body and structuring the rear main surface to have grooves, and forming a metal layer or layer stack on the stress relief layer or layer stack may include covering the structured rear main surface of the semiconductor body with a barrier layer and filling the grooves with a copper layer formed on the barrier layer.

[0023] According to an embodiment of a semiconductor package, the semiconductor package includes a semiconductor device, which includes: a semiconductor body; a stress relief layer or layer stack disposed on at least a portion of the semiconductor body, the stress relief layer or layer stack including a plurality of openings that produce a patterned surface topography for the stress relief layer or layer stack; and a metal layer or layer stack formed on the stress relief layer or layer stack and occupying a plurality of openings in the stress relief layer or layer stack. The patterned surface topography of the stress relief layer or layer stack is transferred to a surface of the metal layer or layer stack that faces away from the semiconductor body. The stress relief layer or layer stack has an elastic modulus different from that of the metal layer or layer stack within a certain temperature range. The semiconductor package also includes a metal connector attached to the metal layer or layer stack. In one embodiment, the stress relief layer or layer stack has an elastic modulus smaller than that of the metal layer or layer stack within a certain temperature range. In another embodiment, the stress relief layer or layer stack has an elastic modulus higher than that of the metal layer or layer stack within a certain temperature range.

[0024] In an embodiment, portions of the stress mitigation layer or layer stack may be free of openings or have larger openings to provide a substantially flat surface topography, upon which the metal layer or layer stack may include contact pads, and metal connectors may be attached to the contact pads.

[0025] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The elements in the figures are not necessarily drawn to scale relative to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. The embodiments are described in detail in the figures and in the following description.

[0027] Figure 1 A cross-sectional view of a portion of a semiconductor device with a stress mitigating layer or layer stack is shown.

[0028] Figure 2 A perspective view showing a stress mitigating layer or layer stack and a metal layer or layer stack formed on the stress mitigating layer or layer stack.

[0029] Figure 3 A perspective view showing a stress mitigation layer or layer stack without a metal layer or layer stack is shown.

[0030] Figure 4A A plan view showing a metal layer or layer stack formed on a stress mitigation layer or layer stack.

[0031] Figure 4B Shown by Figure 4A A cross-sectional view of the structure taken along the line marked AA' in FIG.

[0032] Figure 4C Shown by Figure 4A A cross-sectional view of the structure taken along the line marked BB' in FIG.

[0033] Figure 5 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0034] Figure 6 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0035] Figure 7 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0036] Figure 8 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0037] Fig. 9 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0038] Fig.10 A plan view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0039] Fig.11 A partial cross-sectional view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack having a smaller elastic modulus than the metal layer or layer stack is shown.

[0040] Fig.12 A partial cross-sectional view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0041] Fig.13 A partial cross-sectional view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack is shown.

[0042] Fig.14 Shown including Figure 1 0 is a cross-sectional view of a semiconductor package of a semiconductor device shown in .

[0043] Fig.15A and 15B Corresponding cross-sectional views of portions of semiconductor devices with stress mitigating layers or layer stacks are shown.

[0044] Fig.16 A partial cross-sectional view of another embodiment of a metal layer or layer stack formed on a stress mitigating layer or layer stack having a higher elastic modulus than the metal layer or layer stack is shown. DETAILED DESCRIPTION

[0045] Embodiments described herein provide a stress mitigation layer or layer stack disposed over at least a portion of a semiconductor body for counteracting stress applied by a metal layer or layer stack disposed over the stress mitigation layer or layer stack. The stress mitigation layer or layer stack has a plurality of openings that produce a patterned surface topography. The patterned surface topography for the stress mitigation layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress mitigation layer or layer stack absorbs at least some of the stress applied by the metal layer or layer stack during temperature cycling and / or residual stress stored within the metal layer or layer stack, thereby reducing the likelihood of high mechanical stress and die bending / warping.

[0046] Figure 1A cross-sectional view of a portion of a semiconductor device 100 is shown. The semiconductor device 100 includes a semiconductor body 102. The semiconductor body 102 is a portion of a semiconductor wafer before die singulation, or may be a portion of a semiconductor die (chip) after die singulation. In either case, one or more passive and / or active devices may be formed in the semiconductor body 102. For example, logic devices such as processors, ASICs (application specific integrated circuits), memories, controllers, etc. may be formed in the semiconductor body 102. Additionally or alternatively, power devices such as insulated gate bipolar transistors (IGBTs), power metal oxide semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), power diodes, half bridges, full bridges, etc. may also be formed in the semiconductor body 102. Additionally or alternatively, sensors such as Hall sensors, micro-electromechanical systems (MEMS), etc. may also be formed in the semiconductor body 102. Still other types of passive and / or active devices may also be formed in the semiconductor body 102. For ease of illustration, the device(s) formed in the semiconductor body 102 are shown in FIG. Figure 1 Not shown, but may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc.

[0047] A stress mitigating layer (i.e., a single stress mitigating layer) or a layer stack (i.e., more than one stress mitigating layer stacked one on top of another) 104 is disposed over at least a portion of the semiconductor body 102. That is, the stress mitigating layer or layer stack 104 covers all or only a portion of the semiconductor body 102. For example, the stress mitigating layer or layer stack 104 may cover 10% to 100% of the entire main surface 106 of the semiconductor body 102 over which the stress mitigating layer or layer stack 104 is disposed. In one embodiment, the stress mitigating layer or layer stack 104 may cover the entire main surface 106 of the semiconductor body 102 over which the stress mitigating layer or layer stack 104 is disposed.

[0048] The stress mitigation layer or layer stack 104 has a plurality of openings 108 that produce a patterned surface topography for the stress mitigation layer or layer stack 104. That is, a surface 110 of the stress mitigation layer or layer stack 104 facing away from the semiconductor body 102 has a patterned shape defined by the number, spacing, shape, and size of the openings 108 formed in the stress mitigation layer or layer stack 104. The openings 108 in the stress mitigation layer or layer stack 104 may be arranged in a regular or irregular pattern such that the patterned surface topography of the stress mitigation layer or layer stack 104 has a corresponding regular or irregular pattern, respectively. The openings 108 may be formed by a standard etching process such as masking and wet or dry etching of the stress mitigation layer or layer stack 104, by laser drilling of the stress mitigation layer or layer stack 104, by patterned deposition of the stress mitigation layer or layer stack 104, and the like.

[0049] A metal layer (i.e., a single metal layer) or layer stack (i.e., more than one metal layers stacked one on top of another) 112 is formed on the stress mitigation layer or layer stack 104 and occupies the opening 108 in the stress mitigation layer or layer stack 104. The metal layer or layer stack 112 may partially or completely fill the opening 108 in the stress mitigation layer or layer stack 104. Any commonly used metal(s) or metal stacks in the semiconductor industry may be used.

[0050] The patterned surface topography of the stress mitigation layer or layer stack 104 is transferred to a surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102. Thus, the surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102 has the same or substantially the same patterned shape as the surface 110 of the stress mitigation layer or layer stack 104 facing away from the semiconductor body 102. Although the metal layer or layer stack 112 and the stress mitigation layer or layer stack 104 have the same or substantially the same overall shape / structure / profile, the relative dimensions may be different. For example, the vertical sidewalls 116 of the opening 108 in the stress mitigation layer or layer stack 104 may be covered with slightly more or slightly less material than the horizontal portions 118, and the thickness of the metal layer or layer stack 112 along the sidewalls 116 of the opening 108 may be different from the thickness of the metal layer or layer stack 112 on the horizontal portions 118 of the stress mitigation layer or layer stack 104 and at the bottom 120 of the opening 108. Furthermore, the surface 114 of the metal layer or layer stack 112 having the patterned topography is not planarized. Therefore, the metal layer or layer stack 112 retains the patterned surface topography transferred from the stress mitigation layer or layer stack 104. The metal layer or layer stack 112 may be a thick layer such that the patterned surface topography transferred from the stress mitigation layer or layer stack 104 may be barely visible.

[0051] The stress mitigation layer or layer stack 104 also has a different elastic modulus (e.g., Young's modulus) than the metal layer or layer stack 112 within a certain temperature range, which may or may not be the entire (entire) operating range of the semiconductor device 100. In one embodiment, the stress mitigation layer or layer stack 104 has a smaller elastic modulus than the metal layer or layer stack 112 within the temperature range of interest. For example, the stress mitigation layer or layer stack 104 may include one or more of a stable or soluble polymer, an imide, an alloy of aluminum and copper, and an oxide. The stress mitigation layer or layer stack 104 absorbs at least some of the stress applied by the metal layer or layer stack 112 during temperature cycling and / or residual stress stored in the metal layer or layer stack 112, thereby reducing the possibility of high mechanical stress and die bending / warping.

[0052] In another embodiment, the stress mitigation layer or layer stack 104 has a higher elastic modulus than the metal layer or layer stack 112 in the temperature range of interest. For example, the stress mitigation layer or layer stack 104 may include one or more of a tungsten-based alloy (e.g., with titanium or nitride), nickel or a nickel-based alloy (e.g., with vanadium or phosphorus), doped silicon, and / or polysilicon. In the case of doped silicon, the rear main surface 122 of the semiconductor body 102 may be doped with phosphorus, then structured, e.g., by etching, and then filled, e.g., with copper. The stress mitigation layer or layer stack 104 may compensate for some of the stress and / or residual stress applied by the metal layer or layer stack 112 during temperature cycling in a manner that reduces the likelihood of high mechanical stresses and die bending / warping.

[0053] The metal layer or layer stack 112 and the corresponding stress mitigation layer or layer stack 104 may be applied over either side of the semiconductor body 102. That is, the metal layer or layer stack 112 and the corresponding stress mitigation layer or layer stack 104 may be applied on the front main surface 106 of the semiconductor body 102, on the back main surface 122 of the semiconductor body 102, or on both main surfaces 106, 122.

[0054] The metal layer or layer stack 112 having the same or substantially the same patterned surface topography as the stress mitigation layer or layer stack 104 may be the uppermost (final) metallization of the semiconductor device 100. In this case, the metal layer or layer stack 112 provides one or more external electrical contacts for the device(s) formed in the semiconductor body 102. For example, in the case of power transistor devices such as IGBTs, bipolar transistors, HEMTs, MEMS, etc., the metal layer or layer stack 112 may include a gate pad, a source pad, and / or a drain pad. In the case of a power diode device, the metal layer or layer stack 112 may include an anode pad and / or a cathode pad. In the case of a logic device, the metal layer or layer stack 112 may include a large number of pads.

[0055] Alternatively, the metal layer or layer stack 112 having the same or substantially the same patterned surface topography as the stress mitigation layer or layer stack 104 may be the lowermost (first) metallization closest to the semiconductor body 102. In this case, an additional layer or layer stack 124 may be provided above the metal layer or layer stack 112, such as an oxide or one or more additional metal layers or layer stacks. The number and composition of layers disposed above the metal layer or layer stack 112 may vary for different regions of the semiconductor device 100, independent of the metal layer or layer stack 112 and the stress mitigation layer or layer stack 104. Alternatively, the metal layer or layer stack 112 having the same or substantially the same patterned surface topography as the stress mitigation layer or layer stack 104 may be an intermediate metallization. In this case, one or more additional metal layers or layer stacks are formed above the intermediate metal layer or layer stack, and one or more additional metal layers or layer stacks are formed below the intermediate metal layer or layer stack, wherein an interlayer dielectric separates the different metallization layers.

[0056] Figure 1 A metal layer or layer stack 112 is shown as the uppermost (final) metallization or as an intermediate metallization. In this case, one or more additional metallization layers may be provided between the metal layer or layer stack 112 and the semiconductor body 102, and the additional layer(s) may be arranged between the intermediate metallization and the semiconductor substrate, as indicated by the vertical dashed lines.

[0057] For example, one of the additional layers or layer stacks 124 may be an additional metallization, such as a wiring layer on which the stress mitigation layer or layer stack 104 is formed. A metal layer or layer stack 112 having the same or substantially the same patterned surface topography as the stress mitigation layer or layer stack 104 may be in electrical contact with the additional metallization layer through an opening 108 in the stress mitigation layer or layer stack 104. In one embodiment, the opening 108 in the stress mitigation layer or layer stack 104 is arranged independently of the layout of the additional metallization layer 124. That is, while the opening 108 in the stress mitigation layer or layer stack 104 enables electrical contact between the two metallization layers 112, 124 separated by the stress mitigation layer or layer stack 104, the layout of the opening 108 is designed so that the stress mitigation layer or layer stack 104 absorbs at least some of the stress applied by the overlying metal layer or layer stack 112 and / or residual stress stored in the metal layer or layer stack 112 during temperature cycling.

[0058] Figure 2 A perspective view of a stress mitigating layer or layer stack 104 and a metal layer or layer stack 112 having the same or substantially the same patterned surface topography is shown in accordance with an embodiment. Figure 3A perspective view of the stress mitigation layer or layer stack 104 is shown without the metal layer or layer stack 112. According to this embodiment, the stress mitigation layer or layer stack 104 has rows 126 of regularly spaced openings 108 of the same or substantially the same shape. The shape of the regularly spaced openings 108 can be square, rectangular, hexagonal, elliptical, polygonal, etc. Although in Figure 2 and 3 The openings 108 in the stress mitigation layer or layer stack 104 are shown as being arranged in a regular pattern, but instead, the pattern may be irregular. In either case, the patterned surface topography of the stress mitigation layer or layer stack 104 is transferred to the metal layer or layer stack 112 formed on the stress mitigation layer or layer stack 104, so that the metal layer or layer stack 112 has the same or substantially the same patterned surface topography as the stress mitigation layer or layer stack 104.

[0059] Figure 4A A plan view of a metal layer or layer stack 112 formed on the stress mitigating layer or layer stack 104 is shown. Figure 4B Shown by Figure 4A A cross-sectional view of the structure taken along the line marked AA' in FIG. Figure 4C Shown by Figure 4A As described above, the metal layer or layer stack 112 may be an uppermost (final) metallization, a lowermost (first) metallization, or an intermediate metallization.

[0060] Figure 4B The cross section in FIG. 1 crosses through a row of openings 108 in the stress mitigation layer or layer stack 104, and Figure 4C The cross section in FIG. 1 crosses through the structure between adjacent rows 108. According to this embodiment, the stress mitigation layer or layer stack 104 covers the entire main surface 106 of the semiconductor body 102 on which the stress mitigation layer or layer stack 104 is arranged. Figure 4B and 4C As shown, the surface topography of the metal layer or layer stack 112 follows the surface topography of the stress mitigation layer or layer stack 104. That is, the surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102 has the same or substantially the same patterned shape as the surface 110 of the stress mitigation layer or layer stack 104 facing away from the semiconductor body 102.

[0061] Figure 5 1 shows a plan view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigation layer or layer stack 104. According to this embodiment, the metal layer or layer stack 112 is the uppermost (final) metal layer of the semiconductor device 100. Figure 5, the stress relief layer or layer stack 104 is not in view. However, a portion of the stress relief layer or layer stack 104 has no openings and has a substantially flat surface topography. The substantially flat surface topography is transferred to the metal layer or layer stack 112. The metal layer or layer stack 112 may include one or more contact pads 200 disposed on a portion of the stress relief layer or layer stack 104 without openings, for example, in the case where a current or temperature sensor is laid in a flat portion of the metal layer or layer stack 112. That is, one or more contact pads 200 are formed in a portion 202 of the metal layer or layer stack 112 having a substantially flat surface topography. In another embodiment, a portion of the stress relief layer or layer stack 104 has a large opening to provide a substantially flat surface topography, on which one or more contact pads 200 are formed to, for example, contact a metal layer disposed below the stress relief layer or layer stack 104. In either case, each contact pad 200 has a flat surface relative to the top. External electrical connections can be made to one or more contact pads 200, for example, by bonding wires, metal ribbons, metal clips, solder, etc. The remainder of the metal layer or layer stack 112 has a non-planar surface topography that mimics the non-planar surface topography of the underlying stress mitigation layer or layer stack 104 . Figure 5 The exploded view in magnifies the boundary between the planar and non-planar surface topography of the metal layer or layer stack 112 .

[0062] The metal layer or layer stack 112 may include one or more bridge regions 201 for electrically connecting adjacent regions of the metal layer or layer stack 112 without connecting the metal layer or layer stack 112 to underlying conductive structures, such as metal or polysilicon lines. The underlying conductive structures may be source fingers, gate fingers, etc., which are laid down under the metal layer or layer stack 112. As described herein, a stress mitigation layer or layer stack 104 is present under each bridge region 201 and serves as a bridge mechanism for connecting adjacent regions of the metal layer or layer stack 112 while also isolating the metal layer or layer stack 112 from the underlying conductive structures, such as in the case of metal connections for gate fingers, source fingers, sensors such as current or temperature, etc.

[0063] Figure 6A plan view of another embodiment of a metal layer or layer stack 112 formed on a stress mitigation layer or layer stack 104 is shown. According to this embodiment, the openings 108 in the stress mitigation layer or layer stack 104 are arranged in a checkerboard pattern so that the patterned surface topography of the stress mitigation layer or layer stack 104 has a checkerboard pattern that is transferred to the metal layer or layer stack 112. The spacing (Sp) between adjacent openings 108 in the same row 126 of openings 108 in the stress mitigation layer or layer stack 104 can be approximately equal to the width (W) of the openings 108. Other spacings and widths are contemplated. The spacing (Sp) and width (W) can be different and can be different between rows of openings 108 in the stress mitigation layer or layer stack 104. The openings 108 in the stress mitigation layer or layer stack 104 can be arranged in a checkerboard pattern. Figure 6 Not visible in.

[0064] Figure 7 A plan view of another embodiment of a metal layer or layer stack 112 formed on a stress mitigation layer or layer stack 104 is shown. According to this embodiment, the openings 108 in the stress mitigation layer or layer stack 104 are arranged in a honeycomb pattern so that the patterned surface topography of the stress mitigation layer or layer stack 104 has a honeycomb pattern that is transferred to the metal layer or layer stack 112. The spacing (Sp) between adjacent openings 108 in the same row 126 of openings 108 in the stress mitigation layer or layer stack 104 can be approximately equal to the width (W) of the openings 108. Other spacings and widths are contemplated. The spacing (Sp) and width (W) can be different and can be different between rows of openings 108 in the stress mitigation layer or layer stack 104. The openings 108 in the stress mitigation layer or layer stack 104 can be arranged in a honeycomb pattern. Figure 7 Not visible in.

[0065] Figure 8 A plan view of another embodiment of a metal layer or layer stack 112 formed on a stress mitigation layer or layer stack 104 is shown. According to this embodiment, the metal layer or layer stack 112 covers at least 90% of the semiconductor body 102 and is segmented into separate portions 300, 302, 304. Some of the portions 300, 302, 304 may include contact pads 306, and / or some or all of the portions 300, 302, 304 may themselves form contact pads. In each case, each portion 300, 302, 304 of the metal layer or layer stack 112 has the same or substantially the same patterned shape as the portion of the surface of the stress mitigation layer or layer stack 104 underlying the portion 300, 302, 304. The separated portions 300, 302, 304 may be electrically connected to each other via bridge regions, for example, as previously described herein. Figure 5 as described.

[0066] Fig. 9A plan view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigating layer or layer stack 104 is shown. Fig. 9 The embodiment shown in is similar to Figure 8 However, in contrast, the metal layer or layer stack 112 covers less than 90% of the semiconductor body 102 , for example between approximately 75% and 25%.

[0067] Fig.10 A plan view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigating layer or layer stack 104 is shown. According to this embodiment, the stress mitigating layer or layer stack 104 has a corrugated profile with alternating ridges 400 and grooves 402 in a transverse cross-section through any row of the plurality of openings 108. The metal layer or layer stack 112 has the same or substantially the same corrugated profile as the stress mitigating layer or layer stack 104.

[0068] Fig.11 A partial cross-sectional view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigation layer or layer stack 104 is shown. According to this embodiment, the metal layer or layer stack 112 includes a barrier metal layer 500, such as WTi, Ta, TaN, TiN, Ti, W, TiW, etc., which covers the top major surface 110 of the stress mitigation layer or layer stack 104 and the sidewalls 116 of the opening 108 in the stress mitigation layer or layer stack 104. The metal layer or layer stack 112 includes a copper layer 502 covering the barrier metal layer 500. The barrier metal layer 500 and the copper layer 502 can be formed using any common copper metallurgy process, such as physical or chemical deposition, electroplating, etc. In some cases, the barrier metal layer 500 can be omitted if the base metal composition of the metal layer or layer stack 112 is unlikely to diffuse, for example, in the case of a Cu-Ge alloy such as epitaxial Cu3Ge. The material on which the stress mitigation layer or layer stack 104 is formed may be the semiconductor body 102 , another layer or layer stack 124 (e.g. such as another Cu layer, an AlCu layer, etc.), or an insulating layer (e.g. such as an oxide, a nitride, silicon nitride, an oxynitride, a nitride-based ceramic, SiCOH, etc.).

[0069] Fig.12 A partial cross-sectional view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigating layer or layer stack 104 is shown. Fig.12The exploded view in FIG. 1 magnifies a portion of the semiconductor device shown. According to this embodiment, the stress mitigation layer or layer stack 104 includes an imide and covers the entire main surface 106 of the semiconductor body 102 on which the stress mitigation layer or layer stack 104 is disposed. The overlying metal layer or layer stack 112 includes a barrier metal layer 600, such as WTi, Ta, TaN, TiN, etc., which covers the top main surface 110 of the stress mitigation layer or layer stack 104 and the sidewalls 116 of the opening 108 in the stress mitigation layer or layer stack 104. The overlying metal layer or layer stack 112 includes a copper layer 602 covering the barrier metal layer 600. The barrier metal layer 600 and the copper layer 602 can be formed using any common copper metallurgy process, such as physical or chemical deposition, electroplating, etc. The overlying metal layer or layer stack 112 is in electrical contact with the underlying metal layer or layer stack 124 through the opening 108 in the stress mitigation layer or layer 104. In one embodiment, the underlying metal layer or layer stack 124 includes an AlCu layer 604 on which the stress mitigation layer or layer 104 is formed and a barrier layer 606 such as W, TiW, etc. below the AlCu layer. The barrier layer 606 is separated from the semiconductor body 102 by a dielectric layer 608 such as borophosphosilicate glass (BPSG), for example. The dielectric layer 608 may have a trench that allows electrical contact with the semiconductor body 102.

[0070] The plurality of openings 108 in the stress mitigating layer or layer stack 104 may be arranged in a regular or irregular pattern such that the patterned surface topography of the stress mitigating layer or layer stack 104 has a corresponding regular or irregular pattern, respectively. Fig.12 An embodiment is shown in which the spacing (Sp) between adjacent openings 108 in the same row of openings 108 in the stress mitigation layer or layer stack 104 is approximately equal to the width (W) of the opening 108. For example, the spacing (Sp) and width (W) may be approximately 10 μm (micrometers). Other spacings and widths may be contemplated, and the 10 μm example given above is purely illustrative and should not be considered limiting. The spacing (Sp) and width (W) parameters may be different and may be different between rows of openings 108 in the stress mitigation layer or layer stack 104.

[0071] The height or thickness (H) of the stress mitigation layer or layer stack 104 may be, for example, in the range of about 6 to 11 μm. The inventors have found that increasing the height / thickness (H) of the imide-based stress mitigation layer or layer stack with patterned surface topography (from about 6 μm to 11 μm as described herein) increases bending / warping at lower temperatures below about 250°C, while for higher temperatures above about 250°C, the bending / warping remains substantially unchanged. Alternatively, the height / thickness (H) of the stress mitigation layer or layer stack 104 may be less than 6 μm or greater than 11 μm. The inventors have also found that for a die having an imide-based stress mitigation layer or layer stack with patterned surface topography as described herein, the bending / warping variation (slope) at about 300°C is flatter than for a die having zero coverage by such a patterned imide-based stress mitigation layer or layer stack. This is particularly important because solidification of the solder occurs around this temperature, resulting in a more stable die attach process with respect to process variations in die handling.

[0072] Fig.13 A partial cross-sectional view of another embodiment of a metal layer or layer stack 112 formed on the stress mitigating layer or layer stack 104 is shown. Fig.13 The embodiment shown in is similar to Fig.12 . However, differently, a plurality of openings 108 in the stress mitigation layer or layer stack 104 are formed over a first portion 700 of the semiconductor body 102, and large openings are formed in the stress mitigation layer or layer stack 104 over a second portion 702 of the semiconductor body 102 adjacent to the first portion 700 to provide a substantially flat surface topography. The metal layer or layer stack 112 contacts the additional layer or layer stack 124 below through the large openings. The inventors have found that partial coverage (e.g., about 50% coverage or an inner portion of the die) of a die having a stress mitigation layer or layer stack having a patterned surface topography as described herein is still beneficial in terms of bow / warping reduction, but not to the same extent as full coverage. The same applies to placing the patterned surface topography on the outer half (periphery) of the die.

[0073] In one embodiment, the first portion 700 of the semiconductor body 102 is a central portion of the semiconductor body 102, and the second portion 702 is a peripheral region of the semiconductor body 102, which is located along at least one side of the central portion or laterally surrounds the central portion in its entirety. The semiconductor device formed in the semiconductor body 102 is disposed in the central portion of the semiconductor body 102, which can be considered as an active region of the semiconductor body 102. The active region of the semiconductor body 102 is a region of the semiconductor body 102 that includes components of the device. For example, the active region may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc.

[0074] Fig.14 Shown include Figure 1 8 is a cross-sectional view of a semiconductor package 800 of a semiconductor device 100 shown in . The semiconductor body 102 of the device 100 is attached to a standard substrate 802, such as a printed circuit board (PCB), a lead frame, etc. The semiconductor package 800 also includes a metal connector 804, such as a clip, attached at one end thereof to a metal layer or layer stack 112 of the semiconductor device 100. The opposite end of the metal connector 804 is attached to the substrate 802, for example, to a metal trace of a PCB, a lead of a lead frame, etc. The metal connector 804 can be coupled to the metal layer or layer stack 112 by solder 806. The inventors have discovered that using a metal layer or layer stack having a patterned surface topography as described herein locates and distributes solder voids in a "recessed" or "sunken" area 808 of the metal layer or layer stack 112.

[0075] In one embodiment, portions of the stress mitigation layer or layer stack 104 may have no openings or large openings to provide a substantially flat surface topography. The metal layer or layer stack 112 may have contact pads disposed on the substantially flat surface topography, for example, as described previously herein in conjunction with Figure 5 , 8 9. In this case, the metal connector 804 can be attached to the contact pad. Still other metal connector attachment configurations are contemplated and are within the scope of the embodiments described herein.

[0076] Although the embodiments previously described herein describe the surface 114 of the metal layer or layer stack 112 having the patterned topography as being non-planarized, the surface 114 may instead be subjected to a planarization process, such as chemical mechanical polishing (CMP). Fig.15A The corresponding semiconductor device 900 is shown. Fig.15A As shown, the top surface 114 of the metal layer or layer stack 112 is generally flat. Since the openings 108 in the stress mitigation layer or layer stack 104 are filled with metal, sufficient stress relief is provided by the stress mitigation layer or layer stack 104. In some cases, for example, Fig. 15B As shown, the top surface 110 of the stress mitigation layer or layer stack 104 may be partially visible after planarization of the metal layer or layer stack 112. Depending on the type of planarization process employed or by design, the metal layer or layer stack 112 may be recessed below the top surface 110 of the stress mitigation layer or layer stack 104.

[0077] Fig.16A partial cross-sectional view of an embodiment in which a copper layer 1000 and a barrier metal layer 1002 are formed on the rear main surface 122 of the semiconductor body 102 to form a back side metallization stack is shown. According to this embodiment, the stress mitigation layer or layer stack 104 has a higher elastic modulus than the back side metallization stack 1000 / 1002 in the temperature range of interest. For example, the stress mitigation layer or layer stack 104 may include doped silicon and / or polysilicon. In the case of doped silicon, the rear main surface 122 of the semiconductor body 102 may be doped with phosphorus and then structured, for example by etching, so that the rear main surface 122 of the semiconductor body 102 has a groove. The rear main surface 122 of the semiconductor body 102 is then covered with the barrier metal layer 1002 and the groove is then filled with the copper layer 1000. The stress mitigation layer or layer stack 104 may compensate for some of the stress and / or residual stress applied by the back side metallization stack 1000 / 1002 during temperature cycling in a manner that reduces the possibility of high mechanical stress and die bending / warping, as previously described herein.

[0078] For ease of description, spatially relative terms such as "lower", "beneath", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device other than those depicted in the accompanying drawings. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0079] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0080] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor body; a stress mitigating layer or layer stack disposed over at least a portion of the semiconductor body, the stress mitigating layer or layer stack comprising a plurality of openings that produce a patterned surface topography for the stress mitigating layer or layer stack; as well as a metal layer or layer stack formed on the stress mitigation layer or layer stack and occupying a plurality of openings in the stress mitigation layer or layer stack, wherein the patterned surface topography of the stress mitigation layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body, wherein the stress relief layer or the layer stack has a different elastic modulus than the metal layer or the layer stack within a certain temperature range, wherein the stress mitigation layer or layer stack and the metal layer or layer stack are both formed in an interlayer dielectric separating different metal layers of a semiconductor device, Therein, a stress relief layer or a layer stack is disposed between the semiconductor body and the last of the different metal layers, Wherein, the plurality of openings in the stress mitigation layer or layer stack are arranged in a regular pattern over the entire area of ​​the stress mitigation layer or layer stack, so that the patterned surface morphology of the stress mitigation layer or layer stack has a regular pattern independent of the layout of any wiring layer of the semiconductor device.

2. The semiconductor device of claim 1 , wherein the stress mitigation layer or layer stack comprises a material selected from the group consisting of polymers, imides, alloys of aluminum and copper, oxides, nitrides, silicon nitrides, oxynitrides, nitride-based ceramics, and SiCOH. 3 . The semiconductor device according to claim 1 , further comprising a wiring layer on which a stress mitigation layer or a layer stack is formed, wherein the metal layer or the layer stack is in electrical contact with the wiring layer through a plurality of openings in the stress mitigation layer or the layer stack. 4 . The semiconductor device of claim 3 , wherein the plurality of openings in the stress mitigation layer or layer stack is arranged independently of the layout of the wiring layer. 5 . The semiconductor device of claim 1 , wherein the metal layer or layer stack is a final metal layer of the semiconductor device and provides one or more external electrical contacts for a power transistor device formed in the semiconductor body. 6 . The semiconductor device of claim 5 , wherein the portion of the stress mitigation layer or layer stack has no openings or has large openings to provide a flat surface topography, above which the metal layer or layer stack comprises one or more contact pads.

7. The semiconductor device of claim 1 , wherein the plurality of openings in the stress mitigation layer or layer stack are arranged in a checkerboard pattern, a honeycomb pattern, or stripes, such that the patterned surface topography of the stress mitigation layer or layer stack has a checkerboard pattern, a honeycomb pattern, or a stripe pattern, respectively. 8 . The semiconductor device of claim 1 , wherein the stress mitigating layer or layer stack has a corrugated profile with alternating ridges and grooves in a cross section through any row of the plurality of openings. 9 . The semiconductor device of claim 1 , wherein the plurality of openings in the stress mitigation layer or layer stack comprises rows of regularly spaced openings of identical or substantially identical shape.

10. The semiconductor device of claim 9, wherein the shape of the regularly spaced openings is selected from the group consisting of a square, a rectangle, a hexagon, an ellipse, and a polygon. 11 . The semiconductor device according to claim 1 , wherein the stress mitigation layer or the layer stack covers between 10% and 100% of the entire main surface of the semiconductor body on which the stress mitigation layer or the layer stack is arranged. 12 . The semiconductor device according to claim 11 , wherein the stress mitigating layer or the layer stack covers the entire main surface of the semiconductor body on which the stress mitigating layer or the layer stack is arranged.

13. The semiconductor device of claim 1 , wherein a plurality of openings are formed in a stress mitigation layer or layer stack over a first portion of the semiconductor body, and wherein the stress mitigation layer or layer stack has no openings or has large openings over a second portion of the semiconductor body adjacent to the first portion to provide a flat surface topography for the second portion. 14 . The semiconductor device of claim 13 , wherein the first portion of the semiconductor body is a central portion of the semiconductor body, and wherein the second portion of the semiconductor body is a peripheral region of the semiconductor body laterally surrounding the central portion.

15. The semiconductor device according to claim 1, wherein the metal layer or layer stack comprises: a barrier metal layer covering the top major surface of the stress mitigating layer or layer stack and sidewalls of the opening in the stress mitigating layer or layer stack; as well as A copper layer covering the barrier metal layer. 16 . The semiconductor device of claim 1 , wherein in a same row of openings in the stress mitigation layer or layer stack, a spacing between adjacent ones of the openings is approximately equal to a width of the openings. The semiconductor device of claim 1 , wherein the metal layer or layer stack comprises copper.

18. The semiconductor device of claim 17, further comprising an AlCu layer on which a stress mitigation layer or layer stack is formed, wherein the metal layer or layer stack is in electrical contact with the AlCu layer through a plurality of openings or through a large opening in the stress mitigation layer or layer stack.

19. The semiconductor device according to claim 1, wherein the semiconductor body comprises: an active region including components of the device; and a peripheral region laterally surrounding the active region; Therein, a plurality of openings in the stress mitigation layer or layer stack are formed over the entire active area.

20. A semiconductor package, comprising: A semiconductor device, comprising: Semiconductor body; a stress mitigating layer or layer stack disposed over at least a portion of the semiconductor body, the stress mitigating layer or layer stack comprising a plurality of openings that produce a patterned surface topography for the stress mitigating layer or layer stack; and a metal layer or layer stack formed on the stress mitigation layer or layer stack and occupying a plurality of openings in the stress mitigation layer or layer stack, wherein the patterned surface topography of the stress mitigating layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body, wherein the stress relief layer or the layer stack has a different elastic modulus than the metal layer or the layer stack within a certain temperature range, wherein the stress mitigation layer or layer stack and the metal layer or layer stack are both formed in an interlayer dielectric separating different metal layers of a semiconductor device, wherein a stress mitigation layer or a layer stack is disposed between the semiconductor body and a last one of the different metal layers; and Metal connectors attached to a metal layer or layer stack, wherein the metal connector is a metal clip connected to a metal layer or layer stack by solder, Therein, a patterned surface topography of the stress mitigating layer or layer stack transferred to a surface of the metal layer or layer stack facing away from the semiconductor body positions and distributes the solder voids in recessed or depressed regions of the metal layer or layer stack.

21. The semiconductor package of claim 20, wherein the portion of the stress mitigation layer or layer stack has no openings or has large openings to provide a flat surface topography, upon which the metal layer or layer stack comprises contact pads, and wherein the metal connectors are attached to the contact pads.

22. A semiconductor device comprising: Semiconductor body; a stress mitigating layer or layer stack disposed over at least a portion of the semiconductor body, the stress mitigating layer or layer stack comprising a plurality of openings that produce a patterned surface topography for the stress mitigating layer or layer stack; as well as a metal layer or layer stack formed on the stress mitigation layer or layer stack and occupying a plurality of openings in the stress mitigation layer or layer stack, wherein the patterned surface topography of the stress mitigation layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body, wherein the stress relief layer or the layer stack has a different elastic modulus than the metal layer or the layer stack within a certain temperature range, wherein the stress mitigation layer or layer stack and the metal layer or layer stack are both formed in an interlayer dielectric separating different metal layers of a semiconductor device, Therein, a stress relief layer or a layer stack is disposed between the semiconductor body and the last of the different metal layers, The semiconductor body includes: an active region including components of the device; and a peripheral region laterally surrounding the active region. Therein, a plurality of openings in the stress mitigation layer or layer stack are formed over the entire active area.

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