Semiconductor Package

Abstract

A semiconductor package is provided. The semiconductor package may include: a substrate; a semiconductor chip located on the substrate; a passive element located on the substrate; a conductive structure located on the substrate; and an interposer substrate located on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate may be electrically connected to the conductive structure. The height of the passive element may be greater than the height of the semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application Nos. 10-2018-0055446 (filed on May 15, 2018), 10-2018-0057769 (filed on May 21, 2018), 10-2018-0058343 (filed on May 23, 2018), and 10-2018-0117775 (filed on October 2, 2018), which are hereby incorporated by reference into this application in their entirety. Technical Field

[0003] The disclosure herein relates to semiconductor packages, and more particularly, to stacked semiconductor packages including an interposer substrate. Background Art

[0004] Semiconductor packages can be implemented in a form suitable for electronic products. Generally, semiconductor packages are mounted on a printed circuit board together with a semiconductor chip and are electrically connected to each other using bonding wires or bumps. Due to the development of the electronics industry, various studies are being conducted to improve the reliability and durability of semiconductor packages. High speed, high capacity and miniaturization of semiconductor packages have become more important. Summary of the invention

[0005] The present disclosure provides a semiconductor package having improved electrical characteristics.

[0006] An embodiment of the inventive concept provides a semiconductor package, comprising: a substrate; a semiconductor chip located on the substrate; a passive element located on the substrate, the height of the passive element being greater than the height of the semiconductor chip; a conductive structure located on the substrate; and an interposer substrate located on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate can be electrically connected to the conductive structure.

[0007] In one embodiment of the inventive concept, a semiconductor package includes: a substrate; a semiconductor chip located on an upper surface of the substrate; a passive component located on the upper surface of the substrate; an interposer substrate located on the semiconductor chip and the passive component; a conductive structure located between the substrate and the interposer substrate; a lower solder connection portion located between the substrate and the conductive structure; and an upper solder connection portion located between the conductive structure and the interposer substrate.

[0008] In one embodiment of the inventive concept, a semiconductor package includes: a substrate; a semiconductor chip located on an upper surface of the substrate; a passive component located on an upper surface of the substrate; a conductive structure located on the substrate; an interposer substrate located on the semiconductor chip, the passive component and the conductive structure, the interposer substrate being electrically connected to the conductive structure; and a lower solder connection located between the substrate and the conductive structure, the lower solder connection being connected to the substrate and the conductive structure. The upper surface of the passive component may be disposed at a higher level than the upper surface of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the detailed description, serve to explain the principles of the inventive concept. In the drawings:

[0010] Figure 1A is a top view of a lower semiconductor package according to an embodiment;

[0011] Figure 1B It is along Figure 1A A cross-sectional view taken along line II';

[0012] Figure 1C yes Figure 1B An enlarged view of region A;

[0013] Figure 2A is a top view for explaining a lower semiconductor package according to an embodiment;

[0014] Figure 2B Corresponds to Figure 2A A magnified view of the middle area A';

[0015] Figure 3 is a view for explaining a semiconductor package according to an embodiment;

[0016] Figure 4A is a top view of a semiconductor package according to an embodiment;

[0017] Figure 4B It is along Figure 4A A cross-sectional view taken along line II';

[0018] Figure 5A is a top view of a lower semiconductor package according to an embodiment;

[0019] Figure 5B It is along Figure 5A A cross-sectional view taken along line II-II';

[0020] Figure 5C It is along Figure 5A A cross-sectional view taken along line III-III';

[0021] Fig. 6A is a top view of a semiconductor package according to an embodiment;

[0022] Figure 6B It is along Fig. 6A A cross-sectional view taken along line II-II';

[0023] Figure 6C It is along Fig. 6A A cross-sectional view taken along line III-III';

[0024] FIG. 7A to FIG. 7C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment;

[0025] Fig. 8A is a top view of a lower semiconductor package according to an embodiment;

[0026] Figure 8B and Figure 8C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment;

[0027] Fig.9A is a top view of a lower semiconductor package according to an embodiment;

[0028] Fig. 9B and Fig. 9C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment;

[0029] Fig. 10A is a view for explaining a semiconductor module according to an embodiment;

[0030] Fig. 10B is a view for explaining a semiconductor module according to an embodiment;

[0031] Fig. 10C and Fig. 10D is a view for explaining a semiconductor module according to an embodiment;

[0032] Fig.11A is a top view showing a first lower semiconductor package according to an embodiment;

[0033] Fig. 11B It is along Fig.11A A cross-sectional view taken along line IV-IV';

[0034] Fig. 11C is a top view showing a first semiconductor package according to an embodiment;

[0035] Fig.11D It is along Fig. 11C A cross-sectional view taken along line IV-IV';

[0036] Fig. 12A is a top view showing a second lower semiconductor package according to an embodiment;

[0037] Fig. 12B It is along Fig. 12A A cross-sectional view taken along line V-V';

[0038] Fig.13A is a top view showing a semiconductor module according to an embodiment; and

[0039] Fig. 13B It is along Fig.13A A cross-sectional view taken along line VI-VI'. DETAILED DESCRIPTION

[0040] In this specification, the same reference numerals denote the same components throughout the specification. Hereinafter, a semiconductor package, a method for manufacturing a semiconductor package, and a semiconductor module according to the inventive concept will be described. Throughout the specification, when a component is described as being located on another component, the component is not necessarily in physical contact with the other component.

[0041] Figure 1A is a top view of a lower semiconductor package according to an embodiment. Figure 1B It is along Figure 1A A cross-sectional view taken along line II'. Figure 1C yes Figure 1B Magnified view of area A. Figure 1A , Figure 1B and Figure 1C, the lower semiconductor package 10 includes a lower substrate 100, semiconductor chips 210 and 220, a passive element 310, a conductive structure 400, and an interposer substrate 600. The lower substrate 100 may have a first side 100a and a second side 100b opposite to each other. The lower substrate 100 may have a first region R1 and a second region R2 in a top view. The first region R1 of the lower substrate 100 may be closer to the first side 100a than the second region R2. As an example, a printed circuit board (PCB) having a circuit pattern may be used as the lower substrate 100. The lower substrate 100 may include a substrate pad 110 and a wiring 155. The substrate pad 110 may be exposed on the upper surface 100u of the lower substrate 100. The wiring 155 may be disposed in the lower substrate 100 and may be connected to the substrate pad 110. The solid line in the lower substrate 100 schematically shows the wiring 155 in the lower substrate 100. The external terminal 150 may be disposed on the lower surface of the lower substrate 100. The external terminal 150 may include at least one of a solder ball, a bump, and a pillar. The external terminal 150 may include, for example, metal. The external terminal 150 may be connected to the substrate pad 110 through a wiring 155 .

[0042] The semiconductor chips 210 and 220 may be mounted on the upper surface 100u of the lower substrate 100. The semiconductor chips 210 and 220 may include a first semiconductor chip 210 and a second semiconductor chip 220. The first semiconductor chip 210 may be disposed on the upper surface 100u of the first region R1 of the lower substrate 100. The first semiconductor chip 210 may include integrated circuits with different functions. The first semiconductor chip 210 may include a logic circuit and a memory circuit. The first semiconductor chip 210 may include a logic chip for calculating and processing data. For example, the first semiconductor chip 210 may be any one of a system on chip (SOC), a modem chip, a ModAP chip, an application processor (AP) chip, and a communication processor (CP) chip. The first connection 251 may be between the substrate pad 110 and the first semiconductor chip 210. The first semiconductor chip 210 may be electrically connected to the lower substrate 100 through the first connection 251. In this specification, being electrically connected to a substrate may mean being electrically connected to wiring in the substrate. The fact of being electrically connected to a semiconductor chip may refer to an integrated circuit electrically connected to a semiconductor chip through a chip pad of a semiconductor chip. The first connection portion 251 may include a solder ball, a column, a bump, or a ball grid array. The height H1 of the mounted first semiconductor chip 210 may be defined as a height including the first connection portion 251. In this specification, the height of any component may represent the maximum distance between the upper surface of the component and its lower surface measured in a direction perpendicular to the upper surface 100u of the lower substrate 100.

[0043] The second semiconductor chip 220 may be disposed on the upper surface 100u of the second region R2 of the lower substrate 100. The second semiconductor chip 220 may be spaced apart from the first semiconductor chip 210. The second semiconductor chip 220 may be a semiconductor chip different from the first semiconductor chip 210. The function of the second semiconductor chip 220 is different from that of the first semiconductor chip 210, and may have different sizes. For example, the second semiconductor chip 220 may include a power management integrated circuit (PMIC) to serve as a power management chip. The second connection portion 252 may be between the lower substrate 100 and the second semiconductor chip 220. The second connection portion 252 may include a solder ball, a column, a bump, or a ball grid array. The second semiconductor chip 220 may be electrically connected to the lower substrate 100 through the second connection portion 252. The height H2 of the second semiconductor chip 220 after installation may be defined as the height including the second connection portion 252.

[0044] The passive element 310 may be mounted on the upper surface 100u of the lower substrate 100. In a top view, the passive element 310 may be spaced apart from the first semiconductor chip 210 and the second semiconductor chip 220. The passive element 310 may include any one of an inductor, a resistor, and a capacitor. The first connection terminal 351 may be disposed between the lower substrate 100 and the passive element 310 to be connected to any one of the substrate pads 110. The first connection terminal 351 may include solder or a bump. The first connection terminal 351 may include a conductive material such as a metal. The passive element 310 may be connected to the lower substrate 100 via the first connection terminal 351.

[0045] The passive element 310 may include a plurality of passive elements 310 spaced apart from each other. The passive elements 310 may be the same or different types of passive elements. When the passive elements 310 include different types of passive elements, one of the passive elements 310 may include an inductor, and another of the passive elements 310 may include a capacitor.

[0046] The height H3 of at least one mounted passive element 310 may be greater than the height H1 of the first semiconductor chip 210 and the height H2 of the second semiconductor chip 220 after mounting. At this time, the height H3 of the mounted passive element 310 may be defined as a height including the first connection terminal 351. The upper surface 310a of the at least one passive element 310 is disposed at a higher level than the upper surface 210a of the first semiconductor chip 210 and the upper surface 220a of the second semiconductor chip 220. The plane arrangement, shape, and number of the passive elements 310 are not limited to those shown, but may be variously modified.

[0047] The interposer substrate 600 may be disposed on the first semiconductor chip 210, the second semiconductor chip 220, the passive element 310, and the conductive structure 400. The lower surface of the interposer substrate 600 may face the first semiconductor chip 210, the second semiconductor chip 220, and the passive element 310. The interposer substrate 600 may include an insulating layer 610, a lower pad 621, a conductive pattern 623, and an upper pad 622. Although for simplicity, except for Figure 1C and Figure 2B In addition, only a single insulating layer 610 is shown in the drawings, but the inventive concept is not limited thereto. For example, the insulating layer 610 may include a plurality of insulating layers. The lower pad 621 may be exposed on the lower surface of the interposer substrate 600. The conductive pattern 623 may include a wiring portion and a passage portion. The wiring portion may be arranged between each insulating layer 610. The passage portion may penetrate at least one layer of the insulating layer 610. The upper pad 622 may be exposed on the upper surface 600u of the interposer substrate 600. The upper pad 622 may be connected to the lower pad 621 through the conductive pattern 623. Therefore, the arrangement of the upper pad 622 may be more freely set. For example, the upper pad 622 may not be vertically aligned with the electrically connected lower pad 621, the conductive structure 400, and the substrate pad 110. The vertical direction may be a direction perpendicular to the upper surface 100u of the lower substrate 100. The upper pad 622 may be used as a terminal connected to another package or component. In this specification, electrically connected to the interposer substrate 600 may mean electrically connected to the upper pad 622 of the interposer substrate 600. The upper pad 622 may include, for example, Figure 1B The signal pad 622A and the power pad 622B are shown electrically separated from each other.

[0048] The conductive structure 400 may be between the lower substrate 100 and the interposer substrate 600. The lower solder connection 451 may be disposed between the lower substrate 100 and the lower surface of the conductive structure 400 to connect to the substrate pad 110 and the conductive structure 400. The conductive structure 400 may be electrically connected to the lower substrate 100 through the lower solder connection 451. The lower solder connection 451 may include a solder material. The solder may include tin, silver and / or bismuth. The material of the lower solder connection 451 may be different from the material of the conductive structure 400. For example, the conductive structure 400 may include at least one selected from metals (e.g., copper, aluminum, gold, lead, stainless steel, iron, and alloys thereof). The melting point of the conductive structure 400 may be higher than the melting point of the lower solder connection 451. The height H of the conductive structure 400 may be greater than the thickness of the lower solder connection 451.

[0049] The upper solder connection 452 may be interposed between the upper surface 400a of the conductive structure 400 and the interposer substrate 600 to be connected to the conductive structure 400 and the lower pad 621. The interposer substrate 600 may be electrically connected to the lower substrate 100 through the conductive structure 400. The upper solder connection 452 may include a solder material. The material of the conductive structure 400 may be different from the material of the upper solder connection 452. The melting point of the conductive structure 400 may be higher than the melting point of the upper solder connection 452. The height H of the conductive structure 400 may be greater than the thickness of the upper solder connection 452.

[0050] When the interposer substrate 600 and the lower substrate 100 are connected by a single solder ball or by directly bonding the solder balls, the solder balls or bonding solder balls may have a relatively low height. In this case, the gap between the lower substrate 100 and the interposer substrate 600 is very small, so that the passive component 310 may be difficult to be set on the upper surface 100u of the lower substrate 100. For example, the passive component 310 may be set outside the lower semiconductor package 10. In this case, the length of the electrical path connected to the passive component 310 may increase. When the solder balls or bonding solder balls are formed to have a large height, the diameter and pitch of the solder balls or bonding solder balls may increase.

[0051] According to an embodiment, each conductive structure 400 may be a pin or a metal column. The conductive structure 400 may have a columnar shape, such as a cylindrical or polygonal column. The conductive structure 400 may have a relatively uniform and smaller diameter. The diameter of the lower portion of each conductive structure 400 may be substantially the same as the diameter of the upper portion of the conductive structure 400 and the diameter of the middle portion of the conductive structure 400. The pitch P of the conductive structure 400 may be smaller. The pitch P of the conductive structure 400 may be about 0.01 mm to about 0.5 mm. Therefore, the lower semiconductor package 10 may be miniaturized.

[0052] Since pins or metal pillars are used as the conductive structures 400, each conductive structure 400 may have a relatively large height H. For example, the height H of the conductive structure 400 may be equal to or greater than the height H3 of the passive element 310 after installation. The height H of the conductive structure 400 may be greater than the height H1 of the first semiconductor chip 210 after installation and the height H2 of the second semiconductor chip 220 after installation. At this time, the height H of the conductive structure 400 may be defined as the distance between the upper surface 400a and the lower surface of the conductive structure 400. The upper surface 400a of the conductive structure 400 may be set at the same or higher level as the upper surface 310a of the passive element 310. The upper surface 400a of the conductive structure 400 may be set at a higher level than the upper surface 210a of the first semiconductor chip 210 and the upper surface 220a of the second semiconductor chip 220. Therefore, the gap D between the lower substrate 100 and the interposer substrate 600 may be increased. The gap D between the lower substrate 100 and the interposer substrate 600 may be large enough so that the passive element 310 is disposed between the lower substrate 100 and the interposer substrate 600. The passive element 310 may be electrically connected to at least one of the first semiconductor chip 210 and the second semiconductor chip 220 through the lower substrate 100. The passive element 310 may be electrically connected to the interposer substrate 600 through the lower substrate 100 and the conductive structure 400. Since the passive element 310 is disposed on the upper surface 100u of the lower substrate 100, the length of the electrical path between the passive element 310 and the first semiconductor chip 210, the passive element 310 and the second semiconductor chip 220, and the passive element 310 and the interposer substrate 600 may be reduced. The electrical characteristics of the lower semiconductor package 10 may be improved. Hereinafter, the electrical connection of the lower semiconductor package 10 and the conductive structure 400 will be described in more detail.

[0053] The conductive structure 400 may include a first conductive structure 410 and a second conductive structure 420. The first conductive structure 410 may be disposed on the first region R1 of the lower substrate 100. The first conductive structure 410 may be disposed closer to the first semiconductor chip 210 than the second conductive structure 420. The first conductive structure 410 may be disposed adjacent to the first side 100a of the lower substrate 100. The first conductive structure 410 may be disposed closer to the first semiconductor chip 210 than the second conductive structure 420. The first conductive structure 410 may be disposed adjacent to the first side 100a of the lower substrate 100. The first conductive structure 410 may be arranged in a row parallel to the first direction in a top view, and the first direction may be parallel to the first side 100a of the lower substrate 100. Various modifications may be made to the planar arrangement and array of the first conductive structure 410. For example, the number of columns of the first conductive structure 410 may vary.

[0054] The first conductive structure 410 may include a signal structure. The signal structure may perform the function of transmitting an electrical signal (e.g., a data signal) between any two components. For example, with respect to the signal pad 622A, at least a portion of the first conductive structure 410 may serve as a signal path between the first semiconductor chip 210 and the interposer substrate 600. For example, a signal may be transmitted from the first semiconductor chip 210 to the signal pad 622A through the first conductive structure 410 and the lower substrate 100. Since the first conductive structure 410 is disposed adjacent to the first semiconductor chip 210, the length of the signal path between the first semiconductor chip 210 and the signal pad 622A may be reduced.

[0055] In one example, the first conductive structure 410 also includes a power structure, and the total number of signal structures in the first conductive structure 410 can be greater than the number of power structures in the first conductive structure 410. In another example, the first conductive structure 410 includes a signal structure, but may not include a power structure. For another example, the first conductive structure 410 may also include a ground structure. The ground structure can be used to transfer a ground voltage between two components.

[0056] The second conductive structure 420 may be disposed on the second region R2 of the lower substrate 100. The second conductive structure 420 may be disposed closer to the second semiconductor chip 220 than the first conductive structure 410. The second conductive structure 420 may have the same shape as the first conductive structure 410, and may include the same material as the first conductive structure 410. However, the arrangement, electrical connection, and function of the second conductive structure 420 may be different from the first conductive structure 410. For example, the second conductive structure 420 may be used as a power supply structure. The power supply structure may provide or transmit power from one component to another component. The second conductive structure 420 may be electrically connected to the power supply pad 622B to serve as a power path between the second semiconductor chip 220 and the interposer substrate 600. The power path may refer to a power supply path. For example, the power output from the second semiconductor chip 220 may be transmitted to the power supply pad 622B through the lower substrate 100 and the second conductive structure 420. The second semiconductor chip 220 is used as a power management semiconductor chip, and the second conductive structure 420 includes a power supply structure so that the length of the power path between the second semiconductor chip 220 and the upper pad 622 can be reduced. Therefore, the power integrity (PI) of the lower semiconductor package 10 may be improved. The second conductive structure 420 may be insulated from the first conductive structure 410 .

[0057] In one example, the second conductive structure 420 includes a power structure, but may not include a signal structure. As another example, the second conductive structure 420 may also include a signal structure. In this case, the total number of power structures in the second conductive structure 420 may be greater than the number of signal structures in the second conductive structure 420.

[0058] The second conductive structures 420 may be disposed adjacent to the second side surface 100b of the lower substrate 100. In a top view, the second conductive structures 420 may be arranged in a column parallel to the second side surface 100b. Various modifications may be made to the planar arrangement and array of the second conductive structures 420. For example, the number of columns of the second conductive structures 420 may vary.

[0059] The upper pad 622 may be electrically connected to any one of the first semiconductor chip 210 , the second semiconductor chip 220 , and the passive element 310 through the conductive structure 400 and the lower substrate 100 .

[0060] The lower mold film 500 may fill the gap between the lower substrate 100 and the interposer substrate 600. The lower mold film 500 is disposed on the upper surface 100u of the lower substrate 100 to seal the first semiconductor chip 210, the second semiconductor chip 220, and the passive element 310. The lower mold film 500 may cover the upper surface 210a of the first semiconductor chip 210, the upper surface 220a of the second semiconductor chip 220, the upper surface 310a of the passive element 310, the sidewall of the conductive structure 400, and the lower surface of the interposer substrate 600. The lower mold film 500 may also seal at least one of the first connection portion 251 and the second connection portion 252. For example, the lower mold film 500 may also seal at least one of the sidewalls of the first connection portion 251 and the sidewalls of the second connection portion 252. The lower mold film 500 may include an insulating polymer, such as an epoxy-based molding compound (EMC). As another example, the bottom filling material may be further disposed in at least one of the gap between the lower substrate 100 and the first semiconductor chip 210, the gap between the lower substrate 100 and the second semiconductor chip 220, and the gap between the lower substrate 100 and the third semiconductor chip 720 (see Fig. 10C The bottom filling film 800 in the bottom filling film 800).

[0061] Although not shown in the drawings, electronic components may also be disposed on the upper surface 100u of the lower substrate 100. The electronic components may include an oscillator, such as a crystal oscillator or a real-time clock.

[0062] Figure 2A is a top plan view for explaining a lower semiconductor package according to an embodiment. Figure 2B Corresponds to Figure 2A Enlarged view of area A' in the middle.

[0063] Reference Figure 2A and Figure 2BIn addition to the lower substrate 100, the first semiconductor chip 210, the second semiconductor chip 220 and the lower mold film 500, the lower semiconductor package 11 may further include a connection structure 450. The connection structure 450 may be disposed between the lower substrate 100 and the interposer substrate 600. The connection structure 450 may include a base layer 409 and a conductive structure 400'. The base layer 409 may include a plurality of base layers 409 stacked. The base layer 409 may include an insulating material. For example, the base layer 409 may include an insulating polymer or a silicon-containing insulating material.

[0064] The conductive structure 400' may be disposed in the base layer 409. By providing the connection structure 450, the conductive structure 400' may be provided between the interposer substrate 600 and the lower substrate 100. Figure 2B As shown, the conductive structure 400' may include a first conductive pad 401, a conductive wiring 403, a conductive path 404, and a second conductive pad 402. The first conductive pad 401 may be disposed on the lower surface of the connection structure 450. The conductive wiring 403 may be between the substrate layers 409. The conductive path 404 penetrates the substrate layer 409 and may be connected to the conductive wiring 403. The second conductive pad 402 is disposed on the upper surface of the connection structure 450 and may be connected to any one of the conductive paths 404. The second conductive pad 402 may be electrically connected to the first conductive pad 401 through the conductive path 404 and the conductive wiring 403. The second conductive pad 402 may not be vertically aligned with the first conductive pad 401. The conductive structure 400' may include a metal such as copper.

[0065] The lower solder connection 451 may be disposed between the lower substrate 100 and the conductive structure 400' to connect to the first conductive pad 401 and the at least one substrate pad 110. The upper solder connection 452 is interposed between the conductive structure 400' and the interposer substrate 600 to connect to the second conductive pad 402 and the lower pad 621. The conductive structure 400' may have a higher melting point than the lower solder connection 451 and the upper solder connection 452.

[0066] According to the embodiment, since the connection structure 450 is provided, the upper solder connection portion 452 may be more freely configured and designed. For example, the upper solder connection portion 452 may not be vertically aligned with the lower solder connection portion 451. Therefore, the arrangement freedom of the upper pad 622 may be further improved.

[0067] Figure 3 is a view for explaining a semiconductor package according to an embodiment, and corresponds to a view along Figure 1A A cross section taken along line II'.

[0068] Reference Figure 3, the semiconductor package 30 may include a lower semiconductor package 10 and an upper semiconductor package 20. At this time, reference may be used Figures 1A to 1C The lower semiconductor package 10 described herein. Unlike the one shown, reference Figure 2A and Figure 2B The lower semiconductor package 11 is described.

[0069] The upper semiconductor package 20 may be disposed on the lower semiconductor package 10. The upper semiconductor package 20 may include, for example, an upper substrate 710, a third semiconductor chip 720, and an upper mold film 730. A printed circuit board or a rewiring layer may be used as the upper substrate 710. A metal pad 715 may be disposed on the lower surface of the upper substrate 710. The third semiconductor chip 720 may be mounted on the upper surface of the upper substrate 710. The third semiconductor chip 720 may be a semiconductor chip different from the first semiconductor chip 210 and the second semiconductor chip 220. For example, the third semiconductor chip 720 may be used as a memory chip, and data may be stored in an integrated circuit. The integrated circuit of the third semiconductor chip 720 may include a memory circuit. The memory chip may include a DRAM chip, an SRAM chip, an MRAM chip, and / or a NAND flash memory chip. The third semiconductor chip 720 may be connected to the upper substrate 710 through a third connection 725. The third connection 725 includes a bonding wire and may be disposed on the third semiconductor chip 720. The third connection 725 may include a metal such as gold (Au). As another example, the third connection portion 725 is disposed between the upper substrate 710 and the second semiconductor chip 220, and may include solder, bumps, ball grid arrays, or columns. The third semiconductor chip 720 may be electrically connected to the metal pad 715 through the third connection portion 725 and the internal wiring 705 in the upper substrate 710. The solid lines in the upper substrate 710 schematically illustrate the internal wiring 705. Different from what is shown in the figure, a plurality of third semiconductor chips 720 may be disposed on the upper substrate 710. An upper mold film 730 may be disposed on the upper substrate 710 to cover the third semiconductor chip 720. The upper mold film 730 may include an epoxy resin-based molding compound.

[0070] The conductive terminal 750 may be interposed between the interposer substrate 600 and the upper semiconductor package 20. The conductive terminal 750 is disposed on the upper pad 622 and may be connected to the metal pad 715. The metal pad 715 may be connected to the upper pad 622 through the conductive terminal 750. The conductive terminal 750 may include solder or a bump. The conductive terminal 750 may be formed by a reflow process. The conductive terminal 750 may include a metal. According to an embodiment, since the interposer substrate 600 is provided, the degree of free arrangement of the conductive terminal 750 may be increased. For example, the conductive terminal 750 may not be vertically aligned with the corresponding conductive structure 400.

[0071] The third semiconductor chip 720 may receive a signal of the first semiconductor chip 210 through the conductive terminal 750, the upper pad 622, and the first conductive structure 410. The upper semiconductor package 20 may receive power output from the second semiconductor chip 220 through the conductive terminal 750, the upper pad 622, and the second conductive structure 420. In this specification, being electrically connected to the upper semiconductor package 20 may mean being electrically connected to the third semiconductor chip 720.

[0072] The width W of the upper semiconductor package 20 may be smaller than the width of the lower semiconductor package 10. For example, the width W of the upper semiconductor package 20 may be smaller than the width of the interposer substrate 600. Therefore, in a top view, at least a portion of an upper surface of the interposer substrate 600 may not overlap with the upper semiconductor package 20.

[0073] Figure 4A is a top view of a semiconductor package according to an embodiment. Figure 4B It is along Figure 4A A cross-sectional view taken along line II'.

[0074] Reference Figure 4A and Figure 4B , the semiconductor package 31 may include a lower semiconductor package 12 and an upper semiconductor package 20. The lower substrate 100 may have a central region R10 and an edge region R20 in a top view. Figure 4A As shown, the edge region R20 of the lower substrate 100 may be adjacent to the first side 100a, the second side 100b, the third side 100c, and the fourth side 100d of the lower substrate 100. The third side 100c may be adjacent to the first side 100a. The fourth side 100d may be opposite to the third side 100c. In a top view, the central region R10 of the lower substrate 100 may be surrounded by the edge region R20.

[0075] The conductive structure 400 may be disposed on the edge region R20 of the lower substrate 100. For example, the first conductive structure 410 and the second conductive structure 420 may be disposed on the edge region R20 of the lower substrate 100. The arrangement and electrical connection of the first conductive structure 410 and the second conductive structure 420 on the edge region R20 of the lower substrate 100 may be similar to those described with reference to FIG. Figure 1A and Figure 1B The arrangement and electrical connection of the first conductive structure 410 and the second conductive structure 420 are described.

[0076] The central region R10 of the lower substrate 100 may be configured to be provided with a first semiconductor chip 210, a second semiconductor chip 220, and a passive element 310. At least one conductive structure 400 may be provided on the central region R10 of the lower substrate 100. For example, the conductive structure 400 may be provided between the first semiconductor chip 210 and the second semiconductor chip 220, between the first semiconductor chip 210 and the passive element 310, between the second semiconductor chip 220 and the passive element 310, or between the passive elements 310. The first conductive structure 410 and the second conductive structure 420 may be provided on the central region R10 of the lower substrate 100. As another example, any one of the first conductive structure 410 and the second conductive structure 420 may not be provided in the central region R10.

[0077] As reference Figure 3 As described above, the upper semiconductor package 20 may include an upper substrate 710, a third semiconductor chip 720, and an upper mold film 730. However, the third semiconductor chip 720 may be provided in plurality. The third semiconductor chip 720 may be connected to the upper metal pad 716 by a third connection portion 725. The upper metal pad 716 may be provided on the upper surface of the upper substrate 710 to be connected to the internal wiring 705 of the upper substrate 710. At least some of the upper metal pads 716 may overlap with the central region R10 of the lower substrate 100 in a top view. The third semiconductor chip 720 may be electrically connected to the lower substrate 100 by the conductive structure 400 on the central region R10. Since the conductive structure 400 is provided on the central region R10, the length of the electrical path between the third semiconductor chip 720 and the lower substrate 100 may be further reduced. In addition, the internal wiring 705 of the upper substrate 710 may be designed more freely.

[0078] The lower substrate 100, the first semiconductor chip 210, the second semiconductor chip 220, the passive element 310, the interposer substrate 600, and the lower mold film 500 may be similar to those described in reference to FIG. Figure 1A and Figure 1B The lower substrate 100 , the first semiconductor chip 210 , the second semiconductor chip 220 , the passive element 310 , the interposer substrate 600 , and the lower mold film 500 described are substantially the same.

[0079] Figure 5A is a top view of a lower semiconductor package according to an embodiment. Figure 5B It is along Figure 5A A cross-sectional view taken along line II-II'. Figure 5C It is along Figure 5A A cross-sectional view taken along line III-III'.

[0080] Reference Figure 5A , Figure 5B and Figure 5C, the lower semiconductor package 13 includes a lower substrate 100 , a first semiconductor chip 210 , a second semiconductor chip 220 , a passive element 310 , a conductive structure 400 , a lower mold film 500 , and an interposer substrate 600 .

[0081] The conductive structure 400 may include a first conductive structure 410 and a second conductive structure 420. The first conductive structure 410 is disposed on the first region R1 of the lower substrate 100, and may include a first sub-conductive structure 411, a second sub-conductive structure 412, and a third sub-conductive structure 413. The first sub-conductive structure 411 may be closer to the third side 100c relative to the fourth side 100d of the lower substrate 100. The first sub-conductive structure 411 may be arranged in a row parallel to the second direction. The second direction may be parallel to the third side 100c of the lower substrate 100. The first sub-conductive structure 411 may include a signal structure. The signal structure may be a memory signal structure that transmits a memory signal. In one example, the first sub-conductive structure 411 may also include a grounding structure. As another example, the first sub-conductive structure 411 may also include a power structure, and the total number of signal structures in the first sub-conductive structure 411 may be greater than the total number of power structures in the first sub-conductive structure 411. As another example, the first sub-conductive structure 411 may not include a power structure.

[0082] For example, the second sub-conductive structure 412 may be adjacent to the fourth side 100d of the lower substrate 100. The second sub-conductive structure 412 may be arranged in a row parallel to the second direction. The function of the second sub-conductive structure 412 is different from that of the first sub-conductive structure 411, and may have different electrical connection relationships. The second sub-conductive structure 412 may include a power structure. As another example, in addition to the power structure, the second sub-conductive structure 412 also includes a signal structure, and the total number of power structures in the second sub-conductive structure 412 may be greater than the total number of signal structures in the second sub-conductive structure 412. The second sub-conductive structure 412 may be electrically insulated from the first sub-conductive structure 411.

[0083] The third sub conductive structure 413 may be disposed closer to the first semiconductor chip 210 than the first sub conductive structure 411 and the second sub conductive structure 412. The third sub conductive structure 413 may be disposed between the first semiconductor chip 210 and the passive element 310, between the first semiconductor chip 210 and the second semiconductor chip 220, or between the passive elements 310. As another example, the third sub conductive structure 413 may not be disposed.

[0084] The arrangement of the first to third sub-conductive structures 411, 412 and 413 is not limited to the arrangement shown in the drawings, and various modifications may be made. For example, the first sub-conductive structure 411 or the second sub-conductive structure 412 is disposed adjacent to the first side surface 100a of the lower substrate 100 and may be aligned along the first side surface 100a of the lower substrate 100.

[0085] The second conductive structure 420 may be disposed on the second region R2 of the lower substrate 100. At least some of the second conductive structures 420 may be disposed adjacent to the third side 100c or the fourth side 100d of the lower substrate 100. Other second conductive structures 420 may be disposed adjacent to the second semiconductor chip 220. For example, other second conductive structures 420 may be disposed between the second semiconductor chip 220 and the first semiconductor chip 210, between any one of the passive components 310 and the second semiconductor chip 220, or between the passive components 310. The second conductive structure 420 may include a power supply structure. An external voltage may be transmitted to the second semiconductor chip 220 through the external terminal 150 and the lower substrate 100. In the process of transferring the voltage from the lower substrate 100 to the second semiconductor chip 220, the voltage may also pass through at least one of the passive components 310. Thereafter, the power converted from the second semiconductor chip 220 may be transmitted to the second upper pad 622 through the second conductive structure 420. At this time, the power converted from the second semiconductor chip 220 may be transmitted to the second conductive structure 420 through another passive component 310. According to an embodiment, the second semiconductor chip 220 is used as a power semiconductor chip, and the second conductive structure 420 includes a power structure, so that the length of the power path between the external terminal 150 and the second upper pad 622 can be reduced. Since the passive element 310 is disposed on the second region R2 of the lower substrate 100, the length of the power path between the external terminal 150 and the second upper pad 622 can be further reduced. The arrangement of the second conductive structure 420 is not limited to the arrangement shown in the drawings, and various modifications may be made. For example, in a top view, the second conductive structure 420 may be adjacent to the second side 100b of the lower substrate 100, and may be aligned along the second side 100b.

[0086] The upper pad 622 is exposed on the upper surface of the interposer substrate 600 and may be used as a terminal of the lower semiconductor package 13. The upper pad 622 may be provided in plurality. Some of the upper pads 622 may be electrically connected to the conductive structure 400. At least two upper pads 622 may be electrically connected to each other through the conductive pattern 623.

[0087] Fig. 6A is a top view of a semiconductor package according to an embodiment. Figure 6B It is along Fig. 6A A cross-sectional view taken along line II-II'. Figure 6C It is along Fig. 6A A cross-sectional view taken along line III-III'.

[0088] Reference Fig. 6A and Figure 6B In addition to the lower semiconductor package 13 and the upper semiconductor package 20, the semiconductor package 30 may further include an upper passive component 320. The lower semiconductor package 13 may be similar to the reference semiconductor package 20. FIG. 5A to FIG. 5C The lower semiconductor package 13 is described identically.

[0089] The upper semiconductor package 20 may be disposed on the lower semiconductor package 13. As described with reference to FIG. 2, the upper semiconductor package 20 may include an upper substrate 710, a third semiconductor chip 720, and an upper mold film 730. The width of the upper semiconductor package 20 may be smaller than the width of the interposer substrate 600. The upper semiconductor package 20 is disposed on the first region R1 of the lower substrate 100, but may not be disposed on the second region R2. The upper semiconductor package 20 may not overlap a portion of the upper surface of the interposer substrate 600.

[0090] The conductive terminal 750 may be disposed between the upper pad 622 and the metal pad 715 to be connected to the upper pad 622 and the metal pad 715. Therefore, the upper semiconductor package 20 may be electrically connected to the conductive structure 400 through the interposer substrate 600. The signal of the first semiconductor chip 210 may be transmitted to the third semiconductor chip 720 through the first sub-conductive structure 411, and the signal of the first semiconductor chip 210 may be received from the third semiconductor chip 720 through the first sub-conductive structure 411. Since the first sub-conductive structure 411 overlaps with the upper semiconductor package 20, the length of the signal path between the upper semiconductor package 20 and the first semiconductor chip 210 and between the external terminal and the upper semiconductor package 20 may be further reduced. The second sub-conductive structure 412 may be used as a power path of the third semiconductor chip 720. Since the second conductive structure 420 overlaps with the upper semiconductor package 20, the length of the power path between the upper semiconductor package 20 and the second conductive structure 420 may be further reduced.

[0091] The upper passive element 320 may be mounted on the upper surface of the interposer substrate 600. The upper passive element 320 may overlap with the second region R2 of the lower substrate 100 in a top view. The upper passive element 320 may be spaced laterally from the upper semiconductor package 20. The upper passive element 320 may include any one of an inductor, a resistor, and a capacitor. The second connection terminal 352 may be disposed between the interposer substrate 600 and the upper passive element 320. The second connection terminal 352 may include solder or a bump. The second connection terminal 352 may include a metal, such as tin, silver, and / or bismuth. The second connection terminal 352 may be connected to another upper pad 622. Therefore, the upper passive element 320 may be electrically connected to the interposer substrate 600. The upper passive element 320 may be electrically connected to the upper semiconductor package 20 through the interposer substrate 600, or may be electrically connected to the lower semiconductor package 13. For example, power converted in the second semiconductor chip 220 is transferred to the upper semiconductor package 20 through the passive element 310 , the second conductive structure 420 , the interposer substrate 600 , and the upper passive element 320 .

[0092] The upper passive element 320 may have a relatively large height H4. For example, the height H4 of the upper passive element 320 after installation may be greater than the height H3 of the passive element 310. The height H4 of the upper passive element 320 after installation may be greater than the gap D between the lower substrate 100 and the interposer substrate 600. The height H4 of the upper passive element 320 after installation may be greater than the height H5 of the upper semiconductor package 20 after installation. In this case, the height H4 of the upper passive element 320 after installation may include the height of the second connection terminal 352. The height H5 of the upper semiconductor package 20 after installation may include the height of the conductive terminal 750. For example, the height H5 of the upper semiconductor package 20 may include the height of the conductive terminal 750, the height of the upper substrate 710, and the height of the upper mold film 730. According to an embodiment, the width and arrangement of the upper semiconductor package 20 may be adjusted so that the upper passive element 320 may also be mounted on the lower semiconductor package 13. Therefore, the length of the power path between the upper passive element 320 and the second semiconductor chip 220 may be further reduced. The upper passive element 320 may be provided in plural numbers, but is not limited thereto.

[0093] FIG. 7A to FIG. 7C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment, and corresponds to a view along Figure 5A A cross section taken along line II-II'.

[0094] Reference Fig. 7A, the conductive structure 400 may be attached to the lower surface of the interposer substrate 600. A plurality of lower pads 621 may be provided on the lower surface of the interposer substrate 600. The conductive structure 400 may be provided on the lower surface of the interposer substrate 600 so that the conductive structures 400 are aligned with the lower pads 621, respectively. A plurality of upper solder connections 452 may be formed between the conductive structure 400 and the lower pads 621, respectively. The conductive structure 400 may be physically and electrically connected to the interposer substrate 600 through the upper solder connections 452. The upper solder connections 452 may be manufactured by a welding process using a heat treatment or a hot pressing process. The heat treatment may be performed under a temperature condition equal to or higher than the melting point of the upper solder connections 452. The melting point of the conductive structure 400 may be higher than the heat treatment temperature. The shape of the conductive structure 400 may be maintained during the heat treatment process.

[0095] Reference Figure 7B , the first semiconductor chip 210, the second semiconductor chip 220 and the passive component 310 can be mounted on the lower substrate 100. The installation of the first semiconductor chip 210 can be performed by a surface mounting technique or a reflow process using ultraviolet rays. As another example, the installation of the first semiconductor chip 210 can be performed by a bonding process using heating or laser. The installation of the second semiconductor chip 220 can be performed by a surface mounting technique or a reflow process using ultraviolet rays. The installation of the passive component 310 can be performed by a surface mounting technique. Various modifications can be made to the order of installing the first semiconductor chip 210, installing the second semiconductor chip 220, and installing the passive component 310.

[0096] Reference Figure 7C , in order to make the conductive structure 400 face the lower substrate 100, an interposer substrate 600 may be disposed on the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310. In this case, reference Fig. 7A The conductive structures 400 are connected to the interposer substrate 600. The conductive structures 400 may be aligned with the substrate pads 110, respectively. The conductive structures 400 may be spaced apart from the first semiconductor chip 210, the second semiconductor chip 220, and the passive element 310 in a top view.

[0097] A plurality of lower solder connections 451 may be formed between the conductive structure 400 and the substrate pad 110, respectively. The lower solder connections 451 may be manufactured by a welding process using a heat treatment or a hot pressing process. The conductive structure 400 may be physically and electrically connected to the lower substrate 100 through the lower solder connections 451. The heat treatment may be performed at a temperature equal to or higher than the melting point of the lower solder connections 451. The conductive structure 400 may have a melting point higher than the heat treatment temperature to maintain the shape of the conductive structure 400 during the heat treatment process.

[0098] Refer again Figure 5A and Figure 5B , a lower mold film 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower mold film 500 may be formed by injection and solidification of a molding material. The lower mold film 500 may also fill the gaps between the first semiconductor chip 210 and the interposer substrate 600, between the second semiconductor chip 220 and the interposer substrate 600, and between the passive element 310 and the interposer substrate 600. Thereafter, an external terminal 150 may be formed on the lower surface of the lower substrate 100. Thus, a reference Figure 5A and Figure 5B The lower semiconductor package 13 is described.

[0099] Fig. 8A is a top view of a lower semiconductor package according to an embodiment. FIG. 8B to FIG. 8C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment, and corresponds to a view along Fig. 8A A cross section taken along line II'.

[0100] Reference Fig. 8A and Figure 8B , a bonding structure 470 may be provided on the lower surface of the interposer substrate 600. The bonding structure 470 may include a conductive structure 400 and a fixing portion 480. The fixing portion 480 may have a plate shape. The fixing portion 480 may include plastic or a polymer. The fixing portion 480 may have a first hole 481 and a second hole 482 penetrating the fixing portion 480. The conductive structure 400 may be inserted into the first hole 481 of the fixing portion 480. Therefore, the conductive structure 400 may be provided on the interposer substrate 600 together with the fixing portion 480. The second hole 482 of the fixing portion 480 may be spaced apart from the first hole 481. The conductive structure 400 may not be provided in the second hole 482.

[0101] The conductive structure 400 may be connected to the interposer substrate 600. The connection of the conductive structure 400 and the interposer substrate 600 may include forming upper solder connection portions 452 between the conductive structure 400 and the lower solder pads 621, respectively. While the conductive structure 400 is connected to the interposer substrate 600, the pitch and arrangement of each conductive structure 400 may be easily controlled by the fixing portion 480. The conductive structure 400 may include a reference Figure 1A and Figure 1B A first conductive structure 410 and a second conductive structure 420 are depicted.

[0102] Reference Fig. 8A and Figure 8C, the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310 may be mounted on the lower substrate 100. In order to make the conductive structure 400 face the lower substrate 100, an interposer substrate 600 may be provided on the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310. At this time, the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310 may be provided in the second hole 482 of the fixing part 480. The first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310 may be spaced apart from the fixing part 480. A lower solder connection part 451 may be formed between the conductive structure 400 and the substrate pad 110 to connect the conductive structure 400 to the lower substrate 100.

[0103] Then, a lower mold film 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower mold film 500 may cover the upper surface, the lower surface, and the sidewall of the fixing portion 480. The material of the lower mold film 500 may be different from the material of the fixing portion 480. The external terminal 150 may be formed on the lower surface of the lower substrate 100. Thus, the manufacture of the lower semiconductor package 14 may be completed.

[0104] Reference Figure 3 The semiconductor package 20 described above can be mounted on FIG. 8A to FIG. 8C The semiconductor package is manufactured by placing a semiconductor package on the lower semiconductor package 14.

[0105] Fig.9A is a top view of a lower semiconductor package according to an embodiment. FIG. 9B to FIG. 9C is a view for explaining a method of manufacturing a lower semiconductor package according to an embodiment, and corresponds to a view along Fig.9A A cross section taken along line II'.

[0106] Reference Fig.9A and Fig. 9B , a bonding structure 470 may be provided on the lower surface of the interposer substrate 600. The bonding structure 470 may include a conductive structure 400 and a fixing portion 480. The bonding structure 470 may be similar to the one described with reference to FIG. Fig. 8A and Figure 8B However, the bonding structure 470 may be provided in plurality, and the fixing portion 480 of each bonding structure 470 may not have the second hole 482. One of the bonding structures 470 may be provided on the first region R1 of the lower substrate 100. Another of the bonding structures 470 may be provided on the second region R2 of the lower substrate 100.

[0107] An upper solder connection 452 may be formed between the conductive structure 400 and the interposer substrate 600 to connect the conductive structure 400 to the interposer substrate 600. The conductive structure 400 may include Figure 1A and Figure 1B A first conductive structure 410 and a second conductive structure 420 are shown.

[0108] Reference Fig.9A and Fig. 9C , the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310 may be mounted on the lower substrate 100. In order to make the bonding structure 470 face the lower substrate 100, the interposer substrate 600 may be disposed on the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310. At this time, the bonding structure 470 may be spaced apart from the first semiconductor chip 210, the second semiconductor chip 220 and the passive element 310. The lower solder connection portions 451 may be formed between the conductive structure 400 and the substrate pads 110, respectively.

[0109] The lower mold film 500 may be formed to fill the gap between the lower substrate 100 and the interposer substrate 600. The lower mold film 500 may cover the upper surface, the lower surface, and the sidewall of each fixing portion 480. The external terminal 150 may be formed on the lower surface of the lower substrate 100. Thus, the lower semiconductor package 15 may be manufactured. The lower semiconductor package 15 may include a plurality of bonding structures 470.

[0110] Reference Figure 3 The upper semiconductor package 20 described above can be mounted on a 9A to 9C The lower semiconductor package 15 manufactured as shown is placed on the lower semiconductor package 15 to manufacture a semiconductor package.

[0111] Fig. 10A and Fig. 10B are views for explaining a semiconductor module according to an embodiment, and correspond to Fig. 6A The cross section taken along line II-II' and along Fig. 6A A cross section taken along line III-III'. Fig. 10C and Fig. 10D are views for explaining a semiconductor module according to an embodiment, and correspond to Fig. 6A The cross section taken along the line II-II' and along Fig. 6A A cross section taken along line III-III'.

[0112] Reference FIG. 10A to FIG. 10D , the semiconductor modules 1 and 2 may include a board 1000 and a semiconductor package 32. A printed circuit board may be used as the board 1000. For example, referring to Fig. 6A and Figure 6B The semiconductor package 32 described above may be mounted on the board 1000, so that the semiconductor modules 1 and 2 may be manufactured. Figure 3 The semiconductor package 30 or Figure 4A and Figure 4B As another example, the upper semiconductor package 20 is stacked on FIG. 8A to FIG. 8C On the lower semiconductor package 14, or as 9A to 9C The lower semiconductor package 15 manufactured as shown in the figure can be placed on the lower semiconductor package 15 manufactured as shown, so that the semiconductor package can be manufactured, and the semiconductor package can be mounted on the board 1000. The board 1000 can have a connection pad 1500 on its upper surface. The external terminal 150 can be connected to the connection pad 1500. The semiconductor package 32 can be electrically connected to the board 1000 through the external terminal 150.

[0113] The height H3 of the passive component 310 and the height H4 of the upper passive component 320 may be relatively large. When the passive component 310 and the upper passive component 320 are directly mounted on the board 1000, the passive component 310 and the upper passive component 320 may be connected to the semiconductor package 32 through the board 1000. In this case, the length of the electrical connection path of the semiconductor modules 1 and 2 may be increased.

[0114] According to the embodiment, since the conductive structure 400 is used, the passive element 310 can be disposed between the lower substrate 100 and the interposer substrate 600. Therefore, the length of the electrical path between the first to third semiconductor chips 210, 220, 720 and the passive element 310 can be reduced. Since the upper passive element 320 is disposed on the interposer substrate 600, the length of the electrical path between the upper passive element 320 and the lower semiconductor package 13 or between the upper passive element 320 and the upper semiconductor package 20 can be reduced. The semiconductor modules 1 and 2 can have improved electrical characteristics. The semiconductor modules 1 and 2 can be miniaturized.

[0115] like Fig. 10A and Fig. 10B As shown, the underfill film may not be disposed between the lower semiconductor package 13 and the upper semiconductor package 20 .

[0116] like Fig. 10C and Fig. 10D As shown, the bottom filling film 800 may be further disposed in the gap between the lower semiconductor package 13 and the upper semiconductor package 20 to seal the conductive terminal 750. The bottom filling film 800 may include an insulating polymer. The thermal conductivity of the bottom filling film 800 may be higher than the thermal conductivity of air. During the operation of the lower semiconductor package 13, the heat generated in the lower semiconductor package 13 may be released to the outside more quickly through the bottom filling film 800. Similarly, during the operation of the upper semiconductor package 20, the heat generated in the upper semiconductor package 20 may be released to the outside more quickly through the bottom filling film 800. The bottom filling film 800 may protect the external terminal 150.

[0117] According to an embodiment, Fig. 10C As shown, since the width of the upper semiconductor package 20 is smaller than the width of the interposer substrate 600, the underfill film 800 may be easily formed between the interposer substrate 600 and the upper semiconductor package 20. The underfill film 800 may not extend into the gap between the interposer substrate 600 and the upper passive element 320.

[0118] According to an embodiment, since the gap D between the lower substrate 100 and the interposer substrate 600 is large, the lower semiconductor package 13 may have a relatively large height. Even if a lower bottom filling film (not shown) is formed between the board 1000 and the semiconductor package 32, a separate bottom filling film 800 may be formed between the lower semiconductor package 13 and the upper semiconductor package 20. The bottom filling film 800 may not extend between the board 1000 and the semiconductor package 32. The formation of the bottom filling film 800 may be performed after the semiconductor package 32 is mounted on the board 1000.

[0119] Fig.11A is a top plan view showing a first lower semiconductor package according to an embodiment. Fig. 11B It is along Fig.11A A cross-sectional view taken along line IV-IV'.

[0120] Reference Fig.11A and Fig. 11B The first lower semiconductor package 16 includes a first lower substrate 101, a first semiconductor chip 210, a first conductive structure 410, a first passive element 311 and a first interposer substrate 600'. The first lower substrate 101, the first semiconductor chip 210 and the first conductive structure 410 may be respectively FIG. 5A to FIG. 5C The lower substrate 100, the first semiconductor chip 210 and the first conductive structure 410 of the example are substantially the same. The first passive element 311 may be FIG. 5A to FIG. 5C The passive components 310 on the first region R1 of the lower substrate 100 are substantially the same as those described in the example. For example, the height H3' of at least one mounted first passive component 311 may be greater than the height H1 of the mounted first semiconductor chip 210. The upper surface 311a of at least one first passive component 311 is disposed at a higher level than the upper surface 210a of the first semiconductor chip 210.

[0121] The electrical connection relationship of the first conductive structure 410 can be FIG. 5A to FIG. 5CThe electrical connection relationship described in the example of the first conductive structure 410 is basically the same. For example, the first conductive structure 410 may include a first sub-conductive structure 411, a second sub-conductive structure 412, and a third sub-conductive structure 413. The first sub-conductive structure 411 is disposed adjacent to one side 101c of the first lower substrate 101, and may include a signal structure. The second sub-conductive structure 412 may be disposed adjacent to the other side 101d of the first lower substrate 101. One side 101c of the first lower substrate 101 may be opposite to the other side 101d. The third sub-conductive structure 413 may be disposed between the first semiconductor chip 210 and the first passive element 311 or between the first passive elements 311. The third sub-conductive structure 413 may be disposed in the central region of the first lower substrate 101 in a top view. As another example, the third sub-conductive structure 413 may not be disposed. The first conductive structure 410 may be used as an electrical path between the first lower substrate 101 and the first interposer substrate 600'.

[0122] The height H of the first conductive structure 410 may be greater than the height H3′ of the passive component 310 and the height H1 of the mounted first semiconductor chip 210. The upper surface 410a of the first conductive structure 410 may be disposed at a higher level than the upper surface 311a of the first passive component 311 and the upper surface 210a of the first semiconductor chip 210.

[0123] The first lower solder connection portion 451' is disposed between the first lower substrate 101 and the first conductive structure 410, and the first upper solder connection portion 452' can be disposed between the first conductive structure 410 and the first interposer substrate 600'. The first lower solder connection portion 451' and the first upper solder connection portion 452' can be respectively connected to the reference Figure 1A and Figure 1B The lower solder connection 451 and the upper solder connection 452 are described to be identical.

[0124] The first interposer substrate 600' may include a first insulating layer 610', a first lower pad 621', a first conductive pattern 623', and a first upper pad 622'. The first insulating layer 610', the first lower pad 621', the first conductive pattern 623', and the first upper pad 622' may be respectively similar to those of reference 1. Figures 1A to 1C The insulating layer 610 , the lower pad 621 , the conductive pattern 623 , and the upper pad 622 are depicted. The first interposer substrate 600 ′ may be electrically connected to the first semiconductor chip 210 or the first passive element 311 through the conductive structure 400 and the first lower substrate 101 .

[0125] The first lower mold film 510 may be disposed between the first lower substrate 101 and the first interposer substrate 600' to seal the first semiconductor chip 210 and the first passive element 311. The first lower mold film 510 may cover the sidewalls of the first conductive structure 410. The first lower mold film 510 may include epoxy molding compound.

[0126] The first external terminal 151 may be disposed on the lower surface of the first lower substrate 101. The first external terminal 151 may be connected to the reference Figure 1A and Figure 1B The external terminals 150 described are substantially the same. The first semiconductor package 41 may not include the second semiconductor chip 220 .

[0127] Fig. 11C is a top plan view showing a first semiconductor package according to an embodiment. Fig.11D It is along Fig. 11C A cross-sectional view taken along line IV-IV'.

[0128] Reference Fig. 11C and Fig.11D , the first semiconductor package 41 may include a first lower semiconductor package 16 and a first upper semiconductor package 21. The first lower semiconductor package 16 may be Fig.11A and Fig. 11B The first upper semiconductor package 21 may be stacked on the first lower semiconductor package 16. The first upper semiconductor package 21 may include an upper substrate 710, a third semiconductor chip 720, and an upper mold film 730, which are the same as those described with reference to FIG. Figure 3 The upper substrate 710, the third semiconductor chip 720, and the upper mold film 730 described above are substantially the same. The first upper semiconductor package 21 may be smaller than the first lower semiconductor package 16. For example, the width of the first upper semiconductor package 21 may be smaller than the width of the first lower semiconductor package 16. Here, the width of the component may represent a gap of the component in a direction parallel to the side 101c of the first lower substrate 101. The first upper semiconductor package 21 may have a length equal to or smaller than the first lower semiconductor package 16.

[0129] Each conductive terminal 750 may be interposed between the first upper pad 622′ and the metal pad 715. The first upper semiconductor package 21 may be electrically connected to the first lower semiconductor package 16 through the conductive terminal 750. The third semiconductor chip 720 may be electrically connected to at least one of the first external terminal 151, the first semiconductor chip 210, and the first passive element 311 through the first interposer substrate 600′ and the first conductive structure 410.

[0130] Fig. 12A is a top plan view showing a second lower semiconductor package according to an embodiment. Fig. 12B It is along Fig. 12A A cross-sectional view taken along line V-V'.

[0131] Reference Fig. 12A and Fig. 12B , the second semiconductor package 42 may include a second lower semiconductor package 17 and an upper passive element 320. The second lower semiconductor package 17 includes a second external terminal 152, a second lower substrate 102, a second semiconductor chip 220, a second conductive structure 420, a second passive element 312, a second lower mold film 520, and a second interposer substrate 600″. The second lower substrate 102, the second external terminal 152, the second semiconductor chip 220, and the second conductive structure 420 may be respectively connected to the Figure 5A , Figure 5B , Fig. 6A and Figure 6B The lower substrate 100, the external terminal 150, the second semiconductor chip 220 and the second conductive structure 420 described in the example of FIG. 3 are substantially the same. The second passive element 312 may be the same as in FIG. Figure 5A , Figure 5B , Fig. 6A and Figure 6B The passive elements 310 on the second region R2 of the lower substrate 100 described in the example of is substantially the same. For example, the upper surface 312a of at least one second passive element 312 may be disposed at a higher level than the upper surface 220a of the second semiconductor chip 220. The height H3″ of at least one mounted second passive element 312 may be greater than the height H2 of the mounted second semiconductor chip 220.

[0132] At least some of the second conductive structures 420 may be disposed adjacent to one side 102c and the other side 102d of the second lower substrate 102. The one side 102c and the other side 102d of the second lower substrate 102 may be opposite to each other. Some other second conductive structures 420 may be disposed adjacent to the second semiconductor chip 220. For example, some other second conductive structures 420 may be disposed between the second semiconductor chip 220 and one of the second passive components 312 or between the second passive components 312. The upper surface 420a of the second conductive structure 420 may be disposed at the same or higher level as the upper surface 312a of the second passive component 312 and the upper surface 220a of the second semiconductor chip 220. The height H of the second conductive structure 420 may be equal to or greater than the height H3″ of the second passive component 312 after installation.

[0133] The second lower solder connection portion 451" may be disposed between the second lower substrate 102 and the second conductive structure 420, and the second upper solder connection portion 452" may be disposed between the second conductive structure 420 and the second interposer substrate 600". The second lower solder connection portion 451" and the second upper solder connection portion 452" may be respectively connected to the reference Figure 1A and Figure 1B The lower solder connection 451 and the upper solder connection 452 are described to be identical.

[0134] The second conductive structure 420 may include a power structure. An external voltage is transmitted to the second conductive structure 420 through the second external terminal 152 , the second lower substrate 102 , the second passive element 312 , and the second semiconductor chip 220 .

[0135] The second interposer substrate 600" includes a second insulating layer 610", a second lower pad 621", a second conductive pattern 623", and a second upper pad 622". The second insulating layer 610", the second lower pad 621", the second conductive pattern 623", and the second upper pad 622" may be similar to Figure 1A and Figure 1B However, the second interposer substrate 600" may be connected to the second conductive structure 420. The second upper pad 622" of the second interposer substrate 600" may be used as a power supply pad.

[0136] The second lower mold film 520 may fill a gap between the second lower substrate 102 and the second interposer substrate 600 ″ and seal the second semiconductor chip 220 and the second passive element 312 .

[0137] The upper passive element 320 may be disposed on the second lower semiconductor package 17 . For example, the upper passive element 320 may be mounted on an upper surface of the second interposer substrate 600 ″. The second connection terminal 352 may be interposed between the second interposer substrate 600 ″ and the upper passive element 320 , and may be connected to the second upper pad 622 . The upper passive element 320 may be connected to at least one of the second semiconductor chip 220, the second passive element 312, and the second external terminal 152 through the second interposer substrate 600″, the second conductive structure 420, and the second lower substrate 102. In a top view, the upper passive element 320 may overlap with at least one of the second conductive structures 420. Thus, the length of an electrical path between the upper passive element 320 and the second semiconductor chip 220, between the upper passive element 320 and the second passive element 312, or between the upper passive element 320 and the second external terminal 152 may be reduced. The electrical path may be a power path. The height H4 of the mounted upper passive element 320 may be greater than the gap D′ between the second lower substrate 102 and the second interposer substrate 600″.

[0138] Fig.13A is a top view showing a semiconductor module according to an embodiment. Fig. 13B It is along Fig.13A A cross-sectional view taken along line VI-VI'.

[0139] Reference Fig.13A and Fig. 13B , the semiconductor module 3 may include a board 1000, a first semiconductor package 41, and a second semiconductor package 42. The board 1000 may have a first connection pad 1510 and a second connection pad 1520 on its upper surface. The second connection pad 1520 may be spaced apart from the first connection pad 1510. Any second connection pad 1520 may be electrically connected to any first connection pad 1510 through a connection wiring 1005 in the board 1000.

[0140] The first semiconductor package 41 may be Fig. 11C and Fig.11D The first external terminals 151 are connected to the first connection pads 1510 , respectively, through a reflow process so that the first semiconductor package 41 can be mounted on the board 1000 .

[0141] The second semiconductor package 42 may be Fig. 12A and Fig. 12B The second semiconductor package 42 described above is the same as the second semiconductor package 42 described above. The second semiconductor package 42 may be spaced apart from the first semiconductor package 41. The second external terminals 152 are respectively connected to the second connection pads 1520 by a reflow process so that the second semiconductor package 42 may be mounted on the board 1000. The first semiconductor package 41 and the second semiconductor package 42 may be electrically connected to each other through the connection wiring 1005 of the board 1000. For example, the voltage converted in the second semiconductor chip 220 of the second semiconductor package 42 may be provided to the first semiconductor chip 210 or the third semiconductor chip 720 of the first semiconductor package 41 through the board 1000.

[0142] After the first semiconductor package 41 is mounted on the board 1000, an underfill pattern 801 may be formed between the first lower semiconductor package 16 and the first upper semiconductor package 21. The underfill pattern 801 may seal the conductive terminal 750. The underfill pattern 801 may not extend onto the lower surface of the first lower substrate 101. The underfill pattern 801 includes an insulating polymer, and the thermal conductivity of the underfill pattern 801 may be higher than that of air. As another example, the underfill pattern 801 may not be formed.

[0143] According to the inventive concept, a conductive structure is provided between the lower substrate and the interposer substrate so that the distance between the lower substrate and the interposer substrate can be large enough to set the passive components. Therefore, the passive components can be mounted on the lower substrate. The electrical path between the passive components and the semiconductor chip can be shortened. The conductive structure has a fine pitch so that the semiconductor package can be miniaturized.

[0144] Although some exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the inventive concept claimed herein.

Claims

1. A semiconductor package, comprising: substrate; a semiconductor chip, wherein the semiconductor chip is located on the substrate; A passive component, wherein the passive component is located on the substrate, and the height of the passive component is greater than the height of the semiconductor chip; a conductive structure, the conductive structure being located on the substrate; an interposer substrate, the interposer substrate being located on the semiconductor chip, the passive element and the conductive structure, the interposer substrate being electrically connected to the conductive structure; as well as an upper passive component, the upper passive component being located on the interposer substrate, Wherein, the height of the upper passive element is greater than the gap between the substrate and the interposer substrate. 2 . The semiconductor package of claim 1 , further comprising a solder connection between the conductive structure and the interposer substrate. 3 .

3. The semiconductor package according to claim 2, wherein: The melting point of the conductive structure is greater than the melting point of the solder connection.

4. The semiconductor package according to claim 1, wherein: The height of the conductive structure is greater than the height of the passive element.

5. The semiconductor package according to claim 1, wherein: The semiconductor chip includes a first semiconductor chip and a second semiconductor chip, The first semiconductor chip includes one or more logic circuits, The second semiconductor chip is spaced apart from the first semiconductor chip, and The second semiconductor chip includes one or more power management integrated circuits.

6. The semiconductor package according to claim 5, wherein: The conductive structures include one or more signal structures and one or more power structures, The one or more signal structures are adjacent to the first semiconductor chip; and The one or more power structures are closer to the second semiconductor chip than the one or more signal structures. 7 . The semiconductor package according to claim 1 , further comprising an upper package located on the interposer substrate.

8. The semiconductor package according to claim 1, further comprising: an upper package, the upper package being located on the interposer substrate, Wherein, the upper passive component is spaced apart from the upper package.

9. The semiconductor package according to claim 1, further comprising a plurality of conductive structures on the substrate, wherein: The plurality of conductive structures include the conductive structure, At least one conductive structure of the plurality of conductive structures is located between the semiconductor chip and the passive component or between the passive components.

10. A semiconductor package, comprising: substrate; a semiconductor chip, the semiconductor chip being located on the upper surface of the substrate; a passive component, the passive component being located on the upper surface of the substrate; an interposer substrate, the interposer substrate being located on the semiconductor chip and the passive components; a conductive structure, the conductive structure being located between the substrate and the interposer substrate; a lower solder connection portion, the lower solder connection portion being located between the substrate and the conductive structure; an upper solder connection portion, the upper solder connection portion being located between the conductive structure and the interposer substrate; as well as an upper passive component, the upper passive component being located on an upper surface of the interposer substrate, Wherein, the height of the upper passive element is greater than the gap between the substrate and the interposer substrate.

11. The semiconductor package according to claim 10, wherein: An upper surface of the passive element is at a higher level than an upper surface of the semiconductor chip.

12. The semiconductor package according to claim 10, wherein: The melting point of the conductive structure is greater than the melting point of the lower solder connection, and the melting point of the conductive structure is greater than the melting point of the upper solder connection.

13. The semiconductor package according to claim 10, wherein: The semiconductor chip includes a first semiconductor chip and a second semiconductor chip, and The second semiconductor chip is configured to perform a function different from that of the first semiconductor chip.

14. The semiconductor package according to claim 13, further comprising: an upper package, the upper package being located on the upper surface of the interposer substrate, the upper package comprising a third semiconductor chip, wherein The third semiconductor chip is configured to perform a function different from a function of the first semiconductor chip and a function of the second semiconductor chip.

15. The semiconductor package according to claim 10, wherein: The height of the upper passive component is greater than a height of the passive component.

16. A semiconductor package, comprising: substrate; a semiconductor chip, the semiconductor chip being located on the upper surface of the substrate; a passive component, the passive component being located on the upper surface of the substrate, the upper surface of the passive component being at a higher level than the upper surface of the semiconductor chip; a conductive structure, the conductive structure being located on the substrate; an interposer substrate, the interposer substrate being located on the semiconductor chip, the passive element and the conductive structure, the interposer substrate being electrically connected to the conductive structure; a lower solder connection portion, the lower solder connection portion being located between the substrate and the conductive structure, the lower solder connection portion being connected to the substrate and the conductive structure; as well as an upper passive component, the upper passive component being located on an upper surface of the interposer substrate, Wherein, the height of the upper passive element is greater than the gap between the substrate and the interposer substrate.

17. The semiconductor package according to claim 16, wherein: The upper surface of the conductive structure is at a higher level than the upper surface of the passive component. 18 . The semiconductor package of claim 16 , further comprising an upper solder connection between the conductive structure and the interposer substrate.

19. The semiconductor package according to claim 16, wherein: The conductive structure has a pin shape or a columnar shape, and, The conductive structure includes a material different from a material of the lower solder connection.

20. The semiconductor package according to claim 16, further comprising: an upper package, the upper package being located on an upper surface of the interposer substrate, Wherein, the height of the upper passive component is greater than the height of the upper package.

21. The semiconductor package according to claim 20, further comprising: a conductive terminal, the conductive terminal being located between the interposer substrate and the upper package; as well as A bottom filling film is located in a gap between the interposer substrate and the upper package, wherein: The underfill film is configured to seal the conductive terminal, and A width of the upper package is smaller than a width of the interposer substrate. 22 . The semiconductor package of claim 16 , further comprising a mold film configured to fill a gap between the substrate and the interposer substrate and cover a sidewall of the conductive structure.

23. The semiconductor package according to claim 16, wherein: The semiconductor chip includes a first semiconductor chip and a second semiconductor chip, The first semiconductor chip includes one of a system on chip, a modem chip, a ModAP chip, an application processor chip or a communication processor chip, and The second semiconductor chip includes a power management chip.

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