Data processing device

Abstract

A data processing apparatus is provided that can correctly monitor the status of interrupt processing of virtual machines. The data processing apparatus according to an aspect of the present disclosure includes: an arithmetic unit that executes a plurality of virtual machines respectively; and an interrupt controller that uses virtual machine information for designating at least one of the plurality of virtual machines to instruct the arithmetic unit to execute interrupt processing. The interrupt controller includes a counter that counts the number of interrupts for each virtual machine based on the virtual machine information.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2018-096329, filed on May 18, 2018, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a data processing apparatus capable of executing a plurality of virtual machines. Background Art

[0004] Heretofore, systems for detecting anomalies by monitoring interrupt processing of a CPU (Central Processing Unit) have been proposed.

[0005] For example, Japanese Patent No. 4065131 discloses a system in which the time between events of interrupt processing is measured based on the measured time to detect anomalies in the CPU.

[0006] On the other hand, there is virtualization technology that makes a single physical resource (hardware resource) appear as multiple resources. For example, by adopting such virtualization technology, multiple virtual machines (VMs) can be operated on one CPU, and thus different operating systems (OSs) can be operated on each virtual machine.

[0007] Each virtual machine (VM) needs to satisfy independent functional safety. That is, it is necessary to ensure that these functions are not interfered with each other (Free From Interference (FFI)).

[0008] To ensure this, it is necessary to adopt a scheme capable of monitoring the state of interrupt processing of the virtual machine.

[0009] (Patent Document 1) Japanese Patent No. 4065131 Summary of the Invention

[0010] The present disclosure is completed to solve the above problems by providing a data processing apparatus capable of correctly monitoring the state of interrupt processing of a virtual machine.

[0011] Other problems and new features of the present invention will become apparent from the description of the present specification and the drawings.

[0012] A data processing apparatus according to an embodiment of the present disclosure includes: an arithmetic unit that executes each of a plurality of virtual machines; and an interrupt controller that instructs the arithmetic unit to execute interrupt processing by using virtual machine information for specifying at least one of the virtual machines. The interrupt controller includes a counter that counts the number of interrupts for each virtual machine based on the virtual machine information.

[0013] According to one embodiment, the data processing apparatus according to the present disclosure can correctly monitor the status of interrupt processing of a virtual machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram illustrating an example of a configuration when the data processing apparatus 1 according to Embodiment 1 is used for a vehicle 200;

[0015] Figure 2 is a diagram illustrating the data processing apparatus 1 according to Embodiment 1 and its peripheral circuits;

[0016] Figure 3 is a diagram illustrating the count target setting information CCFG according to Embodiment 1;

[0017] Figure 4 is a diagram illustrating the virtual machine information according to Embodiment 1;

[0018] Figure 5A and Figure 5B is a diagram illustrating the configuration of the VM compliance determination unit 45 according to Embodiment 1;

[0019] Figure 6 is a diagram illustrating the configuration of the additional condition determination unit 50 according to Embodiment 1;

[0020] Figure 7 is a diagram illustrating the configuration of the count indication unit 55 according to Embodiment 1;

[0021] Figure 8A 、 Figure 8B and Figure 8C is a diagram illustrating a specific example of the count processing according to Embodiment 1;

[0022] Figure 9 is a diagram illustrating the access target setting information ACFG according to Embodiment 1;

[0023] Figure 10 is a diagram illustrating the virtual machine information used in the access permission determination unit 25 according to Embodiment 1;

[0024] Figure 11 is a diagram illustrating the configuration of the access permission determination unit 25 according to Embodiment 1;

[0025] Figure 12A and Figure 12B is a diagram illustrating the configuration of the counter access request generation unit 27 according to Embodiment 1;

[0026] Figure 13A and Figure 13B is a diagram illustrating a specific example of the access processing according to Embodiment 1;

[0027] Figure 14 FIG. is a diagram showing the data processing device 1# and its peripheral circuit according to Embodiment 2;

[0028] Figure 15 FIG. is a diagram showing the configuration of the additional condition determination unit 50# according to Embodiment 2;

[0029] Figure 16A 、 Figure 16B and Figure 16C FIG. is a diagram showing a specific example of the counting process according to Embodiment 2; and

[0030] Figure 17 FIG. is a diagram showing the data processing device 1P and its peripheral circuit according to Embodiment 3. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The embodiments are explained in detail with reference to the accompanying drawings. In the following explanations, the same symbols or reference numerals are attached to the same or corresponding elements, and their repeated explanations may be omitted.

[0032] (Embodiment 1)

[0033] Figure 1 FIG. is a block diagram showing an example of the configuration when the data processing device 1 according to Embodiment 1 is used in a vehicle 200.

[0034] Referring to Figure 1 , the data processing device 1, the sensor 210, and the camera 220 are provided in the vehicle 200. The data processing device 1 is an in-vehicle chip.

[0035] The sensor 210 acquires predetermined information about the vehicle 200.

[0036] The camera 220 acquires an image around the vehicle 200.

[0037] The information acquired by the sensor 210 and the camera 220 is provided to the data processing device 1.

[0038] The data processing device 1 performs a predetermined process corresponding to the information acquired by the sensor 210 and the camera 220. In this example, as an example, various functions using the virtual machine VM are performed.

[0039] Figure 2 FIG. is a diagram showing the data processing device 1 and its peripheral circuit according to Embodiment 1.

[0040] Referring to Figure 2 , the data processing device 1 includes a CPU 5, a memory 10, a data bus 15, and an interrupt controller 20.

[0041] The CPU 5 includes an execution unit. The execution unit reads a program for executing a virtual machine from the memory 10 and implements the functions of the virtual machine VM and the virtual machine monitor VMM. As an example, this example illustrates the case where programs for implementing the functions of the virtual machines VM0 to VMi are stored in the memory 10. Programs for implementing the functions of the virtual machine monitor VMM for managing the virtual machines VM are also stored in the memory 10.

[0042] The CPU 5 and the memory 10 send and receive data via the data bus 15. The CPU 5 and the interrupt controller 20 also send and receive data via the data bus 15.

[0043] This example explains a configuration in which one piece of memory 10 is provided. However, without being limited to the specific case, it is also preferable to adopt a configuration in which a plurality of memories are provided. This example explains the case where the CPU 5 accesses the memory 10 via the data bus 15. However, without being limited to the specific case, it is also preferable to provide another path through which the CPU 5 can directly access the memory without passing through the data bus 15.

[0044] The CPU 5 outputs a status signal ST indicating the status of the CPU 5 to the interrupt controller 20. The status signal ST indicates whether the CPU 5 is ready to execute an interrupt process. For example, the status signal ST being "1" indicates that an interrupt process can be received, and the status signal ST being "0" indicates that an interrupt process cannot be received. The above relationship between the status and the value of the status signal ST is an example, and they can be opposite.

[0045] When it is determined based on the status signal ST that the CPU 5 is ready to execute an interrupt process, the interrupt controller 20 instructs the CPU 5 to execute the interrupt process.

[0046] In accordance with the instruction to execute the interrupt process from the interrupt controller 20, the CPU 5 accesses the memory 10, reads a program for implementing the functions of the indicated virtual machines VM0 to VMi or the virtual machine monitor VMM, and executes the program using the execution unit.

[0047] It is also preferable that the interrupt controller 20 can acquire a plurality of pieces of information indicating the status of the CPU 5 via the status signal ST and can determine whether an interrupt process can be executed based on the information stored in the interrupt information storage unit 65 described below.

[0048] The interrupt controller 20 includes an access permission determination unit 25, a counter unit 30, a count condition setting unit 35, a plurality of counter control units 40, an interrupt information storage unit 65, and an interrupt determination unit 60.

[0049] The access permission determination unit 25 determines whether to permit access to the counter unit 30 or the count condition setting unit 35. The processing will be described below.

[0050] The counter unit 30 counts the number CNT of interrupt processing times for each counter channel CCH and stores the number CNT. In this example, (m + 1) counter channels CCH0 to CCHm are provided (hereinafter, they are collectively referred to as counter channels CCH). The number CNT of interrupt processing times is counted and the number CNT is stored in association with each counter channel CCH.

[0051] The count condition setting unit 35 sets count conditions for the counter unit 30 to count the number of interrupt processing times. Specifically, count conditions are set for each counter channel CCH. Specifically, the count conditions include: count target setting information CCFG for setting a virtual machine as a target to be counted, and count additional setting information for setting additional information during counting. In addition to the count conditions, access conditions are also set for each counter channel CCH. Specifically, it includes access target setting information ACFG for setting a virtual machine as a permission target during access.

[0052] For example, the count target setting information CCFG includes several bits. As an example, the top bit is assigned as the setting information of the virtual machine monitor VMM. The subsequent bits are assigned as the setting information of the virtual machines VMi to VM0. Therefore, when the top bit is set to "1", it indicates that the virtual machine monitor VMM is set as the count target in the counter channel CCH. On the other hand, when the top bit is set to "0", it indicates that the virtual machine monitor VMM is not set as the count target in the counter channel CCH. The same applies to other bits.

[0053] Therefore, according to the count target setting information CCFG, the virtual machines VM0 to VMi and the virtual machine monitor VMM that serve as the count target in the counter channel CCH are set. Here, the virtual machines serving as the count target are not limited to one, but multiple virtual machines can be set.

[0054] The count additional setting information CND includes several bits of data. Specifically, the count additional setting information CND includes channel designation data CHE, channel number CHNUM, priority designation data PRE, and priority number PRENUM.

[0055] The channel designation data CHE designates whether the channel number is included as a count condition. For example, when the channel designation data CHE is set to "0", it indicates that the channel number is not included as a count condition. When the channel designation data CHE is set to "1", it indicates that the channel number is included as a count condition.

[0056] The channel number CHNUM is a bit assignment that designates the channel number as a counting condition when the channel number is included as a counting condition (channel designation data CHE(“1”)). For example, when the channel number CHNUM is set to “0”, it indicates that channel number “0” is designated as the counting condition. When the channel number CHNUM is set to “10”, it indicates that channel number “10” is designated as the counting condition.

[0057] The priority designation data PRE designates whether the priority number is included as a counting condition. For example, when the priority designation data PRE is set to “0”, it indicates that the priority number is not included as a counting condition. When the priority designation data PRE is set to “1”, it indicates that the priority number is included as a counting condition.

[0058] When the priority number is included as a counting condition (priority designation data PRE(“1”)), the priority number PRNUM designates the priority number that serves as the counting condition. For example, when the priority number PRNUM is set to “0”, it indicates that priority number “0” is designated as the counting condition. When the priority number PRNUM is set to “10”, it indicates that priority number “10” is designated as the counting condition.

[0059] The access target setting information ACFG includes a number of bits of data. As an example, the top bit is assigned as the setting information of the virtual machine monitor VMM. The subsequent bits are assigned as the setting information of virtual machines VMi to VM0. Therefore, when the top bit is set to “1”, it indicates that the virtual machine monitor VMM is set as an accessible virtual machine in the relevant counter channel CCH. On the other hand, when the top bit is set to “0”, it indicates that the virtual machine monitor VMM is not set as an accessible virtual machine in the relevant counter channel CCH. The same applies to the other bits.

[0060] Therefore, according to the access target setting information ACFG, the virtual machines VM0 to VMi and the virtual machine monitor VMM that can be accessed in the counter channel CCH are set. Here, not only can one virtual machine be set as the target of the accessible virtual machine, but also multiple virtual machines can be set as the target of the accessible virtual machine.

[0061] The counter control unit 40 performs control when counting the number of interrupt processes for each counter channel CCH based on the counting conditions set by the counting condition setting unit 35.

[0062] In this example, (m + 1) counter channels CCH0 to CCHm are provided, and a counter control unit 40 is also provided for each counter channel CCH.

[0063] In Figure 2In order to simplify the explanation, the counter control unit 40x (collectively also referred to as the counter control unit 40) corresponding to the counter channel CCHx is illustrated. The same applies to other counter control units 40.

[0064] The interruption information storage unit 65 stores interruption information for each channel CH. In this example, channels CH0 to CHn are provided, and virtual machine information is stored as an interruption target for each channel CH.

[0065] For example, channel CH is pre-assigned to each output information from a sensor or a camera. Based on the output information from the sensor or the camera, the specified virtual machine information is stored in the pre-assigned channel CH of the interruption information storage unit 65.

[0066] The interruption information storage unit 65 outputs the stored information to the interruption determination unit 60. Specifically, the interruption information storage unit 65 outputs an interruption request signal CREQ, channel CH, virtual machine information (VMD, VMID), and priority data PRI to the interruption determination unit 60.

[0067] In response to the information from the interruption information storage unit 65, the interruption determination unit 60 determines whether interruption processing is acceptable based on the status signal ST from the CPU 5.

[0068] When it is determined that the interruption processing is acceptable based on the status signal ST from the CPU 5, the interruption determination unit 60 instructs the CPU 5 to execute the interruption processing. The interruption determination unit 60 outputs the information including channel CH and virtual machine information output from the interruption information storage unit 65 to the CPU 5.

[0069] When the status signal ST is "1", the interruption determination unit 60 determines that the interruption processing is acceptable and outputs the information from the interruption information storage unit 65 to the counter control unit 40.

[0070] When the status signal ST is "0", the interruption determination unit 60 determines that the interruption processing is unacceptable and waits until the status signal ST is set to "1". Then, when the status signal ST is set to "1", the interruption determination unit 60 outputs the information from the interruption information storage unit 65 to the counter control unit 40.

[0071] The interruption determination unit 60 can obtain a plurality of information indicating the status of the CPU 5 through the status signal ST, and can determine whether interruption processing can be executed based on the information stored in the interruption information storage unit 65.

[0072] The counter control unit 40 includes a VM compliance determination unit 45, an additional condition determination unit 50, and a count indication unit 55.

[0073] The VM compliance determination unit 45 determines whether the virtual machine information that has received the interrupt process is set as the counting target of the counting condition, based on the counting target setting information CCFG set by the counting condition setting unit 35 and the virtual machine information (VM, VMID) output from the interrupt determination unit 60.

[0074] When the VM compliance determination unit 45 determines, based on the counting target setting information CCFG set by the counting condition setting unit 35 and the virtual machine information (VM, VMID) output from the interrupt determination unit 60, that the virtual machine information that has received the interrupt process is set as the counting target of the counting condition, the VM compliance determination unit 45 outputs a compliance signal Vhit to the counting indication unit 55.

[0075] For example, a compliance signal Vhit of "1" indicates that the virtual machine information that has received the interrupt process is set as the counting target of the counting condition.

[0076] On the other hand, a compliance signal Vhit of "0" indicates that the virtual machine information that has received the interrupt process is not set as the counting target of the counting condition.

[0077] The additional condition determination unit 50 determines whether the corresponding additional condition conforms to the virtual machine information that has received the interrupt process, based on the counting additional setting information CND set by the counting condition setting unit 35 and based on the channel CH and the priority data PRI output from the interrupt determination unit 60.

[0078] When the additional condition determination unit 50 determines, based on the counting additional setting information CND set by the counting condition setting unit 35 and based on the channel CH and the priority data PRI output from the interrupt determination unit 60, that the corresponding additional condition conforms to the virtual machine information that has received the interrupt process, the additional condition determination unit 50 outputs a compliance signal Chit to the counting indication unit 55.

[0079] The additional condition determination unit 50 does not necessarily need to perform the determination of the additional condition. When the determination of the additional condition is not performed, the compliance signal Chit is set to "1".

[0080] For example, a compliance signal Chit of "1" indicates that the corresponding additional condition conforms to the virtual machine information that has received the interrupt process.

[0081] On the other hand, a compliance signal Vhit of "0" indicates that the corresponding additional condition does not conform to the virtual machine information that has received the interrupt process.

[0082] The counting instruction unit 55 performs a counting instruction operation according to the interrupt request signal CREQ. Specifically, the counting instruction unit 55 outputs a counting instruction signal for the counter channel CCH based on the coincidence signal Vhit output from the VM coincidence determination unit 45 and the coincidence signal Chit output from the additional condition determination unit 50.

[0083] The counter unit 30 updates the count CNT of the corresponding counter channel CCH according to the counting instruction signal. For example, the counter unit 30 increments the count CNT by one.

[0084] This example explains the configuration in which one interrupt information storage unit 65 is provided. However, for example, a configuration in which the interrupt information storage unit 65 is provided for each CPU may also be adopted.

[0085] Figure 3 The counting target setting information CCFG according to Embodiment 1 is illustrated.

[0086] Refer to Figure 3 , the counting target setting information CCFG sets whether to arrange a virtual machine as a counting target.

[0087] As described above, the counting target setting information CCFG provided for each counter channel CCH sets the virtual machine that serves as the counting target for the counter channel CCH.

[0088] Specifically, when the bit of the target virtual machine is set to "1", counting is performed when interrupt information serving as an event related to the target virtual machine is received. When the bit of the target virtual machine is set to "0", counting is not performed when interrupt information serving as an event related to the target virtual machine is received.

[0089] Figure 4 The virtual machine information according to Embodiment 1 is illustrated.

[0090] Refer to Figure 4 , the virtual machine information includes virtual machine management data VMD and virtual machine identification data VMID.

[0091] The virtual machine management data VMD identifies the virtual machine monitor VMM and the general virtual machine VM. Specifically, the virtual machine management data VMD being "0" represents the virtual machine monitor VMM. On the other hand, the virtual machine management data VMD being "1" represents the general virtual machine VM. Each general virtual machine VM can be identified by the virtual machine identification data VMID.

[0092] In this example, for virtual machine VM0, virtual machine management data VMD is assigned "1", and virtual machine identification data VMID is assigned "0". For virtual machine VM1, virtual machine management data VMD is assigned "1", and virtual machine identification data VMID is assigned "1". For virtual machine VM2, virtual machine management data VMD is assigned "1", and virtual machine identification data VMID is assigned "2". For virtual machine VM3, virtual machine management data VMD is assigned "1", and virtual machine identification data VMID is assigned "3".

[0093] Each of virtual machine VM and virtual machine monitor VMM can be identified based on information about the virtual machine.

[0094] Figure 5A and Figure 5B illustrates the configuration of VM compliance determination unit 45 according to Embodiment 1.

[0095] Referring to Figure 5A , VM compliance determination unit 45 includes virtual machine information determination unit 46.

[0096] Virtual machine information determination unit 46 identifies the virtual machine based on virtual machine management data VMD and virtual machine identification data VMID.

[0097] Figure 5B illustrates a circuit for outputting a compliance signal Vhit, which indicates that the virtual machine information receiving the interrupt processing is a counting target of the counting condition.

[0098] Referring to Figure 5B , VM compliance determination unit 45 further includes a plurality of AND circuits AD0 to AD4 and an OR circuit OR0.

[0099] AND circuits AD0 to AD4 output the AND logic operation results of the determination results of virtual machine information determination unit 46 and each bit of counting target setting information CCFG. Specifically, virtual machine information determination unit 46 sets the determination result of the target virtual machine information to "1" based on virtual machine management data VMD and virtual machine identification data VMID. When the bit of counting target setting information CCFG is set to "1" and the determination result of the virtual machine information is "1", the corresponding AND circuit AD outputs "1" to OR circuit OR0 and compliance signal Vhit is set to "1". That is, it is determined that the virtual machine information receiving the interrupt processing is set as the counting target of the counting condition.

[0100] On the other hand, when compliance signal Vhit is "0", it is determined that the virtual machine information receiving the interrupt processing is not set as the counting target of the counting condition.

[0101] Figure 6 Illustrates the configuration of the additional condition determination unit 50 according to Embodiment 1.

[0102] Referring to Figure 6 , the additional condition determination unit 50 includes comparator circuits GT0 and GT1, AND circuits AD5, AD6, and AD7, and OR circuits OR1 and OR2.

[0103] The comparator circuit GT0 compares the specified channel number CHNUM with the data of channel CH output from the interrupt information storage unit 65 and determines whether they match.

[0104] When the comparator circuit GT0 determines that the data of channel CH output from the interrupt information storage unit 65 matches the specified channel number CHNUM, the comparator circuit GT0 outputs "1". When the comparator circuit GT0 determines that they do not match, the comparator circuit GT0 outputs "0".

[0105] The comparator circuit GT1 compares the specified priority number PRNUM with the priority data PRI output from the interrupt information storage unit 65 and determines whether they match.

[0106] When the comparator circuit GT1 determines that the priority data PRI output from the interrupt information storage unit 65 matches the specified priority number PRNUM, the comparator circuit GT1 outputs "1". When the comparator circuit GT1 determines that they do not match, the comparator circuit GT1 outputs "0".

[0107] When the comparator circuit GT0 outputs "1" and the channel specification data CHE is "1", the AND circuit AD5 outputs the AND logic operation result ("1").

[0108] Otherwise, the AND circuit AD5 outputs the AND logic operation result ("0").

[0109] The OR circuit OR1 receives the output signal from the AND circuit AD5 and the inverted data of the channel specification data CHE and outputs the OR logic operation result to the AND circuit AD7.

[0110] When the comparator circuit GT1 outputs "1" and the priority specification data PRE is "1", the AND circuit AD6 outputs the AND logic operation result ("1").

[0111] Otherwise, the AND circuit AD6 outputs the AND logic operation result ("0").

[0112] The OR circuit OR2 receives the output signal from the AND circuit AD6 and the inverted data of the priority designation data PRE, and outputs the OR logic operation result to the AND circuit AD7.

[0113] The AND circuit AD7 outputs the AND logic operation result of the OR circuits OR1 and OR2.

[0114] When the channel designation data CHE is "0" and the priority designation data PRE is "0", both the OR circuits OR1 and OR2 output "1". Therefore, the AND circuit AD7 sets the coincidence signal Chit to "1". In this case, the condition determination process of the additional condition determination unit 50 is not executed.

[0115] On the other hand, when the channel designation data CHE is "1", the condition determination process for whether the data of channel CH conforms to the designated channel number CHNUM is executed. When the priority designation data PRE is "1", the condition determination process for whether the priority data PRI conforms to the designated priority number PRNUM is executed.

[0116] When the executed condition determination process indicates coincidence, the additional condition determination unit 50 sets the coincidence signal Chit to "1". When the executed condition determination process does not indicate coincidence, the additional condition determination unit 50 sets the coincidence signal Chit to "0". In this case, the count indication signal is not output.

[0117] Figure 7 The configuration of the count indication unit 55 according to Embodiment 1 is illustrated.

[0118] As Figure 7 illustrated, the count indication unit 55 includes an AND circuit AD15.

[0119] The AND circuit AD7 indicates counting based on the coincidence signal Chit, the coincidence signal Vhit, and the interrupt request signal CREQ.

[0120] Specifically, when all of the coincidence signal Chit, the coincidence signal Vhit, and the interrupt request signal CREQ are "1", the count indication unit 55 sets the count indication signal to "1". Otherwise, the count indication unit 55 sets the count indication signal to "0". The counter unit 30 updates the count CNT of the corresponding counter channel CCH according to the count indication signal ("1") output from the count indication unit 55. As an example, the counter unit 30 increments the count CNT by one.

[0121] (Specific example)

[0122] Figure 8A 、 Figure 8B and Figure 8CIllustrates a specific example of the counting process according to Embodiment 1.

[0123] Figure 8A Illustrates an example of the interrupt information storage unit 65.

[0124] Specifically, Figure 8A Illustrates the case where interrupt information corresponding to channels CH10, CH11, CH20, and CH21 is received.

[0125] Here, corresponding to channel CH10, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0".

[0126] Corresponding to channel CH11, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0".

[0127] Corresponding to channel CH20, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "1".

[0128] Corresponding to channel CH21, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "1".

[0129] Figure 8B Illustrates an example of the counter unit 30 and the counting condition setting unit 35.

[0130] Specifically, counter channels CCH0 to CCH3 are set to the counter unit 30. Regarding the counting target setting information CCFG corresponding to counter channel CCH0, only virtual machine VM0 is set to "1". Regarding the counting target setting information CCFG corresponding to counter channel CCH1, only virtual machine VM0 is set to "1". Regarding the counting additional setting information CND, the channel specification data CHE is set to "1". The channel number CHNUM is set to "10". Regarding the counting target setting information CCFG corresponding to counter channel CCH2, only virtual machine VM1 is set to "1". Regarding the counting target setting information CCFG corresponding to counter channel CCH3, only virtual machine VM1 is set to "1". Regarding the counting additional setting information CND, the channel specification data CHE is set to "1". The channel number CHNUM is set to "20".

[0131] Figure 8C Illustrates for Figure 8A the counting process of counter channel CCHx of the illustrated interrupt information storage unit 65.

[0132] Explains the interrupt processing corresponding to channel CH10.

[0133] In the counter control unit 40 provided corresponding to the counter channel CCH0, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50 outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for the counter channel CCH0 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50. Accordingly, the number CNT of times the counter channel CCH0 is updated is updated.

[0134] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55.

[0135] The additional condition determination unit 50 compares the designated channel number CHNUM with the data of the channel CH output from the interrupt information storage unit 65 and determines that they coincide. Accordingly, a coincidence signal Chit ("1") is output to the count indication unit 55. The count indication unit 55 outputs a count indication signal for the counter channel CCH1 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50. Accordingly, the number CNT of times the counter channel CCH1 is updated is updated.

[0136] The counter control unit 40 provided corresponding to the other counter channels CCHx does not output a count indication signal.

[0137] Next, the interrupt processing corresponding to the channel CH11 is explained.

[0138] In the counter control unit 40 provided corresponding to the counter channel CCH0, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50 outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for the counter channel CCH0 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50. Accordingly, the number CNT of times the counter channel CCH0 is updated is updated.

[0139] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55.

[0140] The additional condition determination unit 50 compares the designated channel number CHNUM with the data of channel CH output from the interruption information storage unit 65, and determines that they do not match. Therefore, the additional condition determination unit 50 outputs the match signal Chit ("0") to the count indication unit 55. The count indication unit 55 does not output the count indication signal for the counter channel CCH1 based on the match signal Vhit ("1") output from the VM match determination unit 45 and the match signal Chit ("0") output from the additional condition determination unit 50. Therefore, the count CNT of the counter channel CCH1 is not updated.

[0141] Similarly, for the counter control unit 40 provided corresponding to other counter channels CCHx, the count indication signal is not output.

[0142] The interruption processing corresponding to channel CH20 is explained.

[0143] In the counter control unit 40 provided corresponding to the counter channel CCH2, the VM match determination unit 45 outputs the match signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50 outputs the match signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs the count indication signal for the counter channel CCH2 based on the match signal Vhit ("1") output from the VM match determination unit 45 and the match signal Chit ("1") output from the additional condition determination unit 50. Therefore, the count CNT of the counter channel CCH2 is updated.

[0144] In the counter control unit 40 provided corresponding to the counter channel CCH3, the VM match determination unit 45 outputs the match signal Vhit ("1") to the count indication unit 55.

[0145] The additional condition determination unit 50 compares the designated channel number CHNUM with the data of channel CH output from the interruption information storage unit 65, and determines that they match. Therefore, the match signal Chit ("1") is output to the count indication unit 55. The count indication unit 55 outputs the count indication signal for the counter channel CCH3 based on the match signal Vhit ("1") output from the VM match determination unit 45 and the match signal Chit ("1") output from the additional condition determination unit 50. Therefore, the count CNT of the counter channel CCH3 is updated.

[0146] The counter control unit 40 provided corresponding to other counter channels CCHx does not output the count indication signal.

[0147] Next, the interruption processing corresponding to channel CH21 is explained.

[0148] In the counter control unit 40 provided corresponding to the counter channel CCH2, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50 outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for the counter channel CCH2 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50. Therefore, the number of times CNT of the counter channel CCH2 is updated.

[0149] In the counter control unit 40 provided corresponding to the counter channel CCH3, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55.

[0150] The additional condition determination unit 50 compares the specified channel number CHNUM with the data of the channel CH output from the interrupt information storage unit 65 and determines that they do not match. Therefore, the additional condition determination unit 50 outputs a coincidence signal Chit ("0") to the count indication unit 55. The count indication unit 55 does not output a count indication signal for the counter channel CCH3 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("0") output from the additional condition determination unit 50. Therefore, the number of times CNT of the counter channel CCH3 is not updated.

[0151] Similarly, for the counter control unit 40 provided corresponding to other counter channels CCHx, a count indication signal is not output.

[0152] (Access to the counter channel CCHx)

[0153] Figure 9 The access target setting information ACFG according to Embodiment 1 is illustrated.

[0154] Refer to Figure 9 , the access target setting information ACFG determines whether the virtual machine is set as the access target.

[0155] As described above, the access target setting information ACFG provided for each counter channel CCH sets the virtual machine to act as the access target for the relevant counter channel CCH.

[0156] Specifically, when the bit of the target virtual machine is set to "1", the virtual machine related to the target can access the information corresponding to the counter channel CCH. Specifically, the content of the count target setting information CCFG and the count additional setting information CND can also be changed. On the other hand, when the bit of the target virtual machine is set to "0", the virtual machine related to the target cannot access the information corresponding to the counter channel CCH.

[0157] Figure 10 Illustrated is the virtual machine information used in the access permission determination unit 25 according to Embodiment 1.

[0158] Refer to Figure 10 , the virtual machine information includes virtual machine management data VMD and virtual machine identification data VMID. This is the same as that explained with reference to Figure 4 as explained.

[0159] The virtual machine management data VMD identifies the virtual machine monitor VMM and the general virtual machine VM. Specifically, the virtual machine management data VMD being "0" indicates the virtual machine monitor VMM. On the other hand, the virtual machine management data VMD being "1" indicates the general virtual machine VM. The general virtual machine VM can be respectively identified by the virtual machine identification data VMID.

[0160] In this example, for the virtual machine VM0, the virtual machine management data VMD is assigned "1", and the virtual machine identification data VMID is assigned "0". For the virtual machine VM1, the virtual machine management data VMD is assigned "1", and the virtual machine identification data VMID is assigned "1". For the virtual machine VM2, the virtual machine management data VMD is assigned "1", and the virtual machine identification data VMID is assigned "2". For the virtual machine VM3, the virtual machine management data VMD is assigned "1", and the virtual machine identification data VMID is assigned "3".

[0161] Each of the virtual machine VM and the virtual machine monitor VMM can be identified based on the relevant virtual machine information.

[0162] Figure 11 Illustrated is the configuration of the access permission determination unit 25 according to Embodiment 1.

[0163] Refer to Figure 11 , the access permission determination unit 25 includes an address decoding circuit 26, a counter access request generation unit 27, and a selector 28.

[0164] The address decoding circuit 26 receives the access request AQ and decodes it.

[0165] The address decoding circuit 26 extracts the counter channel number based on the address signal included in the access request AQ.

[0166] The counter access request generation unit 27 further receives virtual machine information about the virtual machine that outputs the access request AQ. The virtual machine information includes virtual machine management data VMD and virtual machine identification data VMID.

[0167] The address decoding circuit 26 generates a counter channel number CCHx and a selection signal SEL_ACFG based on the input address signal.

[0168] The address decoding circuit 26 outputs the selection signal SEL_ACFG to the counter access request generation unit 27.

[0169] The counter access request generation unit 27 identifies the virtual machine based on the virtual machine management data VMD and the virtual machine identification data VMID.

[0170] Then, for the identified virtual machine, it is determined whether the bit of the target virtual machine is set to "1" in the access target setting information ACFG.

[0171] The counter access request generation unit 27 outputs the determination result to the counter unit 30 as a counter access request signal CAQ("1").

[0172] The counter unit 30 outputs a count CNT according to the counter access request signal CAQ. Specifically, the counter unit 30 outputs the count CNT to the accessed virtual machine via the data bus 15.

[0173] The counter access request generation unit 27 permits an access permission signal AP for the access target setting information ACFG according to the access target setting information ACFG.

[0174] When the access permission signal AP("1") is set, the data of the access target setting information ACFG can be edited.

[0175] Figure 12A and Figure 12B FIG. shows the configuration of the counter access request generation unit 27 according to Embodiment 1.

[0176] As Figure 12A shown, the counter access request generation unit 27 includes a virtual access machine information determination unit 27A.

[0177] The virtual access machine information determination unit 27A identifies the virtual machine to be accessed based on the virtual machine management data VMD and the virtual machine identification data VMID.

[0178] The virtual access machine information determination unit 27A sets the determination result of the virtual machine information that has been accessed to "1" based on the virtual machine management data VMD and the virtual machine identification data VMID.

[0179] As Figure 12B shown in the figure, the counter access request generation unit 27 further includes an access determination unit 27B.

[0180] The access determination unit 27B further includes a plurality of AND circuits AD8 to AD14 and an OR circuit OR3.

[0181] The AND circuits AD9 to AD13 output the AND logic operation results of the determination results of the virtual access machine information determination unit 27A and each bit of the access target setting information ACFG. Specifically, the virtual access machine information determination unit 27A sets the determination result of the virtual machine information that has been accessed to "1" based on the virtual machine management data VMD and the virtual machine identification data VMID. When one bit in the bits of the access target setting information ACFG is set to "1" and the determination result of the virtual machine information to be accessed is "1", the AND circuit AD outputs "1" to the OR circuit OR3.

[0182] The AND circuit AD14 outputs the AND logic operation result of the output signal of the OR circuit OR3 and the counter access request command IAQ as the counter access request signal CAQ.

[0183] The counter unit 30 outputs the count CNT according to the counter access request signal CAQ.

[0184] The AND circuit AD8 outputs the AND logic operation result of the bit signal corresponding to the virtual machine monitor (VMM) provided in the access target setting information ACFG and the selection signal SEL_ACFG as the access permission signal AP of the access target setting information ACFG.

[0185] When the access permission signal AP is set to "1", the access target setting information ACFG can be accessed. On the other hand, when the access permission signal AP is set to "0", the access target setting information ACFG cannot be accessed.

[0186] (Specific example)

[0187] Figure 13A and Figure 13B illustrates a specific example of the access process according to Embodiment 1.

[0188] Figure 13A illustrates an example of the counter unit 30 and the count condition setting unit 35.

[0189] Specifically, counter channels CCH0 and CCH1 are set to counter unit 30. Regarding the access target setting information ACFG corresponding to counter channel CCH0, only virtual machine VM0 is set to "1". Regarding the access target setting information ACFG corresponding to counter channel CCH1, only virtual machine monitor VMM and virtual machine VM1 are set to "1".

[0190] Refer to Figure 13B and the access processing according to the Figure 13A described access target setting information is explained.

[0191] Here, the cases where virtual machine monitor VMM and virtual machines VM0 and VM1 access are explained.

[0192] The virtual machine monitor VMM is explained.

[0193] For counter channel CCH0, the access is from virtual machine monitor VMM; thus, access permission signal AP is set to "1". Therefore, access to access target setting information ACFG is permitted. On the other hand, access to other information except access target setting information ACFG is not permitted.

[0194] For counter channel CCH1, the access is from virtual machine monitor VMM; thus, access permission signal AP is set to "1". Therefore, access to access target setting information ACFG is permitted. On the other hand, the access permission of virtual machine monitor VMM itself is set to access target setting information ACFG. Therefore, access to access target setting information ACFG is permitted.

[0195] The virtual machine VM0 is explained.

[0196] For counter channel CCH0, the access is from virtual machine VM0 and counter access request signal CAQ is set to "1". Therefore, access to counter unit 30 is permitted according to the counter access request signal ("1"). On the other hand, access to access target setting information ACFG is not permitted.

[0197] For counter channel CCH1, the access is from virtual machine VM0 and counter access request signal CAQ is set to "0". Therefore, access to counter unit 30 is not permitted. Similarly, access to access target setting information ACFG is not permitted.

[0198] The virtual machine VM1 is explained.

[0199] For counter channel CCH0, the access is from virtual machine VM1 and counter access request signal CAQ is set to "0". Therefore, access to counter unit 30 is not permitted. Similarly, access to access target setting information ACFG is not permitted.

[0200] For the counter channel CCH1, when accessing from the virtual machine VM1, the counter access request signal CAQ is set to "1". Thus, access to the counter unit 30 is permitted. On the other hand, access to the access target setting information ACFG is not permitted.

[0201] By setting the access target setting information ACFG according to the above method, access control can be performed on the relevant information of each virtual machine. In the relevant method, the access permission is determined not by reading the relevant access target setting information ACFG, but by the access permission determination unit 25. Therefore, the determination of the access permission can be performed at high speed.

[0202] In the method according to Embodiment 1, the virtual machine monitor VMM does not need to perform the interrupt processing for performing the counting process, and when performing the interrupt processing for the virtual machine VM, the counting process is performed in parallel.

[0203] Therefore, the number of times of the interrupt processing of a specific channel or the priority of each virtual machine VM can be correctly monitored without sacrificing the interrupt processing performance.

[0204] For example, a security mechanism can also be implemented so that it is possible to determine that a virtual machine VM that generates too many interrupt requests is in an abnormal state and terminate it.

[0205] In addition, the virtual machine VM can be freely set as the counting target. Therefore, it is not necessary to provide a counter for each virtual machine VM, and compared with the case of providing a counter for each virtual machine VM, no useless hardware resources are required. This is also one of the advantages.

[0206] It also includes a function for restricting access to the counter unit. By restricting access to the virtual machine monitor VMM, the number of interrupt occurrences can be correctly counted without being affected by the virtual machine VM that has entered the abnormal state.

[0207] By setting the access permission for a specific virtual machine VM, a security mechanism can also be implemented so that the virtual machine VM can monitor its own number of interrupt occurrences and achieve flexible processing.

[0208] (Embodiment 2)

[0209] Figure 14 FIG. shows the data processing apparatus 1# according to Embodiment 2 and its peripheral circuits.

[0210] Referring to Figure 14 , the data processing apparatus 1# is different from the data processing apparatus 1 in that the interrupt controller 20 is replaced by an interrupt controller 20#. Other configurations are the same as those in Embodiment 1 referring to Figure 2Those configurations explained above are the same. Therefore, their detailed explanations will not be repeated.

[0211] The difference between the interrupt controller 20# and the interrupt controller 20 is that the count condition setting unit 35 is replaced by the count condition setting unit 35#, the interrupt information storage unit 65 is replaced by the interrupt information storage unit 65#, and the additional condition determination unit 50 is replaced by the additional condition determination unit 50#. Other configurations are the same. Therefore, their detailed explanations will not be repeated.

[0212] The count condition setting unit 35# is different from the count condition setting unit 35 in the configuration of the count additional setting information CND#.

[0213] The count additional setting information CND# includes several bits of data. Specifically, the count additional setting information CND# is different in that channel identification designating data CIE and channel identification number IDNUM are provided instead of channel designating data CHE and channel number CHNUM. The priority designating data PRE and the priority number PRENUM are the same as those described above.

[0214] The channel identification designating data CIE designates whether the channel identification number is included as a count condition. For example, when the channel identification designating data CIE is set to "0", it indicates that the channel identification number is not included as a count condition. When the channel identification designating data CIE is set to "1", it indicates that the channel identification number is included as a count condition.

[0215] The channel identification number IDNUM is a bit that designates the channel identification number as a count condition when the channel identification number is included as a count condition (channel identification designating data CIE ("1")). For example, when the channel identification number IDNUM is set to "0", it means that the channel identification number "0" is designated as a count condition. When the channel identification number IDNUM is set to "10", it means that the channel identification number "10" is designated as a count condition.

[0216] In this example, by assigning the same channel identification number to different channels CH, the counting process can be performed as the same group.

[0217] The interrupt information storage unit 65# represents a situation where the channel identification number CID is further associated compared with the interrupt information storage unit 65.

[0218] Specifically, the channel identification number CID is assigned corresponding to each channel CH.

[0219] Figure 15 The configuration of the additional condition determination unit 50# according to Embodiment 2 is illustrated.

[0220] As Figure 15As shown, the data to be input is different from Figure 6 the configuration shown.

[0221] Specifically, the input channel identifier specifies data CIE instead of channel specified data CHE. The input channel identifier number IDNUM instead of channel number CHNUM. The input channel identifier number CID instead of channel CH.

[0222] Comparator circuit GT0 compares the specified channel identifier number IDNUM with the data of the channel identifier number CID output from the interrupt information storage unit 65# and determines whether they match.

[0223] When comparator circuit GT0 determines that the data of the channel identifier number CID output from the interrupt information storage unit 65# matches the specified channel identifier number IDNUM, comparator circuit GT0 outputs "1". When comparator circuit GT0 determines that they do not match, comparator circuit GT0 outputs "0".

[0224] When comparator circuit GT0 outputs "1" and the channel identifier specifies data CIE is "1", AND circuit AD5 outputs the AND logic operation result ("1").

[0225] Otherwise, comparator circuit GT0 outputs the AND logic operation result ("0").

[0226] OR circuit OR1 receives the output signal from AND circuit AD5 and the inverted data of the channel identifier specified data CIE, and outputs the OR logic operation result to AND circuit AD7.

[0227] Other configurations are the same as Figure 6 those explained in. Therefore, their detailed explanations will not be repeated.

[0228] Additional condition determination unit 50# compares the channel identifier number IDNUM with the channel identifier number CID output from the interrupt information storage unit 65# and outputs a match signal Chit based on the comparison result.

[0229] Therefore, even when the channels CH are different, as long as the channel identifier number CID is set to a common value, the counting process can be performed as the same group.

[0230] (Specific example)

[0231] Figure 16A 、 Figure 16B and Figure 16C illustrate specific examples of the counting process according to Embodiment 2.

[0232] Figure 16A illustrates an example of the interrupt information storage unit 65#.

[0233] Specifically, Figure 16A The figure illustrates a situation where interruption information corresponding to channels CH0, CH10, CH11, CH20, and CH21 is received.

[0234] Here, corresponding to channel CH0, the virtual machine management data VMD is set to "0", and the virtual machine identification data VMID is set to "0". The channel identification number CID is set to "0".

[0235] Corresponding to channel CH10, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0". The channel identification number CID is set to "0".

[0236] Corresponding to channel CH11, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0". The channel identification number CID is set to "1".

[0237] Corresponding to channel CH20, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0". The channel identification number CID is set to "2".

[0238] Corresponding to channel CH21, the virtual machine management data VMD is set to "1", and the virtual machine identification data VMID is set to "0". The channel identification number CID is set to "2".

[0239] Figure 16B The figure illustrates an example of the interruption condition setting unit 35#.

[0240] Specifically, counter channels CCH0 to CCH2 are provided in the counter unit 30.

[0241] Regarding the count target setting information CCFG corresponding to the counter channel CCH0, only the virtual machine VM0 is set to "1". The channel identification designation data CIE of the count additional setting information CND# is set to "0".

[0242] Regarding the count target setting information CCFG corresponding to the counter channel CCH1, only the virtual machine VM0 is set to "1". The channel identification designation data CIE of the count additional setting information CND# is set to "1". The channel identification number IDNUM is set to "1".

[0243] Regarding the count target setting information CCFG corresponding to the counter channel CCH2, only the virtual machine VM0 is set to "1". The channel identification designation data CIE of the count additional setting information CND# is set to "1". The channel identification number IDNUM is set to "2".

[0244] Figure 16C illustrates the counting process for the counter channel CCHx of the interrupt information storage unit 65# illustrated in Figure 16A .

[0245] Explains the interrupt processing corresponding to channel CH0.

[0246] In the counter control unit 40 provided corresponding to the counter channel CCH0, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“0”) to the count indication unit 55. The count indication unit 55 does not output the count indication signal of the counter channel CCH0. Therefore, the count CNT of the counter channel CCH0 is not updated.

[0247] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“0”) to the count indication unit 55. Similarly, in the counter control unit 40 provided corresponding to the counter channel CCH2, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“0”) to the count indication unit 55.

[0248] Therefore, the count CNT of the counter channels CCH1 and CCH2 is not updated.

[0249] Next, the interrupt processing corresponding to channel CH10 is explained.

[0250] In the counter control unit 40 provided corresponding to the counter channel CCH0, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“1”) to the count indication unit 55. The additional condition determination unit 50# outputs the coincidence signal Chit (“1”) to the count indication unit 55. The count indication unit 55 outputs the count indication signal of the counter channel CCH0 based on the coincidence signal Vhit (“1”) output from the VM coincidence determination unit 45 and the coincidence signal Chit (“1”) output from the additional condition determination unit 50#. Therefore, the count CNT of the counter channel CCH0 is updated.

[0251] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“0”) to the count indication unit 55.

[0252] Similarly, in the counter control unit 40 provided corresponding to the counter channel CCH2, the VM coincidence determination unit 45 outputs the coincidence signal Vhit (“0”) to the count indication unit 55.

[0253] Therefore, the count CNT of the counter channels CCH1 and CCH2 is not updated.

[0254] Next, the interrupt processing corresponding to channel CH11 is explained.

[0255] In the counter control unit 40 provided corresponding to counter channel CCH0, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50# outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for counter channel CCH0 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50#. Accordingly, the number of times CNT of counter channel CCH0 is updated.

[0256] In the counter control unit 40 provided corresponding to counter channel CCH1, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55.

[0257] The additional condition determination unit 50# compares the channel identification number IDNUM ("1") with the channel identification number CID ("1") and outputs a coincidence signal Chit ("1"). The count indication unit 55 outputs a count indication signal for counter channel CCH1 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50#. Accordingly, the number of times CNT of counter channel CCH1 is updated.

[0258] In the counter control unit 40 provided corresponding to counter channel CCH2, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("0") to the count indication unit 55.

[0259] Accordingly, the number of times CNT of counter channel CCH2 is not updated.

[0260] Next, the interrupt processing corresponding to channel CH20 is explained.

[0261] In the counter control unit 40 provided corresponding to counter channel CCH0, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50# outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for counter channel CCH0 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50#. Accordingly, the number of times CNT of counter channel CCH0 is updated.

[0262] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("0") to the count indication unit 55.

[0263] Therefore, the number of times CNT of the counter channel CCH1 is not updated.

[0264] In the counter control unit 40 provided corresponding to the counter channel CCH2, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("0") to the count indication unit 55.

[0265] The additional condition determination unit 50# compares the channel identification number IDNUM ("2") with the channel identification number CID ("2") and outputs a coincidence signal Chit ("1"). The count indication unit 55 outputs a count indication signal for the counter channel CCH2 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50#. Therefore, the number of times CNT of the counter channel CCH2 is updated.

[0266] Next, the interrupt processing corresponding to the channel CH21 is explained.

[0267] In the counter control unit 40 provided corresponding to the counter channel CCH0, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("1") to the count indication unit 55. The additional condition determination unit 50# outputs a coincidence signal Chit ("1") to the count indication unit 55. The count indication unit 55 outputs a count indication signal for the counter channel CCH0 based on the coincidence signal Vhit ("1") output from the VM coincidence determination unit 45 and the coincidence signal Chit ("1") output from the additional condition determination unit 50. Therefore, the number of times CNT of the counter channel CCH0 is updated.

[0268] In the counter control unit 40 provided corresponding to the counter channel CCH1, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("0") to the count indication unit 55.

[0269] Therefore, the number of times CNT of the counter channel CCH1 is not updated.

[0270] In the counter control unit 40 provided corresponding to the counter channel CCH2, the VM coincidence determination unit 45 outputs a coincidence signal Vhit ("0") to the count indication unit 55.

[0271] The additional condition determination unit 50# compares the channel identification number IDNUM (“2”) with the channel identification number CID (“2”), and outputs a coincidence signal Chit (“1”). The count indication unit 55 outputs a count indication signal for the counter channel CCH2 based on the coincidence signal Vhit (“1”) output from the VM coincidence determination unit 45 and the coincidence signal Chit (“1”) output from the additional condition determination unit 50#. Therefore, the number of times CNT of the counter channel CCH2 is updated.

[0272] According to the relevant method, even when the channels CH are different, the counting process can be performed as a common group by setting the channel identification numbers. According to this setting, even when there are multiple channels CH to be counted from a safety perspective, the number of counters can be reduced by grouping.

[0273] By setting the channel identification number CID for each safety level, it is also possible to handle the case where the channels to be monitored are divided into certain safety levels.

[0274] (Embodiment 3)

[0275] Figure 17 FIG. illustrates the data processing apparatus 1P and its peripheral circuits according to Embodiment 3.

[0276] Refer to Figure 17 , the data processing apparatus 1P is different from the data processing apparatus 1 in that the count condition setting unit 35 is replaced by a count condition setting unit 35P and a notification unit 70 is further provided. Other configurations are the same as those explained with reference to Figure 2 in Embodiment 1. Therefore, the detailed explanation thereof will not be repeated.

[0277] Compared with the count condition setting unit 35, the count condition setting unit 35P sets a conditional OVCND for giving an abnormality notification in terms of the number of times CNT.

[0278] As an example, the conditional OVCND is set with a threshold value of the number of times CNT to give an abnormality notification.

[0279] The notification unit 70 outputs an abnormality notification signal to the CPU 5 based on the number of times CNT of the count corresponding to the counter channel CCH and the information about the conditional OVCND.

[0280] For example, the notification unit 70 compares the number of times CNT with the threshold value set for the conditional OVCND. When the number of times CNT reaches the threshold value of the conditional OVCND, an abnormality notification signal is output to the CPU 5.

[0281] For example, the CPU 5 receives the abnormality notification signal and identifies it as an error.

[0282] For example, the control can be switched to the virtual machine monitor VMM and error handling can be performed.

[0283] When there is no notification function, error handling can be performed after switching the control to the virtual machine monitor VMM. However, according to the configuration of Embodiment 3, when an error occurs, the control can be immediately switched to the virtual machine monitor VMM and error handling can be performed. Therefore, the security level can be improved.

[0284] The condition OVCND is not limited to the threshold for performing exception notification. However, it can include other information.

[0285] For example, the condition OVCND can be information indicating the bit position serving as the determination target for overflow. For example, when the threshold is set to "32", the 6th bit is specified as the determination target. When the 6th bit changes from "0" to "1", it can be determined that an overflow has occurred and an exception notification signal can be output to the CPU 5.

[0286] Alternatively, the condition OVCND can indicate the bit set when the count CNT overflows.

[0287] Alternatively, a threshold range of the upper limit or the lower limit can be set as the condition OVCND. For example, a lower limit "80" and an upper limit "120" can be set.

[0288] When the count CNT is within the relevant range, the notification unit 70 does not output an exception notification signal. On the other hand, when the count CNT is not within the relevant range, the notification unit 70 outputs an exception notification signal.

[0289] In this example, the case where the count CNT increases according to the count indication signal is explained as an example. However, the above case is not particularly limited. It is also preferable to adopt a method in which the count CNT can decrease and be reduced. It is also preferable to adopt a method that combines the above methods and in which the count CNT can be reduced and increased.

[0290] As described above, the present invention completed by the present inventor has been specifically explained based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist.

Claims

1. A data processing device, comprising: An arithmetic unit for executing each of a plurality of virtual machines; And An interrupt controller for instructing the arithmetic unit to perform interrupt processing using virtual machine information that specifies at least one of the virtual machines, Wherein the interrupt controller includes a counter for counting the number of interrupts for each virtual machine based on the virtual machine information, Wherein the interrupt controller further includes a notification unit for notifying the arithmetic unit based on the count value of the counter, and Wherein the notification unit notifies the arithmetic unit that the virtual machine for which the count value of the counter represents a predetermined value is abnormal.

2. The data processing device according to claim 1, Wherein the interrupt controller further uses the virtual machine information to instruct the arithmetic unit to perform interrupt processing, the virtual machine information specifying a virtual machine manager that manages the virtual machine, and Wherein the counter counts the number of interrupts for each virtual machine and each virtual machine manager based on the virtual machine information.

3. The data processing device according to claim 2, Wherein the interrupt controller has a plurality of interrupt channels for receiving requests for the interrupt processing, Wherein the interrupt controller outputs interrupt channel information for specifying at least one of the interrupt channels to the arithmetic unit, and Wherein the counter counts the number of interrupts for each virtual machine based on the virtual machine information and the interrupt channel information.

4. The data processing device according to claim 1, Wherein the interrupt controller further includes: A counting condition setting unit for setting counting conditions for the counter; And A counter control unit for controlling the counter that counts the number of interrupts for each virtual machine based on the counting conditions set by the counting condition setting unit.

5. The data processing device according to claim 4, Wherein the interrupt controller further includes an interrupt determination unit for instructing the execution of an operation on the counter control unit based on the state of the arithmetic unit.

6. The data processing device according to claim 4, Wherein the counter control unit includes: A determination unit for receiving information about the virtual machine that executes the interrupt processing and determining whether the counting conditions are satisfied; And A counting instruction unit for instructing the counter to count based on the determination result of the determination unit.

7. The data processing device according to claim 6, Wherein the determination unit compares the identification information of the virtual machine to be set as the counting target, which is set by the counting condition setting unit, with the identification information of the virtual machine that is included in the received information of the virtual machine and executes the interrupt processing, and Wherein the counting instruction unit instructs the counter to perform the counting based on the comparison result.

8. The data processing device according to claim 6, wherein the determination unit compares channel information to be set as a counting target with channel information associated with received information of the virtual machine, the counting target being set by the counting condition setting unit, and wherein the counting indication unit instructs the counter to perform the counting based on the comparison result.

9. The data processing apparatus according to claim 6, wherein the determination unit compares priority information to be set as a counting target with priority information associated with received information of the virtual machine, the counting target being set by the counting condition setting unit, and wherein the counting indication unit instructs the counter to perform the counting based on the comparison result.

10. The data processing apparatus according to claim 4, wherein the counting condition setting unit further has an access condition, the access condition representing a condition for allowing access to information about the counting condition, and wherein the interrupt controller further includes: an access permission determination unit for controlling access to the information about the counting condition by executing the virtual machine based on the access condition.

11. The data processing apparatus according to claim 6, wherein the determination unit compares channel identification information to be set as a counting target with channel identification information associated with received information of the virtual machine, the counting target being set by the counting condition setting unit, and wherein the counting indication unit instructs the counter to perform the counting based on the comparison result.

12. The data processing apparatus according to claim 4, wherein the counting condition setting unit further has a notification condition, the notification condition representing a condition for notifying the arithmetic unit based on the count value of the counter, and wherein the notification unit notifies the arithmetic unit based on the count value of the counter and the notification condition.

13. A data processing apparatus, comprising: a central processing unit CPU that executes a plurality of virtual machines; a plurality of channels, each of the plurality of channels being assigned to one of the virtual machines and receiving an interruption for the assigned virtual machine; and a plurality of counters, each of the plurality of counters counting the number of received interruptions based on a condition that defines one of the virtual machines and one of the channels, a notification unit for notifying the CPU based on the count value of the counter, and wherein the notification unit notifies the CPU that the virtual machine for which the count value of the counter represents a predetermined value is abnormal.

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