Semiconductor device including metal silicide layer and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device including a metal silicide layer and a method for manufacturing the same. A semiconductor device includes a silicon layer, a metal silicide layer directly arranged on the silicon layer, and a solder layer directly arranged on the metal silicide layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a semiconductor device including a metal silicide layer and a method for manufacturing the same. Background Art

[0002] The electrical contacts of a semiconductor device, such as, for example, a transistor or a diode, may need to be electrically connected to another component, such as, for example, a lead frame or a clip. For this purpose, the electrical contacts of the semiconductor device may include a metal stack. For example, such a metal stack may include stacked layers of titanium, aluminum, nickel-vanadium, and gold-tin. Metal stacks including gold-tin may be very expensive. In addition, the use of such a metal stack to provide an electrical connection may result in mechanical stresses that may occur in the semiconductor device after the electrical connection is formed. Manufacturers of semiconductor devices are constantly striving to improve their products and their manufacturing methods. It may therefore be desirable to develop a semiconductor device and an associated manufacturing method that provide an improved and cost-effective electrical connection between the semiconductor device and another component. Summary of the invention

[0003] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a silicon layer. The semiconductor device further includes a metal silicide layer disposed directly on the silicon layer. The semiconductor device further includes a solder layer disposed directly on the metal silicide layer.

[0004] Another aspect of the present disclosure relates to a method. The method includes forming a solder layer on a silicon layer, wherein the solder layer includes a silicide-forming metal. The method further includes forming a metal silicide layer between the silicon layer and the solder layer, wherein the metal silicide layer is formed by the silicide-forming metal of the solder layer and the silicon of the silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings are included to provide a further understanding of the various aspects and are incorporated into and constitute a part of this specification. The drawings illustrate the various aspects and together with the description are used to explain the principles of the various aspects. Other aspects and many intended advantages of the various aspects will be easily appreciated as they become better understood by reference to the detailed description below. The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals may designate corresponding similar parts.

[0006] Figure 1 A cross-sectional side view of a semiconductor device 100 according to the present disclosure is schematically illustrated.

[0007] Figure 2 includes Figure 2A to 2B , which schematically illustrates a cross-sectional side view of a method for fabricating a semiconductor device 200 according to the present disclosure.

[0008] Figure 3 includes Figures 3A to 3F , which schematically illustrates a cross-sectional side view of a method for fabricating a semiconductor device 300 according to the present disclosure.

[0009] Figure 4 A flow chart illustrating a method for manufacturing a semiconductor device according to the present disclosure is shown. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific aspects in which the present disclosure may be practiced, via illustration. In this regard, directional terms, such as "top," "bottom," "front," "back," and the like, may be used with reference to the orientation of the figures being described. Since the components of the described devices may be positioned in many different orientations, directional terms may be used for illustrative purposes and are by no means restrictive. Other aspects may be utilized, and structural or logical changes may be made without departing from the concept of the present disclosure. Therefore, the following detailed description should not be made in a restrictive sense, and the concept of the present disclosure is defined by the appended claims.

[0011] Figure 1 A cross-sectional side view of a semiconductor device 100 according to the present disclosure is schematically illustrated. The semiconductor device 100 is illustrated in a general manner to qualitatively specify aspects of the present disclosure. The semiconductor device 100 may include components that are not shown in the figure for simplicity. Figure 1 For example, the semiconductor device 100 may be expanded by combining any of the aspects described with other devices and methods according to the present disclosure.

[0012] The semiconductor device 100 includes a silicon layer 2. The semiconductor device 100 further includes a metal silicide layer 4 arranged on the silicon layer 2. In particular, the metal silicide layer 4 is directly arranged on the silicon layer 2. That is, the metal silicide layer 4 is at least partially in contact with the silicon layer 2. The semiconductor device 100 further includes a solder layer 6 arranged on the metal silicide layer 4. In particular, the solder layer 6 is directly arranged on the metal silicide layer 4. That is, the solder layer 6 is at least partially in contact with the metal silicide layer 4.

[0013] The silicon layer 2 may be part of a silicon wafer, a silicon chip, or a silicon die. The following comments about a wafer may also apply to a chip or a die, and vice versa. The silicon layer 2 may include an active device region of the semiconductor device 100. For example, the active device region may include a channel region of a field effect transistor, a base region of a bipolar transistor, a p / n junction of a diode, and the like.

[0014] The semiconductor device 100 can be soldered to a metal component (not shown) via the solder layer 6. Figure 1 ), where the metal silicide layer 4 can be at least partially formed during the welding process. In one example, the backside contact of the silicon chip can be welded to the die pad. In another example, the frontside contact of the silicon chip can be welded to the clip. For multiple chips, the welding process can be performed as a parallel batch process over the entire wafer area, or as sequential chip welding on each chip front side or back side.

[0015] The solder layer 6 may include an active solder material. In particular, the solder layer 6 may include a tin-silver solder alloy. The solder layer 6 may additionally include a silicide-forming metal and a rare earth metal, as will be explained in more detail later. The thickness of the solder layer 6 may, for example, be in the range from 20 microns to 80 microns, more particularly from 20 microns to 70 microns, more particularly from 30 microns to 80 microns, more particularly from 30 microns to 70 microns.

[0016] Arrangement according to the present disclosure can provide direct welding of the front side and / or back side of the chip to the metal component without the need for additional expensive metallization stacks arranged on the front side and / or back side of the chip. In this regard, the front side of the chip can be designated as the following side of the chip, on which an active device area can be formed. The metal silicide layer 4 can be conductive. An ohmic contact can be formed between the silicon material of the chip, i.e., the silicon layer 2 and the formed metal silicide layer 4. Therefore, the use of the metallization stack as an electrical contact may be old-fashioned. The metal silicide layer 4 can be particularly free of gaps and can provide a mechanically stable connection between the chip and the metal component. The solder connection can show reduced mechanical stress compared to conventional solder connections using metallization stacks. Thus, the risk of horizontal chip cracking can be significantly reduced. In addition, because the metallization stack is no longer needed to form an electrical connection, the delamination of the metallization stack at the edge of the chip during or after mechanical dicing and the formation of metal burrs can be avoided.

[0017] According to one embodiment, the solder layer 6 may include a silicide-forming metal corresponding to the metal of the metal silicide layer 4. The silicide-forming metal used to form the metal silicide layer 4 may be provided by silicide-forming metal atoms of the solder layer 6.

[0018] According to one embodiment, the metal silicide layer 4 may include at least one of the following: titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten silicide, molybdenum silicide, zirconium silicide and tantalum silicide. Therefore, the metal forming the silicide of the solder layer 6 may include at least one of the following: titanium, platinum, cobalt, nickel, tungsten, molybdenum, zirconium, and tantalum. More generally, the solder layer 6 may include any transition metal, which is configured to form a metal silicide in combination with silicon. Tantalum silicide may include, for example, TiSi2 and / or TiSi and / or Ti5Si3 or may be composed of, for example, TiSi2 and / or TiSi and / or Ti5Si3. Platinum silicide may include, for example, PtSi or may be composed of, for example, PtSi. Cobalt silicide may include, for example, Co2Si and / or CoSi and / or CoSi2 or may be composed of, for example, Co2Si and / or CoSi and / or CoSi2. Nickel silicide may include NiSi and / or NiSi2 or may be composed of NiSi and / or NiSi2. Tungsten silicide may include, for example, WSi2 or may consist of, for example, WSi2. Molybdenum silicide may include, for example, MoSi2 or may consist of, for example, MoSi2. Zirconium silicide may include, for example, Zr2Si or may consist of, for example, Zr2Si. Tantalum silicide may include, for example, TaSi2 or may consist of, for example, TaSi2.

[0019] According to one embodiment, the metal silicide layer 4 may include Me x Si y , wherein the abbreviation "Me" represents the metal of the metal silicide layer 4. Here, x can have a value of 1, 2 or 5. In addition, y can have a value of 1, 2 or 3. In one example, the metal can be titanium, i.e. Me=Ti. In this case, the following stable chemical compounds or silicides can be possible: Ti5Si3 (x=5, y=3); TiSi (x=1, y=1); and TiSi2 (x=1, y=2). In another example, the metal can be cobalt, i.e. Me=Co. In this case, the following stable chemical compounds or silicides can be possible: Co2Si(x=2, y=1); CoSi (x=1, y=1); and CoSi2 (x=1, y=2).

[0020] According to one embodiment, the solder layer 6 may include a rare earth metal. The technical purpose of the rare earth metal during the formation of the metal silicide layer 4 is specified in more detail below.

[0021] According to one embodiment, the rare earth metal may include at least one of cerium, scandium, lanthanum, praseodymium, promethium, neodymium, samarium, and europium.

[0022] According to one embodiment, the thickness of the metal silicide layer 4 may be in the range of 100 nanometers to 1000 nanometers. More particularly, the thickness of the metal silicide layer 4 may be in the range of 100 nanometers to 800 nanometers, more particularly 100 nanometers to 600 nanometers, more particularly 100 nanometers to 400 nanometers, more particularly 100 nanometers to 200 nanometers.

[0023] According to one embodiment, the semiconductor device 100 may further include an ohmic contact formed between the silicon layer 2 and the metal silicide layer 4. In particular, the ohmic contact may provide a resistance with linear ohmic electrical properties. The ohmic contact may be formed during the formation of the metal silicide layer 4. Such formation will be specified in more detail later. The formation of the metal silicide layer 4 may be adjusted to form an ohmic contact with a resistance that is sufficiently low for a desired semiconductor application, such as, for example, a power MOSFET (metal oxide semiconductor field effect transistor), a power IGBT (insulated gate bipolar transistor), a power diode or a super junction power MOSFET.

[0024] According to one embodiment, the semiconductor device 100 may further include a solder layer 6 and a metal component (not Figure 1 The solder contacts formed between the Figure 1 ). The metal component may include at least one of the following: a lead frame, a die pad, a lead (or pin), a clip, and a metal foil. The metal component may be made of metal and / or associated metal alloys, such as copper, nickel, aluminum, stainless steel, etc. For example, the metal component may be configured to provide electrical connection between internal circuits or active device areas of the semiconductor device 100 and external components.

[0025] According to one embodiment, the silicon layer 2 may be part of a silicon transistor or a silicon diode. In particular, the silicon transistor may be a power MOSFET (metal oxide semiconductor field effect transistor), a power IGBT (insulated gate bipolar transistor) or a super junction power MOSFET. In particular, the silicon diode may be a power diode. The active device region of the transistor or diode may be formed in the silicon layer 2 of the semiconductor device 100.

[0026] Figure 2 includes Figure 2A to 2B , which schematically illustrates a cross-sectional side view of a method for manufacturing a semiconductor device 200 according to the present disclosure. The manufactured semiconductor device 200 may be similar to Figure 1The method of FIG. 2 is illustrated in a general manner in order to qualitatively specify various aspects of the present disclosure. The method may include additional aspects that are not illustrated in FIG. 2 for simplicity. For example, the method may be extended by combining any of the aspects described with other methods and devices according to the present disclosure.

[0027] exist Figure 2A In the embodiment of the present invention, a solder layer 6 is formed on the silicon layer 2. The solder layer 6 includes a metal 8 that forms silicide.

[0028] exist Figure 2B In the embodiment, the metal silicide layer 4 is formed between the silicon layer 2 and the solder layer 6. The metal silicide layer 4 is formed by the silicide-forming metal 8 of the solder layer 6 and the silicon of the silicon layer 2.

[0029] According to one embodiment, the method of Fig. 2 may further include an action for forming a solder contact between the solder layer 6 and a metal component (not illustrated in Fig. 2). For example, a silicon wafer or silicon chip including the silicon layer 2 may be soldered to the metal component via the solder layer 6. The metal component may be, for example, a lead frame, a die pad, leads (or pins), a clip, and a metal foil.

[0030] According to one embodiment, the solder contact may be formed in a temperature range from 150° C. to 500° C. More particularly, the solder contact may be formed in a temperature range from 150° C. to 400° C., more particularly from 200° C. to 500° C., more particularly from 200° C. to 400° C.

[0031] According to one embodiment, the metal silicide layer 4 may be formed at least in part by forming a solder contact. During the soldering process, the metal silicide layer 4 may be formed at least in part by the silicide-forming metal 8 of the solder layer 6 and the silicon of the silicon layer 2. The silicide-forming metal atoms of the solder layer 6 may diffuse to the reaction surface and react with the silicon of the silicon layer 2 to form the metal silicide layer 4.

[0032] According to one embodiment, the metal silicide layer 4 may be formed at least in part by forming a solder layer 6 on the silicon layer 2. When the solder layer 6 may be applied to the silicon layer 2, a portion of the metal silicide layer 4 may be formed before forming the solder contact. The silicide-forming metal atoms 8 in the solder layer 6 may diffuse to the reaction surface between the solder layer 6 and the silicon layer 2 and react with the silicon atoms of the silicon layer 2 to form metal silicide molecules.

[0033] According to one embodiment, the action for forming the solder layer 6 on the silicon layer 2 may include the action of etching the surface of the silicon layer 2. By etching the surface, the unevenness or roughness of the surface can be removed so that a smooth surface of the silicon layer 2 can be obtained. The ohmic contact between the silicon layer 2 and the metal silicide layer 4 can be appropriately formed on such a smooth surface of the silicon layer 2. In particular, a smooth surface can be obtained by applying a wet chemical etching process. It should be noted that the metal silicide layer 4 and the ohmic contact between the silicon layer 2 and the metal silicide layer 4 can also be formed on a rougher surface. Such a rougher surface can be obtained, for example, after the silicon layer 2 may have been thinned by a grinding process. The action for forming the solder layer 6 on the silicon layer 2 may further include an action for forming the solder layer 6 on the etched surface of the silicon layer 2.

[0034] According to one embodiment, after forming the metal silicide layer 4, the solder layer 6 may include a residual portion of the silicide-forming metal 8. The silicide-forming metal 8 of the solder layer 6 may not be completely used to form the metal silicide layer 4, so that the residual portion of the silicide-forming metal 8 may remain in the solder layer 6. For example, at a point in time when the metal silicide layer 4 may have been formed to a certain extent or thickness, the metal silicide layer 4 may form a barrier through which the atoms of the silicide-forming metal 8 cannot further pass. The atoms of the silicide-forming metal 8 can thus no longer reach the reaction surface at the silicon layer 2, so that metal silicide molecules can no longer be formed by the silicon atoms of the silicon layer 2 and the silicide-forming atoms 8 of the solder layer 6.

[0035] According to one embodiment, before forming the metal silicide layer 4, the solder layer 6 may include a rare earth metal. The rare earth metal may include at least one of the following: cerium, scandium, lanthanum, praseodymium, promethium, neodymium, samarium and europium. The radius of the rare earth metal atom may be particularly smaller than the radius of the metal silicide-forming atom 8 in the solder layer 6. When the metal silicide layer 4 is formed at the reaction surface between the solder layer 6 and the silicon layer 2, the rare earth metal atom may therefore diffuse to the reaction surface faster than the atom of the metal 8 forming the silicide. At the reaction surface, before the metal atom 8 forming the silicide can reach the reaction surface, the rare earth metal atom may react with oxygen (if present). Therefore, the metal atom 8 forming the silicide that reaches the reaction surface may react with the silicon of the silicon layer 2 (rather than with oxygen), so that the metal silicide layer 4 may be properly formed. If the amount of the rare earth metal atom in the solder layer 6 is too small, not all oxygen may be combined by the rare earth metal. In this case, the formed metal silicide layer 4 may be at least partially oxidized.

[0036] According to one embodiment, the solder layer 6 may include residual portions of the rare earth metal after forming the metal silicide layer 4. As previously described, the at least partially formed metal silicide layer 4 may form a barrier through which certain atomic types may not pass. As a result, atoms of the rare earth metal may no longer reach the reaction surface at the silicon layer 2, so that the residual portions of the rare earth metal may remain in the solder layer 6.

[0037] According to one embodiment, the thickness of the solder layer 6 may be in the range of 20 to 80 microns before forming the metal silicide layer 4. More particularly, the thickness may be in the range of 20 to 70 microns, more particularly 30 to 80 microns, more particularly 30 to 70 microns.

[0038] Figure 3 includes Figures 3A to 3F , which schematically illustrates a cross-sectional side view of a method for manufacturing a semiconductor device 300 according to the present disclosure. The manufactured semiconductor device 300 can be regarded as Figure 1 In addition, the method of FIG3 can be regarded as a more detailed implementation of the method of FIG2 .

[0039] exist Figure 3A In the embodiment of the present invention, a silicon wafer 10 including a silicon layer can be mounted on a temporary carrier 12. The silicon wafer 10 can include multiple active device regions. In one example, the silicon wafer 10 can be a silicon transistor wafer, i.e., a wafer in which multiple transistor structures can be formed. In another example, the silicon wafer 10 can be a silicon diode wafer, i.e., a wafer in which multiple diode structures can be formed. The silicon wafer 10 including multiple device regions can be separated into multiple semiconductor devices, such as multiple silicon transistors or multiple silicon diodes later.

[0040] exist Figure 3B In the embodiment of the present invention, the back side 14 of the silicon wafer 10 can be thinned. In one example, a wet chemical etching process can be applied to the surface of the back side 14. The unevenness or roughness of the back side 14 can thus be removed so that a smooth surface of the silicon wafer 10 can be obtained. An ohmic contact can be appropriately formed later on such a smooth surface of the silicon wafer 10. In a further example, the silicon wafer 10 can be thinned by applying a grinding process. Here, a rougher surface can be obtained compared to the specified wet chemical etching process. In yet another example, the thinning of the silicon wafer 10 can include a combination of the described actions, wherein the action of providing a rough surface can be applied first, and the action of providing a smooth surface can then be applied.

[0041] exist Figure 3CIn the embodiment, the silicon wafer 10 may be mounted on a tape and (&) frame 16. In addition, the temporary carrier 12 may be removed from the silicon wafer 10 (see arrow).

[0042] exist Figure 3D In the embodiment of the present invention, dicing through the silicon wafer 10 can be performed, wherein the silicon wafer 10 can be separated into a plurality of silicon chips (or dies) 18. In one example, the silicon chip 18 can be a silicon transistor chip. In another example, the silicon chip 18 can be a silicon diode chip. Figure 3D The dicing process may correspond to a plasma dicing process, an ultrasonic mechanical dicing process, a laser dicing process, or a combination thereof. The plasma dicing process may include a plasma etching process using FCl3, Ar, O2 and / or CF6 plasma.

[0043] exist Figure 3E In the embodiment of the present invention, silicon chips 18 may be picked up from the tape and frame 16 by a pick-up tool 20 (see arrow). For example, the pick-up tool 20 may be or may include a vacuum chuck. The actions of 3E may be performed in the back end of a chip manufacturer or a subcontractor.

[0044] exist Figure 3F In FIG. 1 , the silicon chip 18 may be attached to the metal component 22. Figure 3F In the example of, the metal component 22 can be a lead frame, which can be made of copper, for example. In another example, the metal component 22 can correspond to at least one of a die pad, a lead, a clip, and a metal foil. In particular, the back side 24 of the silicon chip 18 can be soldered to the metal component 22 via a solder layer 6. The solder layer 6 can be provided in various ways before the soldering process. In a first example, the solder layer 6 can be deposited on the back side 24 of the silicon chip 18. In this regard, before one or more drops of solder material can be deposited on the back side 24 of the silicon chip 18, the silicon chip 18 can be optionally heated. In a second example, the solder layer 6 can be deposited on the following surface of the metal component 22, to which the silicon chip 18 should be soldered. In this regard, before one or more drops of solder material can be deposited on the metal component 22 at the following position, the metal component 22 can be optionally heated, where the silicon chip 18 should be soldered. After the described deposition of the solder material on the back side 24 of the silicon chip 18 and / or on the metal component 22, the silicon chip 18 can be pressed against the metal component 22, wherein the solder material 6 is arranged in the middle. Note that soldering the silicon chip 18 to the metal component 22 can be performed by additionally pressing the silicon chip 18 against the metal component 22 and / or increasing the temperature at the reaction surface. Additional pressure can be provided, for example, by the weight of the silicon chip 18 pressing against the metal component 22.

[0045] exist Figure 3FIn the example of , the solder layer 6 may, for example, include an active tin-silver solder alloy. In addition, the solder layer 6 may include a silicide-forming metal 8 (see “Me”) and a rare earth metal 26 (see “REM”). Figure 3F In the example of , the metal 8 forming the silicide may specifically include titanium. In a further example, the metal 8 forming the silicide may also include another transition metal, which is configured in combination with silicon to form a metal silicide, such as at least one of platinum, cobalt, nickel, tungsten, molybdenum, zirconium, tantalum. Figure 3F In an example of , the rare earth metal 26 may specifically include cerium. In a further example, the rare earth metal 26 may also include at least one of the following: scandium, lanthanum, praseodymium, promethium, neodymium, samarium, and europium.

[0046] When the silicon chip 18 is soldered to the metal component 22, the metal silicide layer 4 may be at least partially formed between the silicon chip 18 and the solder layer 6. Figure 3F In the example of , the metal silicide layer 4 may in particular include titanium silicide. The metal silicide layer 4 may be formed by the silicide-forming metal 8 of the solder layer 6 and the silicon of the silicon chip 18. It should be noted that when the solder layer 6 may be applied to the back side 24 of the silicon chip 18, a portion of the metal silicide layer 4 may be formed before the welding process. The rare earth metal 26 of the solder layer 6 may be configured to react with (ambient) oxygen during the welding process and / or during the application of the solder layer 6 to the silicon chip 18, so that oxidation of the metal silicide layer 4 may be avoided. During the welding process, an ohmic contact may be formed between the silicon material of the silicon chip 18 and the formed metal silicide layer 4. The active device area of ​​the silicon chip 18 may thus be electrically connected to the metal component 22 via the formed ohmic contact and the conductive metal silicide layer 4.

[0047] The method of FIG. 3 may include additional actions that are not further specified in detail for the sake of simplicity. For example, an additional metal component (not illustrated in FIG. 3 ) may be attached to, for example, the front side 28 of the silicon chip 18. In particular, the additional metal component may be soldered to the silicon chip 18 via an additional solder layer. Similar to the soldering described previously, an additional metal silicide layer may be formed between the additional solder layer and the silicon chip 18. The additional metal component may include at least one of the following: a lead frame, a die pad, a lead, a clip, a metal foil. Figure 3F The action can be applied to Figure 3E Another silicon chip obtained in the action.

[0048] Figure 4 A flow chart illustrating a method for manufacturing a semiconductor device according to the present disclosure is shown. The method may be similar to the method of FIG. 2 and may be read in conjunction with the method of FIG. 2 .

[0049] At 30, a solder layer is formed on the silicon layer, wherein the solder layer includes a silicide-forming metal. At 32, a metal silicide layer is formed between the silicon layer and the solder layer. The metal silicide layer is formed by the silicide-forming metal of the solder layer and the silicon of the silicon layer.

[0050] Example

[0051] Hereinafter, a semiconductor device including a metal silicide layer and a method for manufacturing such a semiconductor device will be explained by way of examples.

[0052] Example 1 is a semiconductor device including: a silicon layer; a metal silicide layer disposed directly on the silicon layer; and a solder layer disposed directly on the metal silicide layer.

[0053] Example 2 is the semiconductor device according to Example 1, wherein the solder layer includes a silicide-forming metal corresponding to the metal of the metal silicide layer.

[0054] Example 3 is a semiconductor device according to Example 1 or 2, wherein the metal silicide layer includes at least one of titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten silicide, molybdenum silicide, zirconium silicide, and tantalum silicide.

[0055] Example 4 is a semiconductor device according to one of the preceding examples, wherein the metal silicide layer includes Me x Si y , where x has the value 1, 2, or 5, and where y has the value 1, 2, or 3.

[0056] Example 5 is a semiconductor device according to one of the preceding examples, wherein the solder layer includes a rare earth metal.

[0057] Example 6 is a semiconductor device according to Example 5, wherein the rare earth metal includes at least one of cerium, scandium, lanthanum, praseodymium, promethium, neodymium, samarium, and europium.

[0058] Example 7 is a semiconductor device according to one of the preceding examples, wherein a thickness of the metal silicide layer is in a range from 100 nanometers to 1000 nanometers.

[0059] Example 8 is a semiconductor device according to one of the preceding examples, further comprising an ohmic contact formed between the silicon layer and the metal silicide layer.

[0060] Example 9 is a semiconductor device according to one of the preceding examples, further comprising a solder contact formed between the solder layer and a metal component, wherein the metal component comprises at least one of the following: a lead frame, a die pad, a lead, a clip, a metal foil.

[0061] Example 10 is a semiconductor device according to one of the preceding examples, wherein the silicon layer is part of a silicon transistor or a silicon diode.

[0062] Example 11 is a method comprising: forming a solder layer on a silicon layer, wherein the solder layer includes a silicide-forming metal; and forming a metal silicide layer between the silicon layer and the solder layer, wherein the metal silicide layer is formed by the silicide-forming metal of the solder layer and the silicon of the silicon layer.

[0063] Example 12 is the method of Example 11, further comprising: forming a solder contact between the solder layer and the metal component.

[0064] Example 13 is the method of Example 12, wherein the solder contact is formed in a temperature range from 150°C to 500°C.

[0065] Example 14 is the method of one of Examples 12 or 13, wherein the metal silicide layer is formed at least in part by forming a solder contact.

[0066] Example 15 is the method according to one of Examples 11 to 14, wherein the metal silicide layer is formed at least in part by forming a solder layer on the silicon layer.

[0067] Example 16 is a method according to one of Examples 11 to 15, wherein forming a solder layer on the silicon layer comprises: etching a surface of the silicon layer; and forming the solder layer on the etched surface of the silicon layer.

[0068] Example 17 is the method according to one of Examples 11 to 16, wherein after forming the metal silicide layer, the solder layer includes a residual portion of the silicide-forming metal.

[0069] Example 18 is the method according to one of Examples 11 to 17, wherein before forming the metal silicide layer, the solder layer includes a rare earth metal.

[0070] Example 19 is the method according to one of Examples 11 to 18, wherein after forming the metal silicide layer, the solder layer includes a residual portion of the rare earth metal.

[0071] Example 20 is the method according to one of Examples 11 to 19, wherein before forming the metal silicide layer, the thickness of the solder layer is in a range from 20 micrometers to 80 micrometers.

[0072] As used in this specification, the terms "connected", "coupled", "electrically connected" and / or "electrically coupled" may not necessarily mean that elements must be directly connected or coupled together. Intermediate elements may be provided between the elements that are "connected", "coupled", "electrically connected" or "electrically coupled".

[0073] In addition, the word "on" used in relation to, for example, a material layer formed on or located "on" a surface of an object may be used herein to mean that the material layer may be "directly" located (e.g., formed, deposited, etc.) on the implied surface, e.g., in direct contact with the implied surface. The word "on" used in relation to, for example, a material layer formed on or located "on" a surface may also be used herein to mean that the material layer may be "indirectly" located (e.g., formed, deposited, etc.) on the implied surface, with, for example, one or more additional layers disposed between the implied surface and the material layer.

[0074] Furthermore, to the extent that the terms "have," "include," "comprises," "with," or variations thereof are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising." That is, as used herein, the terms "have," "includes," "includes," "with," "including," and the like are opening terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0075] In addition, the word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any aspect or design described herein as "exemplary" should not necessarily be interpreted as advantageous over other aspects or designs. On the contrary, the use of the word "exemplary" is intended to present concepts in a concrete way. As used in this application, the term "or" is intended to mean inclusive "or" rather than exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any one of the natural inclusive arrangements. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied under any of the aforementioned examples. In addition, the articles "one" and "an" as used in this application and the appended claims can be generally interpreted to mean "one or more", unless otherwise specified or clear from the context to point to the singular form. Moreover, at least one of A and B, etc. generally means A or B or both A and B.

[0076] Devices and methods for making devices are described herein. Notes made in conjunction with the described devices may also apply to the corresponding methods and vice versa. For example, if a particular component of a device is described, the corresponding method for making the device may include actions for providing the component in a suitable manner, even if such actions are not explicitly described or illustrated in the figures. In addition, the features of the various exemplary aspects described herein may be combined with each other unless otherwise specifically noted.

[0077] Although the disclosure has been shown and described with respect to one or more implementations, other persons skilled in the art will think of equivalent changes and modifications, based at least in part on the reading and understanding of this specification and the accompanying drawings. The disclosure includes all such modifications and changes and is limited only by the concepts of the subsequent claims. In particular, with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, the terms used to describe such components are intended to correspond to any component that performs the specified functions (e.g., functionally equivalent) of the described components unless otherwise indicated, although the component is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementations described herein of the disclosure. In addition, although specific features of the disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous for any given or specific application.

Claims

1. A semiconductor device, comprising: Silicon layer (2); a metal silicide layer (4) disposed directly on the silicon layer (2); as well as a solder layer (6) arranged directly on the metal silicide layer (4), wherein the solder layer (6) comprises a silicide-forming metal (8) corresponding to the metal of the metal silicide layer (4), The solder layer (6) comprises a tin-silver solder alloy.

2. The semiconductor device according to claim 1, wherein the metal silicide layer (4) comprises at least one of the following: titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten silicide, molybdenum silicide, zirconium silicide and tantalum silicide.

3. The semiconductor device according to claim 1 , wherein the metal silicide layer (4) comprises Me x Si y , where x has the value 1, 2, or 5, and where y has the value 1, 2, or 3.

4. The semiconductor device according to one of the preceding claims, wherein the solder layer (6) comprises a rare earth metal (26).

5. The semiconductor device of claim 4, wherein the rare earth metal (26) comprises at least one of the following: cerium, scandium, lanthanum, praseodymium, promethium, neodymium, samarium, and europium.

6. The semiconductor device according to claim 1, wherein the thickness of the metal silicide layer (4) lies in the range from 100 nanometers to 1000 nanometers.

7. The semiconductor device according to claim 1, further comprising: An ohmic contact is formed between the silicon layer (2) and the metal silicide layer (4).

8. The semiconductor device according to claim 1, further comprising: A solder contact is formed between the solder layer (6) and a metal component (22), wherein the metal component (22) comprises at least one of the following: a lead frame, a die pad, a lead, a clip, a metal foil.

9. The semiconductor device according to one of the preceding claims, wherein the silicon layer (2) is part of a silicon transistor or a silicon diode.

10. A method comprising: forming a solder layer (6) on the silicon layer (2), wherein the solder layer (6) includes a silicide-forming metal (8); as well as A metal silicide layer (4) is formed between the silicon layer (2) and the solder layer (6), wherein the metal silicide layer (4) is formed by a silicide-forming metal (8) of the solder layer (6) and silicon of the silicon layer (2). The solder layer (6) comprises a tin-silver solder alloy.

11. The method according to claim 10, further comprising: A solder contact is formed between the solder layer (6) and the metal component (22).

12. The method of claim 11, wherein the solder contact is formed in a temperature range from 150°C to 500°C.

13. The method according to one of claims 11 or 12, wherein the metal silicide layer (4) is formed at least partially by forming the solder contact.

14. The method according to any one of claims 10 to 13, wherein the metal silicide layer (4) is formed at least partially by forming the solder layer (6) on the silicon layer (2).

15. The method according to any one of claims 10 to 14, wherein forming the solder layer (6) on the silicon layer (2) comprises: Etching the surface of the silicon layer (2); as well as The solder layer (6) is formed on the etched surface of the silicon layer (2).

16. The method according to any one of claims 10 to 15, wherein after forming the metal silicide layer (4), the solder layer (6) comprises remnants of the silicide-forming metal (8).

17. The method according to any one of claims 10 to 16, wherein the solder layer (6) comprises a rare earth metal (26) before forming the metal silicide layer (4).

18. The method according to any one of claims 10 to 17, wherein after forming the metal silicide layer (4), the solder layer (6) comprises a remnant of the rare earth metal (26).

19. The method according to any one of claims 10 to 18, wherein before forming the metal silicide layer (4), the thickness of the solder layer (6) is in the range from 20 micrometers to 80 micrometers.

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