Power semiconductor device

Abstract

A power semiconductor device is presented, comprising: a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, the front side structure defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device, wherein the front side structure exhibits a first lateral edge portion, a second lateral edge portion and a first corner portion forming a transition between the first lateral edge portion and the second lateral edge portion; a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current; and a back side emitter region arranged in the semiconductor body in contact with the second load terminal.

Description

TECHNICAL FIELD

[0001] The present specification relates to embodiments of a power semiconductor device. In particular, the present specification relates to embodiments of a power semiconductor device, such as a diode or an IGBT, having a front structure defining a front active area, wherein the front structure exhibits a corner. BACKGROUND

[0002] Many functions of modern devices in automotive applications, consumer applications and industrial applications, such as converting electrical energy and driving electric motors or electrical machines, rely on power semiconductor devices. For example, just to name a few, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body, which can be configured to conduct a load current along a load current path between two load terminals of the device. Further, the load current path can be controlled by means of an insulating electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device in one of a conducting state and a blocking state.

[0004] Further, for conducting the load current, the power semiconductor device can comprise a front structure, which can define a so-called front active area of the power semiconductor device. For example, the front structure can comprise one or more power cells, such as IGBT cells, or an anode region of a power diode. Such a front structure can exhibit one or more corner portions, which form a transition between respective lateral edge portions of the front structure. Further, a drift region and a back emitter region can be provided inside the semiconductor body of the power semiconductor device, wherein the back emitter region can comprise a dopant at a higher dopant concentration than the drift region. For example, the back emitter region can be configured for injecting charge carriers into the drift region in a conducting state of the power semiconductor device. The drift region can comprise a field stop region, which has a higher dopant concentration than a drift region portion outside the field stop region.

[0005] It is a general aim to increase the dynamic robustness of such power semiconductor devices, such as during turn-off. For example, it is thus generally desirable to reduce the charge carrier density near the edge portions in order to limit dynamic avalanches and / or to avoid latch-up. At the same time, it should be avoided that measures for increasing the robustness are at the cost of a significant increase in on-state losses, for example due to a smaller back active area, i.e. a back emitter in case of an IGBT or a cathode region in case of a diode. SUMMARY

[0006] According to an embodiment, the power semiconductor device comprises a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, the front side structure defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device, wherein the front side structure exhibits a first lateral edge portion, a second lateral edge portion, and a first corner portion forming a transition between the first lateral edge portion and the second lateral edge portion; a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current; and a back side emitter region arranged in the semiconductor body in contact with the second load terminal, the emitter region having a net dopant concentration higher than a net dopant concentration of the drift region. In a vertical projection, the back side emitter region laterally terminates at a first distance from the first lateral edge portion and / or the second lateral edge portion and at a second distance from the first corner portion, wherein the second distance is greater than the first distance.

[0007] According to another embodiment, a power semiconductor device comprises a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, wherein the front side structure is a cell field comprising a plurality of IGBT cells, thereby defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device. The front side structure exhibits a recess defining a pad area provided for arranging a contact pad at the front side, a third lateral edge portion extending next to the pad area, a fourth lateral edge portion extending next to the pad area, and a second corner portion forming a transition between the third lateral edge portion and the fourth lateral edge portion; the power semiconductor device further comprises a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current; and a back side emitter region arranged in the semiconductor body in contact with the second load terminal, the emitter region having a net dopant concentration higher than a net dopant concentration of the drift region. In a vertical projection, an overlap of the pad area and the back side emitter region laterally terminates at a third distance from the third lateral edge portion and / or the fourth lateral edge portion and at a fourth distance from the second corner portion, wherein the fourth distance is greater than the third distance.

[0008] According to another embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, the front side structure defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device, wherein the front side structure exhibits a first lateral edge portion, a second lateral edge portion, and a first corner portion forming a transition between the first lateral edge portion and the second lateral edge portion; a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current; and a field stop region comprised in the drift region and having a dopant of the first conductivity type at a higher dopant concentration than the drift region outside the field stop region. The field stop region comprises an inner region and an outer region, the outer region being arranged closer to the first lateral edge portion, the second lateral edge portion, and the first corner portion than the inner region and having a dopant of the first conductivity type at a higher dopant concentration than the inner region. In a vicinity of the first corner portion, the outer region extends further into the front side active area than in a vicinity of each of the first lateral edge portion and the second lateral edge portion.

[0009] According to another embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, the front side structure defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device, wherein the front side structure exhibits a first lateral edge portion, a second lateral edge portion, and a first corner portion forming a transition between the first lateral edge portion and the second lateral edge portion; a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current; and a field stop region comprised in the drift region and having a dopant of the first conductivity type at a higher dopant concentration than the drift region outside the field stop region. The field stop region comprises an inner region and an outer region, the outer region being arranged closer to the first lateral edge portion, the second lateral edge portion, and the first corner portion than the inner region and having a dopant of the first conductivity type at a lower dopant concentration than the inner region. In a vicinity of the first corner portion, the outer region extends further into the front side active area than in a vicinity of each of the first lateral edge portion and the second lateral edge portion.

[0010] According to another embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; a front side structure arranged at the front side and at least partially comprised in the semiconductor body, the front side structure defining a front side active area configured for conducting a load current between the first load terminal structure and the second load terminal structure in an on state of the power semiconductor device, wherein the front side structure exhibits a first lateral edge portion, a second lateral edge portion, and a first corner portion forming a transition between the first lateral edge portion and the second lateral edge portion; and a drift region of a first conductivity type comprised in the semiconductor body and configured for carrying the load current. A lifetime of charge carriers in the drift region is shorter in a vicinity of the first corner portion than in a vicinity of each of the first lateral edge portion and the second lateral edge portion.

[0011] According to yet another embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure and a back side coupled to a second load terminal structure; and a front side structure arranged at the front side and at least partially comprised in the semiconductor body. The front side structure comprises: an active cell field comprising a plurality of IGBT cells each comprising a source region of a first conductivity type and a body region of a second conductivity type complementary to the first conductivity type; and a drainage structure comprising a plurality of drainage cells each comprising a drainage region of the second conductivity type arranged in contact with the first load terminal structure. Each drainage cell does not comprise a source region of the first conductivity type arranged in contact with the first load terminal structure. The drainage structure is arranged laterally between the active cell field and an edge termination region of the semiconductor device and exhibits a first outer edge portion, a second outer edge portion, and an outer corner portion forming a transition between the first outer edge portion and the second outer edge portion. A minimum distance between the active cell field and the outer corner portion is greater than a minimum distance between the active cell field and each of the first outer edge portion and the second outer edge portion.

[0012] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0013] Portions of the accompanying drawings will be understood to those skilled in the art upon reading the following detailed description, and upon viewing the accompanying drawings.

[0014] Figure 1AA section of a vertical cross-section (A-A) of the power semiconductor device of

[0015] Figure 1B A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 1A

[0016] Figure 1C A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 1A

[0017] Figure 2A A section of a vertical cross-section (A-A) of the power semiconductor device of

[0018] Figure 2B A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 2A

[0019] Figure 3A A section of a vertical cross-section (A-A) of the power semiconductor device of

[0020] Figure 3B A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 3A

[0021] Figure 3C A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 3A

[0022] A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 4A

[0023] A section of a vertical cross-section (A-A) of the power semiconductor device of Figure 4B Figure 4A A section of a vertical cross-section (A-A) of the power semiconductor device of

[0024] Figure 5A A section of a vertical cross-section (A-A) of the power semiconductor device of

[0025] Figure 5B Figure 5A A section of a vertical cross-section (A-A) of the power semiconductor device of

[0026] Figure 5C A section of a vertical cross-section (A-A) of the power semiconductor device of​​​​​​Figure 5A Another vertical cross-section (BB) segment of the power semiconductor device;

[0027] Figure 5D yes Figure 5B An enlarged view of a section of the vertical cross-section;

[0028] Figure 5E yes Figure 5C An enlarged view of a section of the vertical cross-section;

[0029] Figure 6A A segment of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0030] Figure 6B The illustration is schematic and exemplary. Figure 6A A segment of the vertical cross-section (AA) of a power semiconductor device;

[0031] Figure 6C The illustration is schematic and exemplary. Figure 6A Another vertical cross-section (BB) segment of the power semiconductor device;

[0032] Figure 7A A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is schematically and exemplaryly illustrated; and

[0033] Figure 7B The illustration is schematic and exemplary. Figure 7A Another vertical cross-section of the power semiconductor device. Detailed Implementation

[0034] In the following detailed description, reference is made to the accompanying drawings, which form a part of the invention, and specific embodiments in which the invention may be practiced are illustrated.

[0035] In this regard, directional terms such as “top,” “bottom,” “lower,” “front,” “rear,” “back,” “head,” “tail,” “lower,” and “upper” can be used with reference to the orientation of the described drawings. Because the various parts of the embodiments can be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0036] Reference will now be made in detail to the various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the application and is not meant as a restriction of the application. For example, features illustrated or described as part of one embodiment, can be used with another embodiment to yield still a further embodiment. It is intended that the present application include such modifications and variations. Specific language is used to describe the examples, but the intent is to convey that the application includes alternative language and formulations. The figures are not drawn to scale, and are merely used to illustrate the principles of the application. For the sake of clarity, identical reference numerals have been used in the different figures to denote identical elements or steps, if any.

[0037] The term "horizontal" as used in this specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This can be, for example, a surface of a semiconductor wafer or die. For example, the first lateral direction X and the second lateral direction Y mentioned below can both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0038] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface, i.e. parallel to a normal direction of a surface of a semiconductor wafer. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0039] In this specification, n-doping is referred to as "first conductivity type" and p-doping is referred to as "second conductivity type". Alternatively, an opposite doping relationship can be employed, such that the first conductivity type can be p-doping and the second conductivity type can be n-doping.

[0040] Further, in this specification, the term "dopant concentration" can refer to an average dopant concentration, or, respectively, to a mean dopant concentration or a sheet charge carrier concentration of a particular semiconductor region or semiconductor zone. Thus, for example, a statement indicating that a particular semiconductor region exhibits a certain dopant concentration that is higher or lower compared to a dopant concentration of another semiconductor region can indicate that the respective average or mean dopant concentrations of the semiconductor regions differ from each other. For example, the average dopant concentration can be determined by averaging the dopant concentration over a volume that is defined by a diffusion length of free charge carriers in the respective semiconductor region or semiconductor zone. For example, this volume can be a cube, wherein the edges of the cube are given by the diffusion length, or can be a sphere, wherein the diameter of the sphere is given by the diffusion length. Alternatively, the averaging can be performed over a given volume, such as a cube or a sphere, that is given by a vertical thickness of a drift region of the semiconductor device.

[0041] In the context of the present specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or low-ohmic current path between two regions, segments, areas, parts or components of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode of a semiconductor device and a part or component of the semiconductor device. Furthermore, in the context of the present specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device, e.g. a transition between two elements that are in direct contact with each other can not include further intermediate elements, etc.

[0042] Furthermore, in the context of the present specification, the term "electrically insulated" is used in the context of its general effective understanding and thus is intended to describe that two or more components are positioned separated from each other and that there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, e.g. mechanically and / or capacitively and / or inductively. For example, two electrodes of a capacitor can be electrically insulated from each other and at the same time be mechanically and capacitively coupled to each other, e.g. by means of an insulator, e.g. a dielectric.

[0043] The specific embodiments described in the present specification are related to, but not limited to, the following: a power semiconductor device, such as a power semiconductor transistor, exhibiting a bar cell configuration or a pin cell configuration, which can be used within a power converter or power supply. Thus, in embodiments, the semiconductor device is configured to carry a load current to be fed to a load and / or provided by a power source, respectively. For example, the semiconductor device can comprise one or more active power unit cells, such as monolithically integrated diode cells, and / or monolithically integrated transistor cells, and / or monolithically integrated IGBT cells, and / or monolithically integrated RC-IGBT cells, and / or monolithically integrated MOS gated diode (MGD) cells, and / or monolithically integrated MOSFET cells and / or derivatives thereof. Such diode cells and / or such transistor cells can be integrated in a power semiconductor module. A plurality of such cells can constitute a cell field arranged with a front-side active area of the power semiconductor device.

[0044] The term "power semiconductor device" as used in the present specification is intended to describe a semiconductor device on a single chip with high voltage blocking capability and / or high current carrying capability. In other words, such a power semiconductor device is intended for high currents, typically in the range of amperes, e.g. up to several or several tens of amperes, or even up to several kA, and / or high voltages, typically above 100 V, more typically 500 V and above, e.g. up to at least 1 kV, up to at least more than 3 kV. For example, the semiconductor device described below can be a semiconductor device exhibiting a bar cell configuration or a needle cell configuration, and can be configured to be used as a power component in low, medium and / or high voltage applications.

[0045] For example, the term "power semiconductor device" as used in the present specification does not relate to a logic semiconductor device for storing data, computing data and / or other types of semiconductor-based data processing.

[0046] Figure 1A A section of a vertical projection of the power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. The illustrated section is parallel to a plane defined by a first lateral direction X and a second lateral direction Y, and orthogonal to a vertical direction Z. Figure 1B A section of a vertical cross-section A-A of the power semiconductor device 1 is shown, and Figure 1A A section of another vertical cross-section B-B of the power semiconductor device 1 is shown. In the following, reference is made to each of Figure 1C Figure 1A A section of another vertical cross-section B-B of the power semiconductor device 1 is shown. In the following, reference is made to each of

[0047] For example, the power semiconductor device 1 is or comprises a diode. In another embodiment, the power semiconductor device 1 can be or can comprise a semiconductor switch, such as an IGBT.

[0048] The power semiconductor device 1 comprises a semiconductor body 10. For example, the semiconductor body 10 is a semiconductor chip, such as a silicon chip. As can be seen in the vertical cross-section of Figure 1B As can be seen in the vertical cross-section of

[0049] The semiconductor body 10 comprises a drift region 100 of a first conductivity type, e.g. n-type. For example, the drift region 100 is an n - ​Drift region. The drift region 100 is configured for carrying a load current flowing between the first load contact structure 11 and the second load contact structure 12 in the on-state of the power semiconductor device 1. For example, the load current flows substantially in the vertical direction Z.

[0050] Further, the power semiconductor device 1 comprises a front-side structure 14 arranged at the front side 10-1. The front-side structure 14 can be at least partially comprised in the semiconductor body 10. The front-side structure 14 can define a front-side active region 15 configured for conducting the load current. For example, in case the power semiconductor device 1 is or comprises a diode, the front-side structure 14 can be an anode region of a second conductivity type complementary to the first conductivity type comprised in the semiconductor body 10. In another embodiment, the front-side structure 14 can be an active cell field comprising a plurality of IGBT cells. Figure 1A (not depicted in -C).

[0051] As Figure 1A illustrated in -C, the front-side structure 14 exhibits a first lateral edge portion 14-1 and a second lateral edge portion 14-2. The first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 can be a substantially straight or linear edge portion. For example, the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 can have a substantially linear shape extending parallel to the second lateral direction Y or the first lateral direction X, respectively (see Figure 1A ). For example, the first lateral edge portion 14-1 and the second lateral edge portion 14-2 can be substantially parallel to the corresponding lateral chip edges 10-4, 10-5 of the semiconductor body 10. The skilled person will appreciate that the front-side structure 14 can exhibit additional lateral edge portions, such as edge portions located opposite to the first and second lateral edge portions 14-1, 14-2, respectively, see Figure 1A .

[0052] For example, in an embodiment, the front side structure 14 comprises a semiconductor region of the second conductivity type (e.g. forming an anode region of a diode or a p-well region which forms one or more body regions of an IGBT cell field) wherein the average dopant concentration of the second conductivity type can decrease when proceeding from a central position within said semiconductor region of the second conductivity type towards the lateral chip edges 10-4, 10-5. In this case, the respective positions of the first and / or second lateral edge portions 14-1, 14-2 (and of the first corner portion 14-7 described below) can be defined by the positions at which the average dopant concentration of the second conductivity type has decreased to 50% of the dopant concentration at said central position when proceeding from the central position towards the first or second lateral chip edge 10-4, 10-5, respectively. It should be noted that said semiconductor region of the second conductivity type can also comprise, for example, a p + type contact region or a part of a VLD edge termination structure.

[0053] Alternatively, the first and second lateral edge portions 14-1, 14-2 (and the first corner portion 14-7 described below) can be defined as the outer boundaries of the regions in which the first load contact structure 11 (e.g. the front side metallization) is in contact with the semiconductor body 10, see Figures 1B-1C . For example, as proposed in the exemplary embodiment of Figures 1B-1C , the two definitions of the positions of the lateral edge portions 14-1, 14-2 and the first corner portion can coincide. However, it should be noted that in general, the two definitions do not need to necessarily coincide. For example, the front side metallization 11 can be terminated at a position further away from the lateral chip edges 10-4, 10-5 than at a position at which the average dopant concentration of the second conductivity type of the semiconductor region of the front side structure 14 has decreased to 50% of the dopant concentration at a central position when proceeding from the central position towards the first or second lateral chip edge 10-4, 10-5, respectively.

[0054] The front side structure 14 further exhibits a first corner portion 14-7 which forms a transition between the first lateral edge portion 14-1 and the second lateral edge portion 14-2. In the exemplary embodiment of Figure 1A , the first corner portion 14-7 is a rounded corner. In another embodiment, the corner portion 14-7 can have a different shape, for example an acute corner. The skilled person will understand that the front side structure 14 can exhibit additional corner portions, such as four corner portions as exemplarily illustrated in Figure 1A .

[0055] For example, in case the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 is substantially a linear edge portion and the first corner portion 14-7 is a rounded corner, the beginning of the first corner portion 14-7, 14-71, 14-72, can be marked by a deviation from the linear shape of the respective edge of the front side structure 14, i.e. by the beginning of a finite curvature of the respective edge of the front side structure 14, as exemplarily illustrated in Figure 1A

[0056] Further, between the chip edge, which can have been formed (e.g. by means of wafer dicing), and the front side structure 14, an edge termination structure 19 can be arranged. Such an edge termination structure 19 can be arranged in and / or on top of the semiconductor body 10. For example, the edge termination structure 19 can completely surround the front side structure 14 in a vertical projection. According to embodiments, the edge termination structure 19 can not be configured for conducting a load current, but can be configured to ensure a reliable blocking capability of the power semiconductor device 1. For example, the edge termination structure 19 comprises a variation-of-lateral-doping (VLD) structure. In other embodiments, at least one of a junction termination extension (JTE) structure and a field ring / field plate termination structure can be provided instead of or in addition to the VLD structure. The skilled person is familiar with these kinds of edge termination structures. For example, a passivation layer 192 can be arranged at the front side 10-1 above the edge termination structure 19, as depicted in Figure 1A

[0057] The power semiconductor device further comprises a backside emitter region 103, which is arranged in the semiconductor body 10 in contact with the second load terminal structure 12. The backside emitter region 103 has a net dopant concentration which is higher than the net dopant concentration of the drift region 100. For example, the net dopant concentration can belong to a first conductivity type, such as n-type. In other words, inside the backside emitter region 103, there can for example be present n-type dopants or a dopant concentration of n-type dopants which is higher than a dopant concentration of p-type dopants. In another embodiment, the net dopant concentration can belong to a second conductivity type which is complementary to the first conductivity type, such as for example p-type. In other words, inside the backside emitter region 103, there can for example be present only p-type dopants or a dopant concentration of p-type dopants which is higher than a dopant concentration of n-type dopants. For example, the backside emitter region 103 can be configured for injecting charge carriers of the respective first or second conductivity type into the drift region 100 in an on-state of the power semiconductor device 1. For example, a bipolar conduction mode of the power semiconductor device 1 can thus be enabled.

[0058] ​​In case the power semiconductor device 1 is or comprises a power diode, the backside emitter region 103 can for example belong to the first conductivity type, i.e. the (n + type) cathode region. In another embodiment in which the power semiconductor device 1 is or comprises an IGBT, the backside emitter region 103 can belong to the second conductivity type, thereby forming a (p + type or p-type) backside emitter region 103 of the IGBT, for example.

[0059] In the vertical projection, as Figure 1A illustrated in Fig. 1 1, the backside emitter region 103 laterally terminates at a first distance dl from the first lateral edge portion 14-1. For example, the common lateral extension of the frontside structure 14 and the backside emitter region 103 (in the present example, along the first lateral direction X) can terminate at the first distance dl from the first lateral edge portion.

[0060] For example, the average dopant concentration of the backside emitter region 103 can decrease when travelling from a central position within the backside emitter region 103 towards the lateral chip edge 10-4, 10-5. In this case, the position at which the backside emitter region 103 laterally terminates can be defined as the position at which the average dopant concentration of the backside emitter region 103 has decreased to 50% of the dopant concentration at the central position when travelling from the central position towards the lateral chip edge 10-4, 10-5. This decrease of the dopant concentration by 50% can occur within the backside emitter region 103 at any position along the vertical direction Z. For example, in case the backside emitter region 103 comprises an n-doped cathode emitter of a diode and a field stop region on top of the cathode emitter, the lateral boundary of the backside emitter region 103 can be defined by the decrease of the dopant concentration by 50% within the field stop region. For example, a backside emitter region 103 having a lateral boundary as defined above can thus define a backside active region of the semiconductor device 1.

[0061] In the exemplary embodiment depicted in Figure 1A Fig. 1 1, the backside emitter region 103 laterally terminates at the same first distance dl from the second lateral edge portion 14-2. However, generally, the distance of the backside emitter region 103 from the first lateral edge portion 14-1 can be different from the distance of the backside emitter region 103 from the second lateral edge portion 14-2. Thus, the first distance dl can be a distance from only one of the first and second lateral edges 14-1, 14-2.

[0062] Furthermore, in the vertical projection, the backside emitter region 103 laterally terminates at a second distance d2 from the first corner portion 14-7, wherein the second distance d2 is larger than the first distance d1. For example, the difference in distance between the second distance d2 and the first distance d1 is larger than zero and can amount to at least one times the diffusion length of the free charge carriers, or can amount to at least half of the vertical extension of the drift region 100. For example, if both the first distance d1 and the second distance d2 are positive, the second distance d2 can amount to at least 1.5 times, such as at least two times, or even at least five times the first distance d1.

[0063] For example, in embodiments in which the frontside structure 14 exhibits several lateral edge portions and associated corner portions, such as the four corner portions illustrated in Figure 1A the same or similar relationships can apply to the corresponding distances between the further corner portions and the backside emitter region 103 and the corresponding distances between the associated lateral edge portions and the backside emitter region 103.

[0064] It should be noted that, in the vertical projection, the shortest distance from the backside emitter region 103 to the first lateral edge portion 14-1 and / or to the second lateral edge portion 14-2 can vary along the respective first or second lateral edge portion 14-1, 14-2, i.e. depending on which exact point at the respective lateral edge portion 14-1, 14-2 is considered. Likewise, the shortest distance from the backside emitter region 103 to the first corner portion 14-7 can vary along the first corner portion 14-7, as illustrated in Figure 1A In other words, the first and second distances d1, d2 can be comprised in the plurality of (e.g. in a continuum) varying shortest distances from the backside emitter region 103 to the respective lateral edge portion 14-1, 14-2 or the first corner portion 14-7.

[0065] For example, the shortest distances as well as the first distance d1 and the second distance d2 can be coarse-grained distances, in the sense that they are averages of the shortest distances from the backside emitter region 103 to the respective lateral edge portion 14-1, 14-2 or the first corner portion 14-7 taken over a coarse-grained length along the respective lateral edge portion 14-1, 14-2 or the first corner portion 14-7. For example, the coarse-grained length can be given by a fraction of the length of the lateral chip edge 104, 10-5, e.g. 30% of the length of the shortest chip edge. Alternatively, the coarse-grained length can correspond to the diffusion length of the free charge carriers in the drift region 100. For example, by considering such coarse-grained distances, abrupt distance variations on very short length scales can be smoothed out.

[0066] In embodiments, where the front-side structure 14 exhibits a further lateral edge portion opposite the first lateral edge portion 14-1 (or opposite the second lateral edge portion 14-2), the first distance dl can be defined as the arithmetic mean of the distance between the back-side emitter region 103 and the first (second) lateral edge portion 14-1 (14-2) (e.g. coarse-grained over a coarse-grained length around a specific point of the first (second) lateral edge portion 14-2) and the distance between the back-side emitter region 103 and said further lateral edge portion opposite the first (second) lateral edge portion 14-1 (14-2) (e.g. coarse-grained over a coarse-grained length around a specific point of said further lateral edge portion, which can be located opposite said point of the first (second) lateral edge portion 14-1 (14-2)). Likewise, the second distance d2 can be defined as the arithmetic mean of the distance between the back-side emitter region 103 and the first corner portion 14-7 (e.g. coarse-grained over a coarse-grained length around a specific point of the first corner portion 14-7) and the distance between the back-side emitter region 103 and said further lateral edge portion opposite the first lateral edge portion 14-1 (e.g. coarse-grained over a coarse-grained length around a specific point of said further lateral edge portion, which can be located opposite said point of the first lateral edge portion 14-7). For example, misalignment errors can be compensated by considering the arithmetic mean.

[0067] It should also be noted that said shortest distance as well as each of the first distance dl and the second distance d2 can be positive or zero or negative. The shortest distance as well as the first and second distances dl, d2 are defined to be positive, where in the perpendicular projection the front-side structure 14 has a smaller distance to the closest lateral chip edge 10-4, 10-5 than the back-side emitter region 103, as illustrated in Figure 1A , whereas in the opposite case they are defined to be negative, as exemplarily illustrated at the first and second lateral edge portions 14-1, 14-2 in Figure 3A .

[0068] In this specification, the requirement that the second distance d2 is greater (i.e. more positive) than the first distance dl is to be understood by considering the sign (i.e. the positive or negative sign) of the respective distances dl, d2 as defined above. For example, if both the first distance dl and the second distance d2 are positive and the second distance d2 has a greater amount than the first distance dl, the second distance d2 is greater than the first distance dl (see Figure 1A ). As another example, if the second distance d2 is positive and the first distance dl is negative, the second distance d2 is greater than the first distance dl, as Figure 3AAs another example, if both the first distance d1 and the second distance d2 are negative and the first distance d1 has a larger magnitude than the second distance d2 (not illustrated), the second distance d2 is also larger than the first distance d1.

[0069] For example, the (potentially, coarse-grained) shortest distance, the first distance d1 and / or the second distance d2 can have a value in the range from 5 to 2000 pm, such as 10 pm to 700 pm, for example 15 pm to 400 pm or 20 pm to 100 pm. One or more of the distances can be zero or negative, such as in the range from 0 pm to -80 pm or from -10 to -50 pm. For example, as Figure 3A As exemplarily depicted in, the shortest distance along the first and second lateral edge portions 14-1, 14-2 can vary in a range including zero and negative values, such as in the range from 0 pm to -80 pm or from -10 pm to -50 pm.

[0070] For example, in the vertical projection, the coarse-grained distance between the backside emitter region 103 and the respective first lateral edge portion 14-1 or first corner portion 14-7 increases (e.g., from the first distance d1 to the second distance d2) when starting from the cut line A-A and moving along the first lateral edge portion 14-1 and the first corner portion 14-7 towards the cut line B-B. When further moving from the cut line B-B along the first corner portion 14-7 and the second lateral edge portion 14-2 towards the line C-C, the coarse-grained distance decreases again (e.g., from the second distance d2 to the first distance d1). Figure 1A

[0071] In embodiments, the first distance d1 amounts to at least 0.5 times the diffusion length of free charge carriers, such as at least 1 times, for example at least two times. For example, the diffusion length can be the diffusion length of the minority charge carriers with respect to the conductivity type of the drift region 100, i.e. the diffusion length of the free charge carriers of the second conductivity type inside the drift region 100. For example, the diffusion length is in the range from 2 pm to 1000 pm, such as in the range from 10 pm to 500 pm.

[0072] For example, each of the first distance d1 and the second distance d2 can be in the range from 5 pm to 2000 pm, such as in the range from 10 pm to 800 pm, or such as in the range from 20 pm to 500 pm, or such as in the range from 40 pm to 160 pm.

[0073] Figure 2A A segment of a vertical cross-section A-A of the power semiconductor device 1 according to further embodiments is illustrated in. Figure 1A A segment of a vertical cross-section A-A of the power semiconductor device 1 according to further embodiments is illustrated in.​Figure 2B A segment of another vertical cross-section B-B of the power semiconductor device 1 is shown. For example, in embodiments according to Figure 2A -B, the front side structure 14 is an active cell field of a plurality of IGBT cells (not shown).

[0074] In embodiments according to Figure 2A -B, the VLD edge termination structure 19 is arranged in the semiconductor body 10 adjacent to the active cell field 14.

[0075] Further, as Figure 2A illustrated in embodiments according to -B, a field stop region 100-1 can be included in the drift region 100, the field stop region 100-1 having dopants of the first conductivity type at a higher dopant concentration than the drift region 100 outside the field stop region 100-1. For example, the field stop region 100-1 is an n-type or n + -type region.

[0076] In variant embodiments, in a vertical projection, the dopant concentration of the dopants of the first conductivity type inside the field stop region 100-1 can be higher near the corner portion 14-7 and / or near the chip corner than near each of the first lateral edge portion 14-1 and the second lateral edge portion 14-2. For example, the local transistor gain a pnp may be locally reduced near the one or more corner portions 14-7 of the active cell field 14 and / or near the chip corner, for example.

[0077] For example, near the first corner portion 14-7, the field stop region 100-1 can include selenium and / or sulfur dopants. For example, the increased dopant concentration of the field stop region 101-1 near the first corner portion 14-7 described above can be achieved by an implantation of selenium and / or sulfur dopants, possibly followed by a laser annealing process. For example, the selenium dopants can be configured to provide deep energy levels that are activated with rising temperature, thereby reducing the free charge carrier injection at high temperatures near the one or more corner portions 14-7 of the active cell field 14 and / or near the chip corner. Alternatively, a field stop layer that can be achieved by proton implantation can include the highest proton-induced doping level near the first corner portion 14-7 by using a higher proton implantation dose in this region, for example.

[0078] In another variant embodiment, in the vertical projection, the dopant concentration of the first conductivity type inside the field stop region 100-1 can be lower near the corner portion 14-7 and / or near the chip corner than near each of the first and second lateral edge portions 14-1, 14-2. For example, in case the power semiconductor device 1 is or comprises a diode (i.e. the front side structure 14 can for example comprise an anode region of a diode and the back side emitter region 103 can form a cathode emitter), the back side emitter efficiency can thus be locally reduced near the corner portion(s) 14-7 of the active cell field 14 and / or near the chip corner, for example.

[0079] It should be noted that such a dopant concentration profile exhibiting a higher (or lower) field stop dopant concentration near the corner portion(s) 147 than near the edge portion(s) 14-1, 14-2 can be achieved completely independently from the size of the back side emitter region described above (i.e. independently from the features regarding the first and second distances dl, d2 from the lateral edge portions and the corner portion, respectively). In other words, the increase (or, respectively, decrease) of the field stop dopant concentration near the corner portion 14-7 compared to the field stop dopant concentration near the first and second lateral edge portions 14-1, 14-2 represents an independent aspect of the present invention. Moreover, it can be combined with all other aspects described herein.

[0080] The back side emitter region 103 can be a region of the second conductivity type, such as a p + type region. With regard to the first and second distances dl, d2, reference is made to the explanations above in connection with Figure 1A -B. With regard to Figure 2A -B, it should be noted that a second back side region 103-1 of the second conductivity type can be provided, the second back side region 103-1 being arranged in contact with the second load terminal 12. The second back side region 103-1 can have a net dopant concentration of the second conductivity type which is lower than the net dopant concentration of the second conductivity type of the back side emitter region 103. For example, if the back side emitter region 103 is a p + doped region, the second back side region 103-1 can be one of a p - doped and a p-doped region. For example, the second back side region 103-1 can be configured for ensuring a reverse blocking capability of the power semiconductor device 1. However, it should be noted that the first and second distances dl, d2 are defined based on the back side emitter region 103 as explained above (as opposed to being based on such a second back side region 103-1 which can be present in addition to the back side emitter region 103).

[0081] According to a variant embodiment, within the edge region of the power semiconductor device 1, the back emitter region 103-1 may include a dopant of the opposite doping type to that of the back emitter of a diode or IGBT to reduce emitter efficiency in edge and / or corner regions (particularly near corner regions, such as below the first corner portion 14-7 of the front structure 14). For example, the opposite doping type can be provided via a masking anti-doping process, which achieves a region with a relatively low net dopant concentration.

[0082] In another variant embodiment, within the corner region of the power semiconductor device 1, such as below the first corner portion 14-7 of the front structure 14, the field stop region 101 provided in the semiconductor body 10 may include a dopant providing at least one deep level. For example, at least one deep level is located at a distance of at least 160 meV (e.g., at least 200 meV) from the edge of the conduction band. The at least one deep level can be configured to reduce the injection of free charge carriers in the edge region. Furthermore, the dopant can be activated in a reverse blocking state, thereby contributing to the reverse blocking capability of the power semiconductor device 1.

[0083] Figure 3A A segment of the vertical projection of a power semiconductor device 1 according to one or more embodiments is schematically and exemplaryly illustrated. The illustrated segment is parallel to the plane defined by a first lateral direction X and a second lateral direction Y and orthogonal to the vertical direction Z. Figure 3B It shows Figure 3A The vertical cross-section AA of the power semiconductor device 1, and Figure 3C Another section of the vertical cross-section BB of the power semiconductor device 1 is shown. Figure 3A The exemplary embodiment shown in -C is consistent with the above reference. Figure 1A The difference in the embodiment explained in -C is that, in vertical projection, the lateral edge of the rear emitter region 103 extends beyond the lateral edges 14-1, 14-2 of the front structure 14. In other words, in lateral projection, the first distance d1 between the rear emitter region 103 on one side and the first and / or second lateral edge portions 14-1, 14-2 on the other side is negative.

[0084] For example, in another embodiment, one or more lateral edges of the rear emitter region 103 may extend substantially below and parallel to the first and / or second rear edge portions 14-1, 14-2 of the front structure 14. In this case, the first distance d1 will be zero or substantially zero. Furthermore, the above regarding... Figure 1A The exemplary embodiments of -C already stated also apply to Figure 3AThe exemplary embodiment illustrated in FIG. C. For example, the backside emitter region 103 terminates at a positive second distance d2 from the first corner portion 14-7 of the frontside structure 14. In other words, the backside emitter region 103 can be laterally recessed with respect to one or more corner portions 14-7 of the frontside structure 14, such as a rounded corner portion 14-7.

[0085] Figure 4A A section of a vertical projection of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. Similar to what has been explained above, in Figure 4A In the exemplary embodiment of FIG. C, the frontside structure 14 can be a cell field comprising a plurality of IGBT cells (not depicted). For example, the frontside structure 14 is an active cell field comprising a plurality of active IGBT cells, wherein each active IGBT cell comprises a source region electrically connected to the first load terminal 11. The IGBT cells may, for example, exhibit a periodicity along the first lateral direction X and / or along the second lateral direction Y. For example, the IGBT cells can be arranged in one of a stripe cell configuration and a pin cell configuration. The skilled person will readily identify the lateral boundaries of such an active cell field 14. For example, outside the active cell field 14, there can be no active IGBT cells (i.e., no cells with a source region connected to the first load contact) or at most a single active IGBT cell that is not arranged in correspondence with the periodicity of the active IGBT cells within the active cell field 14. As Figure 4A As shown in FIG. C, the frontside structure 14 exhibits a recess (considered in the vertical projection) towards the center of the frontside structure 14. The recess can define a pad region 17 provided for arranging a contact pad, such as a gate pad, at the frontside 10-1.

[0086] Figure 4B is an enlarged view of a portion of the pad region 17 of the power semiconductor device 1 of Figure 4A The frontside structure 14 has a third lateral edge portion 14-3 extending next to the pad region 17, a fourth lateral edge portion 144 extending next to the pad region 17, and a second corner portion 14-8 forming a transition between the third lateral edge portion 14-3 and the fourth lateral edge portion 14-4. For example, the third lateral edge portion 14-3 and the fourth lateral edge portion 14-4 can be substantially parallel to corresponding lateral edges of a gate pad (not illustrated) arranged inside the pad region 17 at the frontside 10-1 of the semiconductor body 10.

[0087] As in the above-described embodiments, the power semiconductor device 1 further comprises a drift region (not shown) of the first conductivity type, which is comprised in the semiconductor body 10 and configured for carrying a load current. Further, the power semiconductor device 1 comprises a backside emitter region 103, which is arranged in the semiconductor body 10 in contact with the second load terminal 12. The backside emitter region 103 can have a net dopant concentration which is higher than the net dopant concentration of the drift region. For example, the backside emitter region 103 has the second conductivity type, e.g. p-type or p + type.

[0088] In the vertical projection, the overlap of the pad region 17 and the backside emitter region 103 is laterally terminated at a third distance d3 from the third lateral edge portion 14-3 and / or the fourth lateral edge portion 14-4 and at a fourth distance d4 from the second corner portion 14-8, wherein the fourth distance d4 is greater than the third distance d3. In other words, in the vertical projection, the backside emitter region 103 can extend further into the pad region 17 near the second corner portion 14-8 than near the third lateral edge portion 14-3 and / or the fourth lateral edge portion 14-4. For example, the fourth distance d4 can amount to at least 1.5 times, such as at least two times, or even at least five times the third distance d3.

[0089] In one embodiment, the third distance d3 amounts to at least 0.5 times, such as at least 1 times, e.g. at least two times, the diffusion length of free charge carriers. For example, the diffusion length can be the diffusion length of the minority charge carriers with respect to the conductivity type of the drift region 100, i.e. the diffusion length of the free charge carriers of the second conductivity type inside the drift region 100. For example, the diffusion length is in the range from 2 pm to 1000 pm, e.g. in the range from 10 pm to 500 pm.

[0090] For example, each of the third distance d3 and the fourth distance d4 can be in the range from 5 pm to 500 pm, such as 10 pm to 300 pm, e.g. in the range from 40 pm to 160 pm.

[0091] Additionally, as Figure 4B illustrated in Fig. 1 1, the frontside structure 14 can exhibit a first corner portion 14-7 and a first lateral edge 14-1 portion, wherein the same relationship between the first distance d1 and the second distance d2 as described above can apply.

[0092] Figure 5A A section of a vertical projection of the power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. The illustrated section is parallel to a plane defined by the first lateral direction X and the second lateral direction Y and orthogonal to the vertical direction Z. Figure 5BIt shows Figure 5A The vertical cross-section AA of the power semiconductor device 1, and Figure 5C Another section of the vertical cross-section BB of the power semiconductor device 1 is shown. Figure 5D yes Figure 5B A more detailed view of the vertical cross-section segment, and Figure 5E yes Figure 5C A more detailed view of the vertical cross-section segment. In the following sections, [the text continues with details about the vertical cross-section segment]. Figure 5A -C is used as a reference for each of them.

[0093] according to Figure 5A In an embodiment of -E, the power semiconductor device 1 includes a semiconductor body 10 having a front side 10-1 coupled to a first load terminal structure 11 and a back side 10-2 coupled to a second load terminal structure 12. Furthermore, a front side structure 14 is disposed at the front side 10-1 and is at least partially included in the semiconductor body 10. The front side structure 14 includes an active cell field 141 comprising a plurality of IGBT cells 1410. Each IGBT cell 1410 includes a source region 104 of a first conductivity type arranged to contact the first load terminal structure 11 and a body region 105 of a second conductivity type complementary to the first conductivity type. The active cell field 141 may define a front active region 15 configured to conduct load current between the first load terminal structure 11 and the second load terminal structure 12 when the power semiconductor device 1 is in an on-state.

[0094] The front structure 14 further includes a current-draining structure 142, which includes a plurality of current-draining units 1420. Each current-draining unit 1420 includes a current-draining region 106 of a second conductivity type, which is arranged to contact the first load terminal structure 11. In contrast to the IGBT unit 1410, each current-draining unit 1420 does not include a source region of a first conductivity type arranged to contact the first load terminal structure 11.

[0095] A current-guiding structure 142 is laterally arranged between the active cell field 141 and the edge termination region 19 of the semiconductor device 1. Furthermore, the current-guiding structure 142 exhibits a first outer edge portion 1421, a second outer edge portion 1422, and an outer corner portion 1427, which forms a transition between the first outer edge portion 1421 and the second outer edge portion 1422. The minimum distance d9 between the active cell field 141 and the outer corner portion 1427 is greater than the minimum distance d8 between the active cell field 141 and each of the first and second outer edge portions 1421 and 1422. For example, the minimum distance d9 is at least 1.5 times, such as at least 2 times, or even at least 5 times, the minimum distance d8.

[0096] As mentioned above with reference to Figure 5A Aspects described with respect to the active cell field 141 and the drain structure 142 can be combined with other aspects of the application described above and / or below. It should be noted, however, that the aspects described with respect to the active cell field 141 and the drain structure 142 represent independent aspects of the application.

[0097] Figure 6A A section of a vertical projection of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. Figure 6B A section of a vertical cross-section A-A of a power semiconductor device according to Figure 6A is illustrated, and Figure 6C A section of another vertical cross-section B-B of a power semiconductor device according to Figure 6A is illustrated. In the following, reference is made to each of Figure 6A -C.

[0098] Figure 6A The power semiconductor device 1 of -C comprises a plurality of elements which have previously been described with respect to other embodiments, and in Figure 6A -C this plurality of elements is labeled with the same reference signs as before. For example, the power semiconductor device 1 comprises a front side structure 14 in the form of an active cell field 14 of a plurality of IGBT cells. As can be seen in Figure 6B -C, the cell field 14 comprises a plurality of trenches 144, such as gate trenches, which are separated from a respective adjacent trench 144 of the cell field 14 by a semiconductor mesa region 107 in each case. For example, the mesa region 107 can be configured for conducting at least a portion of a load current in an on-state of the semiconductor device 1.

[0099] A lateral extension t2, t3 of the semiconductor mesa region 107 near an outer edge of the cell field 14, such as near the first corner portion 14-7 and / or the first or second lateral edge portion 14-1, 14-2 as described above, can be greater than a lateral extension tl of the semiconductor mesa region 107 in a central portion of the cell field 14. For example, the lateral extension of the semiconductor mesa region 107 can continuously increase from the central portion of the cell field 14 towards the outer edge of the cell field 14.

[0100] Additionally or alternatively, in embodiments, the lateral extension t3 of the semiconductor mesa region 107 near the first corner portion 14-7 can be greater than the lateral extension t2 of the semiconductor mesa region near the first and / or second lateral edge portion 14-1, 14-2. For example, the lateral extension of the semiconductor mesa region 107 can continuously increase from the first or second lateral edge portion 14-1, 14-2 towards the first corner portion.

[0101] As outlined above with reference to Figure 6A The aspects described with respect to the lateral extension of the semiconductor region 107 can be combined with other aspects of the application described above and / or below. It should be noted, however, that the aspects described with respect to the lateral extension of the semiconductor region 107 represent independent aspects of the application.

[0102] According to a further aspect of the application, as Figure 7A As exemplarily shown in -B, the power semiconductor device 1 comprises a semiconductor body 10 having a front side 10-1 coupled to a first load terminal structure 11 and a back side 10-2 coupled to a second load terminal structure 12. A front side structure 14 is arranged at the front side 10-1 and at least partially comprised in the semiconductor body 10. The front side structure 14 defines a front side active area 15 configured for conducting a load current between the first load terminal structure 11 and the second load terminal structure 12 in an on-state of the power semiconductor device 1. The front side structure 14 exhibits a first lateral edge portion 14-1, a second lateral edge portion 14-2 and a first corner portion 14-7 forming a transition between the first lateral edge portion 14-1 and the second lateral edge portion 14-2. For a definition of the positions of the lateral edge portions 14-1, 14-2 and the corner portion 14-7, reference is made to the above.

[0103] Further, the power semiconductor device 1 comprises a drift region 100 of a first conductivity type comprised in the semiconductor body and a field stop region 100-1 comprised in the drift region 100 and having dopants of the first conductivity type at a higher dopant concentration than the drift region 100 outside the field stop region.

[0104] The field stop region 100-1 comprises an inner region 1012 and an outer region 1011. The outer region 1011 is arranged closer to the first lateral edge portion 141, the second lateral edge portion 14-2 and the first corner portion 14-7 than the inner region 1012 and has dopants of the first conductivity type at a higher dopant concentration than the inner region 1012. In the vicinity of the first corner portion 14-7, the outer region 1011 extends further into the front side active area 15 than in the vicinity of each of the first lateral edge portion 14-1 and the second lateral edge portion 14-2.

[0105] In another variant embodiment, where, for example, the power semiconductor device 1 may be or include a diode, the inner region 1012 may have a dopant of a first conductivity type at a lower dopant concentration than the inner region 1012. As previously described, near the first corner portion 14-7, the outer region 1011 extends further into the front active region 15 than near each of the first lateral edge portions 14-1 and the second lateral edge portions 14-2. For example, the emitter efficiency of the diode's cathode emitter can thus be locally reduced.

[0106] In an embodiment, in vertical projection, the overlap of the front structure 14 and the inner region 1012 may laterally terminate at a fifth distance d5 from the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 and at a sixth distance d6 from the first corner portion 14-7, wherein the sixth distance d6 is greater than the fifth distance d5. For example, the sixth distance d6 may be at least 1.5 times the fifth distance d5, such as at least 3 times, or even 5 times.

[0107] As per the above reference Figure 7A The aspects described in section -B concerning the corresponding extensions of the outer region 1011 and inner region 1012 of the field stop region 100-1 can be combined with other aspects of the invention described above and / or above. However, it should be noted that the aspects concerning the corresponding extensions of the outer region 1011 and inner region 1012 of the field stop region 1001 represent independent aspects of the invention.

[0108] According to a further aspect of the invention, the power semiconductor device 1 includes a semiconductor body 10 having a front side 10-1 coupled to a first load terminal structure 11 and a back side 10-2 coupled to a second load terminal structure 12. A front side structure 14 is disposed at the front side 10-1 and is at least partially included in the semiconductor body 10. The front side structure 14 defines a front active region 15 configured to conduct load current between the first load terminal structure 11 and the second load terminal structure 12 when the power semiconductor device 1 is in an on-state. The front side structure 14 exhibits a first lateral edge portion 14-1, a second lateral edge portion 14-2, and a first corner portion 14-7 forming a transition between the first lateral edge portion 14-1 and the second lateral edge portion 14-2.

[0109] The power semiconductor device 1 further comprises a drift region 100 of the first conductivity type, which is comprised in the semiconductor body 10 and is configured for carrying the load current. The lifetime of charge carriers in the drift region 100 is shorter near the first corner portion 14-7 than near each of the first and second lateral edge portions 14-1, 14-2. For example, in order to locally reduce the charge carrier lifetime, the drift region 100 can comprise one or more recombination regions comprising recombination centers configured for reducing the free charge carrier lifetime.

[0110] In a variant embodiment, as an alternative or in addition to said relation of the charge carrier lifetime near the first corner portion 14-7 and near the lateral edge portions 14-1, 14-2, it can be provided that the charge carrier lifetime near the chip edge (e.g. in an edge termination region) can be shorter than the charge carrier lifetime in the center of the front-side active region 15.

[0111] Such local adaptation of the charge carrier lifetime can be combined with one or more aspects of the invention described above or below. However, it should be noted that the local reduction of the free charge carrier lifetime represents an independent aspect of the invention.

[0112] For example, the power semiconductor device 1 according to one or more embodiments as described above can be formed by means of some or all of the following processing steps:

[0113] - providing a semiconductor body 10 having a front side 10-1 and a back side 10-2;

[0114] - forming a front-side structure 14 arranged at the front side 10-1 and at least partially comprised in the semiconductor body 10, the front-side structure 14 defining a front-side active region 15 configured for conducting a load current between a first load terminal structure 11 coupled to the front side 10-1 and a second load terminal structure 12 coupled to the back side 10-2 in an on-state of the power semiconductor device 1,

[0115] wherein the front-side structure 14 exhibits a first lateral edge portion 14-1, a second lateral edge portion 14-2, and a first corner portion 14-7 forming a transition between the first and second lateral edge portions 14-1, 14-2;

[0116] - providing or forming a drift region 100 of the first conductivity type, which is comprised in the semiconductor body 10 and is configured for carrying the load current; and

[0117] - forming a backside emitter region 103 arranged in the semiconductor body 10 in contact with the second load terminal 12, the emitter region having a net dopant concentration which is higher than the net dopant concentration of the drift region 100;

[0118] wherein, in a vertical projection, the backside emitter region 103 laterally terminates at a first distance dl from the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 and at a second distance d2 from the first corner portion 14-7, wherein the second distance d2 is greater than the first distance dl.

[0119] For example, the above-mentioned processing method further comprises forming a recombination region inside the drift region 100, the recombination region comprising recombination centers configured to reduce the lifetime of free charge carriers, wherein forming the recombination region comprises at least one of a masking irradiation process and a masking diffusion process. For example, for this a masking irradiation with helium atoms, protons or electrons can be used, wherein the irradiation can be performed from the wafer front side or from the wafer backside. Additionally or alternatively, a heavy metal diffusion (e.g. platinum, palladium and / or gold diffusion) can be performed from the wafer front side or from the wafer backside. In a vertical projection, the overlap of the masked region during the irradiation process and / or the diffusion process with the frontside structure 14 can laterally terminate at a first distance dl from the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 and at a second distance d2 from the first corner portion 14-7.

[0120] In a further embodiment, a method of processing a power semiconductor device 1 comprises:

[0121] - providing a semiconductor body 10 having a front side 10-1 and a backside 10-2;

[0122] - forming a frontside structure 14 arranged at the front side 10-1 and at least partially comprised in the semiconductor body 10, the frontside structure 14 defining a frontside active area 15 configured to conduct a load current between a first load terminal structure 11 coupled to the front side 10-1 and a second load terminal structure 12 coupled to the backside 10-2 in an on-state of the power semiconductor device 1,

[0123] wherein the frontside structure 14 exhibits a first lateral edge portion 14-1, a second lateral edge portion 14-2 and a first corner portion 14-7 forming a transition between the first lateral edge portion 14-1 and the second lateral edge.

[0124] - providing or forming a drift region 100 of a first conductivity type comprised in the semiconductor body 10 and configured to carry the load current;

[0125] - forming a backside emitter region 103 arranged in the semiconductor body 10 in contact with the second load terminal 12, the emitter region having a net dopant concentration which is higher than the net dopant concentration of the drift region 100;

[0126] - forming a recombination region inside the drift region 100, the recombination region comprising recombination centers configured for reducing a free charge carrier lifetime, wherein forming the recombination region comprises at least one of a masking irradiation process and a masking diffusion process, wherein an overlap of a masked area during the irradiation process and / or during the diffusion process with the frontside structure 14 in a vertical projection is laterally terminated at a first distance dl from the first lateral edge portion 14-1 and / or the second lateral edge portion 14-2 and at a second distance d2 from the first corner portion 14-7, wherein the second distance d2 is greater than the first distance dl.

[0127] In the foregoing, embodiments relating to power semiconductor devices, such as diodes, MOSFETs or IGBTs, and corresponding processing methods are explained. For example, these devices are based on silicon (Si). Hence, the single crystalline semiconductor regions or layers (e.g., the semiconductor body 10 and its regions / areas, such as 100, 100-1, 103 and 105) can be single crystalline Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be employed.

[0128] However, it should be appreciated that the semiconductor body 10 and its doped regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to: elemental semiconductor materials such as silicon (Si) or germanium (Ge), IV- compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II- VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The aforementioned semiconductor materials are also referred to as "homo-junction semiconductor materials". When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include, but are not limited to: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-carbon silicon (SixCi_x), and silicon-SiGe hetero-junction semiconductor materials. For power semiconductor device applications, currently Si, SiC, GaAs and GaN materials are predominantly used.

[0129] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the respective devices in addition to those depicted in the figures. Further, terms such as "first", "second", and the like, are also used to describe various elements, regions, sections, and the like and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0130] As used herein, the terms "have", "having", "contain", "containing", "include", "including", "comprise", "comprising" and the like are open-ended terms that indicate the presence of the stated element or feature, but do not preclude the presence of additional elements or features.

[0131] With the above ranges in mind, it should be understood that the application is not limited by the foregoing description, nor is it limited by the accompanying drawings. Rather, the application is limited only by the claims and their legal equivalents.

Claims

1. A power semiconductor device (1), comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11) and a back side (10-2) coupled to a second load terminal structure (12); - a front side structure (14) arranged at the front side (10-1) and at least partially comprised in the semiconductor body (10), the front side structure (14) defining a front side active area (15) configured for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12) in an on-state of the power semiconductor device (1), wherein the front side structure (14) exhibits a first lateral edge portion (14-1), a second lateral edge portion (14-2), and a first corner portion (14-7) forming a transition between the first lateral edge portion (14-1) and the second lateral edge portion (14-2); - a drift region (100) of a first conductivity type comprised in the semiconductor body (10) and configured for carrying the load current; and - a back side emitter region (103) arranged in the semiconductor body (10) in contact with the second load terminal (12), the back side emitter region (103) having a net dopant concentration higher than a net dopant concentration of the drift region (100); wherein, in a vertical projection, the back side emitter region (103) laterally terminates at a first distance (dl) from the first lateral edge portion (14-1) and / or the second lateral edge portion (14-2) and at a second distance (d2) from the first corner portion (14-7), wherein the second distance (d2) is greater than the first distance (dl).

2. The power semiconductor device (1) according to claim 1, wherein both the first distance (dl) and the second distance (d2) are positive, and wherein the second distance (d2) amounts to at least 1.5 times the first distance (dl).

3. The power semiconductor device (1) according to claim 1 or 2, wherein a distance difference between the second distance (d2) and the first distance (dl) amounts to at least a diffusion length of free charge carriers.

4. The power semiconductor device (1) according to claim 1 or 2, wherein a distance difference between the second distance (d2) and the first distance (dl) amounts to at least half of a vertical extension of the drift region (100).

5. The power semiconductor device (1) according to claim 1 or 2, wherein the first distance (dl) amounts to at least 0.5 times a diffusion length of free charge carriers.

6. The power semiconductor device (1) according to claim 1 or 2, wherein the first lateral edge portion (14-1) and the second lateral edge portion (14-2) are straight edge portions. ​ 7. The power semiconductor device (1) according to claim 1 or 2, wherein the first lateral edge portion (14-1) and the second lateral edge portion (14-2) are parallel to a corresponding lateral chip edge (10-4, 10-5) of the semiconductor body (10).

8. The power semiconductor device (1) according to claim 1 or 2, wherein the first corner portion (14-7) is a rounded corner (14-7).

9. The power semiconductor device (1) according to claim 1 or 2, wherein the power semiconductor device (1) is a diode or comprises a diode.

10. The power semiconductor device (1) according to claim 9, wherein the front side structure (14) is an anode region of a second conductivity type complementary to a first conductivity type, the anode region being comprised in the semiconductor body (10).

11. The power semiconductor device (1) according to claim 9, wherein the back side emitter region (103) is a cathode region of the first conductivity type.

12. The power semiconductor device (1) according to claim 1 or 2, wherein the power semiconductor device (1) is an IGBT or comprises an IGBT.

13. The power semiconductor device (1) according to claim 12, wherein the front side structure (14) is a cell field comprising a plurality of IGBT cells.

14. The power semiconductor device (1) according to claim 13, wherein the cell field comprises a plurality of trenches (144) which are separated from a respective adjacent trench (144) of the cell field by a semiconductor mesa region (107) in each case, and wherein a lateral extension (t2, t3) of the semiconductor mesa region (107) near an outer edge of the cell field is greater than a lateral extension (tl) of the semiconductor mesa region (107) in a central portion of the cell field.

15. The power semiconductor device (1) according to claim 13, wherein the cell field comprises a plurality of trenches (144) which are separated from a respective adjacent trench (144) of the cell field by a semiconductor mesa region (107) in each case, and wherein a lateral extension (t3) of the semiconductor mesa region (107) near the first corner portion (14-7) is greater than a lateral extension (t2) of the semiconductor mesa region near the first and / or second lateral edge portion (14-1, 14-2).

16. The power semiconductor device (1) according to claim 12, wherein the back side emitter region (103) is of a second conductivity type complementary to the first conductivity type.

17. The power semiconductor device (1) according to claim 16, further comprising a second back side region (103-1) of the second conductivity type, the second back side region (103-1) being arranged in contact with the second load terminal (12) and having a net dopant concentration of the second conductivity type which is lower than a net dopant concentration of the second conductivity type of the back side emitter region (103).

18. The power semiconductor device (1) according to claim 1 or 2, wherein the drift region (100) comprises a field stop region (100-1), wherein, In a vertical projection, a dopant concentration of dopants of the first conductivity type inside the field stop region (100-1) is lower near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

19. A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11) and a back side (10-2) coupled to a second load terminal structure (12); - a front side structure (14) arranged at the front side (10-1) and at least partially comprised in the semiconductor body (10), wherein the front side structure (14) is a cell field comprising a plurality of IGBT cells, thereby defining a front side active area (15) configured for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12) in a conducting state of the power semiconductor device (1), wherein the front side structure (14) exhibits: a recess defining a pad area (17) provided for arranging a contact pad at the front side (10-1); a third lateral edge portion (14-3) extending next to the pad area (17), a fourth lateral edge portion (14-4) extending next to the pad area (17) and a second corner portion (14-8) forming a transition between the third lateral edge portion (14-3) and the fourth lateral edge portion (14-4); - a drift region (100) of a first conductivity type comprised in the semiconductor body (10) and configured for carrying the load current; and - a back side emitter region (103) arranged in the semiconductor body (10) in contact with the second load terminal (12), the back side emitter region (103) having a net dopant concentration higher than a net dopant concentration of the drift region (100); wherein, in a vertical projection, an overlap of the pad area (17) with the back side emitter region (103) is laterally terminated at a third distance (d3) from the third lateral edge portion (14-3) and / or the fourth lateral edge portion (14-4) and at a fourth distance (d4) from the second corner portion (14-8), wherein the fourth distance (d4) is greater than the third distance (d3).

20. The power semiconductor device (1) according to claim 19, wherein the third lateral edge portion (14-3) and the fourth lateral edge portion (14-4) are substantially parallel to corresponding lateral edges of a gate pad arranged inside the pad area (17) at the front side (10-1) of the semiconductor body (10).

21. The power semiconductor device (1) according to claim 19 or 20, wherein the drift region (100) comprises a field stop region (100-1) and the front side structure (14) exhibits a first lateral edge portion (14-1), a second lateral edge portion (14-2) and a corner portion (14-7), the corner portion (14-7) forming a transition between the first lateral edge portion (14-1) and the second lateral edge portion (14-2), wherein, In a vertical projection, the dopant concentration of the dopant of the first conductivity type inside the field stop region (100-1) is lower near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

22. A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11) and a back side (10-2) coupled to a second load terminal structure (12); - a front side structure (14) arranged at the front side (10-1) and at least partially comprised in the semiconductor body (10), the front side structure (14) defining a front side active area (15) configured for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12) in an on-state of the power semiconductor device (1), wherein the front side structure (14) exhibits a first lateral edge portion (14-1), a second lateral edge portion (14-2), and a first corner portion (14-7) forming a transition between the first lateral edge portion (14-1) and the second lateral edge portion (14-2); - a drift region (100) of a first conductivity type comprised in the semiconductor body (10) and configured for carrying a load current; and - a field stop region (100-1) comprised in the drift region (100) and having dopants of the first conductivity type at a higher dopant concentration than the drift region (100) outside the field stop region (100-1), wherein the field stop region (100-1) comprises an inner region (1012) and an outer region (1011), the outer region (1011) being arranged closer to the first lateral edge portion (14-1), the second lateral edge portion (14-2), and the first corner portion (14-7) than the inner region (1012), and the outer region (1011) having dopants of the first conductivity type at a higher dopant concentration than the inner region (1012), and wherein, near the first corner portion (14-7), the outer region (1011) extends further into the front side active area (15) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

23. The power semiconductor device (1) according to claim 22, wherein the drift region (100) comprises a field stop region (100-1), wherein, In a vertical projection, the dopant concentration of the dopant of the first conductivity type inside the field stop region (100-1) is lower near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2). In a vertical projection, the dopant concentration of the dopant of the first conductivity type inside the field stop region (100-1) is lower near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

24. The power semiconductor device (1) according to claim 22, wherein In the vertical projection, the inner region (1012) laterally terminates at a fifth distance (d5) from the first lateral edge portion (14-1) and / or the second lateral edge portion (14-2) and at a sixth distance (d6) from the first corner portion (14-7), wherein the sixth distance (d6) is greater than the fifth distance (d5).

25. A power semiconductor device (1), comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11) and a back side (10-2) coupled to a second load terminal structure (12); - a front side structure (14) arranged at the front side (10-1) and at least partially comprised in the semiconductor body (10), the front side structure (14) defining a front side active area (15) configured for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12) in an on-state of the power semiconductor device (1), wherein the front side structure (14) exhibits a first lateral edge portion (14-1), a second lateral edge portion (14-2) and a first corner portion (14-7) forming a transition between the first lateral edge portion (14-1) and the second lateral edge portion (14-2); - a drift region (100) of a first conductivity type comprised in the semiconductor body (10) and configured for carrying a load current; and - a field stop region (100-1) comprised in the drift region (100) and having a dopant of the first conductivity type at a higher dopant concentration than the drift region (100) outside the field stop region (100-1), wherein the field stop region (100-1) comprises an inner region (1012) and an outer region (1011), the outer region (1011) being arranged closer to the first lateral edge portion (14-1), the second lateral edge portion (14-2) and the first corner portion (14-7) than the inner region (1012), and the outer region (1011) having a dopant of the first conductivity type at a lower dopant concentration than the inner region (1012), and wherein, in the vicinity of the first corner portion (14-7), the outer region (1011) extends further into the front side active area (15) than in the vicinity of each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

26. The power semiconductor device (1) according to claim 25, wherein In a vertical projection, the inner region (1012) laterally terminates at a fifth distance (d5) from the first lateral edge portion (14-1) and / or the second lateral edge portion (14-2) and at a sixth distance (d6) from the first corner portion (14-7), wherein the sixth distance (d6) is greater than the fifth distance (d5).

27. The power semiconductor device (1) according to claim 25 or 26, comprising a field stop region (100-1) which is comprised in the drift region (100) and has dopants of the first conductivity type at a higher dopant concentration than the drift region (100) outside the field stop region (100-1), wherein, Below the first corner portion (14-7), the field stop region (100-1) comprises a dopant providing at least one deep energy level.

28. The power semiconductor device (1) according to claim 27, wherein the at least one deep energy level is located at a distance of at least 160 meV from a conduction band edge.

29. The power semiconductor device (1) according to claim 25 or 26, wherein the drift region (100) comprises a field stop region (100-1), wherein, In a vertical projection, a dopant concentration of dopants of the first conductivity type inside the field stop region (100-1) is higher near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

30. The power semiconductor device (1) according to claim 29, wherein near the first corner portion (14-7), the field stop region (100-1) comprises selenium and / or sulfur dopants.

31. The power semiconductor device (1) according to claim 25 or 26, wherein the drift region (100) comprises a field stop region (100-1), wherein, In a vertical projection, a dopant concentration of dopants of the first conductivity type inside the field stop region (100-1) is lower near the corner portion (14-7) than near each of the first lateral edge portion (14-1) and the second lateral edge portion (14-2).

32. A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11) and a back side (10-2) coupled to a second load terminal structure (12); and - a front side structure (14) arranged at the front side (10-1) and at least partially comprised in the semiconductor body (10), wherein the front side structure (14) comprises an active cell field (141) comprising a plurality of IGBT cells (1410), each IGBT cell (1410) comprising a source region (104) of a first conductivity type arranged in contact with the first load terminal structure (11) and a body region (105) of a second conductivity type complementary to the first conductivity type; and a current steering structure (142) comprising a plurality of current steering cells (1420), each current steering cell (1420) comprising a current steering region (106) of the second conductivity type arranged in contact with the first load terminal structure (11), wherein each current steering cell (1420) does not comprise a source region of the first conductivity type arranged in contact with the first load terminal structure (11); wherein the current steering structure (142) is laterally arranged between the active cell field (141) and an edge termination region (19) of the semiconductor device (1). wherein the drain structure (142) exhibits a first outer edge portion (1421), a second outer edge portion (1422), and an outer corner portion (1427) forming a transition between the first outer edge portion (1421) and the second outer edge portion (1422); and wherein a minimum distance (d9) between the active cell field (141) and the outer corner portion (1427) is greater than a minimum distance (d8) between the active cell field (141) and each of the first outer edge portion (1421) and the second outer edge portion (1422).

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