Semiconductor Structure, Device and Method for Preparing the Same

Abstract

The present invention provides a semiconductor structure, a device and a preparation method thereof. The semiconductor structure includes: a substrate, a nucleation layer, a plurality of spaced channels and an epitaxial layer; the nucleation layer is formed on the substrate and covers the upper surface of the substrate, and is an aluminum-containing nitride layer with a crystal orientation of (0001); the channels penetrate through the nucleation layer and the bottoms are located in the substrate, dividing the nucleation layer into a plurality of spaced nucleation layer platforms; the epitaxial layer is an aluminum-containing nitride layer, formed on the nucleation layer platforms and covering the upper surfaces of the nucleation layer platforms and the openings of the channels. Through the structures of the channels and the nucleation layer, the present invention reduces the probability of the epitaxial layer nucleating on the channels, and further, by selecting the materials of the nucleation layer and the epitaxial layer, increases the probability of the epitaxial layer nucleating on the nucleation layer platforms, so as to further increase the difference in the nucleation probability of the epitaxial layer on the nucleation layer platforms and the channels, and prepare an epitaxial layer with good flatness and integrity.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and relates to a semiconductor structure, a device and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, the third-generation semiconductor materials are mainly wide-bandgap semiconductor materials represented by silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), diamond, and aluminum nitride (AlN). Due to their high breakdown electric field, high thermal conductivity, high electron saturation rate, and high radiation resistance, they are more suitable for making high-temperature, high-frequency, radiation-resistant, and high-power devices, and thus have attracted much attention.

[0003] In order to solve the phenomenon of lattice mismatch between materials, the patterned substrate technology has been widely used. However, it has been found through research that in the patterned substrate technology, when growing an epitaxial layer on the patterned substrate, such as an AlN layer or an AlGaN layer, due to the small growth distance of Al atoms on the growth surface, poor growth selectivity, and small lateral growth rate, it is very difficult to form a continuous and flat epitaxial layer on the surface of the patterned substrate, thereby affecting the quality of the prepared products.

[0004] Therefore, it is necessary to provide a semiconductor structure, a device and a preparation method thereof to effectively improve the surface flatness and integrity of the epitaxial layer. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor structure, a device and a preparation method thereof, which are used to solve the problem that it is difficult to prepare a flat and complete epitaxial layer on the surface of a patterned substrate in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a preparation method of a semiconductor structure, including the following steps:

[0007] Provide a substrate;

[0008] Form a nucleation layer on the substrate, the nucleation layer covers the upper surface of the substrate, and the nucleation layer is an Al-containing nitride layer, and the crystal orientation of the nucleation layer is the (0001) crystal orientation;

[0009] Form a plurality of spaced channels, the channels penetrate the nucleation layer, and the bottom of the channels is located in the substrate to divide the nucleation layer into a plurality of spaced nucleation layer platforms;

[0010] Form an epitaxial layer on the nucleation layer platform, the epitaxial layer is an Al-containing nitride layer, the epitaxial layer covers the upper surface of the nucleation layer platform, and the epitaxial layer covers the opening of the channel.

[0011] Optionally, the nucleation layer includes one or a combination of an AlN layer and an AlGaN layer; the epitaxial layer includes one or a combination of an AlN layer and an AlGaN layer; the method for forming the nucleation layer includes PVD; the method for forming the epitaxial layer includes MOCVD.

[0012] Optionally, the morphology of the opening of the channel includes one or a combination of a circular shape and a polygonal shape; the vertical cross-sectional morphology of the channel includes one or a combination of a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid.

[0013] Optionally, the thickness range of the nucleation layer platform includes 10 nm to 50 nm; the width range of the nucleation layer platform is less than or equal to 5 μm.

[0014] Optionally, the width range of the opening of the channel is less than or equal to 1 μm; the depth range of the channel is less than or equal to 2 μm.

[0015] The present invention also provides a semiconductor structure, which includes:

[0016] A substrate;

[0017] A nucleation layer, which is formed on the substrate, covers the upper surface of the substrate, and is an Al-containing nitride layer, and the crystal orientation of the nucleation layer is the (0001) crystal orientation;

[0018] A plurality of channels arranged at intervals, which penetrate the nucleation layer, and the bottom of the channels is located in the substrate to divide the nucleation layer into a plurality of nucleation layer platforms arranged at intervals;

[0019] An epitaxial layer, which is an Al-containing nitride layer, is formed on the nucleation layer platform and covers the upper surface of the nucleation layer platform, and the epitaxial layer covers the opening of the channel.

[0020] Optionally, the nucleation layer includes one or a combination of an AlN layer and an AlGaN layer; the epitaxial layer includes one or a combination of an AlN layer and an AlGaN layer.

[0021] Optionally, the morphology of the opening of the channel includes one or a combination of a circular shape and a polygonal shape; the vertical cross-sectional morphology of the channel includes one or a combination of a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid.

[0022] Optionally, the thickness range of the nucleation layer platform includes 10 nm to 50 nm; the width range of the nucleation layer platform is less than or equal to 5 μm.

[0023] Optionally, the width of the opening of the channel is less than or equal to 1 μm; the depth of the channel is less than or equal to 2 μm.

[0024] The present invention also provides a semiconductor device, which includes the above semiconductor structure.

[0025] As described above, in the semiconductor structure, device and preparation method thereof of the present invention, a nucleation layer is formed on a substrate, and the nucleation layer is divided into a plurality of nucleation layer platforms arranged at intervals by channels located in the nucleation layer and the substrate. Since the crystal orientation of the nucleation layer is the (0001) crystal orientation, there is a certain selective growth property between the nucleation layer platform with the (0001) crystal plane and the channel when forming the epitaxial layer, that is, when forming the epitaxial layer, the nucleation probability of the epitaxial layer on the nucleation layer platform with the (0001) crystal plane is greater than the nucleation probability in the channel. Therefore, the epitaxial layer can form a flat and complete epitaxial layer covering the nucleation layer platform and the channel opening through lateral growth; further, since both the nucleation layer and the epitaxial layer are aluminum-containing nitride layers, the nucleation layer is more conducive to the growth of the epitaxial layer, thereby increasing the nucleation probability of the epitaxial layer on the nucleation layer platform, and further increasing the nucleation probability difference between the epitaxial layer on the nucleation layer platform and the channel, so as to further prepare an epitaxial layer with good flatness and integrity. Description of the Drawings

[0026] Figure 1 It shows a process flow chart for preparing a semiconductor structure in the present invention.

[0027] Figures 2 to 8 It shows a schematic structural diagram of each step for preparing a semiconductor structure in the present invention, where Figure 8 It shows a schematic structural diagram of the semiconductor structure prepared in the present invention.

[0028] Figure 9 and Figure 10 It shows a schematic structural diagram of each step for preparing a semiconductor device in the present invention, where Figure 10 It shows a schematic structural diagram of the semiconductor device prepared in the present invention.

[0029] Figure 11a and Figure 11b It shows a top view of a microscope for preparing a semiconductor structure in the present invention.

[0030] Element Label Description

[0031] 101 Substrate

[0032] 102 Nucleation layer

[0033] 103 Photoresist layer

[0034] 104 Channel

[0035] 105 epitaxial layer

[0036] 106 N-type GaN layer

[0037] 107 quantum well layer

[0038] 108 P-type GaN layer

[0039] 109 P-type electrode layer

[0040] 110 N-type electrode layer Detailed implementation manners

[0041] The following specific examples are used to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please refer to Figures 1 to 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0043] For example Figure 1 , this embodiment provides a method for preparing a semiconductor structure. By forming a nucleation layer on a substrate and dividing the nucleation layer into a plurality of spaced-apart nucleation layer platforms through channels located in the nucleation layer and the substrate, since the crystal orientation of the nucleation layer is the (0001) crystal orientation, there is a certain selective growth property between the nucleation layer platforms with the (0001) crystal plane and the channels when forming the epitaxial layer. That is, when forming the epitaxial layer, the nucleation probability of the epitaxial layer on the nucleation layer platforms with the (0001) crystal plane is greater than the nucleation probability in the channels. Therefore, through lateral growth, the epitaxial layer can form an epitaxial layer that covers the nucleation layer platforms and the channel openings, with a flat and complete surface; further, since both the nucleation layer and the epitaxial layer are aluminum-containing nitride layers, the nucleation layer is more conducive to the growth of the epitaxial layer, thereby increasing the nucleation probability of the epitaxial layer on the nucleation layer platforms, and further increasing the nucleation probability difference between the epitaxial layer on the nucleation layer platforms and the channels, so as to further prepare an epitaxial layer with good flatness and integrity.

[0044] For example Figures 2 to 8 , it shows a structural diagram of each step for preparing the semiconductor structure.

[0045] For example Figure 2, a substrate 101 is provided, the crystal orientation of the substrate 101 is the (0001) crystal orientation, a nucleation layer 102 is formed on the substrate 101, the nucleation layer 102 covers the upper surface of the substrate 101, and the nucleation layer 102 is an Al-containing nitride layer, and the crystal orientation of the nucleation layer 102 is the (0001) crystal orientation.

[0046] As an example, the nucleation layer 102 may include one or a combination of an AlN layer and an AlGaN layer; the method of forming the nucleation layer 102 may include PVD (physical vapor deposition).

[0047] Specifically, the substrate 101 may include one of a sapphire substrate, an Si substrate, an SiC substrate, a ZnO substrate, and an Al 2 O 3 substrate, and can be specifically selected according to needs to expand the application range of the semiconductor structure. The thickness range of the nucleation layer 102 formed on the substrate 101 by PVD may include 10 nm to 50 nm.

[0048] Such as Figures 3 to 5 , a plurality of spaced-apart channels 104 are formed, the channels 104 penetrate the nucleation layer 102, and the bottom of the channels 104 is located in the substrate 101 to divide the nucleation layer 102 into a plurality of spaced-apart nucleation layer platforms.

[0049] Specifically, such as Figure 3 , a photoresist layer 103 is formed on the upper surface of the nucleation layer 102, and the photoresist layer 103 covers the upper surface of the nucleation layer 102. Then, such as Figure 4 , the photoresist layer 103 is patterned to form an etching window in the photoresist layer 103. After that, such as Figure 5 , using the patterned photoresist layer 103 as a mask, an ICP (inductively coupled plasma) etching process can be used to etch the nucleation layer 102 and the substrate 101 to form the channels 104. Among them, the type of the photoresist layer 103 can be selected according to needs, and can include one of a negative photoresist and a positive photoresist. In this embodiment, the photoresist layer 103 uses a positive photoresist as an example, but is not limited thereto.

[0050] As an example, the morphology of the opening of the channel 104 includes one or a combination of a circle and a polygon; the vertical cross-sectional morphology of the channel 104 includes one or a combination of a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid.

[0051] Specifically, such as Figure 5, in this embodiment, the vertical cross-sectional morphology of the channel 104 takes the "V" shape as an example, but is not limited thereto. The vertical cross-sectional morphology of the channel 104 may also include one of a "U" shape, a rectangle, a square, and a trapezoid, or one of combinations formed by a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid, and no excessive limitation is made here. As Figure 6 and Figure 7 illustrate Figure 5 two top-view structural schematic diagrams of

[0052] . As an example, the range of the width W1 of the opening of the channel 104 is less than or equal to 1 μm; the range of the depth D1 of the channel 104 is less than or equal to 2 μm; the range of the thickness T of the nucleation layer platform includes 10 nm to 50 nm; the range of the width W2 of the nucleation layer platform is less than or equal to 5 μm.

[0053] Specifically, as Figure 5 , the width W1 of the opening of the channel 104 ≤ 1 μm; the depth D1 of the channel 104 ≤ 2 μm; the range of the thickness of the nucleation layer platform includes 10 nm ≤ T ≤ 50 nm; the width W2 of the nucleation layer platform ≤ 5 μm. Among them, it is preferred that W1 ≤ 0.3 μm, D1 ≤ 0.5 μm, and W2 ≤ 2 μm, so as to further reduce the probability of the epitaxial layer nucleating on the surface of the channel 104 during the subsequent formation of the epitaxial layer, increase the selectivity growth difference between the epitaxial layer on the nucleation layer platform and the channel 104, and reduce the influence of the nucleation on the surface of the channel 104 on the lateral growth of the epitaxial layer when the epitaxial layer laterally grows upward above the channel 104, so as to further form the epitaxial layer with good flatness and integrity.

[0054] . As an example, the channel 104 may include one of periodic arrangement and non-periodic arrangement. The number, morphology, and distribution of the channels 104 can be set as needed. Among them, the channels 104 can adopt one of the same morphology or different morphologies and one of equal-spacing distribution and non-equal-spacing distribution to form a periodic arrangement or a non-periodic arrangement, and no excessive limitation is made here.

[0055] As Figure 8 , an epitaxial layer 105 is formed on the nucleation layer platform. The epitaxial layer 105 is an Al-containing nitride layer. The epitaxial layer 105 covers the upper surface of the nucleation layer platform, and the epitaxial layer 105 covers the opening of the channel 104.

[0056] As an example, the epitaxial layer 105 includes one or a combination of an AlN layer and an AlGaN layer; the method for forming the epitaxial layer 105 may include MOCVD (Metal Organic Chemical Vapor Deposition).

[0057] Specifically, when forming the epitaxial layer 105 on the nucleation layer platform, due to the particularity of the structure formed by the channel 104 and the nucleation layer platform having a (0001) crystal plane, the growth process of the epitaxial layer 105 has strong selectivity between the nucleation layer platform and the channel 104, reducing the probability of the epitaxial layer 105 nucleating on the surface of the channel 104. When the epitaxial layer 105 grows laterally upward above the channel 104, the influence of nucleation on the surface of the channel 104 on the lateral growth of the epitaxial layer 105 can be reduced, and the epitaxial layer 105 with good flatness and integrity can be prepared; further, since both the nucleation layer 102 and the epitaxial layer 105 are Al-containing nitride layers, the nucleation layer 102 is more conducive to the growth of the epitaxial layer 105, thereby further increasing the probability of the epitaxial layer 105 nucleating on the nucleation layer platform, increasing the difference in nucleation probability between the nucleation layer platform and the channel 104, so as to further form the epitaxial layer 105 that covers the upper surface of the nucleation layer platform and covers the opening of the channel 104 and has good flatness and integrity.

[0058] Specifically, from Figure 11a it can be seen that the growth process of the epitaxial layer 105 has strong selectivity between the nucleation layer platform and the channel 104. In the initial stage of growth, the epitaxial layer 105 covers the nucleation layer platform but exposes the surface of the channel 104. Thus, when the epitaxial layer 105 grows laterally upward above the channel 104 subsequently, the influence of nucleation on the surface of the channel 104 on the lateral growth of the epitaxial layer 105 can be reduced. Further, since both the nucleation layer 102 and the epitaxial layer 105 are Al-containing nitride layers, the nucleation layer 102 is more conducive to the growth of the epitaxial layer 105, thereby further increasing the difference in nucleation probability between the nucleation layer platform and the channel 104, so as to further form the epitaxial layer 105 that covers the nucleation layer platform, covers the opening of the channel 104 and has good flatness and integrity, as Figure 11b shown.

[0059] As an example, it is preferred that the nucleation layer 102 and the epitaxial layer 105 are made of the same material, so as to further increase the nucleation probability of the epitaxial layer 105 on the nucleation layer platform, and form the epitaxial layer 105 with good flatness and integrity. The nucleation layer 102 and the epitaxial layer 105 can both be AlN layers or AlGaN layers at the same time. Of course, the nucleation layer 102 and the epitaxial layer 105 can also adopt different Al-containing nitride layers, and no excessive restrictions are imposed here.

[0060] As an example, it may further include the steps of forming an N-type epitaxial layer, a P-type epitaxial layer, a light-emitting layer and an electrode on the upper surface of the epitaxial layer 105 to fabricate a semiconductor device.

[0061] Specifically, such as Figure 9 and Figure 10 , the MOCVD method can be used to sequentially deposit and prepare an N-type GaN layer 106, a quantum well layer 107 and a P-type GaN layer 108 on the upper surface of the epitaxial layer 105. Then, a P-type electrode layer 109 electrically connected to the P-type GaN layer 108 is fabricated on the P-type GaN layer 108, and an N-type electrode layer 110 electrically connected to the N-type GaN layer 106 is fabricated on the N-type GaN layer 106 to form an electrical channel and fabricate the semiconductor device. Among them, the structure and fabrication method of the semiconductor device are not limited thereto, and the required epitaxial structure can be fabricated on the epitaxial layer 105 according to needs to expand the application of the semiconductor structure.

[0062] This embodiment also provides a semiconductor structure, and the semiconductor structure can be fabricated by the above fabrication method, but is not limited thereto.

[0063] Such as Figure 8 , the semiconductor structure includes a substrate 101, a nucleation layer 102, a channel 104 and an epitaxial layer 105; wherein, the nucleation layer 102 is formed on the substrate 101, the nucleation layer 101 covers the upper surface of the substrate 101, and the nucleation layer is an Al-containing nitride layer, and the crystal orientation of the nucleation layer 102 is the (0001) crystal orientation; the channel 104 penetrates through the nucleation layer 102, and the bottom of the channel 104 is located in the substrate 101 to divide the nucleation layer 102 into a plurality of nucleation layer platforms arranged at intervals; the epitaxial layer 105 is an Al-containing nitride layer, the epitaxial layer 105 is formed on the nucleation layer platform and covers the upper surface of the nucleation layer platform, and the epitaxial layer 105 covers the opening of the channel 104.

[0064] In this embodiment, due to the particularity of the structure formed by the channel 104 and the nucleation layer platform having a (0001) crystal plane, the growth process of the epitaxial layer 105 can have strong selectivity between the nucleation layer platform and the channel 104, reducing the probability of the epitaxial layer 105 nucleating on the surface of the channel 104. When the epitaxial layer 105 grows laterally above the channel 104, the influence of nucleation on the surface of the channel 104 on the lateral growth of the epitaxial layer 105 can be reduced, and the epitaxial layer 105 with good flatness and integrity can be prepared. Further, since both the nucleation layer 102 and the epitaxial layer 105 are Al-containing nitride layers, the nucleation layer 102 is more conducive to the growth of the epitaxial layer 105, thereby further increasing the probability of the epitaxial layer 105 nucleating on the nucleation layer platform, increasing the nucleation probability difference between the nucleation layer platform and the channel 104, so as to further form the epitaxial layer 105 that covers the upper surface of the nucleation layer platform and covers the opening of the channel 104 and has good flatness and integrity.

[0065] As an example, the substrate 101 may include a sapphire substrate, an Si substrate, an SiC substrate, a ZnO substrate, an Al 2 O 3 substrate, etc. One of them can be specifically selected according to needs to expand the application range of the semiconductor structure.

[0066] As an example, the nucleation layer 102 may include one or a combination of an AlN layer and an AlGaN layer; the epitaxial layer 105 may include one or a combination of an AlN layer and an AlGaN layer. Preferably, the nucleation layer 102 and the epitaxial layer 105 are made of the same material to further form the epitaxial layer 105 with good flatness and integrity.

[0067] As an example, the morphology of the opening of the channel 104 may include one or a combination of a circle and a polygon; the vertical cross-sectional morphology of the channel 104 may include one or a combination of a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid.

[0068] As an example, the width W1 of the opening of the channel 104 ≤ 1 μm; the depth D1 of the channel 104 ≤ 2 μm; the thickness range of the nucleation layer platform includes 10 nm ≤ T ≤ 50 nm; the width W2 of the nucleation layer platform ≤ 5 μm. Among them, it is preferably W1 ≤ 0.3 μm, D1 ≤ 0.5 μm, W2 ≤ 2 μm, so as to further reduce the nucleation probability of the epitaxial layer 105 on the surface of the channel 104 when forming the epitaxial layer 105, so as to increase the selectivity growth difference between the epitaxial layer 105 on the nucleation layer platform and the channel 104. When the epitaxial layer 105 grows laterally above the channel 104, the influence of nucleation on the surface of the channel 104 on the lateral growth of the epitaxial layer 105 is reduced, so as to further form the epitaxial layer 105 with good flatness and integrity.

[0069] As an example, the channel 104 may include one of periodic arrangement and non-periodic arrangement. The number, morphology and distribution of the channels 104 can be set as needed. Among them, the channels 104 can adopt one of the same morphology or different morphologies and one of equal-spacing distribution and non-equal-spacing distribution to form a periodic arrangement or a non-periodic arrangement, and no excessive restrictions are imposed here.

[0070] This embodiment also provides a semiconductor device, and the semiconductor device includes the semiconductor structure.

[0071] Specifically, as Figure 10 , the upper surface of the epitaxial layer 105 may further include an N-type GaN layer 106, a quantum well layer 107 and a P-type GaN layer 108, a P-type electrode layer 109 electrically connected to the P-type GaN layer 108 and an N-type electrode layer 110 electrically connected to the N-type GaN layer 106 to form an electrical channel and constitute the semiconductor device. Among them, the structure of the semiconductor device is not limited thereto, and an epitaxial structure can be prepared on the epitaxial layer 105 as needed to expand the application of the semiconductor structure.

[0072] In summary, for the semiconductor structure, device and its manufacturing method of the present invention, a nucleation layer is formed on a substrate, and the nucleation layer is divided into a plurality of nucleation layer platforms arranged at intervals through channels located in the nucleation layer and the substrate. Since the crystal orientation of the nucleation layer is the (0001) crystal orientation, there is a certain selective growth property between the nucleation layer platform with the (0001) crystal plane and the channel when the epitaxial layer is formed, that is, when the epitaxial layer is formed, the nucleation probability of the epitaxial layer on the nucleation layer platform with the (0001) crystal plane is greater than the nucleation probability in the channel. Therefore, through lateral growth, the epitaxial layer can form an epitaxial layer that covers the nucleation layer platform and the channel opening, and has a flat and complete surface. Further, since both the nucleation layer and the epitaxial layer are Al-containing nitride layers, the nucleation layer is more conducive to the growth of the epitaxial layer, thereby increasing the nucleation probability of the epitaxial layer on the nucleation layer platform, and further increasing the nucleation probability difference between the epitaxial layer on the nucleation layer platform and the channel, so as to further prepare an epitaxial layer with good flatness and integrity.

[0073] The above embodiments merely illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that, it includes the following steps: providing a substrate; forming a nucleation layer on the substrate, the nucleation layer covering the upper surface of the substrate, and the nucleation layer being an Al-containing nitride layer, and the crystal orientation of the nucleation layer being the (0001) crystal orientation; forming a photoresist layer on the upper surface of the nucleation layer, patterning the photoresist layer to form an etching window, and then using the patterned photoresist layer as a mask to etch the nucleation layer and the substrate to form a plurality of spaced channels, the channels penetrating the nucleation layer, and the bottom of the channels being located in the substrate, so as to divide the nucleation layer into a plurality of spaced nucleation layer platforms; forming an epitaxial layer on the nucleation layer platform, the epitaxial layer being an Al-containing nitride layer, the epitaxial layer covering the upper surface of the nucleation layer platform, and the epitaxial layer covering the opening of the channel.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: the nucleation layer includes one or a combination of an AlN layer and an AlGaN layer; the epitaxial layer includes one or a combination of an AlN layer and an AlGaN layer; the method for forming the nucleation layer includes PVD; the method for forming the epitaxial layer includes MOCVD.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: the morphology of the opening of the channel includes one or a combination of a circle and a polygon; the vertical cross-sectional morphology of the channel includes one or a combination of a "U" shape, a "V" shape, a rectangle, a square, and a trapezoid.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: the thickness range of the nucleation layer platform includes 10 nm to 50 nm; the width range of the nucleation layer platform is less than or equal to 5 μm.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: the width range of the opening of the channel is less than or equal to 1 μm; the depth range of the channel is less than or equal to 2 μm.

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