Multiplexed registers

Abstract

The present invention provides a multi-way parallel register for use in computing devices. The register comprises multiple input terminals for inputting data; a clock control terminal for inputting clock signals; multiple output terminals for outputting data; multiple dynamic D flip-flops connected in parallel for latching and / or reading the data under the control of the clock signals; and a clock buffer for buffering the clock signals input from the clock control terminals and then providing clock signals to the multiple dynamic D flip-flops. This register can simplify the back-end layout and routing process, reduce design difficulty, improve performance, and increase practicality.

Description

Technical Field

[0001] The present invention relates to a clock-controlled storage device, and in particular to a multi-way parallel register used in a computing device. Background Art

[0002] The D flip-flop is widely used and can be used for digital signal storage, shift register, frequency division, and waveform generator. The D flip-flop has two inputs, data (Data) and clock (CLK), and one output (Q), which can write data to the D flip-flop or read data from it.

[0003] CN1883116A discloses a Figure 1 The illustrated positive feedback D flip-flop circuit 106 includes an analog switch 300, an inverter 302, an analog switch 304, an inverter 306, an inverter 308, an analog switch 310, an inverter 312, and an analog switch 314. Analog switches 300, 304, 310, and 314 use P-channel / N-channel transistors, and switch operation is performed by CKP, which is in phase with CK, and CKN, which is in phase opposite to CK. Inverters 302, 306, 308, and 312 are CMOS inverters. As can be seen, a conventional D flip-flop generally requires 16 PMOS / NMOS transistors, which occupies a large area.

[0004] For computing devices that require a large number of repetitive logic calculation pipelines, several D flip-flops are needed to store data. This leads to the disadvantages of increased chip area, slower computing speed, and difficult to control leakage in computing devices requiring a large number of D flip-flops.

[0005] CN1883116A also discloses a method such as Figure 2 The dynamic D flip-flop circuit 102 shown includes a first analog switch 200, a first inverter 202, a second analog switch 204, and a second inverter 206. The dynamic D flip-flop circuit 102 forms a sample-and-hold circuit using parasitic capacitances such as the analog switches of the first analog switch 200 and the second analog switch 204, and the gate capacitances of the first inverter 202 and the second inverter 206, as well as wiring capacitance.

[0006] The register composed of the above-mentioned dynamic D flip-flop has the problems of difficult control of analog switches and slow access speed. Summary of the Invention

[0007] In order to solve the above problems, the present invention provides a multi-way parallel register for a computing device, which can effectively reduce the design difficulty, reduce the chip area, reduce power consumption, and achieve clock synchronization.

[0008] In order to achieve the above object, the present invention provides a multi-way parallel register, comprising:

[0009] Multiple input terminals for inputting data;

[0010] A clock control terminal for inputting a clock signal;

[0011] Multiple output terminals for outputting data;

[0012] a clock buffer, configured to buffer the clock signal input from the clock control terminal and then provide the clock signal to the plurality of dynamic D flip-flops;

[0013] a plurality of dynamic D flip-flops connected in parallel between the plurality of input terminals and the plurality of output terminals, and configured to latch and / or read the data under the control of a clock signal, each of the plurality of dynamic D flip-flops comprising a first latch unit, a second latch unit, and an output driver unit;

[0014] Among them, the second latch unit realizes the output of three states of high level, low level and high resistance through a single device under the control of the clock signal; the first latch unit adopts a delay unit, and / or the clock buffer adopts an ultra-low threshold unit.

[0015] In the above-mentioned multi-way parallel register, the second latch unit is a tri-state inverter.

[0016] In the above-mentioned multi-way parallel register, the clock buffer includes a plurality of cascaded buffer units.

[0017] The above-mentioned multi-way parallel register, wherein the three-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series between the power supply and the ground in sequence.

[0018] In the above-mentioned multi-way parallel register, the first PMOS transistor and the second NMOS transistor are switched according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are in opposite phases.

[0019] In the above-mentioned multi-way parallel register, the second PMOS transistor and the first NMOS transistor are switched according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are in opposite phases.

[0020] The use of the multi-way parallel register of the present invention can reduce the chip area by nearly 30%, thereby reducing chip production costs and increasing product competitiveness. It can also simplify the back-end layout and wiring design process, reduce design difficulty, improve performance, and increase practicality.

[0021] In order to better achieve the above-mentioned purpose, the present invention also provides a data operation unit, including an interconnected control circuit, an operation circuit, and multiple multi-way parallel registers, wherein the multiple multi-way parallel registers are connected in series and / or in parallel; wherein the multiple multi-way parallel registers are any one of the multi-way parallel registers described above.

[0022] In order to better achieve the above-mentioned purpose, the present invention also provides a chip, which adopts any one of the above-mentioned data operation units.

[0023] In order to better achieve the above objectives, the present invention also provides a computing power board for a computing device, which adopts any of the above chips.

[0024] In order to better achieve the above-mentioned purpose, the present invention also provides a computing device, comprising a power board, a control board, a connection board, a radiator, and a plurality of computing boards, wherein the control board is connected to the computing board through the connection board, the radiator is arranged around the computing board, and the power board is used to provide power to the connection board, the control board, the radiator, and the computing board, wherein the computing board is any one of the computing boards described above.

[0025] The computing device of the present invention can better save chip area, reduce production costs, and further reduce power consumption of the computing device.

[0026] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention.

[0027] Certain terms are used throughout this specification and the following claims to refer to specific components. A person skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and the following claims do not distinguish components by name, but rather by their functional differences.

[0028] Throughout this specification and the following claims, the words "include" and "comprising" are open-ended terms and should be interpreted as meaning "including, but not limited to." Furthermore, the word "connect" is intended to encompass both direct and indirect electrical connections. Indirect electrical connections include connection through other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of an existing positive feedback D flip-flop;

[0030] Figure 2 It is a schematic diagram of an existing dynamic D flip-flop;

[0031] Figure 3 This is a schematic diagram of a multi-way parallel register of the present invention;

[0032] Figure 4A This is a schematic diagram of a dynamic D flip-flop circuit according to an embodiment of the present invention;

[0033] Figure 4B A schematic diagram of a dynamic D flip-flop circuit according to another embodiment of the present invention;

[0034] Figure 5A This is the equivalent circuit diagram of the dynamic D flip-flop of the present invention when writing data;

[0035] Figure 5B This is an equivalent circuit diagram of the dynamic D flip-flop in the data holding state of the present invention;

[0036] Figure 6 This is a timing diagram of the dynamic D flip-flop of the present invention;

[0037] Figure 7 Schematic diagram of the data operation unit of the present invention;

[0038] Figure 8 Schematic diagram of the chip of the present invention;

[0039] Figure 9 This is a schematic diagram of the hashboard of the present invention;

[0040] Figure 10 Schematic diagram of the computing device of the present invention.

[0041] Wherein, the reference numerals:

[0042] 100: Parasitic capacitance 106: Positive feedback D flip-flop circuit

[0043] 200, 204, 300, 304, 310, 314: Analog switches:

[0044] 400: Multi-way parallel register 102, 401, 500, 600: Dynamic D flip-flop

[0045] 402: Clock buffer 501, 601: Transmission gate

[0046] 502, 602: tri-state inverter

[0047] 202, 206, 302, 306, 308, 312, 503, 603: Inverters

[0048] 506, 510, 511: PMOS transistors 507, 512, 513: NMOS transistors

[0049] 508, 509, 514, 515: Gate terminals 550, 551, 650, 651: Nodes

[0050] D[n], 504: input terminal Q[n], 505: output terminal

[0051] CLK, CLKN, CLKP, clock signals DETAILED DESCRIPTION

[0052] The structural principle and working principle of the present invention are described in detail below with reference to the accompanying drawings:

[0053] Figure 3 This is a schematic diagram of the multi-way parallel register of the present invention. Figure 3 As shown, a multi-way parallel register 400 is composed of multiple parallel-connected dynamic D flip-flops 401, a clock buffer 402, multiple input terminals D[n:0], and multiple output terminals Q[n:0]. Each circuit is composed of a dynamic D flip-flop 401, each of which includes an input terminal D[n] and an output terminal Q[n]. The clock buffer 402 receives an external clock signal CLK, buffers the clock signal CLK, and then provides clock signals CLKP and CLKN to each dynamic D flip-flop.

[0054] Example 1:

[0055] Figure 4A FIG. 4 is a circuit diagram of a dynamic D flip-flop according to an embodiment of the present invention.

[0056] like Figure 4AAs shown, the first latch unit of the dynamic D flip-flop 500 is a transmission gate 501. The transmission gate 501 uses a PMOS transistor 506 and an NMOS transistor 507 connected in parallel to form an analog switch under the control of a clock signal. One end of the transmission gate 501 is connected to the input terminal 504 of the dynamic D flip-flop 500. The gate terminal 508 of the PMOS transistor 506 is controlled by the clock signal CLKP, and the gate terminal 509 of the NMOS transistor 507 is controlled by the clock signal CLKN with a phase opposite to CLKP. When CLKP is high and CLKN is low, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are both off, the transmission gate 501 is closed, and the data at the input terminal 504 cannot be transmitted to the other end of the transmission gate 501. That is, the data at the first node 550 at the other end of the transmission gate 501 is latched and remains in its original state. When CLKP is low and CLKN is high, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are turned on, the transmission gate 501 is turned on, and the data at the input terminal 504 is transmitted to the other end of the transmission gate 501 through the transmission gate 501. The data at the first node 550 is rewritten to the same data as the data at the input terminal 504.

[0057] like Figure 4A As shown, the second latch unit of the dynamic D flip-flop 500 is a tri-state inverter 502, which includes PMOS transistors 510 and 511 and NMOS transistors 512 and 513. The gates of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form the input of the tri-state inverter 502. The source of the PMOS transistor 510 is connected to the power supply VDD, and the source of the NMOS transistor 513 is connected to the ground GND. The drains of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form the output of the tri-state inverter 502. The source of the PMOS transistor 511 is connected to the drain of the PMOS transistor 510, and the source of the NMOS transistor 512 is connected to the drain of the NMOS transistor 513.

[0058] The gate terminal 514 of the PMOS transistor 510 is controlled by the clock signal CLKN, and the gate terminal 515 of the NMOS transistor 513 is controlled by the clock signal CLKP, serving as the clock control terminal of the tri-state inverter 502 .

[0059] When CLKP is low and CLKN is high, the PMOS transistor 510 and the NMOS transistor 513 are both in a non-conducting state, the tri-state inverter 502 is in a high-impedance state, and the data at the first node 550 cannot pass through the tri-state inverter 502. The data at the second node 551 is latched and maintains its original state, thus serving as a data storage.

[0060] When CLKP is at a high level and CLKN is at a low level, the PMOS transistor 510 and the NMOS transistor 513 are both in the on state, and the tri-state inverter 502 inverts the data at its input end, that is, inverts the data at the first node 550 and outputs it to the second node 551, rewriting the data at the second node 551.

[0061] like Figure 4A As shown, the output driving unit is an inverter 503, which inverts the data received from the tri-state inverter 502 to form data with the same phase as the data at the input terminal 504 of the dynamic D flip-flop, and outputs the data through the output terminal 505. At the same time, the output driving unit can also improve the driving capability of the data.

[0062] Example 2:

[0063] like Figure 4B As shown, the first latch unit of dynamic D flip-flop 600 is a transmission gate 601. Transmission gate 601 uses a PMOS transistor 606 and an NMOS transistor 607 connected in parallel to form an analog switch under the control of a clock signal. One end of transmission gate 601 is connected to input 604 of dynamic D flip-flop 600. The gate end 608 of PMOS transistor 606 is controlled by clock signal CLKP, and the gate end 609 of NMOS transistor 607 is controlled by clock signal CLKN, which has a phase opposite to CLKP. When CLKP is high and CLKN is low, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are both non-conductive, the transmission gate is closed, and the data at the input terminal 604 cannot be transmitted to the other end of the transmission gate 601. The data at the first node 650 is latched and maintained in its original state. When CLKP is low and CLKN is high, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are conductive, the transmission gate 601 is turned on, the data at the input terminal 604 is output to the other end through the transmission gate 601, and the data at the first node 650 is rewritten to the same data as the data at the input terminal 604.

[0064] like Figure 4BAs shown, the second latch unit of the dynamic D flip-flop 600 is a tri-state inverter 602, which includes PMOS transistors 610 and 611 and NMOS transistors 612 and 613. The gates of the PMOS transistor 610 and the NMOS transistor 613 are connected together to form the input of the tri-state inverter 602. The source of the PMOS transistor 610 is connected to the power supply VDD, and the source of the NMOS transistor 613 is connected to the ground GND. The drains of the PMOS transistor 611 and the NMOS transistor 612 are connected together to form the output of the tri-state inverter 602. The source of the PMOS transistor 611 is connected to the drain of the PMOS transistor 610, and the source of the NMOS transistor 612 is connected to the drain of the NMOS transistor 613.

[0065] The gate terminal 614 of the PMOS transistor 611 is controlled by the clock signal CLKN, and the gate terminal 615 of the NMOS transistor 612 is controlled by the clock signal CLKP, serving as the clock control terminal of the tri-state inverter 602 .

[0066] When CLKP is low and CLKN is high, the PMOS transistor 611 and the NMOS transistor 612 are both in a non-conducting state, the tri-state inverter 602 is in a high-impedance state, and the data at the first node 650 cannot pass through the tri-state inverter 602. The data at the second node 651 is latched and maintains its original state, thus serving as a data storage.

[0067] When CLKP is high and CLKN is low, the PMOS transistor 611 and the NMOS transistor 612 are both in the on state, and the tri-state inverter 602 inverts the data at its input end, that is, inverts the data at the first node 650 and outputs it to the second node 651, rewriting the data at the second node 651.

[0068] like Figure 4B As shown, the output driving unit is an inverter 603, which inverts the data received from the tri-state inverter 602 to form data with the same phase as the data at the input terminal 604 of the dynamic D flip-flop, and outputs the data through the output terminal 605. At the same time, the output driving unit can improve the driving capability of the data.

[0069] The working principle of the dynamic D flip-flop of the present invention is described in detail below.

[0070] Figure 5A This is the equivalent circuit diagram of the dynamic D flip-flop of the present invention when writing data, Figure 5B This is the equivalent circuit diagram of the dynamic D flip-flop in the data holding state of the present invention.

[0071] Combine Figure 4A 、 Figure 4B as well as Figure 5A As shown, when CLKP is high and CLKN is low, the clock-controlled transistors of the tri-state inverters 502 and 602 are turned on, and the data transmitted from the transmission gates 501 and 601 is written into the parasitic capacitor 100. When the input data is "0", the PMOS transistors 510, 511, 610, and 611 of the tri-state inverters 502 and 602 are all turned on, forming a pull-up path to charge the parasitic capacitor 100, causing the second nodes 551 and 651 to become high, and the data becomes "1". When the input data is "1", the NMOS transistors 512, 513, 612, and 613 of the tri-state inverters 502 and 602 are all turned on, forming a pull-down path to discharge the parasitic capacitor 100, causing the second nodes 551 and 651 to become low, and the data becomes "0".

[0072] like Figure 5B As shown, after the parasitic capacitor 100 is charged, if the tri-state inverters 502 and 602 are in a high-impedance state under the control of the clock signal, the parasitic capacitor 100 will not be further charged, and the data at the second nodes 551 and 651 will be maintained. On the other hand, due to the leakage current of the NMOS transistors 512, 513, 612, and 613, the charge on the parasitic capacitor 100 will gradually leak away, and the high level at the second nodes 551 and 651 will invert to a low level after a certain period of time. The data stored in the parasitic capacitor 100 will change from "1" to "0", ultimately causing data errors.

[0073] Assuming that the charge generated on the parasitic capacitor 100 is Q, the capacitance of the parasitic capacitor 100 is C, and the voltage across the parasitic capacitor plate is V, then

[0074] Q = C * V.

[0075] If the leakage current is I leakage , then the leakage time t is

[0076] t = Q / I leakage = C * V / I leakage 。

[0077] Under existing production processes, the data stored in parasitic capacitor 100 can be maintained for approximately 5 nanoseconds. In other words, if the data stored in the parasitic capacitor is periodically updated during the data retention period, data errors will not occur. Existing computing devices generally operate at frequencies above 500 MHz, far exceeding the required data update frequency, making the dynamic D flip-flop of the present invention applicable to computing devices.

[0078] Figure 6This is the timing diagram of the dynamic D flip-flop of the present invention. Figure 6 As shown, when CLKP is low and CLKN is high, the first latch unit is conductive, and the data at input terminal D passes through the first latch unit. The second latch unit is non-conductive, and the output of the dynamic D flip-flop maintains its original state. When CLKP rises, CLKP jumps to a high level and CLKN jumps to a low level, the first latch unit is non-conductive, cutting off the data input at input terminal D. The second latch unit is conductive, and the retained data at input terminal D is output through output terminal Q. Thus, it can be seen that the state change of the output terminal of the dynamic D flip-flop of the present invention occurs when the rising edge of the clock signal CLKP arrives. When CLKP is high and CLKN is low, the output state remains unchanged.

[0079] The present invention also provides a data operation unit, Figure 7 Schematic diagram of the data operation unit of the present invention. Figure 7 As shown, the data operation unit 700 includes a control circuit 701, an operation circuit 702, and multiple dynamic D flip-flops 500 and 600. The control circuit 701 refreshes the data in the dynamic D flip-flops 500 and 600 and reads data from the dynamic D flip-flops 500 and 600. The operation circuit 702 operates on the read data, and the control circuit 701 outputs the operation result.

[0080] The present invention also provides a chip. Figure 8 FIG. 1 is a schematic diagram of the chip of the present invention. Figure 8 As shown, the chip 800 includes a control unit 801 and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.

[0081] The present invention also provides a computing board. Figure 9 This is a schematic diagram of the hashboard of the present invention. Figure 9 As shown, each computing board 900 includes one or more chips 800.

[0082] The present invention also provides a computing device, Figure 10 Schematic diagram of the computing device of the present invention. Figure 10 As shown, each computing device 1000 includes a connection board 1001, a control board 1002, a heat sink 1003, a power board 1004, and one or more hash boards 900. The control board 1002 is connected to the hash board 900 via the connection board 1001, and the heat sink 1003 is arranged around the hash board 900. The power board 1004 is used to provide power to the connection board 1001, control board 1002, heat sink 1003, and hash board 900.

[0083] It should be noted that, in the description of the present invention, the terms "horizontal", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0084] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

[0085] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A multi-way parallel register, characterized in that: include: Multiple input terminals for inputting data; A clock control terminal for inputting a clock signal; Multiple output terminals for outputting data; a clock buffer, configured to buffer the clock signal input from the clock control terminal and then provide the clock signal to a plurality of dynamic D flip-flops; a plurality of dynamic D flip-flops connected in parallel between the plurality of input terminals and the plurality of output terminals, and configured to latch and / or read the data under the control of a clock signal, each of the plurality of dynamic D flip-flops comprising a first latch unit, a second latch unit, and an output driver unit; Wherein, the second latch unit realizes output of three states of high level, low level and high impedance through a single device under the control of the clock signal.

2. The multi-way parallel register according to claim 1, wherein: The second latch unit is a tri-state inverter.

3. The multi-way parallel register according to claim 2, wherein: The clock buffer includes a plurality of cascaded buffer units.

4. The multi-way parallel register according to claim 3, wherein: The tri-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and a ground.

5. The multi-way parallel register according to claim 4, wherein: The first PMOS transistor and the second NMOS transistor are switched on and off according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are in opposite phases.

6. The multi-way parallel register according to claim 4, wherein: The second PMOS transistor and the first NMOS transistor are switched on and off according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are in opposite phases.

7. A data operation unit comprising a control circuit, an operation circuit, and a plurality of multi-way parallel registers connected in series and / or in parallel; characterized in that: The multiple parallel registers are the multiple parallel registers described in any one of claims 1-6.

8. A chip, characterized in that: Includes any one of the data operation units described in claim 7.

9. A hashboard for computing equipment, characterized in that: The method comprises a plurality of chips according to any one of claims 8.

10. A computing device comprising a power board, a control board, a connection board, a radiator, and a plurality of hash boards, wherein the control board is connected to the hash boards via the connection board, the radiator is disposed around the hash boards, and the power board is used to provide power to the connection board, the control board, the radiator, and the hash boards, characterized in that: The computing board is any one of the computing boards described in claim 9.

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