Semiconductor device and bus generator

Abstract

Embodiments of the present disclosure relate to semiconductor devices and bus generators. A master device issues an access request to a memory. A memory controller receives the access request via a bus. An access control unit controls the output of an access request issued by the master device to the memory controller by granting access rights. The access control unit manages the number of grantable rights indicating the number of times an access right can be granted based on a weight equal to or greater than 0 and less than 1 according to the probability that the granted access right is used, and grants an access right within the range of the number of grantable rights.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2018-118706 filed on June 22, 2018 (including the specification, drawings, and abstract) is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to semiconductor devices, and more particularly to semiconductor devices for accessing memories.

[0004] The present invention also relates to a bus generator for generating a bus in a semiconductor device.

[0005] International Publication No. 2017 / 056132 discloses access control in a bus system in which a plurality of bus masters are connected to a common bus. The semiconductor device described in International Publication No. 2017 / 056132 includes a plurality of masters, a memory controller, a bus connecting the plurality of masters and the memory controller, and a central bus controller. International Publication No. 2017 / 056132 discloses that the central bus controller monitors the traffic volume of each master and selects a master to be granted access rights based on the reserved bandwidth, the monitored traffic volume, and the number of times of grantable permissions of each master.

[0006] In International Publication No. 2017 / 056132, the central bus controller controls the granting of access rights to the request issuing control unit of the sub-bus controller corresponding to each master. When access rights are granted from the central bus controller and when the master issues an access request, the request issuing control unit outputs an access request to the memory controller. When access rights are granted and the master does not issue an access request, the request issuing control unit returns the access rights to the central bus controller without using the access rights. When access rights are not granted from the central bus controller, the request issuing control unit prohibits the output of the access request issued by the master to the memory controller. In other words, in International Publication No. 2017 / 056132, the requests of the masters not granted access rights are masked on the bus between the memory controller and the masters.

[0007] In International Publication No. 2017 / 056132, when a buffer in a memory controller is released, a central bus controller receives a buffer release notification from the memory controller. Each time access permission is granted, the central bus controller decrements the number of times access permission can be granted by 1, and each time the buffer is released, the central bus controller increments the number of times access permission can be granted by 1. By granting access permission according to the processing state in the memory controller, it is possible to avoid the buffer becoming full while there are still unprocessed access requests, and it is possible to avoid a situation where the memory controller does not accept access requests that require low latency. Summary of the Invention

[0008] Here, in International Publication No. 2017 / 056132, it takes several cycles to about twenty cycles for the access permission granted by the central bus controller to reach the request issuing control unit, depending on the physical distance between the central bus controller and the request issuing control unit. Similarly, in the case of returning the access permission, it takes several cycles to about twenty cycles for the returned access permission to reach the central bus controller. Before returning the access permission, the central bus controller recognizes that the request issuing control unit uses the access permission, and the access permission is still consumed during the period from granting the access permission to returning it. Therefore, it is desirable to use more effectively the access permission that can be returned.

[0009] According to the description of this specification and the drawings, other objects and new features will be clear.

[0010] According to one embodiment, a semiconductor device includes an access control unit that controls the output of access requests issued by a master device to a memory controller by granting access permission. The access control unit manages the number of times access permission can be granted based on a weight equal to or greater than 0 and less than 1 according to the probability that the granted access permission is used, and grants access permission within the range of the number of times access permission can be granted.

[0011] According to the above embodiment, even in various situations, congestion of requests on the bus can be eliminated, and memory efficiency can be improved. Brief Description of the Drawings

[0012] Figure 1 is a block diagram showing an electronic device including a semiconductor device according to a first embodiment;

[0013] Figure 2 is a block diagram showing an example of the configuration of a central bus controller;

[0014] Figure 3 is a block diagram showing an example of the configuration of a permission granting selection control unit;

[0015] Figure 4is a flowchart showing the operation steps of parts related to the management of the number of times permissions can be granted;

[0016] Figure 5 is a block diagram showing an electronic device in one aspect;

[0017] Figure 6 is a block diagram showing an example of the configuration of a permission granting selection control unit used in an electronic device according to a second embodiment;

[0018] Figure 7 is a block diagram showing an electronic device including a semiconductor device according to a third embodiment;

[0019] Figure 8 is a block diagram showing the configuration of a central bus controller used in a third embodiment;

[0020] Figure 9 is a block diagram showing a part of an electronic device in one aspect;

[0021] Figure 10 is a memory controller used in an electronic device according to a fourth embodiment;

[0022] Figure 11 is a block diagram showing an example of the hardware configuration of a bus generator;

[0023] Figure 12 is a flowchart showing a schematic process of bus design;

[0024] Figure 13 is a diagram showing an example of a screen for inputting setting information; and

[0025] Figure 14 is a block diagram showing the input data to the bus generator and the output data from the bus generator. Detailed Description of the Invention

[0026] Before describing the embodiments, the background that gives rise to the following embodiments will be described. In an actual product having a master device for accessing a double data rate (DDR) memory, the effective bandwidth of the DDR memory varies by about 50% to 75% depending on the situation, and high efficiency is required. In addition, while it is necessary to shorten the access latency of the master device that requires real-time performance, this also varies, and the access latency must always be set to a low latency. When a certain degree of latency is allowed, the memory access efficiency can be enhanced by waiting until a certain number of access requests to the memory are accumulated to some extent in the memory controller and then performing scheduling (where the processing order of the access requests is changed in consideration of the type (read and write), address, etc. of the memory access). However, in the case where requests requiring low latency with high priority are prioritized, it is not possible to wait until a certain number of access requests are accumulated in the memory controller, and the number of access requests to be scheduled decreases. Therefore, effective memory access cannot be achieved, and the bandwidth efficiency decreases. Therefore, a memory access system that can satisfy these conflicting requirements is needed.

[0027] The utilization rate of the access right varies depending on the master device and the situation, and in some cases, the number of access rights returned may be small, while in other cases, the number of access rights returned may be large. In other words, in some cases, the utilization rate of the access right may be high, while in other cases, the utilization rate of the access right may be low. When the utilization rate of the access right for each master device is high, the memory efficiency is high even if the upper limit of the number of times the access right is granted (the maximum number of times the right can be granted) is small. However, it has been found that when the maximum number of times the right can be granted is set to a large number according to a situation where the utilization rate is very low, if the utilization rate of the access right for each master device increases, the access requests become congested on the bus and the latency deteriorates. As a result of this consideration, the present inventors have proposed the following embodiments.

[0028] Preferred embodiments will be described below with reference to the drawings. For the sake of clarity of illustration, the following description and drawings are appropriately or partially omitted and simplified. These elements illustrated as functional blocks for performing various processes in the drawings may be configured in hardware to have a central processing unit (CPU), a memory, or any other circuit, and may be implemented in software to have a program loaded into the memory. Those skilled in the art can understand that these functional blocks can be implemented in various forms, for example, only by hardware, software, or a combination thereof, and are not limited to any of these. In the drawings, the same constituent elements are identified by the same reference numerals and will not be described repeatedly.

[0029] The above program is stored using various types of non-transitory computer-readable media and can be provided to a computer. Non-transitory computer-readable media include various types of basic recording media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disks), magneto-optical recording media (e.g., magneto-optical discs), compact disc read-only memory (CD-ROM), CD-R, CD-R / W, and semiconductor memories (e.g., mask ROM, programmable ROM (PROM), erasable PROM (EPROM), flash ROM, random access memory (RAM)). The program can be provided to the computer using various types of non-transitory computer-readable media. Examples of non-transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The non-transitory computer-readable media can provide the program to the computer via a wired communication path (such as wires and optical fibers) or a wireless communication path.

[0030] In the following preferred embodiments, as needed and for convenience, separate multiple parts or preferred embodiments will be described. However, unless otherwise stated, they are not mutually unrelated, but rather one part or all of one has a relationship of modification, application examples, details, and supplementary explanations with another. Furthermore, in the following preferred embodiments, in the case of referring to the number of elements (including their quantity, numerical value, quantity, range), unless otherwise stated and unless clearly restricted in principle, the present invention is not limited to the specified numbers, and numbers greater than or less than the specified numbers can be used.

[0031] In the following preferred embodiments, unless otherwise stated and unless they are considered to be obviously necessary in principle, the constituent elements (including operation steps) are not necessarily essential. Similarly, in the following preferred embodiments, in the reference to the form or positional relationship of the constituent elements, unless otherwise stated and unless they are considered to be obviously not necessary in principle, they are intended to include those forms that are approximate or similar to these forms, etc. The same applies to the aforementioned numerical values (including their quantity, numerical value, quantity, range).

[0032] First Embodiment

[0033] Figure 1An electronic device including a semiconductor device according to a first embodiment is shown. The electronic device 10 includes a main device A 20, a main device B 30, a main device X 40, sub-bus controllers 22, 32, and 42, a central bus controller 50, an interconnect 60, a memory controller 70, and a memory 80. Among the components of the electronic device 10, for example, the main device A 20, the main device B 30, the main device X 40, the sub-bus controllers 22, 32, and 42, the central bus controller 50, the interconnect 60, and the memory controller 70 constitute a semiconductor device. Among the components of the semiconductor device, for example, the sub-bus controllers 22, 32, and 42, the interconnect 60, and the memory controller 70 can be configured as hardware circuits. The central bus controller 50 can be configured as a circuit including, for example, a processor.

[0034] The main device A 20, the main device B 30, and the main device X 40 issue access requests to the memory 80. The memory 80 is configured as a memory device such as a double data rate synchronous dynamic random access memory (DDR-SDRAM). The main device A 20, the main device B 30, and the main device X 40 are bus masters and are configured as processors such as a CPU and a graphics processing unit (GPU). The main device A 20, the main device B 30, and the main device X 40 output access requests via respective buses 21, 31, and 41. The access request to the memory 80 includes an access type indicating read or write, address information of an access destination, and the like.

[0035] The main device A 20 is connected to the corresponding sub-bus controller 22 via the bus 21. The sub-bus controller 22 is connected to the interconnect 60 via the bus 24. The sub-bus controller 22 includes a request issuing control unit 23. The request issuing control unit 23 receives the access request issued by the main device A 20 via the bus 21 and controls the output of the received access request to the bus 24.

[0036] The main device B 30 is connected to the corresponding sub-bus controller 32 via the bus 31. The sub-bus controller 32 is connected to the interconnect 60 via the bus 34. The sub-bus controller 32 includes a request issuing control unit 33. Similarly, the main device X 40 is connected to the corresponding sub-bus controller 42 via the bus 41. The sub-bus controller 42 is connected to the interconnect 60 via the bus 44. The sub-bus controller 42 includes a request issuing control unit 43.

[0037] The request issue control unit 23 receives an access request from the master device A. When access permission is granted by the central bus controller 50, the request issue control unit 23 outputs the access request issued by the master device A 20 to the interconnect 60 via the bus 24. The request issue control unit 23 outputs a notification signal indicating whether the access request has been output to the interconnect 60 to the central bus controller 50. When outputting an access request to the interconnect 60, the request issue control unit 23 outputs a notification signal (permission usage notification) indicating that the access permission has been used to the central bus controller 50. When access permission is granted and no access request has been received from the corresponding master device, the request issue control unit 23 outputs a notification signal (return notification) indicating that the access permission is returned without being used to the central bus controller 50. When access permission is not granted, the request issue control unit 23 prohibits the output of the access request issued by the master device A 20 to the interconnect 60. The functions of the request issue control units 33 and 43 are the same as those of the request issue control unit 23.

[0038] The interconnect 60 receives access requests issued by the master device A 20, the master device B 30, and the master device X 40 via the buses 24, 34, and 44. The interconnect 60 is, for example, a bus arbiter and arbitrates access requests input from multiple master devices. The interconnect 60 outputs the access request issued by the master device with the highest priority to the memory controller 70 according to the priority set for each master device. For example, when the interconnect 60 receives access requests from the master device A 20, the master device B 30, and the master device X 40. When obtaining a response to the access request output to the memory controller 70, the interconnect 60 selects the access request of the master device with the second highest priority and outputs the access request to the memory controller 70.

[0039] The memory controller 70 is connected to the master device A 20, the master device B 30, and the master device X 40 via a bus, the interconnect 60, etc., and accesses the memory 80 according to the access request received via the interconnect 60. Although Figure 1 An example in which the electronic device 10 has three master devices is shown, but the number of master devices is not particularly limited. The electronic device 10 may have at least one master device for issuing an access request to the memory 80 to the memory controller 70. When the number of master devices is 1, the interconnect 60 for arbitration is unnecessary.

[0040] The memory controller 70 includes a buffer (request buffer) 71. The buffer 71 stores access requests received by the memory controller 70 via the interconnect 60. The buffer 71 has a plurality of entries and is configured to be able to store a plurality of access requests. In addition to the buffer 71, the memory controller 70 further includes, for example, a scheduler for selecting one of the plurality of access requests stored in the buffer 71 and a memory command generator for generating a memory command (command signal) for accessing the memory 80 according to the selected access request. When an access request is selected from the buffer 71 and processed, the memory controller 70 outputs a buffer release notification indicating that the entry of the buffer 71 has been released to the central bus controller 50.

[0041] The central bus controller 50 uses the sub-bus controllers 22, 32, and 42 and performs access control by granting access rights to each master device to control the output of access requests issued by each master device to the memory controller 70. The central bus controller 50 grants access rights to the access request issuing control units 23, 33, and 43, thereby granting access rights to the master device that issues the access request accepted by each request issuing control unit. The central bus controller 50 together with the sub-bus controllers 22, 32, and 42 constitutes an access controller.

[0042] The user pre-sets, for example, the bandwidth of each master device in the central bus controller 50 and guarantees the quality of service (QoS) within a predetermined time period (time slot). In the present embodiment, it can be considered that there is a master device for each access type, and for example, the bandwidth can be set for each of the read access request (hereinafter also referred to as the read request) and the write access request (hereinafter also referred to as the write request) in the access type. The central bus controller 50 grants access rights to each of the access request issuing control units 23, 33, and 43 according to the content of the predetermined access control, for example. For example, the content of the access control can be the same as that described in International Publication No. 2017 / 056132. The content described in International Publication No. 2017 / 056132 is incorporated herein by reference.

[0043] The central bus controller 50 determines whether to grant access rights to the access request issuing control units 23, 33, and 43 corresponding to the respective master devices based on, for example, the QoS information set for the read requests and write requests of the respective master devices. At this time, the central bus controller 50 can monitor the transactions flowing through the bus by means of a request monitor (transaction monitoring signal) obtained from the buses 24, 34, and 44, and can grant access rights while adjusting the granting of access rights for each time slot based on the transmission volume of the transactions. The central bus controller 50 controls the output of the read requests and write requests issued by each master device to the memory controller 70 by granting access rights.

[0044] The central bus controller 50 manages the number of grantable permissions indicating the number of times access permissions can be granted to a master device based on a weight equal to or greater than 0 and less than 1 according to the probability (ratio) of the access permissions granted to each master device being used, and grants access permissions within the range of the number of grantable permissions. For example, each time access permissions are granted to a master device, the central bus controller 50 reduces the number of grantable permissions by a weight corresponding to the probability of using the access permissions in the master device to which the access permissions are granted. When the central bus controller 50 receives a buffer release notification from the memory controller 70, the central bus controller 50 increases the number of grantable permissions by 1. The weight corresponding to the usage probability can be determined based on, for example, design, simulation results, etc.

[0045] [Central bus controller]

[0046] Figure 2 An example of the configuration of the central bus controller 50 is shown. The central bus controller 50 includes a permission grant selection control unit 501, a QoS information register 502, and a maximum grantable number setting register 503. In Figure 2 this case, Figure 1 the transaction monitoring signal shown is not shown.

[0047] The QoS information register 502 stores the QoS information of each master device. The QoS information register 502 stores the reserved transmission amount for each sub-slot of each master device and the priority of each master device. For example, the time obtained by dividing a predetermined time (time slot) by a plurality of time periods is used as the sub-slot. Alternatively, the QoS information register 502 may store the target transmission amount for each sub-slot of each master device.

[0048] The permission grant selection control unit 501 grants access permissions to the access request issuing control units 23, 33, and 43 (see Figure 1 ). The permission grant selection control unit 501 determines which request issuing control unit is to be granted access permissions when granting access permissions. The permission grant selection control unit 501 determines the request issuing control unit for granting access permissions using, for example, the reserved transmission amount and priority read from the QoS information register 502 and the transmission amount in the sub-slot of each master device. Alternatively, the permission grant selection control unit 501 may use the target transmission amount read from the QoS information register 502 to determine the request issuing control unit for granting access permissions.

[0049] The permission grant selection control unit 501 issues an access permission grant signal indicating that access permission has been obtained to the request issue control unit granted the access permission. For example, the permission grant selection control unit 501 asserts the access permission grant signal to be output to the request issue control unit granted the access permission, and keeps ignoring the access permission grant signal to be output to the request issue control unit not granted the access permission. The permission grant selection control unit 501 determines the master device granted the access permission, for example, for each sub-slot.

[0050] The maximum number of authorizable times setting register 503 stores the maximum number of grantable access permissions (maximum grantable permission times) that the permission grant selection control unit 501 can grant access permissions simultaneously. For example, when the permission grant selection control unit 501 issues access requests to the interconnect 60 the same number of times as the maximum grantable permission times from the request issue control unit, the maximum grantable permission times is set to the number of times the access requests are not congested on the bus. The permission grant selection control unit 501 calculates the grantable access permission times with the maximum grantable permission times stored in the maximum number of authorizable times setting register 503 as the upper limit, and grants access permissions within the calculated grantable permission times.

[0051] In this embodiment, the permission grant selection control unit 501 manages the grantable permission times based on weights according to the probability of using the access permission (access permission utilization rate) in each master device and the maximum grantable permission times. For example, the permission grant selection control unit 501 manages the number of times the access permission is granted (number of times the permission is granted) based on weights according to the utilization rate of the access permission. The permission grant selection control unit 501 manages the difference between the maximum grantable permission times set in the maximum number of authorizable times setting register 503 and the number of times the permission is granted as the remaining grantable permission times. The permission grant selection control unit 501 grants access permissions within the grantable permission times.

[0052] [Permission Grant Selection Control Unit]

[0053] Figure 3 An example of the configuration of the permission grant selection control unit 501 is shown. The permission grant selection control unit 501 includes an access permission grant destination determination unit 551, an authorization availability determination unit 552, an access permission grant unit 553, a correction amount and return amount calculation unit 554, and an access permission utilization rate information register 581. In Figure 3 In, the signal output from Figure 2 the QoS information register 502 is not shown.

[0054] The permission utilization information register 581 stores the master device and the weight corresponding to the utilization rate of the access permission of the master device in an associated manner. For example, when it is assumed that the master device A 20 uses the access permission with a probability of 50%, the permission utilization information register 581 stores the master device A 20 and the weight "0.5" in an associated manner. For example, when it is assumed that the master device B 30 uses the access permission with a probability of 80%, the permission utilization information register 581 stores the master device B 30 and the weight "0.8" in an associated manner. For example, when it is assumed that the master device X 40 uses the access permission with a probability of 100%, that is, when the access permission is not returned, the permission utilization information register 581 stores the master device X 40 and the weight "1" in an associated manner. In the permission utilization information register 581, the weight of the corresponding master device is set by using a CPU (not shown).

[0055] In the above description, the permission utilization rate and the weight are set to the same value, but the present invention is not limited thereto. For example, if a value close to 0 is set as the weight of the master device with a low permission utilization rate, there is a possibility of overgranting the access permission to the master device and deteriorating the latency. In this case, a value greater than the actual permission utilization rate (for example, 0.4) can be set as the weight.

[0056] The access permission grant destination determination unit 551 determines the master device to which the access permission is granted. The access permission grant destination determination unit 551 obtains the weight corresponding to the determined master device from the permission utilization information register 581 and transmits the weight to the authorization availability determination unit 552. The permission grant count register 583 stores the number of times the access permission is granted (the number of times the permission is granted). The authorization availability determination unit 552 refers to the maximum authorizable count setting register 503 and the permission grant count register 583 and determines whether the access permission can be granted to the master device determined by the access permission grant destination determination unit 551 as the grant destination of the access permission.

[0057] More specifically, the authorization availability determination unit 552 calculates the difference (the number of available grantable permissions) between the maximum number of grantable permissions stored in the maximum grantable number setting register 503 and the number of granted permissions stored in the granted permission number register 583. The authorization availability determination unit 552 compares the calculated number of available grantable permissions with the weight corresponding to the access permission utilization rate of the master device determined as the authorized destination of the access permission and received from the access permission grant destination determination unit 551. If the number of available grantable permissions is equal to or greater than the weight received from the access permission grant destination determination unit 551, the authorization availability determination unit 552 determines that the access permission can be granted. If the number of available grantable permissions is less than the weight received from the access permission grant destination determination unit 551, the authorization availability determination unit 552 determines that the access permission cannot be granted.

[0058] When it is determined that the access permission can be granted, the authorization availability determination unit 552 instructs the access permission grant unit 553 to grant the access permission to the master device determined by the access permission grant destination determination unit 551. In addition, the authorization availability determination unit 552 adds the weight received from the access permission grant destination determination unit 551 to the number of granted permissions stored in the granted permission number register 583, thereby consuming the weight of the number of granted permissions. Each time the access permission is granted to the master device, the authorization availability determination unit 552 adds the weight corresponding to the access permission utilization rate of the master device to which the access permission is granted to the number of granted permissions.

[0059] In this embodiment, the number of granted permissions is weighted by the weight corresponding to the access permission utilization rate. For example, when the number of times the access permission is granted is "10", if all the weights corresponding to the access permission utilization rate of the master device to which the access permission is granted are "0.5", the number of granted permissions is 10×0.5 = 5. If the number of times the access permission is granted is "10" and all the weights corresponding to the access permission utilization rate of the master device to which the access permission is granted are "1", the number of granted permissions is 10×1 = 10.

[0060] In this embodiment, the number of available grantable permissions represented by the difference between the maximum number of grantable permissions and the number of granted permissions changes according to the access permission utilization rate, and when the access permission is granted to a master device with a low access permission utilization rate, the number of available grantable permissions increases compared to the case where the access permission is granted to a master device with a high access permission utilization rate. In other words, when the access permission is granted to a master device with a high access permission return rate, the access permission is consumed more compared to the case where the access permission is granted to a master device with a low access permission return rate.

[0061] When an access right is granted by the access right granting unit 553 and an access request is received from the corresponding master device, the request issuing control units 23, 33, and 43 output the access request to the interconnect 60 using the granted access right. At this time, the request issuing control unit outputs a permission usage notification to the central bus controller 50. In the central bus controller 50, when the permission usage notification is received, the correction amount and return amount calculation unit 554 of the permission granting selection control unit 501 corrects the calculated number of permissions to be granted using the weight stored in the permission utilization information register 581 when the access right is granted. The correction amount and return amount calculation unit 554 corrects the number of permissions to be granted based on, for example, the difference between the weight stored in the permission utilization information register 581 and corresponding to the access right utilization rate of the master device and "1".

[0062] More specifically, for example, when the master device A 20 is the destination to which the access right is granted, when the access right is granted, the authorization availability determination unit 552 adds the weight "0.5" stored in the permission utilization information register 581 to the number of permissions granted. When the permission usage notification is received, the correction amount and return amount calculation unit 554 corrects the number of permissions to be granted by the difference between the weight "0.5" stored in the permission utilization information register 581 and "1". In this case, the number of permissions granted is increased by the weight difference "0.5", and one access right is consumed.

[0063] On the other hand, when an access right is granted by the access right granting unit 553 and no access request is received from the corresponding master device, the request issuing control units 23, 33, and 43 return the access right to the central bus controller 50 without using the granted access right. In the central bus controller 50, when the access right is returned, the correction amount and return amount calculation unit 554 of the permission granting selection control unit 501 subtracts the weight stored in the permission utilization information register 581 from the number of permissions granted that was added to the weight stored in the permission utilization information register 581 when the access right was granted. Therefore, when the access right is returned, the number of permissions granted is returned to the state before the grant of the access right, and the number of available permissions can be increased by that amount. The returned access right can be used for the access right to other master devices.

[0064] When a memory access based on an access request stored in buffer 71 is processed and an entry in buffer 71 is released, memory controller 70 outputs a release notification signal to central bus controller 50. In central bus controller 50, when correction amount and return amount calculation unit 554 receives the release notification signal, the number of granted authorities stored in granted authority count register 583 is decreased by 1. Accordingly, the access authority used in an access request that has been processed can be granted to another access request.

[0065] [Operation Steps]

[0066] Next, the operation steps will be described. Figure 4 The operation steps of the part related to the management of the number of grantable authorities are shown. Before the operation of electronic device 10, necessary information is set in authority utilization information register 581 (refer to Figure 3 ). In authority utilization information register 581, a weight corresponding to the access authority utilization predicted (estimated) for each master device is set for each master device. The weight set in authority utilization information register 581 indicates the number of access authorities consumed by the access request of each master device.

[0067] Access authority grant destination determination unit 551 determines the master device (request issue control unit) to which the access authority is to be granted (step A1). Access authority grant destination determination unit 551 acquires the weight corresponding to the master device determined in step A1 that is to be granted the access authority (step A2). Access authority grant destination determination unit 551 transmits the acquired weight to authorization availability determination unit 552.

[0068] Authorization availability determination unit 552 determines whether the access authority can be granted to the master device determined in step A1 based on the weight received from access authority grant destination determination unit 551, the maximum number of grantable authorities stored in maximum grantable authority count register 503, and the number of granted authorities stored in granted authority count register 583 (step A3). In step A3, for example, authorization availability determination unit 552 determines whether the number of grantable authorities obtained by subtracting the number of granted authorities from the maximum number of grantable authorities is equal to or greater than the weight received from access authority grant destination determination unit 551. When the number of grantable authorities is equal to or greater than the weight received from access authority grant destination determination unit 551, authorization availability determination unit 552 determines that the access authority can be granted. When the number of grantable authorities is less than the weight received from access authority grant destination determination unit 551, authorization availability determination unit 552 determines that the access authority cannot be granted.

[0069] When it is determined in step A3 that the access right can be granted, the authorization availability determination unit 552 instructs the access right granting unit 553 to grant the access right. When the granting of the access right is instructed from the authorization availability determination unit 552, the access right granting unit 553 grants the access right to the master device determined in step A1 (step A4). When the master device determined in step A1 is granted the access right, the authorization availability determination unit 552 reduces the number of times the access right can be granted by the weight received from the access right grant destination determination unit 551 (step A5). In other words, the authorization availability determination unit 552 consumes the number of times the access right can be granted by the weight received from the access right grant destination determination unit 551. In step A5, for example, the authorization availability determination unit 552 adds the weight received from the access right grant destination determination unit 551 to the number of times the access right has been granted stored in the granted right count register 583, thereby reducing the number of times the access right can be granted. If it is determined in step A3 that the number of times the access right can be granted is less than the weight received from the access right grant destination determination unit 551, the granting of the access right is suspended. When the number of times the access right can be granted changes and the number of times the access right can be granted becomes equal to or greater than the weight received from the access right grant destination determination unit 551, the access right is granted.

[0070] The request issuing control unit of the master device outputs an access request to the corresponding sub-bus controller. When the access right is granted and an access request is received from the master device, the request issuing control unit outputs the access request to the interconnect 60. At this time, the request issuing control unit transmits a permission usage notification to the central bus controller 50. When the access right is granted and no access request is received from the master device, the request issuing control unit transmits a return notification to the central bus controller 50 and returns the granted access right to the central bus controller 50.

[0071] The correction amount and return amount calculation unit 554 determines whether the access right has been used in the request issuing control unit corresponding to the master device granted the access right (step A6). That is, the correction amount and return amount calculation unit 554 determines whether a permission usage notification or a return notification has been received from the request issuing control unit. When the permission usage notification is received, the correction amount and return amount calculation unit 554 corrects the reduced number of times the access right can be granted in step A5 (step A7). In step A7, the correction amount and return amount calculation unit 554 calculates the difference between the weight obtained in step A2 and "1". The correction amount and return amount calculation unit 554 increases the number of times the access right has been granted stored in the granted right count register 583 by the calculated difference, thereby correcting the number of times the access right consumed by the weight corresponding to the permission utilization rate at the time of granting the access right to "1". If the calculated difference is 0, the number of times the access right can be granted is not corrected.

[0072] When the return notification is received, the correction amount and return amount calculation unit 554 returns the reduced number of grantable authorities in step A5 (step A8). In step A8, the correction amount and return amount calculation unit 554 reduces the number of granted authorities stored in the grant authority number register 583 by the weight obtained in step A2, thereby increasing the number of grantable authorities by the weight obtained in step A2.

[0073] The access request output from the request release control unit is arbitrated by the interconnect 60 and stored in the buffer 71 of the memory controller 70. The memory controller 70 performs a memory access to the memory 80 according to the access request stored in the buffer 71. When the memory access based on the access request is completed, the memory controller 70 releases the entry of the buffer 71. At this time, the memory controller 70 transmits a release notification signal to the central bus controller 50.

[0074] The correction amount and return amount calculation unit 554 determines whether a release notification signal has been received from the memory controller 70 (step A9). When it is determined that the release notification signal has been received, the correction amount and return amount calculation unit 554 increases the number of grantable authorities by 1 (step A10). In step A10, the correction amount and return amount calculation unit 554 reduces the number of granted authorities stored in the grant authority number register 583 by 1, thereby increasing the number of grantable authorities by 1.

[0075] [Operation Example]

[0076] Figure 5 The electronic device 10 of one aspect is shown. In Figure 5 , for simplicity of description, the master device A 20 and the master device B 30, and the associated sub-bus controllers 22 and 32, etc. are omitted. In Figure 5 , it is assumed that ten cycles after the output of the access permission, the access permission granted by the central bus controller 50 reaches the request release control unit 43 of the sub-bus controller 42. It is also assumed that ten cycles after the output of the permission usage notification and the return notification, the permission usage notification and the return notification output from the request release control unit 43 reach the central bus controller 50.

[0077] In Figure 5 , it is assumed that the central bus controller 50 grants one access permission every two cycles. It is assumed that the utilization rate of the access permission in the master device X 40 (request release control unit 43) is 50%, and the permission utilization rate information register 581 (refer to Figure 3 ) stores the master device X 40 and the weight "0.5" in an associated manner. In Figure 5Among them, the access authority 81 sequentially output from the central bus controller 50 every two cycles reaches the request issuing control unit 43 ten cycles after the access authority is respectively output. In this embodiment, the number of grantable authorities is managed in consideration of how much access authority is used among the granted access authorities and the degree to which the access request enters the route from the request issuing control unit 43 to the interconnect 60.

[0078] If the access authority is not received from the master device X 40 when the first access authority is granted, the request issuing control unit 43 outputs a return notice 83 to the central bus controller 50. The return notice 83 reaches the central bus controller 50 ten cycles later. If the access authority is received from the master device X 40 when the second access authority is granted, the request issuing control unit 43 uses the access authority and outputs an access request 84 to the interconnect 60. In addition, the request issuing control unit 43 outputs an authority usage notice 82 corresponding to the output of the access request 84 to the central bus controller 50. The authority usage notice 82 reaches the central bus controller 50 ten cycles later.

[0079] For example, assume that the maximum number of grantable authorities is equal to the number of entries in the buffer 71, and the number of empty entries and the number of grantable authorities in the buffer 71 are "1". In International Publication No. 2017 / 056132, since the number of grantable authorities is consumed by 1 each time an access authority is granted, when the access authority 81 is granted to the master device X 40, the number of grantable authorities becomes "0", and the granting of the access authority stops. When the master device X 40 does not issue an access request, the request issuing control unit 43 outputs a return notice 83 to the central bus controller 50. The return notice 83 reaches the central bus controller 50 twenty cycles after the granting of the access authority 81. In this case, the central bus controller 50 cannot grant a new access authority within twenty cycles.

[0080] Contrary to the above, in this embodiment, when the access authority is granted to the master device X 40, the number of grantable authorities is consumed by "0.5". In this case, since the number of grantable authorities remains "0.5", the central bus controller 50 can continuously grant another access authority to the master device X 40. Since the authority utilization rate of the master device X 40 is 50%, it is very likely that one of the two granted access authorities will be used and the other will be returned. When the return notice 83 is received, the central bus controller 50 restores the number of authorities to be consumed from "0.5" to "0", and when the authority usage notice 82 is received, the central bus controller 50 changes the number of authorities to be consumed from "0.5" to "1". In this case, the number of consumed authorities is subtracted by "1", and the granting of the access authority stops until the buffer 71 is released.

[0081] [Conclusion]

[0082] In this embodiment, the number of permissions that can be granted is managed according to the utilization rate of access permissions by the master device. For example, compared with a master device with a low permission utilization rate, a master device with a high permission utilization rate sets each access permission to consume more permissions. In this case, access permissions can be speculatively granted to the master device with a low permission utilization rate when the return of the access permission is expected. On the other hand, for a master device with a high permission utilization rate, granting excessive access permissions can be prohibited. Therefore, excessive granting of access permissions and insufficient number of authorization times can be prohibited, deterioration of latency and reduction of memory efficiency can be prevented, congestion of requests on the bus in various situations can be eliminated, and memory efficiency can be improved.

[0083] Compared with International Publication No. 2017 / 056132, in International Publication No. 2017 / 056132, when the upper limit of the number of granted access permissions (the maximum number of access permissions that can be granted) is set to be greater than the number of entries in the buffer in the memory controller, access permissions can be speculatively granted to some extent, and the access permissions that can be returned can be effectively used. However, in this case, when the maximum number of permissions that can be granted is set to a smaller number according to a master device with a high permission utilization rate (i.e., a master device that continuously issues requests), the number of access permissions received by the memory controller in a state where a large number of master devices with a low permission utilization rate are operating decreases, and the memory efficiency deteriorates. On the contrary, when the maximum number of permissions that can be granted is set to a large number according to a master device with a low permission utilization rate (i.e., a master device that intermittently issues requests), access requests congest on the bus in a state where a large number of master devices with a high permission utilization rate are operating, and the latency deteriorates. In this embodiment, since weights corresponding to the permission utilization rate at the time of granting access permissions consume multiple permissions, memory efficiency and low latency can be compatible in various situations.

[0084] Second Embodiment

[0085] Next, the second embodiment will be described. Figure 6 An example of the configuration of the permission-granting selection control unit used in the electronic device according to the second embodiment is shown. In this embodiment, the configuration of the electronic device can be the same as that of Figure 1 the configuration of the electronic device 10 shown. The configuration of the central bus controller can be the same as that of Figure 2 the central bus controller 50 shown. The permission-granting selection control unit 501a used in this embodiment has the following configuration: The utilization rate specific weight information register 582 and the usage and return history storage unit 584 are added to Figure 3In the configuration of the permission granting selection control unit 501 used in the first embodiment shown, the permission utilization information register 581 in the permission granting selection control unit 501 is replaced by a weight generation unit 557. Other points may be the same as those in the first embodiment.

[0086] The usage and return history storage unit 584 stores the permission usage notification and return notification notified from the request issuing control unit. The weight generation unit 557 refers to the usage and return history storage unit 584, estimates the permission utilization rate of the master device based on the usage and return history of the access permission stored in the usage and return history storage unit 584, and generates a weight corresponding to the estimated permission utilization rate. The utilization rate specific weight information register 582 stores the permission utilization rate and weight of the access permission in an associated manner. The weight generation unit 557 obtains the weight corresponding to the estimated permission utilization rate from the utilization rate specific weight information register 582, and outputs the obtained weight to the access permission granting destination determination unit 551, the correction amount and return amount calculation unit 554, etc.

[0087] The weight generation unit 557 and the usage and return history storage unit 584 are arranged, for example, corresponding to each of the plurality of master devices included in the electronic device 10. The usage and return history storage unit 584 corresponding to each master device stores the history of the right usage notification and return notification notified from the request issuing control unit corresponding to each master device. The weight generation unit 557 corresponding to each master device refers to the usage and return history storage unit 584 corresponding to each master device, and generates a weight corresponding to the permission utilization rate of each master device.

[0088] When outputting access requests issued by the master device A 20, the master device B 30, and the master device X 40 to the interconnect 60 respectively, the request issuing control units 23, 33, and 43 (refer to Figure 1 ) output a permission usage notification to the central bus controller 50. When no access request is received, the request issuing control units 23, 33, and 43 notify the central bus controller 50 of a return notification. For example, the usage and return history storage unit 584 stores a predetermined number of permission usage notifications and return notifications for each master device.

[0089] The weight generation unit 557 calculates the average utilization rate of the access rights in the master device based on, for example, the number of permission usage notifications or return notifications stored in the usage and return history storage unit 584 and the number of access rights granted by the access right granting unit 553. In the weight generation unit 557, the time for counting the number of times the granted access rights are used and the time for counting the number of usage times or return times can be configured to be changeable by register setting. The weight generation unit 557 sets, for example, the average value of several past permission utilization rates as the average utilization rate. At this time, the weight generation unit 557 can increase the weight of the most recent permission utilization rate and calculate the weighted average value of the permission utilization rate. The calculation method of the average utilization rate in the weight generation unit 557 can be configured to be switchable by using, for example, a register (not shown).

[0090] The weight generation unit 557 acquires the weight corresponding to the calculated average utilization rate from the utilization rate specific weight information register 582. In the weight generation unit 557, for example, a weight similar to the weight set in the permission utilization rate information register 581 (refer to Figure 3 ) can be set as the initial value. When determining the master device to which the access right is granted, the access right granting destination determination unit 551 acquires the weight corresponding to the permission utilization rate of the master device to which the access right is granted from the weight generation unit 557. When granting the access right, the authorization availability determination unit 552 uses the weight acquired from the weight generation unit 557 to update the number of granted permissions stored in the granted permission count register 583.

[0091] When receiving a permission usage notification from the request issuing control unit to which the access right is granted, the correction amount and return amount calculation unit 554 corrects the number of granted permissions stored in the granted permission count register 583 based on the difference between the weight added to the granted permission count register 583 at the time of granting the access right and "1". When receiving a return notification from the request issuing control unit to which the access right is granted, the correction amount and return amount calculation unit 554 subtracts the weight added to the granted permission count register 583 at the time of granting the access right from the number of granted permissions stored in the granted permission count register 583.

[0092] Here, there is a predetermined time difference between the timing at which the permission granting selection control unit 501a grants an access permission to the request issuing control unit and the timing at which a permission usage notification or a return notification is received from the request issuing control unit. To adjust this time difference, the correction and return amount calculation unit 554 can receive the weights generated by the weight generation unit 557 via, for example, a first-in first-out (FIFO) to delay data by a predetermined time. In this case, even if the weights generated by the weight generation unit 557 change between the granting of the access permission and the reception of the permission usage notification or the return notification, the correction amount and return amount calculation unit 554 can correct the number of granted permissions using the weights used at the time of granting the access permission, or increase the number of granted permissions by the weights used at the time of granting the access permission.

[0093] [Conclusion]

[0094] In the present embodiment, the weight generation unit 557 estimates the utilization rate of the access permission of the master device based on the actual usage of the access permission, and generates a weight at the time of granting the access permission. By using the history of the usage of the access permission, the usage amount of the access permission and the amount of the access permission returned by the master device can be estimated more accurately, and by using the weights corresponding to the estimated permission utilization rate, the deterioration of the delay and the deterioration of the memory efficiency can be prevented.

[0095] Third Embodiment

[0096] Next, the third embodiment will be described. Figure 7 An electronic device including a semiconductor device according to the third embodiment is shown. The electronic device 10b according to the present embodiment is different from the electronic device 10 according to the first embodiment shown in Figure 1 that the interconnect 60 outputs a bus pass master device notification to the central bus controller 50b. In the present embodiment, the central bus controller 50b uses the bus pass master device notification to determine whether an access request is congested on the bus. Other aspects may be the same as those in the first embodiment or the second embodiment.

[0097] When the granted access right is returned from the request issue control unit, several cycles are required before the central bus controller 50b receives the return notification. Therefore, before receiving the return notification, the central bus controller 50b cannot know whether the access right has been used and whether the access request has passed through the request issue control unit. In this embodiment, the interconnect 60 arranged immediately before the memory controller 70 outputs, as a bus master notification, for example, the ID of the master device indicating the issue access request to be selected. By referring to the AxID signal, the central bus controller 50b can determine from which master device the access request stored in the buffer 71 originated. In this embodiment, the central bus controller 50b determines which master device's access request is stored in the buffer 71 of the memory controller 70, calculates the number of requests congested on the bus, and determines the congestion of the bus.

[0098] Figure 8 The configuration of the central bus controller 50b used in this embodiment is shown. In addition to the configuration of the central bus controller 50 used in the Figure 2 first embodiment shown, the central bus controller 50b further includes a bus congestion request prediction unit 504. The bus congestion request prediction unit 504 receives the bus master notification from the interconnect 60. The bus congestion request prediction unit 504 obtains information about the following from the privilege grant selection control unit 501: the master device to which the access right is granted, the master device that uses or returns the access right, the privilege utilization rate of the master device, etc. The bus congestion request prediction unit 504 predicts that access requests will congest on the bus based on, for example, the number of times the access right is granted, the number of times the access right is used, the privilege utilization rate, and the bus master notification.

[0099] When the number of access requests congested on the bus is equal to or greater than a predetermined threshold, the bus congestion request prediction unit 504 determines that the bus is congested. In this case, the bus congestion request prediction unit 504 notifies the privilege grant selection control unit 501 of the information identifying the congested bus. When receiving the information identifying the congested bus from the bus congestion request prediction unit, the privilege grant selection control unit 501 stops granting access rights to the master devices connected to the bus. The privilege grant selection control unit 501 can refer to the QoS information register 502 and stop granting access rights to the master devices with low QoS priorities among the master devices connected to the congested bus. By stopping granting access rights to the master devices connected to the congested bus, the deterioration of latency can be suppressed. In addition, the access rights not granted to the master devices connected to the congested bus can be granted to the master devices connected to the non-congested bus, and the memory efficiency can be improved by effectively using the access rights.

[0100] [Operation Example]

[0101] Figure 9 A part of an electronic device showing one aspect is illustrated. Here, an example is considered in which the electronic device 10b has four master devices 201 to 204. The master devices 201 to 204 are respectively connected to request issue control units 205 to 208. The request issue control units 205 and 206 output access requests to the arbiter 210, and the request issue control units 207 and 208 output access requests to the arbiter 211.

[0102] The arbiter 210 arbitrates between the access requests issued by the master device 201 and the access requests issued by the master device 202. The arbiter 211 arbitrates between the access requests issued by the master device 203 and the access requests issued by the master device 204. The arbiter 212 arbitrates between the access requests passing through the arbiter 210 and the access requests passing through the arbiter 211. The arbiters 210 and 211 correspond to Figure 1 the shown interconnection 60 etc. In this example, the arbiter 212 arranged immediately before the memory controller 70 when viewed from the master device outputs an AxID signal (bus notification through the master device) to the central bus controller 50b.

[0103] In Figure 9 , it is assumed that the time required for the access permission output from the central bus controller 50b to reach the request issue control units 205 to 208 corresponding to the master devices 201 to 204 is ten cycles. It is assumed that the time required for the permission usage notification or return notification output from the request issue control units 205 to 208 to reach the central bus controller 50b is ten cycles. In addition, it is assumed that the time required for the access requests (transactions) passing through the request issue control units 205 to 208 to reach the final-stage arbiter 212 is at least ten cycles, that is, in a state where the bus is not congested.

[0104] In Figure 9 , it is assumed that it takes one cycle for the access permission and the access request to pass through one square shown on the path. In Figure 9 , for simplicity, only the path between the request issue control unit 208 and the central bus controller 50b for granting access permission and for transmitting the permission usage notification or return notification is shown, but the paths between the request issue control units 205 to 207 and the central bus controller 50b for granting access permission and for transmitting the permission usage notification or return notification exist in the same way.

[0105] In Figure 9In this case, it is assumed that the right utilization rates of master devices 201 and 202 are 0.5, and the central bus controller 50b grants one access right to each of master devices 201 and 202 in each cycle (two rights in each cycle). In this case, the utilization rate on the path from master devices 201 and 202 to arbiter 210 is approximately half, and the path from arbiter 210 to arbiter 212 is not just almost congestion-free. In this case, if the right utilization rate of any master device exceeds 0.5, congestion occurs on the bus, and the access rights granted to request issue control units 205 and 206 are returned at a constant rate.

[0106] As an extreme case, when the right utilization rates of the two master devices are 1, the return of access rights occurs when access rights are granted to the two master devices for four consecutive cycles. From the viewpoint of effectively using access rights, unnecessary granting of access rights should be avoided. The central bus controller 50b can limit the granting of access rights so that the sum of the products of the number of access rights granted within a specific time period and the right utilization rate becomes equal to or less than a specific value. For example, when the sum of the products of the number of access rights granted within a specific time period and the right utilization rate exceeds 1.2, the granting of access rights can be stopped.

[0107] Alternatively, the scheduling performed by memory controller 70 can cause access requests to become congested at arbiter 212. For example, when the right utilization rate of master device 201 is 0.5 and only master device 201 is operating, the above-mentioned congestion of access requests does not occur. However, if the memory controller 70 does not accept access requests for any reason, congestion of access requests occurs on the bus. When the access requests cannot pass through arbiter 212 for about ten cycles, the congestion of access requests is propagated to master device 201, and the access rights are returned from request issue control unit 205. The congestion can be determined by monitoring the transaction ID (which master device transaction) at arbiter 212.

[0108] As a countermeasure against this, the central bus controller 50b calculates the value obtained by adding the product of the number of granted access rights and the value of the right utilization rate to the total number of access requests that have not passed through at the timing of passing through arbiter 212. If the calculated value is equal to or greater than a predetermined value, the central bus controller 50b can stop granting access rights to the master device. The timing when the access requests should pass through arbiter 212 can be estimated based on the time required for the granted access rights to reach the request issue control unit and the time required for the access requests output from the request issue control unit to reach arbiter 212. For example, if arbiter 212 can be passed through within twenty cycles of the granted access rights, the central bus controller 50b can suspend granting access rights to the master device when the calculated value is 15 or more. InFigure 9 In the example of , since the path from arbiter 210 to arbiter 212 is common to master device 201 and master device 202, six cycles need to be calculated together with master device 202. As an exception to the above, even if the above conditions are met, the central bus controller 50b will not stop granting access rights to the master device with high priority under severe latency constraints.

[0109] [Conclusion]

[0110] In this embodiment, the central bus controller 50b receives a bus pass master device notification from the interconnect 60. The central bus controller 50b knows which master device has output an access request to the memory controller 70, and can predict the congestion of access requests on the bus based on the number of granted access rights, the number of returns, the permission utilization rate, etc. When access requests are congested on the bus, the central bus controller 50b stops granting access rights to the master devices connected to the bus. In this case, the deterioration of access right congestion can be suppressed. In addition, access rights can be granted to the master devices connected to the bus where there is no congestion of access rights, and the access rights can be effectively used.

[0111] Fourth Embodiment

[0112] Next, the fourth embodiment will be described. Figure 10 FIG. shows a memory controller used in an electronic device according to the fourth embodiment. In this embodiment, the configuration of the electronic device can be the same as that Figure 1 shown. The configuration of the central bus controller can be the same as that Figure 2 shown. In this embodiment, in addition to the buffer 71, the memory controller 70c further includes a cache 72, a prefetch control unit 73, and a control register 74. Other points can be the same as those in the first embodiment or the second embodiment.

[0113] In the memory access to the memory 80, when reading from the memory controller 70c to the memory 80, by reading (prefetching) slightly more than the actual access size and storing it in the cache 72, when there is an access to the part that has been over-read (read hit), no read to the memory 80 occurs, and low latency can be achieved. However, when the prefetch data is not used, or when the data is evicted from the cache before use, the prefetch data is wasted and the access efficiency to the memory 80 is reduced. In this embodiment, the memory controller 70c controls prefetching based on information such as QoS.

[0114] The prefetch control unit 73 of the memory controller 70c determines whether to perform prefetch when reading from the memory 80. The control register 74 stores information for identifying the master device to be prefetched, the maximum access size during prefetch, etc. Prefetch is effective when an access request to consecutive addresses occurs, and whether prefetch is effective is determined based on the characteristics of the memory access of the master device. In the control register 74, the master device that generates the access request to consecutive addresses is set as the master device to be prefetched. The prefetch control unit 73 determines whether to prefetch the master device stored as the prefetch target in the control register 74. When prefetch is performed, the prefetch control unit 73 temporarily stores the prefetch data in the cache 72. When the access type of the access request is read, the prefetch control unit 73 uses the access size information to prefetch the cache 72, thereby improving the efficiency of memory access.

[0115] More specifically, the prefetch control unit 73 obtains the permission utilization rate from the central bus controller 50c and predicts whether the master device to be prefetched will issue a large number of access requests. In addition, the prefetch control unit 73 determines whether the master device to be prefetched will issue a large number of access requests from now on based on the QoS setting information stored in the QoS information register 502 (see Figure 2 ), the information about the status of the recently granted access permission, etc. The prefetch control unit 73 checks the master device that issues the access request stored in the buffer 71 and checks how many access requests issued by a master device different from the master device to be prefetched are stored in the buffer 71. For example, the prefetch control unit 73 comprehensively determines the latest permission utilization rate of each master device, the future bandwidth of the target master device predicted from the QoS setting, the bandwidth of another master device predicted from the QoS setting, the number of access requests issued by the target master device and stored in the buffer 71, and the number of access requests issued by another master device and stored in the buffer 71, and determines whether to perform prefetch.

[0116] For example, in the case where a large number of access requests issued by the target master device are stored in the buffer 71, the target master device issues more access requests, so prefetch is very likely to be effective. When the target master device has issued a large number of access requests, the prefetch control unit 73 may decide to perform prefetch. Regarding the QoS setting, for example, when the bandwidth of the target master device is large, the possibility of using the prefetch data is high. When the bandwidth of the master device other than the target master device is small, the data retention time until the data stored in the cache 72 is overwritten is long when prefetch is performed. When the bandwidth of the target master device is large or the bandwidth of the master device other than the target master device is small, the prefetch control unit 73 may decide to perform prefetch. The prefetch control unit 73 may decide whether to perform prefetch by comprehensively determining the above matters.

[0117] [Conclusion]

[0118] In this embodiment, the prefetch control unit 73 determines whether to perform prefetch based on the permission utilization rate of the master device, the state of granting access permissions to the master device, etc. For example, when it is expected that the master device outputs a large number of read requests to consecutive addresses, memory access can be effectively performed through prefetch. In particular, in the case of a DDR memory or the like, if the read size is not equal to or greater than a specific value, the efficiency may be significantly reduced, so prefetch is more effective.

[0119] Fifth Embodiment

[0120] [Bus Generator]

[0121] Next, the fifth embodiment will be described. In this embodiment, a bus generator for generating circuit information of a bus in a semiconductor device from various setting information will be described. Figure 11 An example of the hardware configuration of the bus generator 800 is shown. The bus generator 800 is configured as a computer device, including, for example, a CPU 801, a memory 802, a keyboard 804, a mouse 805, a display 806, and a bus 807. The memory 802 stores a bus generation tool 803 for operating the computer device as the bus generator 800. In the computer device, the CPU 801 executes processing according to the bus generation tool 803 read from the memory 802, so that the computer device can operate as the bus generator 800.

[0122] Figure 12 A schematic flow of bus design is shown. First, use cases in the market, etc. are assumed (step S101), and the performance required for the bus is considered (step S102). Next, the bus structure is considered based on the required performance, etc. (step S103). For example, considering the bus structure includes considering whether to use the central bus controller 50 (reference Figure 1 ).

[0123] When the bus structure is determined, the setting information required for the determined bus structure is input to the bus generator (step S104). The bus generator generates and outputs the circuit information of the bus (step S105). For example, the circuit information is described at the register transfer level (RTL). Thereafter, the circuit information of the bus is logically synthesized (step S106), and then layout design is performed (step S107). Steps S104 and S105 represent the stages of performing design using the bus generator.

[0124] Figure 13 An example of a screen for inputting setting information is shown. For example, a screen prompting the input of setting information is displayed on the display 806 (reference Figure 7), and the user uses the keyboard 804 and the mouse 805 to provide various settings to the bus generator 800. For example, in the Figure 13 shown screen, when the user selects "QoS" from the menu 901, the sub-menu 902 is displayed. When the user selects "Initial value" in the sub-menu 902, the input screen 903 for inputting the access size of each master device is displayed. The user can input, for example, the information set in the privilege utilization information register 581 (refer to Figure 3 ).

[0125] For example, the user inputs information such as information about the access destination of the master device, information about the clock to be used, information about the bus width, information about functional safety, etc. into the bus generator 800 as information about the master device that outputs an access request to the memory. In addition, as information about the slave device accessed from the master device, information about the address area, information about the clock to be used, information about the bus width, information about functional safety, etc. is input. Furthermore, as information related to the arbiter, information specifying the QoS method, detailed settings for each method, etc. is input.

[0126] Figure 14 shows the input data to the bus generator and the output data from the bus generator. The bus generator 800 includes, for example, a bus structure information generation unit, a bus component generation unit, a central bus controller generation unit, a sub-bus controller generation unit, a merging unit, etc. as functional blocks. The bus generator 800 receives clock information 101, connection information 102, slave device information 103, master device information 104, QoS method selection information 105, and detailed QoS method setting information 106. For example, these information are input through a screen for inputting setting information as Figure 13 shown.

[0127] The bus generator 800 uses the clock information 101, connection information 102, slave device information 103, master device information 104, etc. to generate the structure information of the bus for connecting between the master device and the slave device. In addition, the bus generator 800 generates the circuit information of various bus components based on the generated structure information of the bus and the circuit information of various functional blocks provided by, for example, suppliers that provide various IP cores.

[0128] The bus generator 800 uses the structure information of the bus, the QoS method selection information 105, the circuit information of various functional blocks, etc. to generate the circuit information of the central bus controller that performs access control in response to the access request output from the master device. The circuit information of the central bus controller generated by the bus generator 800 indicates, for example, the Figure 2 shown circuit configuration of the central bus controller 50.

[0129] The bus generator 800 uses the circuit information of the central bus controller to generate the circuit information of the sub-bus controllers that operate based on the central control. The circuit information of the sub-bus controllers indicates, for example, Figure 1 the circuit configurations of the sub-bus controllers 22, 32, and 42 shown. The bus generator 800 combines the circuit information of the bus components, the circuit information of the central bus controller, and the circuit information of the sub-bus controllers, and outputs the circuit information of the bus (bus RTL 113). The circuit information of the bus (bus RTL 113) describes the circuit portions in the RTL related to the bus from each master device to the memory 80 in the electronic device 10 shown, for example, Figure 1 in the electronic device 10 shown.

[0130] [Conclusion]

[0131] In this embodiment, the bus generator 800 is used to generate a bus system. By inputting various setting information and the like into the bus generator 800, a bus system can be automatically generated, for example, Figure 1 between each master device and the memory 80 in the electronic device 10 shown.

[0132] Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various changes can be made without departing from its scope.

Claims

1. A semiconductor device, comprising: A master device that issues an access request to a memory; A memory controller coupled to the master device and accessing the memory according to the access request; And An access control unit that controls the output of the access request issued by the master device to the memory controller by granting access permissions, wherein the access control unit determines a weight equal to or greater than 0 and less than 1 based on the probability that the granted access permission is used, manages the number of grantable permissions indicating the number of times the access permission can be granted based on the weight, and grants the access permission within the range of the number of grantable permissions, wherein the access control unit includes a central bus controller, and the central bus controller includes: A grant availability determination unit that calculates the difference between the maximum number of grantable permissions indicating the maximum number of times the access permission can be granted and the number of times the access permission has been granted as the number of grantable permissions, compares the number of grantable permissions with the weight to determine whether to grant the access permission, and adds the weight to the number of times the access permission has been granted each time the access permission is granted to the master device.

2. The semiconductor device according to claim 1, wherein the access control unit comprises: A sub-bus controller including a request issue control unit that receives the access request issued by the master device; And The central bus controller grants the access permission to the request issue control unit, wherein when the access permission is granted by the central bus controller, the request issue control unit outputs the access request to the memory controller using the access permission, and when the access permission is not granted, the request issue control unit prohibits the output of the access request to the memory controller.

3. The semiconductor device according to claim 2, wherein when the access permission is granted from the central bus controller and the access request is not received from the master device, the request issuing control unit returns to the central bus controller without using the access permission.

4. The semiconductor device according to claim 2, wherein each time the access permission is granted, the central bus controller subtracts the weight from the number of times the permission can be granted.

5. The semiconductor device according to claim 2, wherein the request issuing control unit outputs a notification signal to the central bus controller, the notification signal indicating whether the access request has been output to the memory controller using the access permission, and wherein the central bus controller corrects the number of granted permissions based on the notification signal output from the request issuing control unit.

6. The semiconductor device according to claim 5, wherein when the notification signal output from the request issuing control unit indicates that the access permission has been used, the central bus controller corrects the number of granted permissions by the difference between the weight and 1, and when the notification signal output from the request issuing control unit indicates that the access permission has not been used, the central bus controller subtracts the weight from the number of granted permissions.

7. The semiconductor device according to claim 1, The memory controller includes a request buffer for receiving and storing the access requests, and when a memory access based on the access requests stored in the request buffer is processed and an entry in the request buffer is released, the memory controller outputs a release notification signal indicating that the request buffer is released to the central bus controller, and when the release notification signal is received from the memory controller, the central bus controller decrements the number of granted permissions by 1.

8. The semiconductor device according to claim 2, wherein the master device includes a first master device, wherein the sub-bus controller includes a first sub-bus controller, wherein the request issuance control unit includes a first request issuance control unit, and wherein the semiconductor device further includes: A second master device that issues the access request to the memory; A second sub-bus controller including a second request issue control unit that receives the access request issued by the second master device; And An interconnect that arbitrates the access requests output from the first master device and the second master device and outputs the arbitrated access request to the memory controller, wherein the first sub-bus controller is disposed between the first master device and the interconnect via a first bus, and wherein the second sub-bus controller is disposed between the second master device and the interconnect via a second bus.

9. The semiconductor device according to claim 8, wherein the weight is set for each of the first master device and the second master device.

10. The semiconductor device according to claim 8, wherein the interconnect outputs information identifying the first master device or the second master device that issued the access request output to the memory controller to the central bus controller as a bus pass master device notification, and wherein the central bus controller determines whether the access request is congested on the first bus or the second bus based on the number of granted access permissions, the number of used access permissions, the probability that the granted access permission is used, and the bus pass master device notification.

11. The semiconductor device according to claim 10, wherein the central bus controller stops granting the access permission to the first request issuance control unit or the second request issuance control unit associated with the first master device or the second master device, and the first master device or the second master device is coupled to the first bus or the second bus on which the access permission is determined to be congested.

12. The semiconductor device according to claim 10, wherein the central bus controller calculates a value obtained by adding the product of the number of times of the granted access right to the first request issuing control unit or the second request issuing control unit and the probability of using the granted access right to the total number of access requests that have not passed through the interconnect at a predetermined timing determined based on the timing of granting the access right to the first request issuing control unit or the second request issuing control unit, and stops granting the access right when the calculated value is greater than a predetermined value.

13. The semiconductor device according to claim 1, wherein the memory controller includes: A cache; And A prefetch control unit that controls the prefetch of data for obtaining data having a size larger than the size of the access data from the memory, and stores the obtained data in the cache when the access request is a read, wherein the prefetch control unit determines whether to perform the prefetch based on the probability of using the access permission and the status of granting the access permission.

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