No-hold Dynamic D Flip-Flop

Abstract

The present invention provides a hold-free dynamic D flip-flop used in a computing device, comprising an input terminal, an output terminal and a clock signal terminal; a first latch unit for transmitting data at the input terminal and latching the data under the control of a clock signal; a second latch unit for latching data at the output terminal and inverting and transmitting the data latched by the first latch unit under the control of a clock signal; an output drive unit for inverting and outputting the data received from the second latch unit; the first latch unit, the second latch unit and the output drive unit are sequentially connected in series between the input terminal and the output terminal; wherein the second latch unit realizes the output of three states of high level, low level and high impedance through a single element under the control of a clock signal; and the first latch unit adopts a delay unit. The back-end layout and wiring process can be simplified, the design difficulty can be reduced, the performance can be improved, and the practicality can be increased.

Description

Technical Field

[0001] The present invention relates to a storage device controlled by a clock, and in particular to a retention-free dynamic D trigger applied in a computing device. Background Art

[0002] The D flip-flop is widely used and can be used for digital signal storage, shift storage, frequency division and waveform generator, etc. The D flip-flop has two inputs, data (Data) and clock (CLK), and one output (Q), which can write data into the D flip-flop or read data from it.

[0003] CN1883116A discloses a Figure 1 The positive feedback D flip-flop circuit 106 shown includes an analog switch 300, an inverter 302, an analog switch 304, an inverter 306, an inverter 308, an analog switch 310, an inverter 312, and an analog switch 314. The analog switches 300, 304, 310, and 314 are analog switches using P-channel / N-channel transistors, and the switching action is performed by CKP in the same phase as CK and CKN in the opposite phase to CK. Inverters 302, 306, inverters 308, and 312 are CMOS inverters. It can be seen that a traditional D flip-flop basically requires 16 PMOS / NMOS transistors, which occupies a large area.

[0004] For massive computing processes of a large number of repetitive logic computing pipelines, several D flip-flops are needed to store data. This will lead to the disadvantages of increased chip area, slower computing speed, and poor control of leakage in computing devices that require a large number of D flip-flops.

[0005] CN1883116A also discloses a method such as Figure 2 The dynamic D flip-flop circuit 102 shown in FIG. 1 includes a first analog switch 200, a first inverter 202, a second analog switch 204, and a second inverter 206. The dynamic D flip-flop circuit 102 forms a sample-and-hold circuit through the analog switches of the first analog switch 200 and the second analog switch 204, and the parasitic capacitances such as the gate capacitance and wiring capacitance of the first inverter 202 and the second inverter 206.

[0006] The register composed of the above-mentioned dynamic D flip-flop has the problem that the analog switch is difficult to control and the access speed is slow. Summary of the invention

[0007] In order to solve the above problems, the present invention provides a hold-free dynamic D flip-flop for a computing device, which can effectively reduce the design difficulty, reduce the chip area, reduce power consumption, and achieve clock synchronization.

[0008] In order to achieve the above object, the present invention provides a hold-free dynamic D flip-flop, comprising:

[0009] An input terminal, an output terminal and a clock signal terminal;

[0010] a first latch unit, used for transmitting the data of the input terminal and latching the data under the control of a clock signal;

[0011] a second latch unit, used for latching the data of the output terminal and transmitting the data latched by the first latch unit in an inverted manner under the control of a clock signal;

[0012] an output driving unit, configured to invert and output the data received from the second latch unit;

[0013] The first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

[0014] Among them, the second latch unit realizes the output of three states of high level, low level and high impedance through a single element under the control of the clock signal; and the first latch unit adopts a delay unit design.

[0015] In the above-mentioned hold-free dynamic D flip-flop, the clock signal terminal is connected to a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

[0016] In the above-mentioned retention-free dynamic D flip-flop, the second latch unit is a three-state inverter.

[0017] The above-mentioned hold-free dynamic D flip-flop, wherein the three-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series between the power supply and the ground in sequence.

[0018] In the above-mentioned hold-free dynamic D flip-flop, the first PMOS transistor and the second NMOS transistor are switched according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

[0019] In the above-mentioned hold-free dynamic D flip-flop, the second PMOS transistor and the first NMOS transistor are switched according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

[0020] The use of the non-hold dynamic D flip-flop of the present invention can reduce the chip area by nearly 30%, thereby reducing the production cost of the chip and increasing product competitiveness. It can simplify the back-end layout and wiring design process, reduce the design difficulty, improve performance, and increase practicality.

[0021] In order to better achieve the above-mentioned purpose, the present invention also provides a data operation unit, including a control circuit, an operation circuit, and a plurality of hold-free dynamic D flip-flops that are interconnected, and the plurality of hold-free dynamic D flip-flops are connected in series and / or in parallel; wherein the plurality of hold-free dynamic D flip-flops are any one of the hold-free dynamic D flip-flops described above.

[0022] In order to better achieve the above-mentioned purpose, the present invention also provides a chip, which adopts any one of the above-mentioned data operation units.

[0023] In order to better achieve the above-mentioned purpose, the present invention also provides a computing board for a computing device, which adopts any one of the above-mentioned chips.

[0024] In order to better achieve the above-mentioned purpose, the present invention also provides a computing device, including a power board, a control board, a connecting board, a radiator and a plurality of computing boards, wherein the control board is connected to the computing board through the connecting board, the radiator is arranged around the computing board, and the power board is used to provide power to the connecting board, the control board, the radiator and the computing board, wherein the computing board is any one of the computing boards mentioned above.

[0025] The computing device of the present invention can better save chip area, reduce production costs, and further reduce power consumption of the computing device.

[0026] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0027] Certain terms are used in the specification and subsequent claims to refer to specific components. A person with ordinary knowledge in the field should understand that manufacturers may use different terms to refer to the same component. This specification and subsequent claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0028] The words "include" and "comprising" mentioned throughout the specification and in the subsequent claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the word "connect" is used herein to include any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1It is a schematic diagram of an existing positive feedback D flip-flop;

[0030] Figure 2 It is a schematic diagram of an existing dynamic D flip-flop;

[0031] Figure 3A This is a schematic diagram of the structure of a hold-free dynamic D flip-flop according to an embodiment of the present invention;

[0032] Figure 3B A schematic diagram of the structure of a clock-controlled dynamic D flip-flop without holding according to an embodiment of the present invention;

[0033] Figure 4A This is a schematic diagram of a hold-free dynamic D flip-flop circuit according to an embodiment of the present invention;

[0034] Figure 4B This is a schematic diagram of a hold-free dynamic D flip-flop circuit according to another embodiment of the present invention;

[0035] Figure 5A It is an equivalent circuit diagram of the present invention when the non-hold dynamic D flip-flop writes data;

[0036] Figure 5B It is an equivalent circuit diagram of the data holding state of the non-hold dynamic D flip-flop of the present invention;

[0037] Figure 6 This is a timing diagram of a hold-free dynamic D flip-flop of the present invention;

[0038] Figure 7 This is a schematic diagram of a data operation unit of the present invention;

[0039] Figure 8 It is a schematic diagram of the chip of the present invention;

[0040] Fig. 9 This is a schematic diagram of the computing board of the present invention;

[0041] Fig.10 Schematic diagram of the computing device of the present invention.

[0042] Wherein, the reference numerals are:

[0043] 100: Parasitic capacitance

[0044] 102: Dynamic D Flip Flop

[0045] 106: Positive feedback D flip-flop circuit

[0046] 200, 204, 300, 304, 310, 314: Analog switches

[0047] 400, 400', 500, 600: Dynamic D flip-flop without retention

[0048] 401: first latch unit

[0049] 402: Second latch unit

[0050] 403: Output drive unit

[0051] 404: Input

[0052] 405: Output

[0053] 406: Clock Buffer

[0054] 501, 601: Transmission gate

[0055] 502, 602: Three-state inverter

[0056] 202, 206, 302, 306, 308, 312, 503, 603: Inverter

[0057] 506, 510, 511: PMOS transistors

[0058] 507, 512, 513: NMOS transistors

[0059] 508, 509, 514, 515: Gate terminal

[0060] 550, 551, 650, 651: nodes

[0061] 504, 604: Input terminal

[0062] 505, 605: Output terminal

[0063] CLK, CLKN, CLKP, clock signal DETAILED DESCRIPTION

[0064] The structural principle and working principle of the present invention are described in detail below in conjunction with the accompanying drawings:

[0065] Figure 3A FIG. 1 is a schematic diagram of a structure of a dynamic D flip-flop without retention according to an embodiment of the present invention. Figure 3A As shown, the non-holding dynamic D flip-flop 400 is composed of a first latch unit 401, a second latch unit 402 and an output driving unit 403. The first latch unit 401, the second latch unit 402 and the output driving unit 403 are sequentially connected in series between the input terminal 404 and the output terminal 405 of the non-holding dynamic D flip-flop 400.

[0066] Figure 3B FIG. 1 is a schematic diagram of a clock-controlled dynamic D flip-flop structure without holding according to an embodiment of the present invention. Figure 3BAs shown, the non-retention dynamic D flip-flop 400' with clock control is composed of the non-retention dynamic D flip-flop 400 and a clock buffer 406. The clock signal CLK is buffered by the clock buffer 406 and then provides a clock control signal to the non-retention dynamic D flip-flop 400.

[0067] The first latch unit 401 of the non-hold dynamic D flip-flop of the present invention adopts a delay unit design, and the clock buffer 406 adopts a high-speed unit design.

[0068] Embodiment 1:

[0069] Figure 4A FIG. 4 is a circuit diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention.

[0070] like Figure 4A As shown, the first latch unit 401 of the non-holding dynamic D flip-flop 500 is a transmission gate 501, and the transmission gate 501 uses a PMOS transistor 506 and an NMOS transistor 507 connected in parallel, and forms an analog switch under the control of a clock signal. Among them, one end of the transmission gate 501 is connected to the input end 504 of the non-holding dynamic D flip-flop 500, the gate end 508 of the PMOS transistor 506 is controlled by the clock signal CLKP, and the gate end 509 of the NMOS transistor 507 is controlled by the clock signal CLKN with a phase opposite to CLKP. The clock signals CLKP and CLKN are both provided by a clock buffer (not shown in the figure). When CLKP is at a high level, CLKN is at a low level, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are not turned on, the transmission gate 501 is closed, and the data of the input terminal 504 cannot be transmitted to the other end of the transmission gate 501, that is, the data at the first node 550 at the other end of the transmission gate 501 is latched and maintained in the original state; when CLKP is at a low level, CLKN is at a high level, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are turned on, the transmission gate 501 is turned on, the data of the input terminal 504 is transmitted to the other end of the transmission gate 501 through the transmission gate 501, and the data at the first node 550 is rewritten into the same data as the data of the input terminal 504.

[0071] like Figure 4AAs shown, the second latch unit 402 of the non-hold dynamic D flip-flop 500 is a tri-state inverter 502, and the tri-state inverter 502 includes PMOS transistors 510, 511 and NMOS transistors 512, 513. The gates of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form the input end of the tri-state inverter 502. The source of the PMOS transistor 510 is connected to the power supply VDD, and the source of the NMOS transistor 513 is connected to the ground GND. The drains of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form the output end of the tri-state inverter 502. The source of the PMOS transistor 511 is connected to the drain of the PMOS transistor 510, and the source of the NMOS transistor 512 is connected to the drain of the NMOS transistor 513.

[0072] The gate terminal 514 of the PMOS transistor 510 is controlled by the clock signal CLKN, and the gate terminal 515 of the NMOS transistor 513 is controlled by the clock signal CLKP, serving as the clock control terminal of the tri-state inverter 502 .

[0073] When CLKP is at a low level, CLKN is at a high level, the PMOS transistor 510 and the NMOS transistor 513 are both in a non-conducting state, the three-state inverter 502 is in a high-impedance state, the data at the first node 550 cannot pass through the three-state inverter 502, and the data at the second node 551 is latched and maintains the original state, which plays the role of data storage.

[0074] When CLKP is at a high level, CLKN is at a low level, the PMOS transistor 510 and the NMOS transistor 513 are both in the on state, and the three-state inverter 502 inverts the data at its input end, that is, inverts the data at the first node 550 and outputs it to the second node 551, rewriting the data at the second node 551.

[0075] like Figure 4A As shown, the output driving unit is an inverter 503, which inverts the data received from the tri-state inverter 502 again to form data with the same phase as the data of the input terminal 504 of the dynamic D flip-flop, and outputs the data through the output terminal 505. At the same time, the output driving unit can also improve the driving capability of the data.

[0076] Embodiment 2:

[0077] like Figure 4BAs shown, the first latch unit 401 of the non-holding dynamic D flip-flop 600 is a transmission gate 601, and the transmission gate 601 uses a PMOS transistor 606 and an NMOS transistor 607 connected in parallel, and forms an analog switch under the control of a clock signal. One end of the transmission gate 601 is connected to the input end 604 of the non-holding dynamic D flip-flop 600, the gate end 608 of the PMOS transistor 606 is controlled by the clock signal CLKP, and the gate end 609 of the NMOS transistor 607 is controlled by the clock signal CLKN with a phase opposite to that of CLKP. The clock signals CLKP and CLKN are both provided by a clock buffer (not shown in the figure). When CLKP is at a high level, CLKN is at a low level, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are not turned on, the transmission gate is closed, the data of the input terminal 604 cannot be transmitted to the other end of the transmission gate 601, and the data at the first node 650 is latched and maintained in the original state; when CLKP is at a low level, CLKN is at a high level, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are turned on, the transmission gate 601 is turned on, the data of the input terminal 604 is output to the other end through the transmission gate 601, and the data at the first node 650 is rewritten into the same data as the data of the input terminal 604.

[0078] like Figure 4B As shown, the second latch unit 402 of the non-hold dynamic D flip-flop 600 is a tri-state inverter 602, and the tri-state inverter 602 includes PMOS transistors 610, 611 and NMOS transistors 612, 613. The gates of the PMOS transistor 610 and the NMOS transistor 613 are connected together to form the input end of the tri-state inverter 602. The source of the PMOS transistor 610 is connected to the power supply VDD, and the source of the NMOS transistor 613 is connected to the ground GND. The drains of the PMOS transistor 611 and the NMOS transistor 612 are connected together to form the output end of the tri-state inverter 602. The source of the PMOS transistor 611 is connected to the drain of the PMOS transistor 610, and the source of the NMOS transistor 612 is connected to the drain of the NMOS transistor 613.

[0079] The gate terminal 614 of the PMOS transistor 611 is controlled by the clock signal CLKN, and the gate terminal 615 of the NMOS transistor 612 is controlled by the clock signal CLKP, serving as the clock control terminal of the tri-state inverter 602 .

[0080] When CLKP is at a low level, CLKN is at a high level, the PMOS transistor 611 and the NMOS transistor 612 are both in a non-conducting state, the three-state inverter 602 is in a high-impedance state, the data at the first node 650 cannot pass through the three-state inverter 602, and the data at the second node 651 is latched and maintains the original state, which plays a role in data storage.

[0081] When CLKP is high, CLKN is low, the PMOS transistor 611 and the NMOS transistor 612 are both in the on state, and the three-state inverter 602 inverts the data at its input end, that is, inverts the data at the first node 650 and outputs it to the second node 651, rewriting the data at the second node 651.

[0082] like Figure 4B As shown, the output driving unit is an inverter 603, which inverts the data received from the tri-state inverter 602 again to form data with the same phase as the data at the input terminal 604 of the dynamic D flip-flop, and outputs the data through the output terminal 605. At the same time, the output driving unit can improve the driving capability of the data.

[0083] The working principle of the hold-free dynamic D flip-flop of the present invention is described in detail below.

[0084] Figure 5A This is the equivalent circuit diagram of the present invention when the non-hold dynamic D flip-flop writes data. Figure 5B This is an equivalent circuit diagram of the data retention state of the non-retention dynamic D flip-flop of the present invention.

[0085] Combination Figure 4A , Figure 4B as well as Figure 5A As shown, when CLKP is at a high level and CLKN is at a low level, the transistors controlled by the clock of the three-state inverters 502 and 602 are turned on, and the data transmitted from the transmission gates 501 and 601 are written into the parasitic capacitor 100. When the input data is "0", the PMOS transistors 510, 511, 610, and 611 of the three-state inverters 502 and 602 are all in a conducting state, forming a pull-up path to charge the parasitic capacitor 100, and the second nodes 551 and 651 become high level, and the data become "1"; when the input data is "1", the NMOS transistors 512, 513, 612, and 613 of the three-state inverters 502 and 602 are all in a conducting state, forming a pull-down path, so that the parasitic capacitor 100 is discharged, and the second nodes 551 and 651 become low level, and the data become "0".

[0086] like Figure 5BAs shown, after the parasitic capacitor 100 is charged, if the three-state inverters 502 and 602 are in a high-impedance state under the control of the clock signal, the parasitic capacitor 100 will not be further charged, and the data at the second nodes 551 and 651 will be kept. On the other hand, due to the influence of the leakage current of the NMOS transistors 512, 513, 612, and 613, the charge on the parasitic capacitor 100 will gradually be leaked, and the high level on the second nodes 551 and 651 will be reversed to a low level after a certain length of time, and the data stored in the parasitic capacitor 100 will change from "1" to "0", eventually causing data errors.

[0087] Assuming that the charge generated on the parasitic capacitor 100 is Q, the capacitance value of the parasitic capacitor 100 is C, and the voltage across the parasitic capacitor plate is V, then

[0088] Q = C * V.

[0089] If the leakage current is I leakage , then the leakage time t is

[0090] t = Q / I leakage = C * V / I leakage 。

[0091] Under the existing production process, the data stored in the parasitic capacitor 100 can be maintained for about 5ns. In other words, if the data stored in the parasitic capacitor is periodically updated during the data retention period, data errors will not occur. The operating frequency of existing computing devices is generally above 500MHz, which far exceeds the required data update frequency, so that the dynamic D flip-flop of the present invention can be used in computing devices.

[0092] Figure 6 This is the timing diagram of the non-hold dynamic D flip-flop of the present invention. Figure 6 As shown, when CLKP is at a low level and CLKN is at a high level, the first latch unit 401 is turned on, and the data of the input terminal D passes through the first latch unit 401, the second latch unit 402 is not turned on, and the output of the dynamic D flip-flop maintains the original state. When the rising edge of CLKP comes, CLKP jumps to a high level and CLKN jumps to a low level, the first latch unit 401 is not turned on, cutting off the data input of the input terminal D, and the second latch unit 402 is turned on, and the maintained data of the input terminal D is output through the output terminal Q. It can be seen that the state change of the output terminal of the dynamic D flip-flop of the present invention occurs when the rising edge of the clock signal CLKP comes, and when CLKP is at a high level and CLKN is at a low level, the output state remains unchanged.

[0093] like Figure 6As shown in the figure, the setup time of a hold-free dynamic D flip-flop refers to the time that the data at the data input of the flip-flop must remain unchanged before the clock edge arrives; the setup time determines the maximum delay of the combinational logic between the flip-flops. The hold time of a dynamic D flip-flop refers to the time that the data at the data input of the flip-flop must remain unchanged after the clock edge arrives; the hold time determines the minimum delay of the combinational logic between the flip-flops.

[0094] In the retention-free dynamic D flip-flop 400 , an increase in the retention time will cause the data reading speed of the retention-free dynamic D flip-flop 400 to slow down, and in severe cases, data reading errors may occur.

[0095] Therefore, it is necessary to increase the data transmission time of the non-hold dynamic D flip-flop. The first latch unit 401 of the non-hold dynamic D flip-flop in the present invention, namely the transmission gates 501 and 601, adopts a delay unit design, which reduces the speed by adopting a high threshold device, adopts a small size, reduces leakage and transmission speed, and uses layout parasitic resistance and capacitance to slow down the transmission speed. Thus, the holding time of the dynamic D flip-flop is reduced.

[0096] In addition, the clock buffer 406 in the present invention adopts a high-speed unit design, including at least one cascaded clock buffer unit, and uses low threshold voltage devices and increases device size to enhance driving capability; adopts a reasonable clock delay distribution scheme to balance the driving balance between loads and increase the overall driving speed, thereby reducing the holding time of the dynamic D flip-flop.

[0097] The first latch unit 401 adopts a delay unit design and the clock buffer 406 adopts a high-speed unit design and can be used in the non-hold dynamic D flip-flop circuit of the present invention alone or simultaneously.

[0098] The present invention also provides a data operation unit. Figure 7 Schematic diagram of the data operation unit of the present invention. Figure 7 As shown, the data operation unit 700 includes a control circuit 701, an operation circuit 702, and a plurality of hold-free dynamic D flip-flops 500 and 600. The control circuit 701 refreshes the data in the hold-free dynamic D flip-flops 500 and 600 and reads data from the hold-free dynamic D flip-flops 500 and 600, the operation circuit 702 operates on the read data, and then the control circuit 701 outputs the operation result.

[0099] The present invention also provides a chip. Figure 8 FIG. 2 is a schematic diagram of the chip of the present invention. Figure 8As shown, the chip 800 includes a control unit 801 and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.

[0100] The present invention also provides a computing board. Fig. 9 This is a schematic diagram of the computing board of the present invention. Fig. 9 As shown, each computing board 900 includes one or more chips 800 to perform hash operations on working data.

[0101] The present invention also provides a computing device, which is used for any other massive computing. Fig.10 FIG. 1 is a schematic diagram of a computing device according to the present invention. Fig.10 As shown, each computing device 1000 includes a connection board 1001, a control board 1002, a radiator 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the computing board 900 through the connection board 1001, and the radiator 1003 is arranged around the computing board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the radiator 1003 and the computing board 900.

[0102] It should be noted that, in the description of the present invention, the terms "lateral", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc. indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0103] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

[0104] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, technicians familiar with the field can make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A hold-free dynamic D flip-flop, characterized in that: include: An input terminal, an output terminal and a clock signal terminal; a first latch unit, used for transmitting the data of the input terminal and latching the data under the control of a clock signal; a second latch unit, used for latching the data of the output terminal and transmitting the data latched by the first latch unit in an inverted manner under the control of a clock signal; an output driving unit, configured to invert and output the data received from the second latch unit; The first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end; Among them, the second latch unit realizes the output of three states of high level, low level and high resistance through a single element under the control of the clock signal; the first latch unit adopts a delay unit design, the first latch unit is a transmission gate, the transmission gate adopts a PMOS transistor and an NMOS transistor connected in parallel, and forms an analog switch under the control of the clock signal.

2. The hold-free dynamic D flip-flop as claimed in claim 1, characterized in that: The clock signal terminal is connected to a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

3. The hold-free dynamic D flip-flop as claimed in claim 2, characterized in that: The second latch unit is a tri-state inverter.

4. The hold-free dynamic D flip-flop as claimed in claim 3, characterized in that: The tri-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and a ground.

5. The hold-free dynamic D flip-flop as claimed in claim 4, characterized in that: The first PMOS transistor and the second NMOS transistor are switched according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are inversely proportional.

6. The hold-free dynamic D flip-flop as claimed in claim 4, characterized in that: The second PMOS transistor and the first NMOS transistor are switched on and off according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are in opposite phases.

7. A data operation unit, comprising a control circuit, an operation circuit, and a plurality of hold-free dynamic D flip-flops connected to each other, wherein the plurality of hold-free dynamic D flip-flops are connected in series and / or in parallel; characterized in that: The multiple hold-free dynamic D flip-flops are the hold-free dynamic D flip-flops described in any one of claims 1-6.

8. A chip, characterized in that: Includes any one of the data operation units described in claim 7.

9. A computing board for computing equipment, characterized in that: Comprising a plurality of chips described in any one of claims 8.

10. A computing device, comprising a power board, a control board, a connection board, a radiator and a plurality of computing boards, wherein the control board is connected to the computing board through the connection board, the radiator is arranged around the computing board, the power board is used to provide power to the connection board, the control board, the radiator and the computing board, and characterized in that: The computing board is any one of the computing boards described in claim 9.

Images