Light emitting device package, display apparatus including the same, and method of manufacturing the same

Abstract

A light emitting device package, a display apparatus including the light emitting device package, and a method of manufacturing the light emitting device package are provided. The light emitting device package includes a substrate having a first surface and a second surface, and having a first opening and a second opening spaced apart from each other, a light emitting structure disposed on the first surface of the substrate and vertically overlapping the first opening, and an image sensor including a photoelectric conversion region disposed in the substrate and vertically overlapping the second opening. Light from the light emitting structure is emitted toward the second surface of the substrate through the first opening.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0073459, filed on June 26, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus and method of exemplary embodiments of the present invention relate to a compound semiconductor-based light-emitting device package, a display device including the light-emitting device package, and a method of manufacturing the light-emitting device package. Background Technology

[0004] Semiconductor light-emitting devices are widely used as light sources for display devices and lighting devices. Recently, a display device has been proposed in which the light-emitting device is used as a pixel. In addition, mobile devices such as smartphones or wearable devices equipped with fingerprint sensors are widely used, but in these devices, the thickness of the display device increases because a separate substrate with the fingerprint sensor is attached to the display panel. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a light-emitting device package and a display device using the light-emitting device package, wherein the light-emitting device package integrally provides a display fingerprint sensor and a support substrate for the light-emitting device, and does not require a separate substrate for mounting the fingerprint sensor thereon.

[0006] According to an example embodiment, a light-emitting device package is provided, which may include: a substrate having a first surface and a second surface, and having a first opening and a second opening spaced apart from each other; a light-emitting structure disposed on the first surface of the substrate and vertically overlapping the first opening; and a sensor including a photoelectric conversion region disposed in the substrate and vertically overlapping the second opening, wherein light from the light-emitting structure is emitted through the first opening toward the second surface of the substrate.

[0007] According to an example embodiment, a display device is provided, which may include a display area and a fingerprint sensing area overlapping at least a portion of the display area, wherein the fingerprint sensing area includes the aforementioned light-emitting device package.

[0008] According to an example embodiment, a display device is provided, which includes a plurality of pixels, wherein at least one of the plurality of pixels includes the above-mentioned light-emitting device package.

[0009] According to an example embodiment, a method for manufacturing a light-emitting device package is provided. The method may include: forming a plurality of light-emitting structures on a first surface in a first region of a substrate; forming a photoelectric conversion region in a second region of the substrate; removing the first region of the substrate from the second surface opposite to the first surface of the substrate to form a plurality of first openings exposing the plurality of light-emitting structures; and removing the second region of the substrate from the second surface of the substrate to form a plurality of second openings exposing the photoelectric conversion region.

[0010] According to an example embodiment, a display device is provided that includes a plurality of pixels, each of which includes a plurality of sub-pixels, wherein the plurality of sub-pixels includes and shares a light-emitting structure configured to generate and emit light, wherein the light-emitting structure is formed on a first surface of a substrate and includes the same number of regions as the plurality of sub-pixels, and wherein at least one image sensor is disposed on a second surface of the substrate opposite to the first surface, the light-emitting structure being divided in the substrate to form the respective regions of the light-emitting structure, and the at least one image sensor being configured to sense light reflected by an object on the substrate based on light emitted from the light-emitting structure. Attached Figure Description

[0011] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a perspective view of a representative configuration of a display device according to an example embodiment;

[0013] Figure 2 According to the example embodiment Figure 1 A planar image of one pixel;

[0014] Figure 3 It is a planar view of one pixel according to the example embodiment;

[0015] Figure 4 This is a plan view of the main structure of the light-emitting device package according to an example embodiment;

[0016] Figure 5 It is according to the example embodiment along Figure 4 A cross-sectional view taken from line A1-A1';

[0017] Figure 6 It is according to the example embodiment along Figure 4 A cross-sectional view taken from line B1-B1';

[0018] Figure 7 It is according to the example embodiment along Figure 4 A cross-sectional view taken from line C1-C1';

[0019] Figure 8According to the example embodiment Figure 6 A magnified view of part of BX2;

[0020] Figure 9 According to the example embodiment Figure 7 A magnified view of part of CX2;

[0021] Figure 10 This is a circuit diagram of a sensor according to an example embodiment;

[0022] Figure 11 and Figure 12 This is a cross-sectional view of the light-emitting device package according to an example embodiment;

[0023] Figure 13 This is a cross-sectional view of the light-emitting device package according to an example embodiment;

[0024] Figure 14 This is a cross-sectional view of the light-emitting device package according to an example embodiment;

[0025] Figure 15 This is a cross-sectional view of the light-emitting device package according to an example embodiment;

[0026] Figure 16 and Figure 17 This is a cross-sectional view of the light-emitting device package according to an example embodiment;

[0027] Figures 18A to 24C A cross-sectional view showing a method for manufacturing a light-emitting device package according to an example embodiment, arranged in the order of processing; and

[0028] Figure 25 This is a schematic diagram illustrating a cross-sectional structure of a quantum dot (QD) that can be used as a wavelength conversion material in a light-emitting device package according to an example embodiment. Detailed Implementation

[0029] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. The same reference numerals throughout the specification and drawings refer to the same elements.

[0030] The exemplary embodiments provided in the following description are not excluded from being associated with one or more features of another example or another embodiment that are also provided herein or that are not provided herein but are consistent with the inventive concept. For example, even if a matter described in a particular example is not described in its different examples, such matter may be understood to be related to or combined with the different examples unless otherwise mentioned in its description.

[0031] It should be understood that when an element or layer is referred to as being "above," "over," "on," "connected to," or "coupled to" another element or layer, it may be directly above, above, on, connected to, or coupled to the other element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as being "directly above," "over," "on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers present. The same reference numerals always refer to the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “on,” and “above” are used herein to describe the relationship between one element or feature shown in the accompanying drawings and another element or feature. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures were inverted, an element described as “below other elements” or “below other elements” would therefore be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both the orientations of “above” and “below.” The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0033] As used herein, when expressions such as “at least one of” appear after a list of elements, they modify the entire list of elements, not individual elements within the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, a and b, a and c, b and c, or all of a, b, and c.

[0034] Figure 1 This is a perspective view of a representative configuration of the display device 1 according to an example embodiment. Figure 2 yes Figure 1 The image shown is a planar view of a single pixel PX.

[0035] Reference Figure 1 and Figure 2The display device 1 may include a display panel 10, and the display panel 10 may include a display area APR and a peripheral area EPR surrounding the display area APR in a plan view. The display area APR may include a plurality of pixels PX capable of displaying an image in response to a signal. The display panel 10 may include a printed circuit board (not shown) and a light-emitting device package (not shown) mounted on the printed circuit board. The light-emitting device package may include a plurality of light-emitting devices corresponding to the plurality of pixels PX respectively.

[0036] Display panel 10 may include a fingerprint sensing region FSR that overlaps with at least a portion of display area APR. The fingerprint sensing region FSR can optically identify an object touching display panel 10 (e.g., a user's finger) and convert fingerprint information into an image signal. For example, when light emitted from the fingerprint sensing region FSR is reflected by the ridges and valleys between the ridges of a fingerprint, the reflected light can be sensed by an image sensor in the fingerprint sensing region FSR, thereby identifying the fingerprint. A plurality of pixels PX in the fingerprint sensing region FSR can emit light for fingerprint sensing and also sense light reflected by the fingerprint.

[0037] Figure 1 An example is shown where the fingerprint sensing area FSR is formed in a portion of the lower part of the display panel 10, but the location and area of ​​the fingerprint sensing area FSR are not limited thereto. In other embodiments, the fingerprint sensing area FSR may be arranged throughout the entire area of ​​the display panel 10 to have the same area as the display area APR.

[0038] like Figure 2 As shown, the fingerprint sensing area FSR may include a plurality of pixels PX, each including an image sensor FSU. Each of the plurality of pixels PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 arranged consecutively in one direction. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may respectively include the first sensor FSU1, the second sensor FSU2, and the third sensor FSU3.

[0039] The first to third sub-pixels (SPX1, SPX2, and SPX3) can emit light of different wavelengths in response to an input signal. For example, the first to third sub-pixels (SPX1, SPX2, and SPX3) can emit red (R), green (G), and blue (B) light, respectively. In an example embodiment, the first to third sub-pixels (SPX1, SPX2, and SPX3) can include compound semiconductor light-emitting devices that emit light of different wavelengths from a compound semiconductor material layer. For example, the compound semiconductor material layer can include group II and IV semiconductor materials.

[0040] The first to third sensors (FSU1, FSU2, and FSU3) can be formed in a substrate to support the compound semiconductor light-emitting devices in the first to third sub-pixels (SPX1, SPX2, and SPX3). Therefore, the compound semiconductor light-emitting devices and the sensor FSUs (i.e., the first to third sensors (FSU1, FSU2, and FSU3)) can be integrally disposed. For example, light emitted by the first to third sub-pixels (SPX1, SPX2, and SPX3) in pixel PX can be reflected by the ridges and valleys of the fingerprint, and the image sensor FSU can sense the reflected light to generate an image signal of the fingerprint.

[0041] Figure 3 This is a plan view of a pixel PX according to an example embodiment.

[0042] Reference Figure 3 Pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4 arranged in a matrix. For example, the first to fourth sub-pixels (SPX1, SPX2, SPX3, and SPX4) may be arranged in a 2×2 matrix.

[0043] At least one of the first to fourth sub-pixels (SPX1, SPX2, SPX3 and SPX4) may include an image sensor FSU. Figure 3 An example is shown where the first sub-pixel SPX1 includes a first sensor FSU1, the fourth sub-pixel SPX4, arranged diagonally relative to the first sub-pixel SPX1, includes a second sensor FSU2, and the second sub-pixel SPX2 and the third sub-pixel SPX3 do not include sensors. However, the inventive concept is not limited thereto.

[0044] Figure 4 This is a bottom plan view of the main structure of the light-emitting device package 100 according to an example embodiment. Figure 5 It is along Figure 4 A cross-sectional view taken from line A1-A1'. Figure 6 It is along Figure 4 The cross-sectional view taken by line B1-B1', and Figure 7 It is along Figure 4 The cross-sectional view taken from line C1-C1'. Figure 8 yes Figure 6 A magnified view of part of BX2, and Figure 9 yes Figure 7 A magnified view of part of CX2. The light-emitting device package 100 may be the same as that of the display panel 10 and the reference. Figure 1 and Figure 2 The portion corresponding to a pixel PX of the described display device 1.

[0045] Reference Figures 4 to 9 The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be spaced apart in sequence in the X direction. The first sub-pixel SPX1 may include a first light-emitting structure LS1, a first switch SW1, and a first sensor SU1; the second sub-pixel SPX2 may include a second light-emitting structure LS2, a second switch SW2, and a second sensor SU2; and the third sub-pixel SPX3 may include a third light-emitting structure LS3, a third switch SW3, and a third sensor SU3.

[0046] In the first sub-pixel SPX1, the first light-emitting structure LS1 and the first sensor SU1 can be arranged horizontally or laterally. For example... Figure 4 As shown, the first light-emitting structure LS1 and the first sensor SU1 may not overlap each other vertically. Furthermore, in the first sub-pixel SPX1, the first light-emitting structure LS1 and the first switch SW1 may be arranged horizontally.

[0047] like Figure 4 As shown, the first common pad PA1 of the semiconductor layer 122c of the second conductivity type, which is commonly connected to the first to third light-emitting structures (LS1, LS2, and LS3), may overlap with one end of each of the first to third light-emitting structures (LS1, LS2, and LS3) in the plan view, and the second common pad PA2 of the semiconductor layer 122a of the first conductivity type, which is commonly connected to the first to third light-emitting structures (LS1, LS2, and LS3), may overlap with the other end of the first to third light-emitting structures (LS1, LS2, and LS3) in the plan view. The first to third connecting pads (PB1, PB2, and PB3) may be arranged on the first to third switches (SW1, SW2, and SW3), respectively, and the fourth to sixth connecting pads (PC1, PC2, and PC3) may be arranged on the first to third sensors (SU1, SU2, and SU3), respectively. However, the arrangement and shape of the first common pad PA1, the second common pad PA2, and the first to sixth connecting pads (PB1, PB2, PB3, PC1, PC2, and PC3) are not limited thereto. For example, the first connecting pad PB1 and the fourth connecting pad PC1 can be connected to each other to form a single pad.

[0048] The substrate 110 can be used as a support substrate for supporting the first to third light-emitting structures (LS1, LS2, and LS3), and can also be used as a wall structure for separating the first to third light-emitting structures (LS1, LS2, and LS3). For example, the substrate 110 may have a first surface 110F1 and a second surface 110F2 opposite to each other, and may have a plurality of first openings 110H1 and a plurality of second openings 110H2 (see...). Figure 7Each first opening 110H1 may overlap with the first to third light-emitting structures (LS1, LS2 and LS3) in a plan view (for example, each first opening 110H1 may vertically overlap with the first to third light-emitting structures (LS1, LS2 and LS3) in a plan view), and each second opening 110H2 may overlap with the first to third sensors SU1, SU2 and SU3 in a plan view.

[0049] The first to third light-emitting structures (LS1, LS2, and LS3) may be located on the first surface 110F1 of the substrate 110 to overlap with the plurality of first openings 110H1. Figure 5 As shown, each of the first openings 110H1 may have a sidewall that is inclined at a specific angle relative to the first surface 110F1 of the substrate 110 or may have a vertical sidewall.

[0050] like Figure 5 As shown, substrate 110 may include semiconductor substrate 112 and epitaxial semiconductor layer 114 located on the upper surface of semiconductor substrate 112.

[0051] For example, semiconductor substrate 112 may include a group IV semiconductor substrate doped with a first impurity at a first concentration. The group IV semiconductor substrate may include a silicon substrate, a silicon-germanium (SiGe) substrate, a germanium (Ge) substrate, or a silicon carbide (SiC) substrate. For example, semiconductor substrate 112 may be a silicon substrate oriented along the {111} crystal plane of silicon.

[0052] The epitaxial semiconductor layer 114 may include a semiconductor layer grown on the semiconductor substrate 112 by an epitaxial growth process, and may, for example, include silicon. For example, the epitaxial semiconductor layer 114 may be doped with a second impurity at a concentration lower than a first concentration. In an example embodiment, the semiconductor substrate 112 may include p-type impurities, and the epitaxial semiconductor layer 114 may include n-type impurities. However, the inventive concept is not limited thereto.

[0053] The substrate 110, having a structure of stacked semiconductor substrate 112 and epitaxial semiconductor layer 114, can be a growth substrate or template substrate for forming the first to third light-emitting structures (LS1, LS2, and LS3). For example, the exposed surface of the epitaxial semiconductor layer 114 of the substrate 110 can correspond to the first surface 110F1 of the substrate 110, and the exposed surface of the semiconductor substrate 112 can correspond to the second surface 110F2 of the substrate 110. The first to third light-emitting structures (LS1, LS2, and LS3) can be located on the first surface 110F1 of the substrate 110 (i.e., the exposed surface of the epitaxial semiconductor layer 114).

[0054] Each of the first to third light-emitting structures (LS1, LS2, and LS3) may include a light-emitting stack 122, and the light-emitting stack 122 may include a first conductivity type semiconductor layer 122a, an active layer 122b, and a second conductivity type semiconductor layer 122c arranged sequentially on a first surface 110F1 of the substrate 110. The light-emitting stack 122 may include a mesa etched portion 122E in which a portion of the light-emitting stack 122 has been removed, and the bottom of the mesa etched portion 122E may extend to the upper surface of the first conductivity type semiconductor layer 122a.

[0055] The semiconductor layer 122a of the first conductivity type can be composed of n-type In x Al y Ga (1-x-y) The semiconductor is an N-type (0≤x<1, 0≤y<1, and 0≤x+y<1) nitride semiconductor, and the n-type impurity may be, for example, silicon (Si). For example, the semiconductor layer 122a of the first conductivity type may have GaN including the n-type impurity.

[0056] In an example embodiment, the semiconductor layer 122a of the first conductivity type may include a semiconductor contact layer of the first conductivity type and a current diffusion layer. The impurity concentration of the semiconductor contact layer of the first conductivity type may be approximately 2 × 10⁻⁶. 18 cm -3 Approximately 9×10 19 cm -3 Within this range. The thickness of the semiconductor contact layer of the first conductivity type can be from about 1 μm to about 5 μm. The current diffusion layer can have multiple In atoms with different compositions or different impurity contents. x Al y Ga (1-x-y) A structure in which N layers (0≤x, y≤1, and 0≤x+y≤1) are stacked alternately. For example, the current diffusion layer may have an n-type GaN layer with a thickness of about 1 nm to about 500 nm and / or an Al layer with a thickness of about 1 nm to about 500 nm. x In y Ga z An n-type superlattice structure with N layers (0≤x, y, z≤1, and x+y+z≠0) stacked alternately. The impurity concentration of the current-diffusing layer can be approximately 2×10⁻⁶. 18 cm -3 Approximately 9×10 19 cm -3 .

[0057] The active layer 122b may be located between a semiconductor layer 122a of a first conductivity type and a semiconductor layer 122c of a second conductivity type, and may emit light with specific energy through recombination of electrons and holes. The active layer 122b may have a multiple quantum well (MQW) structure with alternating quantum well layers and quantum barrier layers. For example, the quantum well layers and quantum barrier layers may include In with different compositions. x Al y Ga (1-x-y) N (0≤x, y≤1, and 0≤x+y≤1). For example, the quantum well layer may include In. x Ga 1-x The number of quantum well layers is N (0 ≤ x ≤ 1), and the quantum barrier layer may include GaN or AlGaN. The thickness of the quantum well layer and the quantum barrier layer can range from about 1 nm to about 50 nm. The active layer 122b is not limited to the MQW structure, but may have a single quantum well structure.

[0058] The second conductivity type of semiconductor layer 122c can be composed of p-type In x Al y Ga (1-x-y) A nitride semiconductor layer of N (0≤x<1, 0≤y<1, and 0≤x+y<1), and the p-type impurity may be, for example, magnesium (Mg).

[0059] In an example embodiment, the semiconductor layer 122c of the second conductivity type may include an electron blocking layer, a low-concentration p-type GaN layer, and a high-concentration p-type GaN layer serving as a contact layer. For example, the electron blocking layer may have multiple In atoms having a thickness of about 5 nm to about 100 nm and having different compositions or different impurity contents. x Al y Ga (1-x-y) A structure consisting of N layers (0≤x, y≤1, and 0≤x+y≤1) stacked alternately, or possibly including Al y Ga (1-y) A monolayer of N (0 < y ≤ 1). The band gap of the electron blocking layer can decrease as the distance from the active layer 122b increases. For example, the Al composition of the electron blocking layer can decrease as the distance from the active layer 122b increases.

[0060] The insulating layer 124 may be located on the upper surface and sidewalls of the light-emitting stack 122, and may also be conformally disposed on the inner wall of the mesa etched portion 122E. The insulating layer 124 may comprise silicon oxide or silicon nitride. Although the insulating layer 124 is located on... Figures 5 to 9 The material layer 124 is shown as a single layer, but the insulating layer 124 can be formed as a stacked structure of multiple insulating layers.

[0061] A first electrode 127 may be disposed on the upper surface of a semiconductor layer 122c of a second conductivity type, and a second electrode 128 may be disposed on the upper surface of a semiconductor layer 122a of a first conductivity type. Each of the first electrode 127 and the second electrode 128 may comprise Ag, Al, Ni, Cr, Cu, Au, Pd, Pt, Sn, W, Rh, Ir, Ru, Mg, Zn, or combinations thereof. Each of the first electrode 127 and the second electrode 128 may comprise a metallic material with high reflectivity. For example, the first electrode 127 and the second electrode 128 may be formed by etching a portion of an insulating layer 124 to expose the surfaces of the semiconductor layer 122a and the semiconductor layer 122c of the first conductivity type, and then depositing a conductive material on the exposed surfaces. Optionally, ohmic electrodes (not shown) may also be formed between the first electrode 127 and the semiconductor layer 122c of the second conductivity type, and between the second electrode 128 and the semiconductor layer 122a of the first conductivity type.

[0062] A connecting electrode 132 may be disposed on the first electrode 127, and a molding member 134 may be disposed on the insulating layer 124, the first electrode 127, and the connecting electrode 132. The molding member 134 may fill the space between adjacent light-emitting stacks 122 (e.g., the space between each of the first to third light-emitting structures (LS1, LS2, and LS3)) and the mesa etched portion 122E. The molding member 134 may comprise silicone, epoxy, or acrylic resin. A connecting via 136 may pass through the molding member 134 in the mesa etched portion 122E to connect to the second electrode 128.

[0063] A multilayer insulating structure 162 may be disposed on the molding member 134. The multilayer insulating structure 162 may include a first insulating layer 162a and a second insulating layer 162b arranged sequentially on the molding member 134. A wiring layer 164 may be formed between the first insulating layer 162a and the second insulating layer 162b, and conductive vias (166a, 166b, 166c, and 166d) may be formed to pass through at least a portion of the multilayer insulating structure 162. A first common pad PA1 and a second common pad PA2 electrically connected to the corresponding conductive vias (166a, 166b, 166c, and 166d), as well as first to sixth connecting pads (PB1, PB2, PB3, PC1, PC2, and PC3), may be disposed on the multilayer insulating structure 162. The multilayer insulating structure 162 may be formed separately in the same manner as a printed circuit board and attached to the molding member 134. However, the inventive concept is not limited thereto.

[0064] The first to third wavelength conversion layers (181, 182, and 183) may be arranged in the plurality of first openings 110H1. The first to third wavelength conversion layers (181, 182, and 183) may respectively cover the first to third light-emitting structures (LS1, LS2, and LS3) and may include different materials capable of converting the light emitted from the first to third light-emitting structures (LS1, LS2, and LS3) into a desired color. For example, the first to third wavelength conversion layers (181, 182, and 183) may include phosphors capable of converting the light emitted from the first to third light-emitting structures (LS1, LS2, and LS3) into red (R), green (G), and blue (B) light, respectively.

[0065] Each of the first to third wavelength conversion layers (181, 182, and 183) may include a resin containing a phosphor dispersed therein or a phosphor-containing film. For example, each of the first to third wavelength conversion layers (181, 182, and 183) may include a phosphor film in which phosphor particles are uniformly dispersed at a specific concentration. The first to third wavelength conversion layers (181, 182, and 183) may include two or more types of phosphor particles with different particle size distributions to increase the density of phosphor particles and improve color uniformity.

[0066] Fluorescent particles may have the following composition and color.

[0067] Based on oxides: yellow and green Y3Al5O 12 Ce、Tb3Al5O 12 Ce, Lu3Al5O 12 :Ce

[0068] Based on silicides: yellow and green (Ba,Sr)2SiO4:Eu, yellow and orange (Ba,Sr)3SiO5:Ce

[0069] Nitride-based: Green β-SiAlON:Eu, Yellow La3Si6N 11 Ce, orange α-SiAlON:Eu, red CaAlSiN3:Eu, Sr2Si5N8:Eu, SrSiAl4N7:Eu, SrLiAl3N4:Eu, Ln 4-x (Eu z M 1-z ) x Si 12-y Al y O 3+x+y N 18-x-y (0.5≤x≤3, 0<z<0.3, and 0<y≤4)---Equation (1)

[0070] In formula (1), Ln can be at least one element selected from the group consisting of group IIIa elements and rare earth elements, and M can be at least one element selected from the group consisting of calcium (Ca), barium (Ba), strontium (Sr) and magnesium (Mg).

[0071] Fluoride-based: Red K2SiF6:Mn4 based on KSF + K2TiF6:Mn4 + NaYF4:Mn4 + NaGdF4:Mn4 + K3SiF7:Mn4 +

[0072] The composition of a phosphor must substantially conform to chemical calculations, and each element can be substituted by other elements included in the various groups of the periodic table. For example, strontium (Sr) can be substituted by at least one of barium (Ba), calcium (Ca), and magnesium (Mg) selected from the Alkaline Earth II group, and Y can be substituted by at least one of terbium (Tb), lutetium (Lu), scandium (Sc), and gadolinium (Gd) selected from the lanthanides. Additionally, depending on the desired energy level, europium (Eu), as an activator, can be substituted by at least one of cerium (Ce), terbium (Tb), praseodymium (Pr), erbium (Er), and ytterbium (Yb). Activators can be used alone, or additional sub-activators can be used to modify properties.

[0073] Specifically, fluoride-based red phosphors can be coated with manganese-free fluorides to improve reliability under high temperature and humidity conditions. Alternatively, the surface of the fluoride-based red phosphor or the surface of the manganese-free fluoride coating can also be coated with organic materials. Unlike other phosphors, fluoride-based red phosphors can achieve narrow full width at half maximum (FWHM) of about 40 nm or less, thus enabling their application in high-resolution televisions such as Ultra High Definition (UHD) televisions.

[0074] Figure 25 This is a schematic diagram showing a cross-sectional structure of a quantum dot (QD) that can be used as a wavelength conversion material in a light-emitting device package according to an example embodiment.

[0075] Reference Figure 25 Quantum dots (QDs) can have a core-shell structure utilizing III-V or II-VI compound semiconductors. For example, a quantum dot can have a core such as CdSe or InP and a shell such as ZnS or ZnSe. Additionally, the quantum dot may include ligands for stabilizing the core and shell. For example, the diameter of the core can be from about 1 nm to about 30 nm, and more specifically, from about 3 nm to about 10 nm. The thickness of the shell can be from about 0.1 nm to about 20 nm, and more specifically, from about 0.5 nm to about 2 nm.

[0076] Quantum dots can be made in a variety of colors depending on their size. Specifically, when used as a substitute for phosphors, quantum dots can be used as red or green phosphors. By utilizing quantum dots, narrow full width at half maximum (FWHM) can be achieved (e.g., about 35 nm).

[0077] Return to reference Figures 4 to 9 Encapsulation layer 186 may be disposed on wavelength conversion layers (181, 182 and 183) and on the second surface 110F2 of substrate 110.

[0078] like Figure 6 and Figure 8 As shown, an active region AC for the first to third switches (SW1, SW2, and SW3) may be defined in a substrate 110 located on one side of each of the first to third light-emitting structures (LS1, LS2, and LS3). The first to third switches (SW1, SW2, and SW3) may include driving transistors for driving the first to third light-emitting structures (LS1, LS2, and LS3), respectively.

[0079] The active region AC may include a p-well 142 formed on the inner side of the first surface 110F1 of the substrate 110 and doped with p-type impurities. Although not shown in the figure, the active region AC may also include an n-pocket (not shown) surrounding the p-well 142 and doped with n-type impurities.

[0080] A gate insulating layer 144I and a gate electrode 144G may be sequentially arranged on the active region AC. A source electrode 144S and a drain electrode 144D may be arranged on the first surface 110F1 of the substrate 110 on both sides of the gate electrode 144G. A source region 143a and a drain region 143b may be formed in the active region AC below the source electrode 144S and the drain electrode 144D. Vias 146a and 146b may be formed on the gate electrode 144G and the drain electrode 144D, and the vias 146a and 146b may be electrically connected to their corresponding conductive vias 166c and 166d.

[0081] Since the active regions AC for the first to third switches (SW1, SW2 and SW3) are formed in the substrate 110, an additional substrate (e.g., a separate thin-film transistor (TFT) substrate) including driving transistors for driving the first to third light-emitting structures (LS1, LS2 and LS3) can be omitted, and the display panel 10 including the light-emitting device package 100 can be formed to have a small thickness.

[0082] like Figure 7 and Figure 9As shown, a device region (not shown) for the first to third sensors (SU1, SU2, and SU3) may be defined in a substrate 110 located on one side of each of the first to third light-emitting structures (LS1, LS2, and LS3). The sensors (SU1, SU2, and SU3) may include image sensors for sensing light emitted from the first to third light-emitting structures (LS1, LS2, and LS3) and reflected by an object (e.g., a fingerprint) located on the display panel.

[0083] The photoelectric conversion region PD and the well region PW can be disposed in the substrate 110. The photoelectric conversion region PD and the well region PW can be located in a region that vertically overlaps with the plurality of second openings 110H2. A device isolation layer STI with a specific depth can be disposed from the first surface 110F1 of the substrate 110 to the interior of the substrate 110, and the impurity region 152 and the floating diffusion region FD can be defined by the device isolation layer STI. The transfer transistor gate 154G can be disposed between the impurity region 152 and the floating diffusion region FD, and the transfer transistor gate insulating layer 154I can be disposed between the transfer transistor gate 154G and the substrate 110. The transfer transistor gate 154G can have a concave gate structure that fills the depression formed in the substrate 110.

[0084] Connection vias 156a and 156b can be formed on the gate 154G and the impurity region 152 of the transfer transistor, and connection vias 156a and 156b can be electrically connected to their corresponding conductive vias 166c and 166d.

[0085] In the following text, reference will be made to Figure 10 Briefly describe the sensor driving method.

[0086] Figure 10 This is a circuit diagram of the sensor SU according to an example embodiment.

[0087] Reference Figure 10 The sensor SU includes: a photoelectric conversion region PD for receiving light, generating charge through photoelectric conversion, and storing the generated charge; a transfer transistor Tx for transferring the charge generated in the photoelectric conversion region PD to a floating diffusion region FD; a reset transistor Rx for periodically resetting the charge stored in the floating diffusion region FD; a drive transistor Dx that acts as a source follower buffer amplifier and is used to buffer a signal based on the charge being charged in the floating diffusion region FD; and a selection transistor Sx that performs the function of selecting a pixel PX (see [link to sensor]). Figure 2 ( ) has switching and addressing functions.

[0088] The photoelectric conversion region PD can be a photodiode including both N-type and P-type impurity regions. The floating diffusion region FD can be the source of the reset transistor Rx, and the floating diffusion region FD can be connected to the gate of the drive transistor Dx. (Refer to...) Figure 10 The reset signal RS is applied to the gate of the reset transistor Rx, the transfer signal TG is applied to the gate of the transfer transistor Tx, and the select signal SEL is applied to the gate of the select transistor Sx. The reset transistor Rx, the drive transistor Dx, and the select transistor Sx can be shared by adjacent pixels.

[0089] When light is blocked, and a power supply voltage is applied to the drain of the reset transistor Rx and the drain of the drive transistor Dx, and the reset transistor Rx is turned on, the charge remaining in the floating diffusion region FD can be discharged. Then, when the reset transistor Rx is turned off, and light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD by the incident light. Holes can move to the P-type impurity region and accumulate there, and electrons can move to the N-type impurity region and accumulate there. By turning on the transfer transistor Tx, electrons can transfer to and / or accumulate in the floating diffusion region FD. The gate bias voltage of the drive transistor Dx can be changed according to the amount of accumulated charge, and therefore, the source potential of the drive transistor Dx can be changed. In this case, the selection transistor Sx can be turned on to output the signal OUT caused by the charge.

[0090] Return to reference Figure 7 and Figure 9 The first to third sensors (SU1, SU2, and SU3) can be arranged at positions overlapping with the plurality of second openings 110H2, and the photoconductive insulating layer 158 can be arranged in the plurality of second openings 110H2. The photoconductive insulating layer 158 may have an upper surface that is coplanar with the second surface 110F2 of the wavelength conversion layer (181, 182, and 183) and the substrate 110.

[0091] The plurality of second openings 110H2 and the light-guiding insulating layer 158 filling the plurality of second openings 110H2 can be collectively referred to as the light-guiding portion 158G. The light-guiding portion 158G provides an optical path so that light incident into the plurality of second openings 110H2 can reach the photoelectric conversion region PD without loss of light quantity. The light-guiding portion 158G can be disposed in the substrate 110 through the plurality of second openings 110H2, so that although a separate or additional lens for converging light is not formed on the substrate 110, a sufficient amount of light can be transmitted to the first to third sensors (SU1, SU2 and SU3) for fingerprint identification.

[0092] Recently, optical fingerprint sensing methods have been developed to reduce the weight of portable electronic devices such as smartphones or wearable devices, thereby increasing the display area. In optical fingerprint sensing methods, a fingerprint sensor substrate with an image sensor formed therein, along with an intermediate substrate with a light guide path formed therein, is attached to the bottom surface of a display panel such as an organic light-emitting device (OLED) panel. In this case, the fingerprint sensor substrate and the intermediate substrate are relatively thick, thus increasing the thickness of the display device.

[0093] However, in the light-emitting device package 100 according to the above example embodiment, since the first to third sensors (SU1, SU2, and SU3) are formed in the first to third sub-pixels (SPX1, SPX2, and SPX3), the same number of sensors (i.e., the first to third sensors (SU1, SU2, and SU3)) as the number of light-emitting structures (i.e., the first to third light-emitting structures (LS1, LS2, and LS3)) can be formed, and a high-resolution fingerprint recognition sensor can be realized. Furthermore, since the first to third light-emitting structures (LS1, LS2, and LS3) and the first to third sensors (SU1, SU2, and SU3) are arranged horizontally in the pixel, the first to third sensors (SU1, SU2, and SU3) can be formed in a relatively large area within the pixel, thus improving fingerprint recognition performance.

[0094] In addition, the first to third sensors (SU1, SU2 and SU3) can be arranged in the substrate 110, which serves as a support substrate, and the wall structure of the first to third light-emitting structures (LS1, LS2 and LS3) and the light-guiding portion 158G for the first to third sensors (SU1, SU2 and SU3) can be provided by the second opening 110H2 formed in the substrate 110, so the thickness of the display panel can be reduced.

[0095] Figure 11 and Figure 12 This is a cross-sectional view of the light-emitting device package 100A according to an example embodiment. Figure 11 and Figure 12 The corresponding figures are shown respectively. Figure 6 The enlarged section of part BX2 and the corresponding cross section Figure 7 A cross-section of a magnified view of part of CX2. Figure 11 and Figure 12 In, with Figures 1 to 10 The same label in the code indicates the same component.

[0096] Reference Figure 11 and Figure 12A recessed region 114R can be formed in the first surface 110F1 of the substrate 110 surrounding the light-emitting stack 122. The recessed region 114R can be located in the edge portion of the substrate 110 corresponding to the switch SW1 and the sensor SU1. The recessed region 114R can be formed in the process of etching the light-emitting stack 122 by over-etching a portion of the upper surface of the epitaxial semiconductor layer 114, which serves as the growth substrate.

[0097] Although Figure 11 and Figure 12 An example is shown in which the insulating layer 124 is conformally arranged in the recessed region 114R, but the insulating layer 124 may be formed only on the sidewall of the recessed region 114R.

[0098] Figure 13 This is a cross-sectional view of the light-emitting device package 100B according to an example embodiment. Figure 13 It shows the corresponding Figure 7 A cross-section of a magnified view of part of CX2. Figure 13 In, with Figures 1 to 12 The same label in the text refers to the same component.

[0099] Reference Figure 13 The sensor SU1 may have a planar transfer transistor gate 154GB. The transfer transistor gate 154GB may be disposed on a gate insulating layer 154IB formed on a first surface 110F1 of the substrate 110, gate spacers 154GS may be disposed on two sidewalls of the transfer transistor gate 154GB, and a capping layer 154GM may be disposed on the upper surface of the transfer transistor gate 154GB.

[0100] In this example, the gate insulating layer 154IB may be formed using the same process as insulating layer 124, or may comprise the same material as insulating layer 124. Alternatively, the gate insulating layer 154IB may be formed by depositing an insulating material on a first surface 110F1 of a substrate 110 where insulating layer 124 has been removed.

[0101] Figure 14 This is a cross-sectional view of the light-emitting device package 100C according to an example embodiment. Figure 14 It shows the correspondence along Figure 4 The cross section intercepted by line C1-C1'. Figure 14 In, with Figures 1 to 13 The same label in the text refers to the same component.

[0102] Reference Figure 14 The reflective layer 187 can be disposed on the inner wall of the plurality of first openings 110H1. The reflective layer 187 can reflect light emitted from the light-emitting stack 122, thereby improving light extraction efficiency.

[0103] In an example embodiment, reflective layer 187 may be a metal layer comprising Ag, Al, Ni, Cr, Au, Pt, Pd, Sn, W, Rh, Ir, Ru, Mg, Zn, or combinations thereof. In other embodiments, reflective layer 187 may be a resin layer such as polyphthalamide (PPA) containing a metal oxide (such as titanium oxide or aluminum oxide). In other embodiments, reflective layer 187 may be a distributed Bragg reflector layer. For example, a distributed Bragg reflector layer may have a structure in which multiple insulating films with different refractive indices are repeatedly stacked several to hundreds of times. Each of the insulating films in the distributed Bragg reflector layer may include an oxide or nitride, such as SiO2, SiN, SiO2, etc. x N y TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN or TiSiN or combinations thereof.

[0104] Optionally, the light guide portion 158GC may include a reflective layer 159 located on the inner wall of the plurality of second openings 110H2. The reflective layer 159 may include a material similar to that of the reflective layer 187.

[0105] Figure 15 This is a cross-sectional view of the light-emitting device package 100D according to an example embodiment. Figure 15 It shows the corresponding Figure 7 A cross-section of a magnified view of part of CX2. Figure 15 In, with Figures 1 to 14 Labels with the same number in the code refer to the same component.

[0106] Reference Figure 15 The sensor SU1 may also include a device isolation structure (DTI). The device isolation structure DTI may fill the interior of a recess (not shown) extending from a first surface 110F1 of the substrate 110 into the interior of the substrate 110 of the sensor SU1. In an example embodiment, the device isolation structure DTI may include an insulating layer filling the interior of the recess. In other embodiments, the device isolation structure DTI may include a conductive layer filling the interior of the recess, and a bias voltage may be applied to the conductive layer.

[0107] Figure 16 and Figure 17 This is a cross-sectional view of the light-emitting device package 100E according to an example embodiment. Figure 16 and Figure 17 The diagrams corresponding to the directions along the lines are shown respectively. Figure 4 The cross section intercepted by line B1-B1' and the cross section corresponding to the section along B1-B1' Figure 4 The cross section intercepted by line C1-C1'. Figure 16 and Figure 17 In, with Figures 1 to 15 The same label in the text refers to the same component.

[0108] Reference Figure 16 and Figure 17 Substrate 110 may consist only of semiconductor substrate 112, and reference may be omitted. Figures 4 to 9 The epitaxial semiconductor layer 114 is described. For example, the semiconductor substrate 112 can be used as a growth substrate for growing the light-emitting stack 122, the active region AC for the switches (SW1, SW2 and SW3) can be formed in a portion of the semiconductor substrate 112, and the device region (not shown) for the sensors (SU1, SU2 and SU3) can be formed in a portion of the semiconductor substrate 112.

[0109] Figures 18A to 24C This is a cross-sectional view showing a method for manufacturing a light-emitting device package 100 according to an exemplary embodiment, based on the processing sequence. Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It corresponds to along Figure 4 A cross-sectional view of the section intercepted by line A1-A1'. Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B It corresponds to along Figure 4 A cross-sectional view of the section intercepted by line B1-B1', and Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C and Figure 24C It corresponds to along Figure 4 A cross-sectional view of the section cut by line C1-C1'.

[0110] Reference Figures 18A to 18C An epitaxial growth process can be performed on the semiconductor substrate 112 to form an epitaxial semiconductor layer 114.

[0111] In an example embodiment, the semiconductor substrate 112 may be a silicon (Si) substrate, and may be a substrate heavily doped with a first impurity and having a silicon {111} crystal plane. However, the inventive concept is not limited thereto, and the semiconductor substrate 112 may include a silicon-germanium (SiGe) substrate, a germanium (Ge) substrate, or a silicon carbide (SiC) substrate.

[0112] In an example embodiment, a second impurity may be doped in situ into the epitaxial semiconductor layer 114 during the epitaxial growth process. In other embodiments, the second impurity may be implanted into the epitaxial semiconductor layer 114 after its formation.

[0113] In the following text, the semiconductor substrate 112 and the epitaxial semiconductor layer 114 are collectively referred to as substrate 110. The surface of the epitaxial semiconductor layer 114 is exposed on the first surface 110F1 of the substrate 110.

[0114] Next, the light-emitting stack 122 can be formed on the first surface 110F1 of the substrate 110.

[0115] The light-emitting stack 122 may include a first conductivity type semiconductor layer 122a, an active layer 122b, and a second conductivity type semiconductor layer 122c formed sequentially on a first surface 110F1 of the substrate 110.

[0116] Reference Figures 19A to 19C A mask pattern (not shown) may be formed on the light-emitting stack 122, and the mask pattern may be used as an etching mask to remove a portion of the light-emitting stack 122 to form a mesa etch portion 122E. The mesa etch portion 122E may expose the upper surface of the semiconductor layer 122a of the first conductivity type.

[0117] Although not shown, ohmic electrodes (not shown) can be formed on the upper surface of the first conductivity type semiconductor layer 122a and / or the upper surface of the second conductivity type semiconductor layer 122c exposed by the mesa etching portion 122E using a conductive ohmic material.

[0118] Then, an isolation process can be performed to separate the light-emitting stack 122 into multiple light-emitting regions. For example, a portion of the light-emitting stack 122 can be removed by an etching process or a cutting process until the first surface 110F1 of the substrate 110 is exposed to form an isolation region 122IS. Thus, the light-emitting stack 122 can be separated into multiple light-emitting regions spaced apart from each other by the isolation region 122IS.

[0119] In the isolation process, a portion of the substrate 110 surrounding the light-emitting stack 122 can be over-etched, and a recessed region 114R can be formed in the substrate 110 surrounding the light-emitting stack 122. In this case, a reference can be formed. Figure 11 and Figure 12 The light-emitting device package 100A is described.

[0120] Next, an insulating layer 124 may be formed to cover the light-emitting stack 122 and the first surface 110F1 of the substrate 110 exposed through the isolation region 122IS.

[0121] Reference Figures 20A to 20C The active region AC of the switch SW can be formed in a portion of the substrate 110 exposed through the isolation region 122IS by performing an ion implantation process on the first surface 110F1 of the substrate 110.

[0122] In an example embodiment, to form the active region AC, a first mask pattern (not shown) can be formed on the insulating layer 124, and the first mask pattern can be used as an ion implantation mask to implant impurity ions into the substrate 110 through the isolation region 122IS to form a p-well 142. The first mask pattern can then be removed. Next, a second mask pattern (not shown) can be formed on the insulating layer 124, and the source region 143a and drain region 143b can be formed in the substrate 110 through the isolation region 122IS by using the second mask pattern as an ion implantation mask. The second mask pattern can then be removed.

[0123] The device region of the sensor SU can be formed in another portion of the substrate 110 exposed through the isolation region 122IS by performing an ion implantation process on the first surface 110F1 of the substrate 110.

[0124] In an exemplary embodiment, to form the device region, a third mask pattern (not shown) may be formed on the insulating layer 124, and impurity ions may be implanted into the substrate 110 in the isolation region 122IS using the third mask pattern as an ion implantation mask to form a photoelectric conversion region PD and a well region PW. For example, the photoelectric conversion region PD may be doped with n-type impurities, and the well region PW may be doped with p-type impurities. At least one of the photoelectric conversion region PD and the well region PW may have a structure comprising multiple impurity regions doped with impurities of different concentrations.

[0125] The photoelectric conversion region PD and the well region PW can be formed within the epitaxial semiconductor layer 114. Since the epitaxial semiconductor layer 114 has a p-type impurity concentration that is lower than that of the semiconductor substrate 112, the epitaxial semiconductor layer 114 is more suitable for forming the device regions of the photoelectric conversion region PD and the well region PW.

[0126] A fourth mask pattern (not shown) may be formed on the first surface 110F1 of the substrate 110, and the substrate 100 may be etched using the fourth mask pattern as an etch mask to form a device isolation trench (not shown). Then, a device isolation layer STI may be formed on the first surface 110F1 of the substrate 110 to fill the device isolation trench with an insulating material.

[0127] The transfer transistor gate 154G can be formed on the first surface 110F1 of the substrate 110, and the floating diffusion region FD and the impurity region 152 can be formed by ion implantation process.

[0128] Then, a portion of the insulating layer 124 on the light-emitting stack 122 can be removed, and the first electrode 127 and the second electrode 128 can be formed on the first conductivity type semiconductor layer 122a and the second conductivity type semiconductor layer 122c, respectively, using conductive materials. A portion of the insulating layer 124 on the active region AC can be removed, and the source electrode 144S and the drain electrode 144D can be formed on the source and drain regions 143a and 143b, respectively, using conductive materials. In the example embodiment, the first electrode 127, the second electrode 128, the source electrode 144S, and the drain electrode 144D can be formed using the same process and / or the same materials. A connection electrode 132 for electrically connecting the first electrode 127 to the source electrode 144S can be formed.

[0129] Then, a gate insulating layer 144I and a gate electrode 144G can be formed on the active region AC. In an example embodiment, the gate insulating layer 144I may be a portion of the insulating layer 124 remaining on the active region AC. Alternatively, the gate insulating layer 144I may be formed on the active region AC using an insulating material after the insulating layer 124 has been removed.

[0130] While this document describes an example process for forming a portion of a switch SW and a portion of a sensor SU in and / or on substrate 110, the inventive concept is not limited to the manufacturing method described above. It is known that the processing order, manufacturing method, or shape of the switch SW and sensor SU may be varied.

[0131] Reference Figures 21A to 21C Insulating material can be deposited on the light-emitting stack 122 and the insulating layer 124 while filling the isolation region 122IS, and the upper part of the insulating material can be planarized to form a molded component 134. The molded component 134 can cover the switch SW and sensor SU in the isolation region 122IS.

[0132] Then, a connecting via 136 can be formed through the molded component 134.

[0133] In this case, the connection vias 146a and 146b electrically connected to the gate electrode 144G and the drain electrode 144D can be formed in the switch SW, and the connection vias 156a and 156b connected to the gate of the transfer transistor 154G and the impurity region 152 can be formed in the sensor SU.

[0134] Then, a multilayer insulating structure 162 can be fabricated. The multilayer insulating structure 162 can be formed separately in the same manner as a printed circuit board and attached to the molding member 134. Alternatively, the multilayer insulating structure 162 can be formed by sequentially forming an insulating layer and a metal layer on the molding member 134.

[0135] Reference Figures 22A to 22CThe light-emitting stack 122 attached to the substrate 110 can be inverted so that the second surface 110F2, which is opposite to the first surface 110F1 of the substrate 110, faces upward. The horizontal height of the second surface 110F2 of the substrate 110 can then be reduced by removing the upper portion of the substrate 110 from the second surface 110F2 using a polishing process. In this case, a support substrate (not shown) can be attached to the second surface 110F2 of the substrate 110.

[0136] Then, a mask pattern (not shown) can be formed on the second surface 110F2 of the substrate 110, and the mask pattern can be used as an etching mask to form a second opening 110H2 in the substrate 110. The second opening 110H2 can be formed at a location overlapping with the sensor SU. The second opening 110H2 can pass through the semiconductor substrate 112 and extend into the interior of the epitaxial semiconductor layer 114, so that the upper surface of the epitaxial semiconductor layer 114 can be exposed through the bottom of the second opening 110H2.

[0137] Reference Figures 23A to 23C A light-conducting insulating layer 158 can be formed to fill the interior of the second opening 110H2. The light-conducting insulating layer 158 can be formed using an insulating material.

[0138] Then, a mask pattern (not shown) can be formed on the second surface 110F2 of the substrate 110, and the mask pattern can be used as an etching mask to form a first opening 110H1 in the substrate 110. The first opening 110H1 can be formed at a position overlapping with the light-emitting stack 122. The first opening 110H1 can pass through both the semiconductor substrate 112 and the epitaxial semiconductor layer 114, and the upper surface of the light-emitting stack 122 can be exposed through the first opening 110H1.

[0139] In reference Figures 23A to 23C In the described process, the semiconductor layer 122 of the first conductivity type exposed at the bottom of the first opening 110H1 can be etched to form a bumpy structure (not shown). In this case, the light extraction efficiency of the light-emitting device package 100 can be further improved.

[0140] Additionally, before forming the photoconductive insulating layer 158, a conductive layer (not shown) may be formed on the second surface 110F2 of the substrate 110 and the inner wall of the second opening 110H2, and an anisotropic etching process may be performed on the conductive layer to form a reflective layer 159 on the sidewall of the second opening 110H2. Then, a conductive layer (not shown) may be formed on the second surface 110F2 of the substrate 110 and the inner wall of the first opening 110H1, and an anisotropic etching process may be performed on the conductive layer to form a reflective layer 187 on the sidewall of the first opening 110H1. In this case, a reference layer may be formed. Figure 14The light-emitting device package 100C is described.

[0141] Reference Figures 24A to 24C This can form a wavelength conversion layer (181, 182 and 183) that fills the interior of the first opening 110H1.

[0142] In an example embodiment, wavelength conversion layers (181, 182, and 183) can be formed by applying or dispersing a resin in which phosphor particles are dispersed into a first opening 110H1. The wavelength conversion layers (181, 182, and 183) may include two or more types of phosphor particles with different particle size distributions, such that the phosphor particles are uniformly distributed in the first opening 110H1.

[0143] Then, return to the reference. Figures 5 to 7 Encapsulation layer 186 may be formed on the second surface 110F2 of substrate 110, wavelength conversion layers (181, 182 and 183) and photoconductive insulating layer 158.

[0144] In an example embodiment, after the encapsulation layer 186 is formed, the substrate 110 can be individually diced into individual light-emitting device packages 100. Each light-emitting device package 100 can be individually diced into a unit comprising a pixel including a first to a third light-emitting structure (LS1, LS2, and LS3). Alternatively, the light-emitting device package 100 can be diced into various sizes to include multiple pixels arranged in a matrix.

[0145] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A light-emitting device package, comprising: A substrate having a first surface, a second surface, a first opening extending through the substrate from the first surface to the second surface, and a second opening extending from the second surface into the interior of the substrate and spaced apart from the first opening; A light-emitting structure is arranged on the first surface of the substrate and vertically overlaps with the first opening; as well as An image sensor includes a photoelectric conversion region disposed in a substrate and vertically overlapping a second opening. Light from the light-emitting structure is emitted toward the second surface of the substrate through the first opening.

2. The light-emitting device package according to claim 1, wherein, The image sensor is configured to sense light reflected from an object on the substrate based on light emitted from the light-emitting structure.

3. The light-emitting device package according to claim 1, wherein, The substrate includes a light-guiding portion defined by the inner wall of the second opening, and The light guide portion provides a light path through which light incident on the second opening reaches the photoelectric conversion area.

4. The light-emitting device package according to claim 1, further comprising: A wavelength conversion layer that fills the first opening; as well as A photoconductive insulating layer that fills the second opening, and the upper surface of the photoconductive insulating layer is coplanar with the upper surface of the wavelength conversion layer.

5. The light-emitting device package according to claim 1, wherein, The substrate includes a semiconductor substrate and an epitaxial semiconductor layer disposed on the upper surface of the semiconductor substrate, and The light-emitting structure is disposed on the upper surface of the epitaxial semiconductor layer, and the photoelectric conversion region is disposed inside the epitaxial semiconductor layer.

6. The light-emitting device package according to claim 5, wherein, The first opening passes through both the semiconductor substrate and the epitaxial semiconductor layer, and The second opening passes through the semiconductor substrate and extends into the epitaxial semiconductor layer, and the photoelectric conversion region is disposed below the bottom of the second opening.

7. The light-emitting device package according to claim 5, wherein, The semiconductor substrate includes a silicon substrate, the epitaxial semiconductor layer includes silicon, and the light-emitting structure includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer arranged sequentially on the epitaxial semiconductor layer.

8. The light-emitting device package according to claim 1, further comprising: A switch disposed in the substrate and electrically connected to the light-emitting structure is configured to drive the light-emitting structure.

9. A display device comprising a display area and a fingerprint sensing area overlapping at least a portion of the display area. in, The fingerprint sensing area includes the light-emitting device package according to claim 1, and The image sensor is configured to sense light reflected from an object on a substrate based on light emitted from the light-emitting structure.

10. The display device according to claim 9, wherein, The fingerprint sensing area includes multiple pixels. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and The first light-emitting structure in the first sub-pixel, the second light-emitting structure in the second sub-pixel, and the third light-emitting structure in the third sub-pixel are spaced apart from each other, and at least one of the first sub-pixel to the third sub-pixel includes the image sensor.

11. The display device according to claim 10, wherein, The first sub-pixel to the third sub-pixel respectively include a first image sensor, a second image sensor, and a third image sensor, and The first image sensor and the first light-emitting structure are arranged horizontally in the first sub-pixel.

12. A display device comprising a plurality of pixels, wherein, At least one of the plurality of pixels includes the light-emitting device package according to claim 1, and The image sensor is configured to sense light reflected from an object on the substrate based on light emitted from the light-emitting structure.

13. The display device according to claim 12, wherein, The object includes the user's finger, and The image sensor is also configured to sense reflected light and output an image signal of the fingerprint.

14. The display device according to claim 12, further comprising: A switch disposed in the substrate and electrically connected to the light-emitting structure, the switch being configured to drive the light-emitting structure.

15. A method for manufacturing a light-emitting device package, comprising: Multiple light-emitting structures are formed on the first surface of the first region of the substrate; A photoelectric conversion region is formed in the second region of the substrate; A first region of the substrate is removed from a second surface opposite to a first surface of the substrate to form a plurality of first openings extending through the substrate from the first surface to the second surface, thereby exposing the plurality of light-emitting structures; as well as A second region of the substrate is removed from the second surface of the substrate to form a plurality of second openings that expose the photoelectric conversion region.

16. The method according to claim 15, wherein, The plurality of first openings pass through the substrate, and the plurality of second openings extend into the interior of the substrate.

17. The method according to claim 15, wherein, The substrate includes a semiconductor substrate and an epitaxial semiconductor layer formed on the semiconductor substrate by an epitaxial growth process, and The step of forming the photoelectric conversion region includes forming the photoelectric conversion region by implanting impurities into the epitaxial semiconductor layer.

18. The method of claim 15, further comprising: A wavelength conversion layer is formed to fill the plurality of first openings; as well as A light-conducting insulating layer is formed to fill the plurality of second openings.

19. The method of claim 15, further comprising: The active region of the switch is formed in the third region of the substrate.

20. A display device comprising a plurality of pixels, each of the plurality of pixels comprising a plurality of sub-pixels, in, The plurality of sub-pixels include and share a light-emitting structure configured to generate and emit light. The light-emitting structure is formed on a first surface of the substrate and includes the same number of regions as the plurality of sub-pixels. In this embodiment, at least one image sensor is disposed on a second surface of the substrate opposite to the first surface, the light-emitting structure is divided in the substrate to form various regions of the light-emitting structure, and the at least one image sensor is configured to sense light reflected through an object on the encapsulation layer based on light emitted from the light-emitting structure. The second surface is located between the encapsulation layer and the first surface. Multiple openings are formed through the substrate, and One of the first openings of the plurality of openings extends through the substrate from the first surface to the second surface and exposes one of the plurality of sub-pixels.

21. The display device according to claim 20, wherein, The number of the at least one sensor is the same as the number of regions of the light-emitting structure.

22. The display device according to claim 20, wherein, On the second surface of the substrate where the light-emitting structure is divided to form various regions of the light-emitting structure, at least one switch is respectively disposed on one side of the at least one image sensor, and The at least one switch is configured to drive the light-emitting structure.

23. The display device according to claim 20, wherein, The second of the plurality of openings is filled with a light-guiding insulating layer, and light emitted from the light-emitting structure and incident into the second opening is guided through the light-guiding insulating layer to the second surface of the substrate.

24. The display device according to claim 23, wherein, The at least one image sensor includes a photoelectric conversion region that vertically overlaps with the second opening.

Images