A driving circuit for a controlled NMOS tube

Abstract

The present invention relates to the field of driving circuits. The present invention discloses a driving circuit of a controlled NMOS tube, comprising a pull-up tube M3, a pull-down tube M0, a pull-down resistor and a control logic circuit, and also comprising a first switch circuit, wherein the output end SRG of the driving circuit is connected to a power supply VIN through the pull-up tube M3, and is grounded through the pull-down tube M0 and the pull-down resistor in parallel, the control ends of the pull-up tube M3 and the pull-down tube M0 are connected to the control output end of the control logic circuit, the first switch circuit is connected between the output end SRG of the driving circuit and the control end of the pull-down tube M0, and the first switch circuit is configured to turn on the first switch circuit when the voltage of the power supply VIN is less than the working voltage of the driving circuit and the voltage of the output end SRG of the driving circuit is greater than the turn-on voltage of the first switch circuit; and the first switch circuit is turned off when the voltage of the power supply VIN is greater than or equal to the working voltage of the driving circuit. The present invention can avoid the controlled NMOS tube from being mis-turned on when the power supply voltage of the driving circuit is very low, thereby improving safety and reliability.

Description

Technical Field

[0001] The invention belongs to the field of driving circuits, and in particular relates to a driving circuit for a controlled NMOS tube. Background Art

[0002] The flyback converter is a commonly used AC to DC converter. Its typical circuit structure is as follows: Figure 1 As shown, it includes a primary control circuit and a secondary synchronous rectification circuit, and the synchronous rectification circuit includes a synchronous rectifier tube SR and a synchronous rectification controller for driving the synchronous rectifier tube SR. The traditional synchronous rectification controller mainly includes an internal linear regulator and the required external voltage stabilization capacitor C0, a pull-up PMOS tube M3, a pull-down NMOS tube M0 and a passive pull-down resistor R0, as shown in FIG. Figure 2 shown.

[0003] This traditional synchronous rectification controller circuit design has two disadvantages:

[0004] The first disadvantage is that during the start-up phase of the flyback converter, the power supply VIN of the synchronous rectifier controller is very low, so the entire synchronous rectifier controller cannot work properly, and the output terminal SRG of the synchronous rectifier controller is only pulled down to the ground by the internal pull-down resistor R0. Since the flyback converter is working, SEC is a violent switching signal, so the voltage of the output terminal SRG is raised through the parasitic capacitance coupling of the synchronous rectifier tube SR (NMOS tube). Although there is an internal pull-down resistor R0 to pull down the voltage of the output terminal SRG during the startup process, the resistance value of the pull-down resistor R0 will not be too low in actual design considering the influence of power consumption and area. Therefore, during the start-up phase of the flyback converter, the pull-down ability of the pull-down resistor R0 is insufficient, and the coupling voltage will still exceed the turn-on voltage of the synchronous rectifier tube SR, thereby causing the primary switch and the secondary synchronous rectifier tube SR to be turned on at the same time, causing the transformer inductance to be saturated, thereby burning the transformer and the primary and secondary switch tubes.

[0005] The second disadvantage is: since the VGS voltage of the external synchronous rectifier SR is about 0 to 12V when it is normally turned on, and the output voltage of the flyback converter will be greater than 12V, in order to ensure that the voltage of the switch does not exceed the withstand voltage of the synchronous rectifier SR, a linear regulator needs to be integrated internally to limit the maximum voltage output by the output terminal SRG. The linear regulator not only occupies a large circuit area, but also requires an external voltage-stabilizing capacitor C0 to work properly. Therefore, it is necessary to add a chip pin and an external capacitor C0, which results in a large circuit area and high cost. Summary of the invention

[0006] One of the purposes of the present invention is to provide a driving circuit of a controlled NMOS tube to solve the first disadvantage mentioned above.

[0007] A second object of the present invention is to provide a controlled NMOS transistor driving circuit to solve the second disadvantage mentioned above.

[0008] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a driving circuit of a controlled NMOS tube, comprising a pull-up tube M3, a pull-down tube M0 and a control logic circuit, and also comprising a first switch circuit, wherein an output terminal SRG of the driving circuit is connected to a power supply VIN through the pull-up tube M3, and is grounded through the pull-down tube M0, and control terminals of the pull-up tube M3 and the pull-down tube M0 are connected to a control output terminal of the control logic circuit, and the first switch circuit is connected between the output terminal SRG of the driving circuit and the control terminal of the pull-down tube M0, and the first switch circuit is configured such that when the voltage of the power supply VIN is less than the working voltage of the driving circuit and the voltage of the output terminal SRG of the driving circuit is greater than the turn-on voltage of the first switch circuit, the first switch circuit is turned on; when the voltage of the power supply VIN is greater than or equal to the working voltage of the driving circuit, the first switch circuit is turned off.

[0009] Further, the first switch circuit includes a PMOS tube M5, a PMOS tube M6, a diode D0 and a resistor R1, the drain of the PMOS tube M5 is connected to the output end SRG of the drive circuit, the source of the PMOS tube M5 is connected to the source of the PMOS tube M6, the drain of the PMOS tube M6 is connected to the control end of the pull-down tube M0, the resistor R1 is connected in parallel with the PMOS tube M5, the positive end of the diode D0 is connected to the gate of the PMOS tube M5, the negative end of the diode D0 is connected to the source of the PMOS tube M5, the gates of the PMOS tube M5 and the PMOS tube M6 are connected to a first control voltage, and the first control voltage is configured such that when the voltage of the power supply VIN is less than the working voltage of the drive circuit, the first control voltage is zero; when the voltage of the power supply VIN is greater than or equal to the working voltage of the drive circuit, the first control voltage VPRE is greater than or equal to the voltage of the output end SRG.

[0010] Furthermore, it also includes a second switch circuit, which is connected between the control end of the pull-down tube M0 and the control output end of the control logic circuit. The second switch circuit is configured to be turned off when the voltage of the power supply VIN is less than the operating voltage of the drive circuit; and turned on when the voltage of the power supply VIN is greater than or equal to the operating voltage of the drive circuit.

[0011] Furthermore, the second switch circuit is implemented by an NMOS tube M4, the drain of the NMOS tube M4 is connected to the control output end of the control logic circuit, the source of the NMOS tube M4 is connected to the control end of the pull-down tube M0, and the gate of the NMOS tube M4 is connected to the first logic level SREN. The first logic level SREN is configured such that when the voltage of the power supply VIN is less than the operating voltage of the drive circuit, the first logic level SREN is 0; when the voltage of the power supply VIN is greater than or equal to the operating voltage of the drive circuit, the first logic level SREN is 1.

[0012] Furthermore, it also includes an N-type transistor M8 and a third switch circuit, wherein the N-type transistor M8 is connected in parallel with the pull-up tube M3, the control electrode of the pull-up tube M3 is connected to the first control output terminal of the control logic circuit through a first level conversion circuit, the power input terminal of the first level conversion circuit is connected to the power supply VIN, the control electrode of the N-type transistor M8 is connected to the first control output terminal of the control logic circuit through a second level conversion circuit, the power input terminal of the second level conversion circuit is connected to the voltage VPRE, and the voltage VPRE is configured such that when the voltage of the power supply VIN is greater than or equal to the withstand voltage of the controlled NMOS tube, the voltage VPRE is equal to the withstand voltage of the controlled NMOS tube, and the third switch circuit is configured such that when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube, the pull-up tube M3 is controlled to be turned off.

[0013] Furthermore, the N-type transistor M8 is an NMOS transistor.

[0014] Furthermore, it also includes a voltage stabilizing circuit, the input end of the voltage stabilizing circuit is connected to the power supply VIN, the output end of the voltage stabilizing circuit outputs a voltage VPRE, and the voltage stabilization value of the voltage stabilizing circuit is the withstand voltage of the controlled NMOS tube.

[0015] Furthermore, the voltage stabilizing circuit includes a PMOS tube M10, a PMOS tube M11, an NMOS tube M9, a voltage stabilizing tube zener1, a voltage stabilizing tube zener2, a voltage stabilizing tube zener3, a resistor R2 and a resistor R3, the source of the PMOS tube M11 is connected to the power supply VIN, the drain of the PMOS tube M11 is connected in series with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 in sequence and grounded, the resistor R3 is connected in series with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 in sequence and grounded, The transistor zener2 and the voltage stabilizing transistor zener3 are connected in parallel, the source of the PMOS transistor M10 is connected to the power supply VIN, the drain of the PMOS transistor M10 is respectively connected to the gate of the PMOS transistor M11, the gate of the PMOS transistor M10 and the drain of the NMOS transistor M9, the source of the NMOS transistor M9 is connected in series with a resistor R2 connected to ground, the gate of the NMOS transistor M9 is connected to a first logic level SREN, and the node between the PMOS transistor M11 and the voltage stabilizing transistor zener1 serves as the output end of the voltage stabilizing circuit.

[0016] Further, the third switch circuit includes a PMOS tube M7, a source of the PMOS tube M7 is connected to the power supply VIN, a drain of the PMOS tube M7 is connected to the control electrode of the pull-up tube M3, and a gate of the PMOS tube M7 is connected to a second control voltage VIN_OV. The second control voltage VIN_OV is configured such that when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube, the second control voltage VIN_OV turns on the PMOS tube M7; when the voltage of the power supply VIN is less than or equal to the withstand voltage of the controlled NMOS tube, the second control voltage VIN_OV turns off the PMOS tube M7.

[0017] Furthermore, a pull-down resistor R0 is included, and the pull-down resistor R0 is connected in parallel with the pull-down tube M0.

[0018] Beneficial technical effects of the present invention:

[0019] The present invention can prevent the controlled NMOS tube from being mis-conducted when the power supply voltage of the driving circuit is very low, thereby improving safety and reliability.

[0020] The present invention can prevent the output voltage of the driving circuit from exceeding the withstand voltage of the controlled NMOS tube, causing the controlled NMOS tube to burn out, and there is no need to use a linear regulator, so there is no need to add a chip pin and an external capacitor C0, so that the circuit area occupied is greatly reduced and the chip driving cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 Schematic diagram of a typical circuit structure of a flyback converter;

[0023] Figure 2 is a circuit diagram of a traditional synchronous rectification controller;

[0024] Figure 3 is a circuit diagram of Embodiment 1 of the present invention;

[0025] Figure 4 is a circuit diagram of a voltage stabilizing circuit according to a first embodiment of the present invention;

[0026] Figure 5 This is a circuit diagram of Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0027] To further illustrate the various embodiments, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, a person of ordinary skill in the art should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0028] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0029] Embodiment 1

[0030] like Figure 3 As shown, a driving circuit of a controlled NMOS tube includes a pull-up tube M3, a pull-down tube M0, a pull-down resistor R0, a control logic circuit 1 and a first switch circuit. The output terminal SRG of the driving circuit is used to be connected to the gate of the controlled NMOS tube SR to drive the controlled NMOS tube SR. In this specific embodiment, the controlled NMOS tube SR is a synchronous rectifier tube of a flyback converter, but is not limited to this.

[0031] The output terminal SRG of the driving circuit is connected to the power supply VIN through the pull-up tube M3, and is grounded through the parallel pull-down tube M0 and the pull-down resistor R0. The control terminal of the pull-up tube M3 is connected to the first control output terminal of the control logic circuit 1 through the first level conversion circuit 2. The power input terminal of the first level conversion circuit 2 is connected to the power supply VIN, and the control terminal of the pull-down tube M0 is connected to the second control output terminal of the control logic circuit 1. This part of the circuit is the same as the circuit of the traditional synchronous rectification controller. The specific structure and driving principle can refer to the existing technology, which will not be described in detail.

[0032] In this specific embodiment, the pull-up tube M3 is preferably a PMOS tube, and the pull-down tube M0 is preferably an NMOS tube, but it is not limited thereto. In other embodiments, the pull-up tube M3 can also be implemented by other P-type transistors, and the pull-down tube M0 can also be implemented by other N-type transistors.

[0033] The first switch circuit is connected between the output terminal SRG of the drive circuit and the gate (control terminal) of the NMOS tube M0. The first switch circuit is configured to be turned on when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit (that is, the control logic circuit 1 cannot work normally at this time), and the voltage of the output terminal SRG of the drive circuit is greater than the turn-on voltage of the first switch circuit; thereby transmitting the voltage of the output terminal SRG to the gate of the NMOS tube M0 to turn on the NMOS tube M0. Once the NMOS tube M0 is turned on, since the on-resistance of the NMOS tube M0 is very small, the voltage of the output terminal SRG will be quickly lowered, thereby limiting the voltage of the output terminal SRG to not turn on the external controlled NMOS tube SR before reaching the operating voltage UVLO, thereby avoiding mis-conduction of the controlled NMOS tube SR and improving safety and reliability.

[0034] When the voltage of the power source VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the first switch circuit is turned off, thereby not affecting the normal operation of the NMOS tube M0.

[0035] In this specific embodiment, the first switch circuit includes a PMOS tube M5, a PMOS tube M6, a diode D0 and a resistor R1, the drain of the PMOS tube M5 is connected to the output terminal SRG of the drive circuit, the source of the PMOS tube M5 is connected to the source of the PMOS tube M6, the drain of the PMOS tube M6 is connected to the gate of the NMOS tube M0, the resistor R1 is connected in parallel with the PMOS tube M5, the positive end of the diode D0 is connected to the gate of the PMOS tube M5, the negative end of the diode D0 is connected to the source of the PMOS tube M5, the PMOS tube M5 and the PMOS tube M6 are connected to the gate of the NMOS tube M0. The gate of the OS transistor M6 is connected to a first control voltage, and the first control voltage is configured such that when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit, the first control voltage is zero; when the voltage of the power supply VIN is greater than or equal to the operating voltage UVLO of the drive circuit, the first control voltage is greater than or equal to the voltage of the output terminal SRG. With this circuit structure, the NMOS transistor M0 can be turned on when the voltage of the output terminal SRG is very small, further improving safety and reliability. However, this is not limited to this. In other embodiments, other existing switch circuits can also be used for implementation.

[0036] In this specific embodiment, a second switch circuit is also included, and the second switch circuit is connected between the gate of the NMOS tube M0 and the second control output terminal of the control logic circuit 1. The second switch circuit is configured to be turned off when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit; and turned on when the voltage of the power supply VIN is greater than or equal to the operating voltage UVLO of the drive circuit. By setting the second switch circuit, when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit, the first switch circuit and the second control output terminal of the control logic circuit 1 can be prevented from affecting each other, thereby improving reliability.

[0037] In this specific embodiment, the second switch circuit is preferably implemented by an NMOS tube M4, the drain of the NMOS tube M4 is connected to the second control output terminal of the control logic circuit 1, the source of the NMOS tube M4 is connected to the gate of the NMOS tube M0, and the gate of the NMOS tube M4 is connected to the first logic level SREN, and the first logic level SREN is configured such that when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit, the first logic level SREN is 0; when the voltage of the power supply VIN is greater than or equal to the operating voltage UVLO of the drive circuit, the first logic level SREN is 1. The first logic level SREN can be provided by the third control output terminal of the control logic circuit 1, when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit, the control logic circuit 1 cannot work normally, and the output of the third control output terminal is 0; when the voltage of the source VIN is greater than or equal to the operating voltage UVLO of the drive circuit, the control logic circuit 1 works normally, and the output of the third control output terminal is 1.

[0038] In this specific embodiment, the first control voltage is provided by a voltage stabilizing circuit, the input end of the voltage stabilizing circuit is connected to the power supply VIN, the output end of the voltage stabilizing circuit outputs a voltage VPRE as the first control voltage, and the voltage stabilization value of the voltage stabilizing circuit is the withstand voltage of the controlled NMOS tube SR, which is set to 15V in this specific embodiment, but is not limited to this.

[0039] Specifically, Figure 4 As shown, in this embodiment, the voltage stabilizing circuit includes a PMOS tube M10, a PMOS tube M11, an NMOS tube M9, a voltage stabilizing tube zener1, a voltage stabilizing tube zener2, a voltage stabilizing tube zener3, a resistor R2 and a resistor R3, the source of the PMOS tube M11 is connected to the power supply VIN, the drain of the PMOS tube M11 is connected in series with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 in sequence and is grounded, the resistor R3 is connected in series with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 In parallel, the source of the PMOS tube M10 is connected to the power supply VIN, the drain of the PMOS tube M10 is respectively connected to the gate of the PMOS tube M11, the gate of the PMOS tube M10 and the drain of the NMOS tube M9, the source of the NMOS tube M9 is connected to the ground in series with the resistor R2, the gate of the NMOS tube M9 is connected to the first logic level SREN, and the node between the PMOS tube M11 and the voltage regulator tube zener1 is used as the output terminal output voltage VPRE of the voltage regulator circuit, which is used to provide the first control voltage to the gates of the PMOS tubes M5 and M6. Of course, in other embodiments, other existing voltage regulator circuits can also be used to achieve this.

[0040] In this specific embodiment, an N-type transistor M8 and a third switch circuit are also included. The N-type transistor M8 is connected in parallel with the PMOS tube M3. The gate of the PMOS tube M3 is connected to the first control output terminal of the control logic circuit 1 through the first level conversion circuit 2. The power input terminal of the first level conversion circuit 2 is connected to the power supply VIN. The control electrode of the N-type transistor M8 is connected to the first control output terminal of the control logic circuit 1 through the second level conversion circuit 3. The power input terminal of the second level conversion circuit 3 is connected to the voltage VPRE, that is, connected to the output terminal of the voltage stabilization circuit. The third switch circuit is configured to control the PMOS tube M3 to turn off when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube SR. It can avoid that the output voltage of the driving circuit exceeds the withstand voltage of the controlled NMOS tube SR, causing the controlled NMOS tube SR to burn out, and a simple voltage stabilization circuit can be used without using a linear voltage regulator, so there is no need to add a chip pin and an external capacitor C0, so that the circuit occupancy area is greatly reduced, and the chip driving cost is reduced.

[0041] In this specific embodiment, the N-type transistor M8 is preferably an NMOS transistor with a small on-resistance, but is not limited thereto. In other embodiments, other N-type transistors may also be used, such as an NPN transistor.

[0042] In this specific embodiment, the third switch circuit includes a PMOS tube M7, the source of the PMOS tube M7 is connected to the power supply VIN, the drain of the PMOS tube M7 is connected to the gate of the PMOS tube M3, the gate of the PMOS tube M7 is connected to the second control voltage VIN_OV, and the second control voltage VIN_OV is configured to turn on the PMOS tube M7 when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube SR, which is set to 15V in this specific embodiment; when the voltage of the power supply VIN is less than or equal to the withstand voltage of the controlled NMOS tube SR, the second control voltage VIN_OV turns off the PMOS tube M7. Of course, in other embodiments, the third switch circuit can also be implemented by other existing circuit structures.

[0043] When the voltage of the power supply VIN reaches the operating voltage UVLO of the drive circuit, the first logic level SREN is 1, the NMOS tube M4 is turned on, the PMOS tube M10, the PMOS tube M11 and the NMOS tube M9 are turned on, the voltage stabilizing circuit outputs the voltage VPRE, the voltage VPRE=min(VIN, 15V), the PMOS tube M5 and the PMOS tube M6 are turned off, and the NMOS tube M0 is controlled by the control logic circuit 1 and can work normally; when the voltage of the power supply VIN is less than the operating voltage UVLO of the drive circuit, the first logic level SREN is 0, the NMOS tube M4 is turned off, the PMOS tube M10, the PMOS tube M11 and the NMOS tube M9 are turned off, and ... The circuit output is 0. When the voltage at the output end SRG is greater than the turn-on voltage of the PMOS tube M6, the PMOS tubes M5 and M6 are turned on, thereby transmitting the voltage at the output end SRG to the gate of the NMOS tube M0, thereby turning on the NMOS tube M0. Once the NMOS tube M0 is turned on, since the on-resistance of the NMOS tube M0 is very small, the voltage at the output end SRG will be quickly pulled down, thereby limiting the voltage at the output end SRG. Before the voltage of the power supply VIN reaches UVLO, the external synchronous rectifier tube SR will not be turned on, thereby avoiding the switch on the primary side of the flyback converter and the synchronous rectifier tube SR on the secondary side being turned on at the same time, causing the transformer inductance to be saturated, thereby burning the transformer and the switch tubes on the primary and secondary sides.

[0044] When the power supply voltage VIN exceeds 15V (the withstand voltage of the synchronous rectifier SR), the PMOS tube M7 turns off the PMOS tube M3, and the NMOS tube M8 is turned on as a pull-up tube. At this time, the voltage of the output terminal SRG is the voltage VPRE-VGS, where VGS is the VGS of the NMOS tube M8, which will not exceed the withstand voltage of the synchronous rectifier SR; when the power supply voltage VIN is greater than the operating voltage UVLO of the driving circuit and less than 15V, the PMOS tube M3 and the NMOS tube M8 are both turned on and serve as pull-up tubes together. At this time, the voltage of the output terminal SRG is the voltage of the power supply VIN, which will not exceed the withstand voltage of the synchronous rectifier SR. Therefore, the VGS withstand voltage requirement of the synchronous rectifier SR is met, and there is no need to use a linear regulator, so there is no need to add a chip pin and an external capacitor C0, which greatly reduces the circuit area occupied and reduces the chip driving cost.

[0045] Embodiment 2

[0046] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that: in this embodiment, the first switch circuit is implemented by a PNP transistor M5, the emitter of the PNP transistor M5 is connected to the output terminal SRG of the drive circuit, the collector of the PNP transistor M5 is connected to the gate of the NMOS tube M0, and the base of the PNP transistor M5 is connected to the first control voltage VPRE.

[0047] In this embodiment, the second switch circuit is implemented by an NPN transistor M4, the collector of the NPN transistor M4 is connected to the second control output terminal of the control logic circuit 1, the emitter of the NPN transistor M4 is connected to the gate of the NMOS transistor M0, and the base of the NPN transistor M4 is connected to the first logic level SREN.

[0048] The circuit of the present invention can also be used in other types of driving circuits, and is not limited to synchronous rectification driving circuits, and can be used in scenarios where it is necessary to prevent the external MOS from being turned on when it is not needed.

[0049] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A controlled NMOS tube driving circuit, comprising a pull-up tube M3, a pull-down tube M0 and a control logic circuit, characterized in that: It also includes a first switch circuit, the output end SRG of the drive circuit is connected to the power supply VIN through the pull-up tube M3, and is grounded through the pull-down tube M0, the control ends of the pull-up tube M3 and the pull-down tube M0 are connected to the control output end of the control logic circuit, the first switch circuit is connected between the output end SRG of the drive circuit and the control end of the pull-down tube M0, and the first switch circuit is configured to turn on when the voltage of the power supply VIN is less than the working voltage of the drive circuit and the voltage of the output end SRG of the drive circuit is greater than the turn-on voltage of the first switch circuit; when the voltage of the power supply VIN is greater than or equal to the working voltage of the drive circuit, the first switch circuit is turned off.

2. The driving circuit of the controlled NMOS tube according to claim 1, characterized in that: The first switch circuit includes a PMOS tube M5, a PMOS tube M6, a diode D0 and a resistor R1, the drain of the PMOS tube M5 is connected to the output end SRG of the drive circuit, the source of the PMOS tube M5 is connected to the source of the PMOS tube M6, the drain of the PMOS tube M6 is connected to the control end of the pull-down tube M0, the resistor R1 is connected in parallel with the PMOS tube M5, the positive end of the diode D0 is connected to the gate of the PMOS tube M5, the negative end of the diode D0 is connected to the source of the PMOS tube M5, the gates of the PMOS tube M5 and the PMOS tube M6 are connected to a first control voltage, and the first control voltage is configured such that when the voltage of the power supply VIN is less than the working voltage of the drive circuit, the first control voltage is zero; when the voltage of the power supply VIN is greater than or equal to the working voltage of the drive circuit, the first control voltage VPRE is greater than or equal to the voltage of the output end SRG.

3. The driving circuit of the controlled NMOS tube according to claim 1 or 2, characterized in that: The second switch circuit is also included, the second switch circuit is connected between the control end of the pull-down tube M0 and the control output end of the control logic circuit, and the second switch circuit is configured to be turned off when the voltage of the power supply VIN is less than the working voltage of the drive circuit; When the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the second switch circuit is turned on.

4. The driving circuit of the controlled NMOS tube according to claim 3, characterized in that: The second switch circuit is implemented by an NMOS tube M4, a drain of the NMOS tube M4 is connected to the control output end of the control logic circuit, a source of the NMOS tube M4 is connected to the control end of the pull-down tube M0, and a gate of the NMOS tube M4 is connected to a first logic level SREN, wherein the first logic level SREN is configured such that when the voltage of the power supply VIN is less than the operating voltage of the drive circuit, the first logic level SREN is 0; when the voltage of the power supply VIN is greater than or equal to the operating voltage of the drive circuit, the first logic level SREN is 1.

5. The driving circuit of the controlled NMOS tube according to claim 1, characterized in that: It also includes an N-type transistor M8 and a third switch circuit, wherein the N-type transistor M8 is connected in parallel with the pull-up tube M3, the control electrode of the pull-up tube M3 is connected to the first control output terminal of the control logic circuit through a first level conversion circuit, the power input terminal of the first level conversion circuit is connected to the power supply VIN, the control electrode of the N-type transistor M8 is connected to the first control output terminal of the control logic circuit through a second level conversion circuit, the power input terminal of the second level conversion circuit is connected to the voltage VPRE, and the voltage VPRE is configured such that when the voltage of the power supply VIN is greater than or equal to the withstand voltage of the controlled NMOS tube, the voltage VPRE is equal to the withstand voltage of the controlled NMOS tube, and the third switch circuit is configured such that when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube, the pull-up tube M3 is controlled to be turned off.

6. The driving circuit of the controlled NMOS tube according to claim 5, characterized in that: The N-type transistor M8 is an NMOS transistor.

7. The driving circuit of the controlled NMOS tube according to claim 5, characterized in that: It also includes a voltage stabilizing circuit, wherein the input end of the voltage stabilizing circuit is connected to a power source VIN, the output end of the voltage stabilizing circuit outputs a voltage VPRE, and the voltage stabilizing value of the voltage stabilizing circuit is the withstand voltage of the controlled NMOS tube.

8. The driving circuit of the controlled NMOS tube according to claim 7, characterized in that: The voltage stabilizing circuit includes a PMOS tube M10, a PMOS tube M11, an NMOS tube M9, a voltage stabilizing tube zener1, a voltage stabilizing tube zener2, a voltage stabilizing tube zener3, a resistor R2 and a resistor R3. The source of the PMOS tube M11 is connected to a power source VIN, the drain of the PMOS tube M11 is connected in series with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 in sequence and grounded, the resistor R3 is connected in parallel with the voltage stabilizing tube zener1, the voltage stabilizing tube zener2 and the voltage stabilizing tube zener3 connected in series, the source of the PMOS tube M10 is connected to the power source VIN, the drain of the PMOS tube M10 is connected to the gate of the PMOS tube M11, the gate of the PMOS tube M10 and the drain of the NMOS tube M9 respectively, the source of the NMOS tube M9 is connected in series with the resistor R2 and grounded, the gate of the NMOS tube M9 is connected to the first logic level SREN, and the node between the PMOS tube M11 and the voltage stabilizing tube zener1 serves as the output end of the voltage stabilizing circuit.

9. The driving circuit of the controlled NMOS tube according to claim 5, characterized in that: The third switch circuit includes a PMOS tube M7, a source of the PMOS tube M7 is connected to a power supply VIN, a drain of the PMOS tube M7 is connected to a control electrode of the pull-up tube M3, and a gate of the PMOS tube M7 is connected to a second control voltage VIN_OV. The second control voltage VIN_OV is configured such that when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube, the second control voltage VIN_OV turns on the PMOS tube M7; when the voltage of the power supply VIN is less than or equal to the withstand voltage of the controlled NMOS tube, the second control voltage VIN_OV turns off the PMOS tube M7.

10. The driving circuit of the controlled NMOS tube according to claim 1, characterized in that: The device also includes a pull-down resistor R0, which is connected in parallel with the pull-down transistor M0.

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