Electronic circuits with electrostatic discharge protection

Abstract

A semiconductor substrate includes a doped region having an upper surface. The doped region may include a conductive terminal (such as a cathode) of a diode or a conductive terminal (such as a drain) of a transistor. A silicide layer is provided at the doped region. The silicide layer has a region that only partially covers an area of ​​the upper surface of the doped region. The partial coverage helps modulate the threshold voltage and / or leakage current of the integrated circuit device.

Description

[0001] Priority Declaration

[0002] This application claims priority from French patent application No. 1 870 781, filed on June 29, 2018, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and, more particularly, to protection circuits from the effects of electrostatic discharge. Background Art

[0004] Problems caused by electrostatic discharge (ESD) are becoming more pronounced as the size of components in electronic circuits decreases. Protecting electronic circuits from the effects of ESD is an important issue in ensuring the reliability and durability of electronic circuits.

[0005] Therefore, an electrostatic discharge protection circuit with better performance is needed. Summary of the Invention

[0006] Embodiments overcome all or part of the disadvantages of known protection circuits against electrostatic discharge effects.

[0007] An embodiment provides a device including a silicide layer partially covering a doped region.

[0008] According to an embodiment, the device further comprises a MOS type transistor.

[0009] According to an embodiment, the device further comprises a diode.

[0010] According to an embodiment, the cathode of the diode and the drain of the transistor are formed by the first N-type doping region.

[0011] According to an embodiment, the dopant atomic concentration of the first N-type doping region is 10 17 to 10 18 atoms / cm 3 within the range.

[0012] According to an embodiment, the doped region includes at least a first N-type doped region partially covered by the silicide layer.

[0013] According to an embodiment, the doped region includes only the first N-type doped region.

[0014] According to an embodiment, a portion of the anode of the diode is covered by the control electrode.

[0015] According to an embodiment, the thickness of the silicide layer is in the range of 10 nm to 20 nm.

[0016] According to an embodiment, the device is formed inside and on top of a silicon-on-insulator type structure.

[0017] According to an embodiment, the device is formed inside and on top of an ultra-thin silicon-on-insulator structure.

[0018] According to an embodiment, the doped region is covered by a single portion of the silicide layer.

[0019] According to an embodiment, the doped region is covered by at least a portion of the silicide layer.

[0020] According to an embodiment, the doped regions are regularly covered by portions of the silicide layer.

[0021] Another embodiment provides a protection circuit for preventing the effects of electrostatic discharge, which includes the device described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The foregoing and other features and advantages are discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0023] Figure 1 An electrical diagram showing a protection circuit against the effects of electrostatic discharge;

[0024] Figure 2 Shown Figure 1 A cross-sectional view of an embodiment of a circuit;

[0025] Figure 3 Shown Figure 2 A top view of an embodiment of the present invention;

[0026] Figure 4 It shows Figure 1 The current characteristic and voltage characteristic curve diagram of the circuit;

[0027] Figure 5 It shows Figure 1 Another graph of current characteristics and voltage characteristics of the circuit;

[0028] Figure 6 Shown Figure 1 A top view of another embodiment of a circuit; and

[0029] Figure 7 Shown Figure 1 A top view of another embodiment of a circuit. DETAILED DESCRIPTION

[0030] In different drawings, the same elements have been denoted by the same reference numerals. Specifically, the structural elements and / or functional elements common to different embodiments may be denoted by the same reference numerals and may have the same structural characteristics, dimensional characteristics, and material characteristics.

[0031] For the sake of clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail. In particular, the manufacture of the protection circuit against the effects of electrostatic discharge is not described in detail.

[0032] Throughout this disclosure, the term "connected" is used to indicate a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term "coupled" is used to indicate an electrical connection between circuit elements that may be direct or via one or more intervening elements.

[0033] Typically, the following terms are used:

[0034] -Lightly doped semiconductor layer means that the concentration of dopant atoms is in the range of 10 14 to 10 16 atoms / cm 3 layer;

[0035] - Doped semiconductor layer means that the concentration of dopant atoms is in the range of 10 17 to 10 18 atoms / cm 3 layers; and

[0036] -Heavily doped semiconductor layers indicate dopant atomic concentrations in the range of 10 18 to 10 21 atoms / cm 3 layer.

[0037] In the following description, when reference is made to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", etc.) or when reference is made to terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise stated, they refer to the orientation of the drawings.

[0038] The terms "about," "substantially," and "approximately" are used herein to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0039] Figure 1 FIG. 1 is an electrical diagram of a protection circuit 10 for preventing the effects of electrostatic discharge.

[0040] The circuit 10 comprises a diode 12. The diode 12 is provided with a control electrode which is arranged on a part of the anode region of the diode 12. The control electrode enables the conduction of the PN junction of the diode 12 to be improved. Figure 2 The control electrode of diode 12 is described in more detail.

[0041] Circuit 10 further includes a transistor 14. Transistor 14 is a MOS type transistor, more specifically, an N-channel MOS transistor.

[0042] The diode 12 and the transistor 14 are connected in series. More specifically, the cathode of the diode 12 is connected to the drain of the transistor 14, and more specifically, in relation to Figure 2 In the depicted embodiment, the cathode of diode 12 and the drain of transistor 14 are formed from the same N-type doped region. The anode of diode 12, the source of transistor 14, the control electrode of diode 12, and the gate of transistor 14 are coupled to contacts C1, C2, C3, and C4, respectively, external to the integrated circuit chip of circuit 10. For example, contact C5 (dashed line in the figure) can be coupled to the cathode of diode 12 and the drain of transistor 14.

[0043] The operation of the circuit 10 may be similar to the operation of a thyristor.

[0044] Combine Figure 2 The structure of the circuit 10 will be described in more detail.

[0045] Figure 2 It is a combination Figure 1 A cross-sectional view of an embodiment of a structure 20 of a circuit of the type described is shown.

[0046] The structure 20 is formed inside and on top of a silicon-on-insulator (SOI) type structure, which includes a semiconductor substrate 101, for example, made of silicon, which supports an insulating layer 103, for example, made of silicon oxide, on which a semiconductor layer 105, for example, made of silicon, rests. More specifically, the structure 20 is formed inside and on top of an FD-SOI ("fully depleted silicon-on-insulator") type structure (i.e., an ultra-thin silicon-on-insulator type structure). The thickness of the insulating layer 103 is, for example, in the range of 15 nm to 30 nm, for example, approximately 25 nm. The thickness of the conductive layer 105 is, for example, in the range of 5 nm to 22 nm, for example, approximately 15 nm.

[0047] The semiconductor layer 105 is divided into a plurality of doping regions or areas. Figure 2 From left to right, it is as follows:

[0048] - P-type heavily doped region 107 (P+);

[0049] -P-type lightly doped region 109 (P-);

[0050] - N-type doped region 111 (N);

[0051] - P-type lightly doped region 113 (P-); and

[0052] - N-type heavily doped region 115 (N+).

[0053] Insulated gates 117 and 119, or control electrodes 117 and insulated gates 119, are arranged on top of regions 109 and 113, respectively, and in contact with regions 109 and 113, respectively. Each gate 117, 119 is formed by a layered structure (not explicitly shown), which includes a gate oxide layer, on which a conductive layer rests. More specifically, the insulated gates 117 and 119 are HKMG-type gates ("high-K metal gates"). Therefore, the gate oxide layer is made of a high dielectric constant dielectric material, such as hafnium oxide. The gate oxide layer usually does not rest directly on the silicon region, and an interface layer, such as silicon oxide, needs to be present. For example, the thickness of the gate oxide layer is in the range of 1 nm to 10 nm, for example, about 2 nm. The conductive layer is usually a stack of different conductive layers, such as a titanium nitride layer and a polysilicon layer. For example, the thickness of the conductive layer is, for example, about 50 nm. In Figure 2 1 and 1. Gates 117 and 119 are shown as blocks without detailing the layers forming them. Gates 117 and 119 are laterally delimited by insulating walls 121. Each insulating wall 121 is, for example, arranged at the junction between two doped regions of layer 105. Insulating walls 121 are made, for example, of silicon nitride and / or silicon oxide.

[0054] Contacts C1, C2, C3 and C4 (at Figure 2 The regions 107 and 115 (represented by squares in FIG) are formed on the regions 107 and 115 and on the regions of the gates 117 and 119. The contacts C1, C2, C3 and C4 are made of metal, for example. For manufacturing reasons, the contacts C1, C2, C3 and C4 cannot be formed directly on the regions 107 and 115 and the gates 117 and 119, and an intermediate conductive layer, for example made of silicide, is required. For this purpose, the regions 107 and 115 and the gates 117 and 119 are each covered by a conductive layer S made of silicide. More specifically, the contacts C3 and C4 are not arranged directly above the gates 117 and 119 (see FIG. Figure 3 ). Layer S is made of, for example, nickel silicide (NiSi). The thickness of layer S is, for example, in the range of 10 nm to 30 nm, for example, approximately 12.5 nm. For example, the silicide layers may have different thicknesses depending on what they cover. For example, the thickness of the silicide layer S covering regions 107 and 115 may be approximately 15 nm, and the thickness of the silicide layer S covering gates 117 and 119 may be approximately 25 nm.

[0055] Region 111 is further partially covered by a silicide layer S'. The silicide layer S' has the same size and material properties as the silicide layer S. Figure 3The distribution pattern of the layer S′ on the region 111 is described in further detail. For example, a contact C5 may also be formed on the layer S′ and the region 111 .

[0056] Regions 107, 109, 111 and gate 117 are assembled to form diode 12. Regions 107 and 109 form the anode of diode 12. Region 111 forms the cathode of diode 12. Insulated gate 117 forms the control electrode of diode 12.

[0057] Regions 111, 113, 115, and gate 119 are assembled to form transistor 14. Region 111 forms the drain of transistor 14. Region 113 forms the channel region of transistor 14. Region 115 forms the source of transistor 14. Gate 119 forms the gate of transistor 14.

[0058] Figure 3 It is a combination Figure 2 A top view of the structure of the circuit 10 is shown. Figure 3 In the diagram, the positions of contacts C1, C2, C3, C4 and C5 are as follows: Figure 2 The same way as in the example above, a square is used to represent it.

[0059] As previously indicated, the silicide region S' only partially covers the region 111. Figure 3 In the example shown, layer S' covers region 111 over its entire width, but not along its entire length L. Layer S' then has a length d. For example, for a length L of approximately 10 μm, length d may be equal to 2, 4, 6, or 8 μm. Alternatively, layer S' may not cover region 115 over its entire width.

[0060] The inventors have observed that by controlling (selecting) the proportion of the N-type doped region 111 covered by the silicide layer S′, the threshold voltage of the circuit 10 formed by the structure 20 can be adjusted.

[0061] The inventors have also observed that controlling (selecting) the proportion of the area 111 covered by the silicide layer S′ makes it possible to modulate the value of the leakage current of the circuit 10 .

[0062] Furthermore, contacts C3 and C4 are formed on portions of the silicide layer S that do not directly rest on the gates 117 and 119. In practice, conventional contact formation methods risk degrading the gates 117 and 119.

[0063] Figure 4 is a graph drawn on a logarithmic scale, which shows Figure 1 The current characteristics and voltage characteristics of the circuit type. More specifically, Figure 4ACS (Average Current Slope) type current and voltage characteristics are shown, that is, current and voltage characteristics obtained by gradually increasing the current sent to the anode of the diode 12 and by measuring the voltage between the potential of the anode 12 and a reference potential. The ACS type current and voltage characteristics make it possible to determine the value of the threshold voltage of the circuit 10.

[0064] In practice, depending on the purpose of the protection circuit against electrostatic discharge, the threshold voltage or turn-on voltage of the circuit 10 should be lower than the maximum voltage authorized by the circuit or terminal to be protected.

[0065] Figure 4 The graph includes two curves 30 and 32. Each curve 30, 32 represents a Figure 2 and Figure 3 The current and voltage characteristics of a circuit of the type described for structure 20 are shown. Curve 30 represents the current and voltage characteristics of a circuit whose silicide layer S' covers a smaller portion of region 111 than the circuit whose current and voltage characteristics are represented by curve 32. It should be noted that the threshold voltage Vt30 of the circuit of curve 30 is lower than the threshold voltage Vt32 of the circuit of curve 32. Therefore, reducing the size of the portion of region 111 covered by silicide layer S' enables a reduction in the threshold voltage of the corresponding circuit.

[0066] Figure 5 It shows Figure 1 Other current characteristics and voltage characteristics of the circuit type are shown in the graph. More specifically, Figure 5 Shown are current and voltage characteristics of the AVS (“Average Voltage Slope”) type, that is, current and voltage characteristics obtained by gradually increasing the voltage between the potential of the anode 12 and a reference potential and by measuring the current flowing on the anode of the diode 12. The AVS type current and voltage characteristics make it possible to determine a value that does not exceed the maximum voltage across the protection circuit against the influence of electrostatic discharge, thereby avoiding excessive current consumption and leakage current.

[0067] In fact, by setting the limiting current Ilimit on the current characteristic and the voltage characteristic, the maximum voltage that the circuit can withstand can be determined without exceeding the limiting current Ilimit.

[0068] Figure 5 The graph includes curves 40 and 42. Each curve 40, 42 shows a graph having a combined Figure 2 and Figure 3The current and voltage characteristics of a circuit of the type described in structure 20 are shown. Curve 40 shows the current and voltage characteristics of a circuit whose silicide layer S' covers a smaller portion of doped region 111 than the silicide layer S' of a circuit characterized by curve 42. It should be noted that the voltage Vm40 reached for the limited current Ilimit in circuit 40 is less than the voltage Vm42 reached for the limited current Ilimit in circuit 42. Therefore, the more region 111 of a circuit is covered with silicide, the less significant the current consumption and leakage currents.

[0069] Therefore, for a given application, it is important to determine the proportion of the silicide layer S' so as to obtain sufficient threshold voltage and power consumption.

[0070] Figure 6 is a top view of another embodiment of structure 20. The cross-sectional view along line II is similar to Figure 2 In this embodiment, the silicide layer S also partially covers the regions 107 and 115 and the gates 117 and 119.

[0071] Figure 7 is a top view of yet another embodiment of structure 20. The cross-sectional view along line II-II is similar to Figure 2 Cross-sectional view of .

[0072] In this embodiment, the region 111 is, for example, uniformly covered by a plurality of portions of the silicide layer S′ rather than being covered by a single portion of the silicide layer S′.

[0073] The advantage of this embodiment is that, by dividing the silicide layer S′ into a plurality of parts, their distribution is more regular, which makes it possible to avoid irregularities in the current flow at the structural level.

[0074] Combine Figures 1 to 7 An advantage of the described embodiments is that their production method does not require additional costs compared to methods for producing circuits whose doped regions and whose gates are completely covered by silicide.

[0075] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0076] Specifically, in Figure 3 In the embodiment shown, the structure 20 has a rectangular shape in a top view, but as a variant, the structure 20 may for example have the shape of a ring or any other shape suitable for the operation of the structure 20 .

[0077] Furthermore, regarding Figure 6 The described embodiments may be used in conjunction with Figure 7 Combinations of the described embodiments.

[0078] Further, the region 111 is an N-type doped region, but it may be an N-type heavily doped region.

[0079] Furthermore, depositing a partial silicide layer on the doped portion can be applied to other types of protection circuits against electrostatic discharge, such as those described in S. Athanasiou et al., entitled “Preliminary 3D TCAD Electro-thermal Simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology,” 2015 Intl. Conf. on IC Design and Technology.

[0080] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0081] These changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the present invention. Therefore, the foregoing description is intended to be illustrative only and not restrictive. The present invention is limited only by the following claims and their equivalents.

Claims

1. An integrated circuit device comprising: semiconductor substrates; a transistor having a transistor gate extending in a length direction on a channel region of the semiconductor substrate; a diode having a diode gate extending in the length direction on the anode region of the semiconductor substrate; wherein the semiconductor substrate comprises a doped region located between the transistor gate and the diode gate, the doped region extending in the length direction and having an upper surface; a silicide layer in contact with the upper surface of the doped region, wherein the silicide layer has an area that only partially covers an area of ​​the upper surface of the doped region, the area of ​​the silicide layer having a length shorter than a length of the area of ​​the upper surface of the doped region, wherein the length of the area of ​​the silicide layer and the length of the area of ​​the upper surface of the doped region both extend parallel to the length direction; wherein the doped region forms a cathode of the diode and a drain of the transistor which are electrically connected in series with each other; wherein the semiconductor substrate further comprises a source region for the transistor, the source region extending in the length direction and having an upper surface; as well as another silicide layer in contact with the upper surface of the source region, wherein the another silicide layer has an area that only partially covers an area of ​​the upper surface of the source region, and the area of ​​the another silicide layer has a length shorter than a length of the area of ​​the upper surface of the source region, wherein the length of the area of ​​the another silicide layer and the length of the area of ​​the upper surface of the source region both extend parallel to the length direction. 2 . The integrated circuit device according to claim 1 , wherein a portion of the anode of the diode is covered by the control electrode.

3. The integrated circuit device according to claim 1 , wherein the dopant atomic concentration of the doped region is 10 17 to 10 18 atoms / cm 3 within the range.

4. An integrated circuit device according to claim 1, wherein the semiconductor substrate further includes an anode region for the diode, the anode region extending in the length direction and having an upper surface, and the integrated circuit device further includes a further silicide layer in contact with the upper surface of the anode region, wherein the further silicide layer has a region that only partially covers an area of ​​the upper surface of the anode region, the region of the further silicide layer has a length shorter than a length of the region of the upper surface of the anode region, wherein the length of the region of the further silicide layer and the length of the region of the upper surface of the anode region both extend parallel to the length direction.

5. The integrated circuit device according to claim 1, wherein the diode and the transistor electrically connected in series with each other form a protection circuit against influence of electrostatic discharge. 6 . The integrated circuit device of claim 1 , wherein a thickness of the silicide layer is in a range of 10 nm to 30 nm.

7. The integrated circuit device according to claim 1, wherein the semiconductor substrate is a semiconductor layer of a silicon-on-insulator structure.

8. The integrated circuit device according to claim 7, wherein the silicon-on-insulator structure is of an ultra-thin silicon-on-insulator type.

9. The integrated circuit device of claim 1, wherein the area of ​​the upper surface of the doped region is covered by only a single portion of the silicide layer.

10. The integrated circuit device of claim 1, wherein the doped region is part of a protection circuit for preventing the effects of electrostatic discharge.

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