Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device comprises: a peripheral circuit structure including a peripheral circuit insulating layer; an intermediate connection structure located on the peripheral circuit insulating layer, the intermediate connection structure including the intermediate connection insulating layer, and the bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer; a stacking structure located on a side of the intermediate connection structure; and a channel structure extending vertically through each stacking structure, wherein at least one side surface of the intermediate connection insulating layer is an inclined surface, and the cross-sectional area of ​​the intermediate connection insulating layer decreases along an upward direction oriented away from the peripheral circuit insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims the priority of Korean Patent Application No. 10-2018-0081149, entitled “Semiconductor Memory Device and Method of Manufacturing the Same”, filed on Jul. 12, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods consistent with example embodiments relate to a three-dimensional (3D) semiconductor memory device having improved integration density and reliability and a method of manufacturing the device. Background Art

[0004] In order to manufacture lightweight, thin, simple and small electronic devices and improve price competitiveness, it is necessary to increase the integration density of semiconductor memory devices. In recent years, in order to overcome the integration limitations of two-dimensional (2D) semiconductor memory devices, three-dimensional (3D) semiconductor memory devices including three-dimensionally arranged memory cells have been developed. The 3D semiconductor memory device includes a channel structure, which includes a plurality of vertically stacked layers and is formed to pass through a plurality of layers to increase the integration density. The 3D semiconductor memory device includes a cell array region and a connection region, and the connection region is arranged between the cell array regions. The process of forming the connection region using an etching process and a gap filling process may affect the reliability of the 3D semiconductor memory device. Summary of the invention

[0005] According to an example embodiment, there is provided a semiconductor memory device, comprising: a peripheral circuit structure having a peripheral circuit insulating layer; an intermediate connection structure disposed on the peripheral circuit insulating layer and including the intermediate connection insulating layer; a stacked structure disposed on a side of the intermediate connection structure; and a channel structure formed to vertically penetrate the stacked structure. The bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer, and the cross-sectional area of ​​the intermediate connection insulating layer decreases upward, so that at least one side surface layer of the intermediate connection insulating layer is formed as an inclined surface.

[0006] According to an example embodiment, there is provided a semiconductor memory device, comprising: a peripheral circuit structure having a peripheral circuit insulating layer; an intermediate connection structure disposed on the peripheral circuit insulating layer and including the intermediate connection insulating layer; a stacked structure disposed on a side of the intermediate connection insulating layer above the peripheral circuit insulating layer; and a channel structure formed to vertically penetrate the stacked structure. Each stacked structure comprises a plurality of layers, a bottom surface of a lowermost layer of each stacked structure contacts a top surface of the peripheral circuit insulating layer, and a bottom surface of a penultimate lower layer of each stacked structure contacts a top surface of the lowermost layer and a side surface of the intermediate connection insulating layer.

[0007] According to example embodiments, there is provided a method for manufacturing a semiconductor memory device, the method comprising: depositing an intermediate connection insulating layer on a top surface of a peripheral circuit insulating layer; forming a stacked structure on a side of the intermediate connection insulating layer; and forming a channel structure, the channel structure being configured to vertically penetrate the stacked structure. The bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer, and the cross-sectional area of ​​the intermediate connection insulating layer decreases upward, so that at least one side surface layer of the intermediate connection insulating layer is formed as an inclined surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A schematic plan view of a semiconductor memory device according to example embodiments is shown.

[0010] Figure 2 Shown along Figure 1 A vertical cross-sectional view taken along line AA.

[0011] Figure 3 Shows Figure 1 An enlarged plan view of portion B.

[0012] Figure 4A Shown along Figure 3 A vertical cross-sectional view taken along line DD.

[0013] Figure 4B Shows Figure 4A An enlarged view of part E of FIG.

[0014] Figure 4C Shows Figure 4A An enlarged view of part F.

[0015] Figure 5 Shows Figure 1 An enlarged plan view of portion C of FIG.

[0016] FIG. 6A to FIG. 6K Views illustrating a process of manufacturing a semiconductor memory device according to example embodiments.

[0017] Fig. 7A The corresponding Figure 4A A vertical cross-sectional view of a semiconductor memory device.

[0018] Figure 7B Shows Fig. 7A An enlarged view of portion G.

[0019] FIG. 8A to FIG. 8E Views illustrating a process of manufacturing a semiconductor memory device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, a semiconductor memory device and a method of manufacturing the same according to example embodiments will be described with reference to the accompanying drawings.

[0021] Figure 1 is a schematic plan view of a semiconductor memory device according to example embodiments. Figure 2 It is along Figure 1 A vertical cross-sectional view taken along line AA.

[0022] refer to Figure 1 and Figure 2 , a semiconductor memory device 100 according to example embodiments may include a cell array region 10 , a peripheral circuit region 20 , an intermediate connection region 30 , and a peripheral connection region 40 .

[0023] Hereinafter, the first direction D1 indicates a direction in which one cell array region 10 extends, and the second direction D2 indicates a direction perpendicular to the first direction D1, and the cell array regions 10 are spaced apart from each other along the second direction D2. The third direction D3 is a direction perpendicular to the first direction D1 and the second direction D2, and the cell array region 10 and the intermediate connection region 30 are stacked on the peripheral circuit region 20 along the third direction D3. Figure 1 , one lateral side and the other lateral side respectively represent the second direction D2 and its opposite direction (for example, Figure 1 right and left sides of the ). Based on Figure 1 , the front side and the rear side respectively represent the first direction D1 and its opposite direction (for example, respectively Figure 1 top and bottom of the structure in ).

[0024] The semiconductor memory device 100 may be a three-dimensional (3D) semiconductor memory device. For example, the semiconductor memory device 100 may be a 3D NAND flash memory device. The semiconductor memory device 100 may have a cell-on-periphery (COP) structure in which a cell array region 10 and an intermediate connection region 30 are stacked on a peripheral circuit region 20. The semiconductor memory device 100 may include a peripheral connection region 40 formed on the peripheral circuit region 20.

[0025] The plurality of cell array regions 10 may be formed to extend in the first direction D1 and may be spaced apart from each other in the second direction D2 . The peripheral circuit region 20 may be disposed under the cell array region 10 .

[0026] The intermediate connection region 30 may be disposed between the cell array regions 10. The intermediate connection region 30 may be formed to have different lengths and widths according to its position and purpose. The intermediate connection region 30 may be formed to have different areas according to its position and purpose. For example, the intermediate connection region 30 may include a first intermediate connection region 30a having a relatively large length along the first direction D1 and a second intermediate connection region 30b having a relatively small length along the first direction D1. The first intermediate connection region 30a and the second intermediate connection region 30b may be formed to have different widths or lengths from each other.

[0027] The first intermediate connection regions 30a may extend along the first direction D1, for example, the longitudinal direction of the first intermediate connection regions 30a may extend along the first direction D1, and may be spaced apart from each other along the second direction D2, for example, each first intermediate connection region 30a may be located between two unit array regions 10. For example, the first lateral side, the second lateral side, and the rear side of the first intermediate connection region 30a may, for example, be in direct contact with the unit array region 10, and the front side of the first intermediate connection region 30a may, for example, be in direct contact with the peripheral connection region 40. In another example, the front side of the first intermediate connection region 30a may, for example, not be in direct contact with the peripheral connection region 40, but may be formed to be spaced apart from the peripheral connection region 40 along the first direction D1, as shown in FIG. Figure 1 shown.

[0028] All side surfaces of the second intermediate connection region 30b may, for example, be in direct contact with the cell array region 10. The second intermediate connection region 30b may be spaced apart from the rear side of the first intermediate connection region 30a along the first direction D1. The second intermediate connection regions 30b may be spaced apart from each other along the second direction D2, and may be spaced apart from the first intermediate connection region 30a by different distances. For example, Figure 1 As shown, the distance between adjacent second intermediate connection regions 30b along the second direction D2 may be different from the distance between adjacent first intermediate connection regions 30a along the second direction D2. Figure 1 As shown, heights of the intermediate connection region 30 and the cell array region 10 along the third direction D3 may be equal to each other.

[0029] The peripheral connection region 40 may extend along the first direction D1 and be disposed on the first lateral side and the second lateral side of the cell array region 10. For example, two peripheral connection regions 40 may extend along the first direction D1 and be spaced apart from each other along the first lateral side and the second lateral side of the cell array region 10 in the second direction D2. The peripheral connection region 40 may be disposed at the front and rear sides of the cell array region 10 in the first direction D1. For example, two peripheral connection regions 40 may extend along the second direction D2 and be spaced apart from each other along the front and rear sides of the cell array region 10 in the first direction D1. Figure 1 As shown, the peripheral connection region 40 may define a frame surrounding, for example, the entire periphery of the cell array region 10 .

[0030] Figure 3 yes Figure 1 An enlarged plan view of portion B.

[0031] refer to Figure 3 , the cell array region 10 may include a stacked structure 110, a channel structure 120, and a common source line (CSL) 130. Each cell array region 10 may include at least two common source lines 130. The stacked structure 110 may extend along a first direction D1 and be stacked along a third direction D3. The channel structure 120 may be formed in the stacked structure 110 along the third direction D3, and may be spaced apart from each other along the first direction D1 and the second direction D2. The stacked structure 110 may also include an isolation wall 115 disposed adjacent to the intermediate connection region 30, for example, the isolation wall 115 may separate the intermediate connection region 30 from the adjacent stacked structure 110.

[0032] The intermediate connection region 30 may be disposed between the cell array regions 10 and include an intermediate connection structure 150. The intermediate connection region 30 may not be formed in the gate contact region of the cell array region 10. The intermediate connection structure 150 may include an intermediate connection insulating layer 151 and an intermediate connection contact 152. Although not specifically shown, the peripheral connection region 40 may have a structure similar to that of the intermediate connection region 30.

[0033] Figure 4A It is along Figure 3 A vertical cross-sectional view taken along line DD. Figure 4B yes Figure 4A An enlarged view of part E of FIG. Figure 4C yes Figure 4A An enlarged view of part F. Figure 5 yes Figure 1 An enlarged plan view of portion C of FIG.

[0034] refer to Figure 3 , Figure 4A and Figure 4B , the semiconductor memory device 100 may include a stack structure 110, a channel structure 120, a common source line 130, a peripheral circuit structure 140, and an intermediate connection structure 150. The semiconductor memory device 100 may also include a bit line BL. The stack structure 110, the channel structure 120, and the common source line 130 may be disposed in the cell array region 10, and the peripheral circuit structure 140 may be disposed in the peripheral circuit region 20, for example, disposed below the stack structure 110. The intermediate connection structure 150 may be disposed in the intermediate connection region 30.

[0035] refer to Figure 3 , the intermediate connection structure 150 may be disposed in the first intermediate connection region 30a, and the stacked structure 110 may be disposed on both sides of the intermediate connection structure 150, for example, as Figure 4A Further, refer to Figure 5 , the intermediate connection structure 150 may be formed in the second intermediate connection region 30b, and the stacked structure 110 may be disposed on both lateral sides, the front side, and the rear side of the intermediate connection structure 150, for example, around the periphery. Hereinafter, the case where the intermediate connection structure 150 is disposed in the first intermediate connection region 30a will be mainly described. In the case where the intermediate connection structure 150 is disposed in the second intermediate connection region 30b, the difference compared to the case where the intermediate connection structure 150 is disposed in the first intermediate connection region 30a will be mainly described.

[0036] refer to Figure 4A-4C , the stacked structure 110 may include a sub-substrate 111, an interlayer insulating layer 112, a gate electrode 113, and an interlayer supporting layer 114. The stacked structure 110 may further include an isolation wall 115. The stacked structure 110 may further include: a mold insulating layer 118 configured to surround and insulate a region including an upper portion of the interlayer insulating layer 112; and an upper insulating layer 160 configured to insulate the bit line BL above the mold insulating layer 118. In the stacked structure 110, the gate electrode 113 may be formed at the same level as the interlayer supporting layer 114, as shown in FIG. Figure 4B That is, the gate electrode 113 may be replaced by the interlayer support layer 114. The stack structure 110 may be formed by alternately stacking the electrodes 113 and the interlayer insulating layer 112 on the sub-substrate 111 and overlappingly stacking the interlayer support layer 114 and the interlayer insulating layer 112.

[0037] The stacked structure 110 may include a plurality of layers. The lowest layer of the stacked structure 110 may be a sub-substrate 111, and the penultimate lower layer of the stacked structure 110 may be an interlayer insulating layer 112, for example, the lowest interlayer insulating layer 112-1 of the interlayer insulating layer 112 may be directly located on the sub-substrate 111. In addition, the gate electrode 113 and the interlayer insulating layer 112 may be alternately stacked on the interlayer insulating layer 112, for example, stacked on the lowest interlayer insulating layer 112-1 of the interlayer insulating layer 112. The bottom surface of the sub-substrate 111 (as the lowest layer of the stacked structure 110) may be in contact with the top surface of the peripheral circuit insulating layer 145 included in the peripheral circuit structure 140. The bottom surface of the lowest interlayer insulating layer 112-1 of the interlayer insulating layer 112, i.e., the penultimate lower layer of the stacked structure 110, may be in contact with the top surface of the sub-substrate 111 and the side surface of the intermediate connection insulating layer 151 of the intermediate connection structure 150.

[0038] The sub-substrate 111 may include a semiconductor material. For example, the sub-substrate 111 may be a silicon (Si) single crystal substrate, a germanium (Ge) single crystal substrate, or a silicon germanium (SiGe) single crystal substrate. The sub-substrate 111 may be a P-type semiconductor substrate. The sub-substrate 111 may include P-type impurities, for example, boron (B), gallium (G), or indium (In). The sub-substrate 111 is not limited to a P-type semiconductor substrate. The sub-substrate 111 may be a silicon on insulator (SOI) substrate.

[0039] refer to Figure 2 , Figure 4A and Figure 4C , the sub-substrate 111 may include a semiconductor pattern 121 formed on the peripheral circuit region 20. The sub-substrate 111 may include a substrate trench 111a, which may have a predetermined width and extend through the sub-substrate 111 along the first direction D1. The substrate trench 111a may be formed at a position where the intermediate connection structure 150 is formed. A lower portion of the intermediate connection structure 150 may be inserted into the substrate trench 111a and combined with the substrate trench 111a. The substrate trench 111a may be formed in a shape corresponding to the lower portion of the intermediate connection structure 150. The substrate trench 111a may be formed in a shape extending along the first direction D1. Reference Figure 3 and Figure 5 , the substrate trench 111a formed in the sub-substrate 111 may be, for example, corresponding to Figure 1 The first intermediate connecting region 30a and the second intermediate connecting region 30b have a quadrilateral shape.

[0040] The sub-substrate 111 may include a common source region 111b, such as Figure 4CThe common source region 111b may be formed in the sub-substrate 111 and extend along the first direction D1. The common source region 111b may have a different conductive material from the sub-substrate 111, for example, may include N-type impurities such as arsenic (As) or phosphorus (P).

[0041] The interlayer insulating layer 112 may include a plurality of insulating layers, for example, interlayer insulating layers 112-1, 112-2, 112-3, 112-4, 112-5, 112-6, and 112-7. The interlayer insulating layers 112 may be stacked on the sub-substrate 111 to be spaced apart from each other along the third direction D3. The interlayer insulating layer 112-7, which is the uppermost layer of the interlayer insulating layer 112, may be used as an etching barrier layer. In this case, the interlayer insulating layer 112-7 may be formed of a material having an etching selectivity relative to the intermediate connection insulating layer 151. In addition, all interlayer insulating layers 112 may be formed of a material having an etching selectivity relative to the intermediate connection insulating layer 151.

[0042] Each interlayer insulating layer 112 may include an insulating lateral portion 112a and an insulating inclined portion 112b. Figure 4B As shown. The insulating lateral portion 112a and the insulating inclined portion 112b may be sequentially formed toward the intermediate connection structure 150. For example, the insulating lateral portion 112a may be a portion formed parallel to the sub-substrate 111, and the insulating inclined portion 112b may extend from an edge of the insulating lateral portion 112a facing the intermediate connection structure 150 along (e.g., and parallel to) the sidewall of the intermediate connection structure 150. For example, the insulating lateral portion 112a of the interlayer insulating layer 112-1 (as the lowermost layer of the interlayer insulating layer 112) may contact the top surface of the sub-substrate 111.

[0043] Specifically, the insulating inclined portion 112b may be a portion formed at the end of the insulating lateral portion 112a and inclined at a predetermined inclination angle θ relative to the lateral direction. The inclination angle θ of the insulating inclined portion 112b may correspond to the inclination angle of the side surface of the intermediate connection insulating layer 151. The insulating inclined portion 112b may be a portion formed parallel to the inclined surface of the intermediate connection insulating layer 151. A first lateral side of the insulating inclined portion 112b may be connected to an edge of the insulating lateral portion 112a, and a second lateral side of the insulating inclined portion 112b may extend upward so as to be inclined at the inclination angle θ. For example, the insulating inclined portion 112b of the interlayer insulating layer 112-1 (as the lowermost layer of the interlayer insulating layer 112) may be in contact with both side surfaces of the intermediate connection insulating layer 151, for example, may be in direct contact with the side wall of the intermediate connection insulating layer 151 while completely surrounding the intermediate connection insulating layer 151. In addition, referring to Figure 5, the insulating inclined portion 112b may be in contact with both side surfaces, the front surface, and the rear surface of the intermediate connection insulating layer 151. The insulating inclined portion 112b may be stacked in a direction perpendicular to the side surface of the intermediate connection structure 150. A side section of the insulating inclined portion 112b may be exposed at the top surface of the stacked structure 110. The interlayer insulating layer 112 may include an insulating material, such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0044] The gate electrode 113 may include a plurality of electrodes, for example, gate electrodes 113-1, 113-2, 113-3, 113-4, 113-5, and 113-6. The gate electrodes 113 and the interlayer insulating layer 112 may be alternately stacked on the sub-substrate 111 along the third direction D3. The gate electrodes 113 may be electrically insulated from each other by the interlayer insulating layer 112. The gate electrode 113 may be disposed between the insulating lateral portions 112a of the interlayer insulating layer 112, rather than between the insulating inclined portions 112b of the interlayer insulating layer 112, for example, the gate electrode 113 may extend only along the second direction D2 to terminate at the isolation wall 115. The gate electrode 113 may include a conductive film. For example, the gate electrode 113 may include a semiconductor film (e.g., a silicon film doped with impurities), a metal silicide film (e.g., a cobalt silicide film, a nickel silicide film, a titanium silicide film, a tungsten silicide film, or a tantalum silicide film), a metal nitride film (e.g., a titanium nitride film, a tungsten nitride film, or a tantalum nitride film), a metal film (e.g., a tungsten film, a nickel film, a cobalt film, a titanium film, a ruthenium film, or a tantalum film), and / or a film formed by a combination thereof. The gate electrode 113 may be combined with the channel structure 120 to constitute a memory cell. Therefore, the gate electrode 113 may be used as a control electrode of the memory cells arranged in an array in the cell array region 10.

[0045] The interlayer support layer 114 may include a plurality of support layers, for example, interlayer support layers 114-1, 114-2, 114-3, 114-4, 114-5, and 114-6. The interlayer support layer 114 may be disposed between the interlayer insulating layers 112 and between the gate electrode 113 and the intermediate connection insulating layer 151. The interlayer support layer 114 may be stacked on the same horizontal plane as the gate electrode 113. The interlayer support layer 114 may be disposed between the interlayer insulating layers 112 outside the gate electrode 113. The interlayer support layer 114 may support the interlayer insulating layer 112 during the formation of the gate electrode 113.

[0046] Specifically, Figure 4BAs shown, each interlayer support layer 114 may include a support transverse portion 114a and a support inclined portion 114b. The support transverse portion 114a may be a portion formed parallel to the sub-substrate 111, for example, at the same horizontal plane as a corresponding gate electrode 113, and the support inclined portion 114b may extend from the support transverse portion 114a along the sidewall of the intermediate connection insulating layer 151, for example, between the insulating inclined portions 112b.

[0047] Specifically, the supporting lateral portion 114a may be a portion formed parallel to the insulating lateral portion 112a. The supporting lateral portion 114a may be formed between the insulating lateral portions 112a, for example, the supporting lateral portion 114a may be aligned with the corresponding gate electrode 113 on the opposite side of the isolation wall 115 along the second direction D2 and the third direction D3 ( Figure 4B ).

[0048] The support inclined portion 114b may be a portion formed to be inclined at a predetermined inclination angle θ relative to the lateral direction toward the third direction D3. The inclination angle θ of the support inclined portion 114b may correspond to the inclination angle of the side surface of the intermediate connection insulating layer 151. The support inclined portion 114b may be disposed between the insulating inclined portions 112b. A first lateral side of the support inclined portion 114b may be connected to the support lateral portion 114a, and a second lateral side of the support inclined portion 114b may extend in an upward direction so as to be inclined at an inclination angle θ. The inclination angle θ of the support inclined portion 114b may correspond to the inclination angle of the side surface of the intermediate connection structure 150. The support inclined portion 114b may be stacked in a direction perpendicular to the side surface of the intermediate connection structure 150, for example, the support inclined portion 114b and the insulating inclined portion 112b may alternate from the side wall of the intermediate connection structure 150. The side section of the support inclined portion 114b may be exposed at the top surface of the stacked structure 110.

[0049] Depending on the time point of forming the isolation wall 115, the interlayer support layer 114 may be formed by an interlayer sacrificial layer 114d ( Figure 6G ) or the gate electrode 113. For example, when the isolation wall 115 is formed and the interlayer sacrificial layer 114d is removed, the interlayer support layer 114 can be formed by leaving the interlayer sacrificial layer 114d. In addition, when the gate electrode 113 is formed and the isolation wall 115 is formed, the interlayer support layer 114 can be formed by the gate electrode 113. In this case, the interlayer support layer 114 can be electrically isolated from the gate electrode 113 by the isolation wall 115.

[0050] The isolation walls 115 may be formed to vertically (i.e., along the third direction D3) penetrate the interlayer insulating layer 112 between the gate electrode 113 and the interlayer supporting layer 114. Each isolation wall 115 may be formed in the shape of a wall body configured to isolate the gate electrode 113 from the interlayer supporting layer 114. The isolation walls 115 may extend to the top surface of the sub-substrate 111, or to a predetermined depth from the top surface of the sub-substrate 111.

[0051] The isolation wall 115 may prevent the gate electrode 113 from being formed between the insulating inclined portions 112b of the interlayer insulating layer 112. Figure 3 , the isolation walls 115 may be formed as strip-type wall bodies along both sides of the intermediate connection insulating layer 151, for example, extending along the first direction D1 and spaced apart from each other along the second direction D2. Figure 5 The isolation wall 115 may be formed as a wall body having a quadrilateral shape (eg, a continuous ring shape) along the circumference of the intermediate connection insulating layer 151 of the second intermediate connection region 30b. The isolation wall 115 may prevent the gate electrode 113 from being formed between the insulating inclined portions 112b of the interlayer insulating layer 112.

[0052] Because the thickness of the insulating inclined portion 112b is less than the thickness of the insulating lateral portion 112a, if the gate electrode 113 is to be formed between the insulating inclined portions 112b, a short circuit may occur between the gate electrodes 113 due to the thin thickness of the insulating inclined portions 112b. In addition, a side cross-section of the gate electrode 113 may be exposed at the top surface of the stacked structure 110 and electrically connected to other patterns. In contrast, according to example embodiments, the gate electrode 113 is formed only between the insulating lateral portions 112a, and the isolation wall 115 prevents the gate electrode 113 from being formed between the thin insulating inclined portions 112b of the interlayer insulating layer 112.

[0053] The formation of the isolation wall 115 may include forming an isolation cutout IC through the interlayer insulating layer 112 and filling the isolation cutout IC with an insulating material using, for example, an atomic layer deposition (ALD) process, as will be described below with reference to FIG. Figure 6H-Figure 6I More detailed description. The isolation cutout IC can be formed in a groove type, and the groove can be formed to pass through the stacked structure 110 and extend along the first direction D1 and the third direction D3. The isolation cutout IC can be formed on the top surface of the sub-substrate 111, or etched to a predetermined depth from the top surface of the sub-substrate 111. The isolation wall 115 can be formed of a material having an etching selectivity relative to the interlayer support layer 114. The isolation wall 115 can be formed of an oxide film or a nitride film. The isolation wall 115 may include an insulating material, such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0054] refer to Figure 3 and Figure 4A-4C , the channel structure 120 may extend along the third direction D3 and be formed to vertically penetrate the stack structure 110 ( Figure 4A ). A plurality of channel structures 120 may be arranged in the cell array region 10 along the first direction D1 and the second direction D2. Figure 3 As shown, the channel structures 120 may be arranged in a zigzag shape along the first direction D1 and adjacent to each other along the second direction D2.

[0055] The channel structure 120 may include various layer structures formed outside the central axis of the channel structure 120. For example, Figure 4C As shown, the channel structure 120 may include an information storage pattern 122, a channel pattern 123, and a buried insulating pattern 124 in order from the outside to the inside of the channel structure 120. The channel structure 120 may also include a semiconductor pattern 121, a conductive pad 125, and a bit contact 126.

[0056] The semiconductor pattern 121 may be disposed at the lowest portion of the channel structure 120. The semiconductor pattern 121 may be in direct contact with the sub-substrate 111 and electrically connected to the sub-substrate 111. A portion of the semiconductor pattern 121 may be buried in the sub-substrate 111, and another portion of the semiconductor pattern 121 may have a cylindrical shape vertically protruding from the top surface of the sub-substrate 111. The semiconductor pattern 121 may include, for example, silicon (Si). The semiconductor pattern 121 may be an epitaxial pattern including, for example, single crystal silicon or polycrystalline silicon. The semiconductor pattern 121 may include, for example, germanium (Ge), silicon germanium (SiGe), a III-V semiconductor compound, or a II-VI semiconductor compound. The semiconductor pattern 121 may be an undoped pattern without impurities, or a pattern doped with impurities having the same conductivity type as the sub-substrate 111.

[0057] The information storage pattern 122 may be disposed on the top surface of the semiconductor pattern 121 or the top surface of the sub-substrate 111 and, for example, extend along the inner sidewall of the channel structure 120 in the third direction D3. The information storage pattern 122 may have a tubular shape having a hollow inner portion and open upper and lower ends. The lower end of the information storage pattern 122 may contact the semiconductor pattern 121 or the sub-substrate 111. The information storage pattern 122 may include a thin film configured to store data.

[0058] The channel pattern 123 may be disposed on the top surface of the semiconductor pattern 121 or the top surface of the sub-substrate 111, and, for example, extend in the third direction D3 along the information storage pattern 122. The channel pattern 123 may have a tubular shape having a hollow inner portion and an open upper end and lower end. The lower end of the channel pattern 123 may contact and be electrically connected to the semiconductor pattern 121 or the sub-substrate 111. The outer circumferential surface of the channel pattern 123 may contact the inner circumferential surface of the information storage pattern 122. The channel pattern 123 may include at least one of the following: for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The channel pattern 123 may include an undoped semiconductor material without impurities, or include a semiconductor material doped with impurities having the same conductivity type as the sub-substrate 111.

[0059] The buried insulating pattern 124 may be disposed on the top surface of the semiconductor pattern 121 or the top surface of the sub-substrate 111 and extend along the third direction D3. The buried insulating pattern 124 may be formed to fill the empty space formed in the channel pattern 123. The buried insulating pattern 124 may be formed in a columnar shape. The outer circumferential surface of the buried insulating pattern 124 may contact the channel pattern 123. The buried insulating pattern 124 may be formed of, for example, a silicon oxide film or a silicon nitride film.

[0060] The conductive pad 125 may be disposed on the channel pattern 123. The conductive pad 125 may be formed on the buried insulating pattern 124. The conductive pad 125 may include a conductive material. The conductive pad 125 may be omitted.

[0061] The bit contact 126 may be formed to extend upward from the top surface of the conductive pad 125. The bit contact 126 may electrically connect the conductive pad 125 with the bit line BL. The bit contact 126 may include a conductive material, such as doped silicon, metal silicide, or metal.

[0062] The common source line 130 may include a common source plug 131 and a common source spacer 132. The common source line 130 may be disposed between cell blocks. The common source line 130 may be disposed within a word line cutout WLC ( Figure 4C). The word line cutout WLC may be formed by etching the stack structure 110 along the first direction D1. More specifically, the word line cutout WLC may be formed as a type of trench that may be formed to pass through the stack structure 110 and extend along the first direction D1. The word line cutout WLC may be formed on the top surface of the sub-substrate 111, or may be etched to a predetermined depth from the top surface of the sub-substrate 111. The common source line 130 may extend to the common source region 111b of the sub-substrate 111, and be electrically connected to the common source region 111b.

[0063] The common source plug 131 may extend in the first direction D1 along the common source region 111b in the word line cutout WLC. The common source plug 131 may extend from the common source region 111b to the upper portion of the stack structure 110. The common source plug 131 may be formed to have a wall structure. When viewed from above, the common source plug 131 may be formed to have a wall structure, for example. Figure 3 The common source line 130 is shown as a strip extending along the first direction D1. The common source plug 131 may include a conductive material such as tungsten, copper, titanium, titanium nitride, tantalum, tantalum nitride, silicon or aluminum.

[0064] like Figure 4C As shown, a common source spacer 132 may be formed between the inner side surface of the word line cutout WLC and the common source plug 131. The common source spacer 132 may, for example, continuously fill the space between the entire common source plug 131 and the stack structure 110. The common source spacer 132 may cover the sidewall of the stack structure 110. The common source spacer 132 may electrically insulate the common source plug 131 from the gate electrode 113 of the stack structure 110. The common source spacer 132 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0065] like Figure 4A As shown, the bit line BL may be formed in the upper portion of the cell array region 10 and the intermediate connection region 30, or in the upper portion of the peripheral circuit region 20. The bit line BL may contact the upper portion of the bit contact 126 of the channel structure 120 and be electrically connected to the channel structure 120. The bit line BL may include a conductive metal such as aluminum, copper, or tungsten.

[0066] like Figure 4A As further shown in FIG. 1 , the peripheral circuit structure 140 may include a main substrate 141 , a peripheral transistor 142 , a peripheral circuit interconnect 143 , a peripheral circuit contact 144 , and a peripheral circuit insulation layer 145 .

[0067] The main substrate 141 may include a semiconductor substrate, such as a silicon wafer. The main substrate 141 may be formed of the same material as the sub-substrate 111. The main substrate 141 may be formed to have an area larger than that of the sub-substrate 111, and the entire sub-substrate 111 may overlap at least a portion of the main substrate 141. Although not specifically shown, the main substrate 141 may include a device isolation film formed between the peripheral transistors 142 to electrically insulate the peripheral transistors 142.

[0068] The peripheral transistor 142 may include a peripheral gate insulating film 142a, a peripheral gate electrode 142b, and a source-drain region 142c. The peripheral transistor 142 may also include a peripheral gate spacer. The peripheral gate electrode 142b may be disposed on the peripheral gate insulating film 142a. The peripheral gate electrode 142b may include, for example, silicon, metal silicide, nickel silicide, cobalt silicide, titanium silicide, tantalum silicide (TaSi) or metal. The source-drain region 142c may be disposed in the main substrate 141 and include N-type impurities (e.g., phosphorus (P)) or P-type impurities (e.g., boron (B)). A plurality of peripheral transistors 142 may be formed in the peripheral circuit region 20. The peripheral transistor 142 may include a high voltage or low voltage transistor.

[0069] The peripheral circuit interconnect 143 may include a metal interconnect deposited on the main substrate 141. The peripheral circuit interconnect 143 may be formed in a linear shape or a pad shape extending in the first direction D1 or the second direction D2. The peripheral circuit interconnect 143 may be formed at various locations according to the location of the peripheral transistor 142. The peripheral circuit interconnect 143 may include a lower circuit interconnect 143a and an upper circuit interconnect 143b, which are sequentially deposited above the main substrate 141. A plurality of peripheral circuit interconnects 143 may be formed in various shapes and numbers at various locations according to the location and number of the peripheral transistor 142.

[0070] The peripheral circuit contact 144 may include a metal contact deposited on the main substrate 141. The peripheral circuit contact 144 may be formed in the type of a through hole extending along the third direction D3. The peripheral circuit contact 144 may include a lower circuit contact 144a and an upper circuit contact 144b, which are sequentially deposited on the main substrate 141. The lower circuit contact 144a may contact and electrically connect the peripheral transistor 142 and the lower circuit interconnect 143a. The upper circuit contact 144b may contact and electrically connect the lower circuit interconnect 143a and the upper circuit interconnect 143b. A plurality of peripheral circuit contacts 144 may be formed in various shapes at various positions according to the position of the peripheral transistor 142.

[0071] A peripheral circuit insulating layer 145 may be formed on the main substrate 141 to cover the peripheral transistor 142, the peripheral circuit interconnection 143, and the peripheral circuit contact 144. The peripheral circuit insulating layer 145 may be formed between the main substrate 141 and the sub-substrate 111. Although not specifically shown, the peripheral circuit insulating layer 145 may include a plurality of insulating layers according to the number of layers of the peripheral circuit interconnection 143. The peripheral circuit insulating layer 145 may be formed of, for example, a silicon oxide film or a low-k dielectric material.

[0072] The intermediate connection structure 150 may include an intermediate connection insulating layer 151 and an intermediate connection contact 152. The intermediate connection structure 150 may be disposed in the intermediate connection region 30. Figure 1 , the intermediate connection region 30 may be formed to have different lateral areas according to the position. Therefore, the intermediate connection structure 150 may also be formed to have different lateral areas according to the lateral area of ​​the intermediate connection region 30. In the following, Figure 3 The intermediate connection structure 150 formed in the first intermediate connection region 30a is shown. Figure 5 An intermediate connection structure 150 formed in the second intermediate connection region 30 b is shown.

[0073] The intermediate connection structures 150 may be formed to have different widths or lengths depending on the intermediate connection regions 30 in which the intermediate connection structures 150 are formed. The plurality of intermediate connection structures 150 may be formed to have different areas. For example, the intermediate connection structure 150 formed in the first intermediate connection region 30a may be formed to have a different lateral area, for example, a length along the first direction D1, from the intermediate connection structure 150 formed in the second intermediate connection region 30b.

[0074] refer to Figure 3 , Figure 4A , Figure 4B , the intermediate connection insulating layer 151 may be deposited on the top surface of the peripheral circuit structure 140 in an upward direction. The intermediate connection insulating layer 151 may be deposited on the top surface of the peripheral circuit insulating layer 145 of the peripheral circuit structure 140 in an upward direction. The stacked structure 110 may be disposed on both sides of the intermediate connection insulating layer 151. In addition, referring to Figure 5 , the intermediate connection insulating layer 151 of the second intermediate connection region 30b may be formed to have a quadrilateral cross section. Figure 5 The stacked structure 110 shown in FIG. 1 may be disposed on both lateral sides, the front side, and the rear side of the intermediate connection insulating layer 151. For example, referring to Figure 1 and Figure 5 , in a top view, the stacked structure 110 may completely surround the periphery of each intermediate connection insulating layer 151. The plurality of intermediate connection insulating layers 151 may be formed to have different lateral areas.

[0075] The intermediate connection insulating layer 151 may be formed to have a shape whose cross-sectional area decreases in an upward direction, for example, its width gradually decreases from the bottom to the top in a direction oriented away from the sub-substrate 111. Figure 4A As shown, the width of the bottom of the intermediate connection insulating layer 151 along the second direction D2 (e.g., as measured between the opposite surfaces of the substrate groove 111a) may be greater than the width of the top of the intermediate connection insulating layer 151 along the second direction D2 (e.g., measured along the bottom surface of the mold insulating layer 118). The side surface of the intermediate connection insulating layer 151 may be inclined inward at a predetermined inclination angle. At least one side surface of the intermediate connection insulating layer 151 may be inclined at a predetermined inclination angle. More specifically, the side surface of the intermediate connection insulating layer 151 exposed above the sub-substrate 111 may be formed as an inclined surface. The inclined surface of the intermediate connection insulating layer 151 may contact the bottom surface of the insulating inclined portion 112b of the interlayer insulating layer 112, which is located at the lowest position of the stacked structure 110.

[0076] A side surface of the intermediate connection insulating layer 151 facing the stack structure 110 may be formed as an inclined surface. Figure 3 , the side surfaces of the intermediate connection insulating layer 151 along the second direction D2 and the direction opposite to the second direction D2 may be formed as inclined surfaces. Figure 5 , side surfaces of the intermediate connection insulating layer 151 in the first direction D1 and a direction opposite to the first direction D1 and side surfaces in the second direction D2 and a direction opposite to the second direction D2 may be formed as inclined surfaces.

[0077] The lower portion of the intermediate connection insulating layer 151 may be combined with the substrate trench 111a of the sub-substrate 111. The bottom surface of the intermediate connection insulating layer 151 may contact the top surface of the peripheral circuit insulating layer 145. The side surface of the lower portion of the intermediate connection insulating layer 151 may contact the inner side surface of the substrate trench 111a. The bottom surface of the intermediate connection insulating layer 151 may be substantially coplanar with the bottom surface of the sub-substrate 111.

[0078] The top surface of the intermediate connection insulating layer 151 may be formed to have an area required to electrically insulate the intermediate connection contact 152 from the stacked structure 110 near the intermediate connection contact 152. The length of the intermediate connection insulating layer 151 may be formed to correspond at least to the height of the stacked structure 110. The top surface of the intermediate connection insulating layer 151 may be coplanar with the top surface of the stacked structure 110. The intermediate connection insulating layer 151 may surround the side of the intermediate connection contact 152, for example, the entire periphery, and electrically insulate the intermediate connection contact 152. The intermediate connection insulating layer 151 may be formed of a silicon oxide film or a low-k dielectric material.

[0079] The formation of the relevant intermediate connection insulating layer may include etching the stacked structure according to the groove shape to form a centerline cut, and gap-filling the interior of the centerline cut with an insulating material. That is, the relevant intermediate connection insulating layer may be formed by etching the stacked structure and gap-filling with an insulating material. During the process of etching the stacked structure, delamination may occur between the layers included in the stacked structure. In addition, during the process of gap-filling with an insulating material, a gap may be formed in the intermediate connection insulating layer. In particular, when the same process is used to gap-fill centerline cuts with different widths, a gap may be formed in the intermediate connection insulating layer of the centerline cut with a relatively large width.

[0080] In contrast, according to example embodiments, since the intermediate connection insulating layer 151 is formed by using a deposition process and then an etching process (rather than gap filling), the possibility of forming a void in the intermediate connection insulating layer 151 can be significantly reduced. In particular, even when the intermediate connection insulating layer 151 having different widths is formed using the same process, the possibility of forming a void in the intermediate connection insulating layer 151 can be reduced. In addition, since the stacked structure 110 according to an embodiment is formed after the intermediate connection insulating layer 151 is formed, delamination between layers can be prevented or significantly reduced.

[0081] The intermediate connection contact 152 may be formed to extend along the third direction D3 within the intermediate connection insulating layer 151. The intermediate connection contact 152 may be exposed above the intermediate connection insulating layer 151. A plurality of intermediate connection contacts 152 may be spaced apart from each other along the first direction D1 or the second direction D2. The lower portion of the intermediate connection contact 152 may contact and electrically connect the peripheral circuit contact 144 of the peripheral circuit structure 140. The upper portion of the intermediate connection contact 152 may contact and electrically connect the bit line BL. The intermediate connection contact 152 may electrically connect the channel structure 120 and the peripheral circuit contact 144. The intermediate connection contact 152 may be formed in an arrangement and number corresponding to the arrangement and number of the channel structure 120 and the peripheral circuit contact 144. The intermediate connection contact 152 may be electrically insulated from the stack structure 110 by the intermediate connection insulating layer 151. The intermediate connection contact 152 may include a conductive material, such as silicon or tungsten.

[0082] Next, a method of manufacturing a semiconductor memory device according to example embodiments will be described. FIG. 6A to FIG. 6K is a view of a process of manufacturing a semiconductor memory device according to an example embodiment. Hereinafter, specific processes of a method of manufacturing a semiconductor memory device according to the present exemplary embodiment will be mainly described, and a detailed description of common processes will be omitted.

[0083] refer to Fig. 6A , Figure 4A and Figure 1 , the sub-substrate film 111c and the etching stopper film 119a may be sequentially formed on the top surface of the peripheral circuit insulating layer 145. The main substrate 141 may be formed below the peripheral circuit insulating layer 145, and the peripheral transistor 142, the peripheral circuit contact 144, and the peripheral circuit interconnection 143 may be formed on the main substrate 141, for example, the peripheral circuit insulating layer 145 may cover the peripheral transistor 142, the peripheral circuit contact 144, and the peripheral circuit interconnection 143 on the main substrate 141. The sub-substrate film 111c and the etching stopper film 119a may be formed on the top surface of the peripheral circuit insulating layer 145 in the cell array region 10 and the intermediate connection region 30. In addition, the sub-substrate film 111c and the etching stopper film 119a may also be formed in the region where the peripheral connection structure is formed. The etching stopper film 119a may be formed on the entire top surface of the sub-substrate film 111c. The etching stopper film 119a may be formed of a material having an etching selectivity relative to the intermediate connection insulating layer 151. For example, the intermediate connection insulating layer 151 may be formed of a silicon oxide film, and the etching stopper film 119a may be formed of a silicon nitride film.

[0084] refer to Figure 6B , the sub-substrate film 111c and the etching barrier film 119a may be etched and patterned in an area other than the area where the stacked structure 110 is formed, for example, the sub-substrate film 111c and the etching barrier film 119a may be etched and patterned to form a substrate groove 111a, thereby dividing the sub-substrate 111 into a plurality of parts. The sub-substrate film 111c may be formed as a sub-substrate 111, and the etching barrier film 119a may be formed as an etching barrier layer 119. The etching barrier layer 119 may be disposed on the top surface of the sub-substrate 111. The substrate groove 111a may be formed between the parts of the sub-substrate 111, and the top surface of the peripheral circuit insulating layer 145 may be exposed through the substrate groove 111a. The etching groove 119b corresponding to the substrate groove 111a may be formed in the etching barrier layer 119. The shape of the substrate groove 111a may be formed to correspond to the shape of the lower portion of the intermediate connection insulating layer 151 to be formed in a subsequent process.

[0085] refer to Figure 6C , the intermediate connection insulating film 151a may be formed in a region including the top surface of the etching stopper layer 119, the etching trench 119b, and the substrate trench 111a. The intermediate connection insulating film 151a may be formed to fill the substrate trench 111a and the etching trench 119b, and have a predetermined height from the top surface of the etching stopper layer 119. The intermediate connection insulating film 151a may be formed to have a height greater than that of the stacked structure 110. The intermediate connection insulating film 151a may be formed of a material having an etching selectivity with respect to the etching stopper layer 119.

[0086] refer to Fig.6D , the intermediate connection insulating film 151a disposed on the etching stopper layer 119 may be etched, for example, via a mask to form an intermediate connection insulating layer 151. The intermediate connection insulating layer 151 may be formed in a stripe type having a predetermined height and width and extending along the first direction D1. The intermediate connection insulating layer 151 may be formed to have a height greater than that of the stacked structure 110.

[0087] refer to Fig. 6E , the etching stopper layer 119 may be etched and removed. During the removal of the etching stopper layer 119, the top surface of the sub substrate 111 may be exposed.

[0088] refer to Fig. 6F , a plurality of interlayer insulating films 112c and a plurality of interlayer sacrificial films 114c may be stacked alternately and conformally, for example, on the top surface of the sub-substrate 111, the side surface of the intermediate connection insulating layer, and the top surface of the intermediate connection insulating layer 151, for example, via deposition. The uppermost interlayer insulating film 112c may be formed as an etching barrier film 119a. That is, the uppermost interlayer insulating film 112c may be formed as an etching barrier film 119a having an etching selectivity relative to the intermediate connection insulating layer 151. The interlayer sacrificial films 114c may be formed in number corresponding to the number of gate electrodes 113 included in the stacked structure 110. The interlayer insulating film 112c and the interlayer sacrificial film 114c may be formed on the top surface of the sub-substrate 111 and the top surface of the intermediate connection insulating layer 151 in the same manner. The interlayer insulating film 112c and the interlayer sacrificial film 114c may also be formed on the side surface of the intermediate connection insulating layer 151 in the same manner.

[0089] However, the interlayer insulating film 112c and the interlayer sacrificial film 114c formed on the side surface of the intermediate connection insulating layer 151 may be inclined relative to the top surface of the sub-substrate 111 and formed to have a thickness less than the thickness of other portions. Each of the interlayer insulating film 112c and the interlayer sacrificial film 114c may include a lateral portion formed on the top surface of the sub-substrate 111, an inclined portion formed on the side surface of the intermediate connection insulating layer 151, and a lateral portion formed on the top surface of the intermediate connection insulating layer 151. The uppermost interlayer insulating film 112c formed above the sub-substrate 111 may be formed to have a height less than that of the intermediate connection insulating layer 151.

[0090] refer to Figure 6G, the interlayer insulating film 112c and the interlayer sacrificial film 114c stacked on the top surface and the side surface of the intermediate connection insulating layer 151 can be etched based on the height of the uppermost interlayer insulating film 112c formed above the sub-substrate 111, for example, to expose the top surface of the intermediate connection insulating layer 151. In this case, a portion of the uppermost interlayer insulating film 112c formed above the sub-substrate 111 can also be etched. The etching process can be performed using a chemical mechanical polishing (CMP) process. In addition, before the CMP process, an etching process can be used to partially remove the protruding interlayer insulating film 112c and the protruding interlayer sacrificial film 114c formed on the intermediate connection insulating layer 151. When the protruding interlayer insulating film 112c and the protruding interlayer sacrificial film 114c are first partially removed, the interlayer insulating film 112c and the interlayer sacrificial film 114c can be effectively and uniformly etched during the CMP process.

[0091] Because the interlayer insulating film 112c and the interlayer sacrificial film 114c are partially etched, the upper portion of the sub-substrate 111 and the upper portion of the intermediate connection insulating layer 151 can completely form a flat surface. The interlayer insulating film 112c can be formed as the interlayer insulating layer 112, and the interlayer sacrificial film 114c can be formed as the interlayer sacrificial layer 114d. The interlayer insulating layers 112 can be exposed to be spaced apart from each other by a distance corresponding to the width of the substrate trench 111a above the sub-substrate 111, and the top surface of the intermediate connection insulating layer 151 can be exposed between the interlayer insulating layers 112. In addition, the side sections of the interlayer insulating layer 112 and the interlayer sacrificial layer 114d can be exposed between the interlayer insulating layer 112 and the intermediate connection insulating layer 151. That is, since the interlayer insulating layer 112 and the interlayer sacrificial layer 114d formed on the side surface of the intermediate connection insulating layer 151 are formed to be inclined, side sections of the interlayer insulating layer 112 and the interlayer sacrificial layer 114d may be exposed when etched in a lateral direction.

[0092] refer to Figure 6H and Figure 4A , the channel structure 120 may be formed to pass through the interlayer insulating layer 112 and the interlayer sacrificial layer 114d and extend along the third direction D3. A typical method may be used to form the channel structure 120, and its detailed description will be omitted. The word line cutout WLC may be formed between the channel structures 120 and extend along the first direction D1. The isolation cutout IC may be formed at a position adjacent to the intermediate connection structure 150 in a lateral portion of the interlayer insulating layer 112 and the interlayer sacrificial layer 114d disposed on the top surface of the sub-substrate 111, and may extend in a direction parallel to the side surface of the intermediate connection insulating layer 151. The isolation cutout IC may extend along the first direction D1 in the same manner as the word line cutout WLC. The isolation cutout IC may be formed using the same process as the word line cutout WLC.

[0093] refer to Fig.6I , the isolation cutout IC may be filled with an insulating material to form an isolation wall 115. The isolation wall 115 may be formed using an ALD process. The isolation wall 115 may be formed of a material having an etching selectivity relative to the interlayer sacrificial film 114c. The isolation wall 115 may be formed on the top surface of the sub-substrate 111, or may be formed to have a predetermined depth from the top surface of the sub-substrate 111. In this case, the word line cutout WLC may remain unfilled.

[0094] refer to Figure 6J , the interlayer sacrificial layer 114d exposed by the word line cutout WLC may be removed to form a trench opening 130a. The interlayer sacrificial layer 114d may be selectively etched relative to the isolation wall 115. That is, when the interlayer sacrificial layer 114d is etched, the isolation wall 115 may not be etched. The trench opening 130a may expose a portion of the sidewall of the channel structure 120, the top and bottom surfaces of the interlayer insulating layer 112, and a portion of the sidewall of the isolation wall 115. The portion of the interlayer sacrificial layer 114d disposed toward the word line cutout WLC relative to the isolation wall 115 may be etched. In addition, the portion of the interlayer sacrificial layer 114d disposed toward the intermediate connection insulating layer 151 relative to the isolation wall 115 may not be etched, but formed as an interlayer support layer 114. The interlayer insulating layer 112 disposed toward the word line cutout WLC may be supported by the channel structure 120 during the removal of the interlayer sacrificial layer 114d, so that the distance between the interlayer insulating layers 112 may be maintained. The interlayer insulating layer 112 disposed toward the intermediate connection insulating layer 151 may be supported by the interlayer supporting layer 114 .

[0095] Since the channel structure 120 is not formed between the isolation wall 115 and the intermediate connection insulating layer 151, when the interlayer sacrificial layer 114d is etched, the interlayer insulating layer 112 may collapse without the isolation wall 115. However, the formation of the isolation wall 115 can suppress the etching of the interlayer supporting layer 114 disposed between the isolation wall 115 and the intermediate connection insulating layer 151, and prevent the interlayer insulating layer 112 from collapsing.

[0096] The interlayer sacrificial layer 114d may be removed using an isotropic etching process. The etching process may be performed using an etchant having an etching selectivity with respect to the interlayer insulating layer 112 and the spacer 115. For example, when the interlayer sacrificial layer 114d is formed of a silicon nitride film and the interlayer insulating layer 112 and the spacer 115 are formed of a silicon oxide film, the etching process may be performed using an etchant containing phosphoric acid.

[0097] refer to Figure 6K, a gate electrode 113 may be formed to fill the word line cutout WLC and the trench opening 130a. Although not specifically shown, a gate electrode film 113a may be formed to fill the trench opening 130a where the interlayer sacrificial film 114c is located. The gate electrode film 113a formed in the word line cutout WLC may be patterned to form a gate electrode 113. The gate electrodes 113 disposed in a vertical direction may be electrically isolated from each other by the interlayer insulating layer 112. Therefore, the interlayer insulating layer 112 and the gate electrode 113 may be alternately stacked on the sub-substrate 111.

[0098] Return to reference Figure 5 , a common source line 130 including a common source plug 131 and a common source spacer 132 may be formed to fill the word line cutout WLC. First, an insulating film may be deposited in the word line cutout WLC, and an anisotropic etching process may be performed to form the common source spacer 132. Next, the inner space of the common source spacer 132 may be filled with a conductive material (e.g., tungsten) to form the common source plug 131.

[0099] Next, a semiconductor memory device according to example embodiments will be described.

[0100] refer to Fig. 7A , Figure 7B and Figure 4A , the semiconductor memory device 200 according to the example embodiment may include a stack structure 210, a channel structure 120, a common source line 130, a peripheral circuit structure 140, and an intermediate connection structure 150. In the semiconductor memory device 200 according to the example embodiment, the stack structure 210 may be arranged in a manner similar to that according to the embodiment. Figures 1 to 5 The semiconductor memory device 100 of the illustrated example embodiment is formed in a different manner. Hereinafter, a stack structure 210 of the semiconductor memory device 200 according to the example embodiment will be mainly described.

[0101] The stacked structure 210 may include a lower etch stopper layer 216, a sub-substrate 211, an interlayer insulating layer 112, a gate electrode 113, and an interlayer supporting layer 114. The stacked structure 210 may further include an isolation wall 115. In the stacked structure 210, the lower etch stopper layer 216 and the sub-substrate 211 may be formed to have the same Figures 1 to 5 The semiconductor memory device of the exemplary embodiment shown has a different structure. Therefore, the lower etching stopper layer 216 and the sub-substrate 211 will now be mainly described. In addition, the detailed description of the gate electrode 113, the interlayer support layer 114 and the spacer 115 will be omitted.

[0102] The stacked structure 210 may include a plurality of layers. The lowest layer of the stacked structure 210 may be a lower etch barrier layer 216, and the penultimate lower layer of the stacked structure 210 may be a sub-substrate 211. In addition, interlayer insulating layers 112 and gate electrodes 113 may be alternately stacked on the sub-substrate 211. The bottom surface of the lower etch barrier layer 216 (as the lowest layer of the stacked structure 210) may be in contact with the top surface of the peripheral circuit insulating layer 145 included in the peripheral circuit structure 140. The bottom surface of the sub-substrate 211 (as the penultimate lower layer of the stacked structure 210) may be in contact with the top surface of the lower etch barrier layer 216 and the side surface of the intermediate connection insulating layer 151 of the intermediate connection structure 150.

[0103] The lower etching barrier layer 216 may be deposited on the top surface of the peripheral circuit insulating layer 145 of the peripheral circuit structure 140. The lower etching barrier layer 216 may include a lower etching groove 216a, which may be formed to pass through the lower etching barrier layer 216 from the top surface of the lower etching barrier layer 216 to the bottom surface thereof. The lower etching groove 216a may have a predetermined width and extend along the first direction D1. The lower etching groove 216a may be formed in a region where the intermediate connection structure 150 is formed. The lower etching groove 216a may expose the top surface of the peripheral circuit insulating layer 145 of the peripheral circuit structure 140. The lower etching barrier layer 216 may be formed of a silicon oxide film or a silicon nitride film.

[0104] The sub-substrate 211 may include a substrate lateral portion 211a and a substrate inclined portion 211b. The substrate lateral portion 211a may be formed on the top surface of the lower etching barrier layer 216. The substrate inclined portion 211b may be formed to be inclined at a predetermined inclination angle in an upward direction relative to the substrate lateral portion 211a. In this case, the substrate inclined portion 211b may be formed to be inclined in an upward direction of the lower etching trench 216a. The substrate inclined portion 211b may be formed to be inclined at an angle corresponding to the inclination angle of the intermediate connection insulating layer 151. The inclination angle of the substrate inclined portion 211b may correspond to the inclination of the side surface of the intermediate connection structure 150. The side section of the substrate inclined portion 211b may be exposed at the top surface of the stacked structure 110. That is, one lateral side of the substrate inclined portion 211b may be connected to the substrate lateral portion 211a, and the other lateral side of the substrate inclined portion 211b may extend upward so as to be inclined at the inclination angle and exposed at the top surface of the stacked structure 210.

[0105] The interlayer insulating layer 112 may include a plurality of insulating layers, for example, 112-1, 112-2, 112-3, 112-4, 112-5, and 112-6. The interlayer insulating layer 112 may be stacked on the sub-substrate 211. The interlayer insulating layer 112 may include an insulating lateral portion 112a and an insulating inclined portion 112b. The insulating lateral portion 112a may be a portion formed parallel to the substrate lateral portion 211a. That is, the insulating lateral portion 112a may be formed on the top surface of the substrate lateral portion 211a and formed above the substrate lateral portion 211a to be spaced apart from each other. The insulating inclined portion 112b may be a portion formed parallel to the substrate inclined portion 211b. The insulating inclined portion 112b may be formed on the top surface of the substrate inclined portion 211b and formed above the substrate inclined portion 211b to be spaced apart from each other.

[0106] Next, a method of manufacturing a semiconductor memory device according to example embodiments will be described.

[0107] FIG. 8A to FIG. 8E is a view of a process of manufacturing a semiconductor memory device according to an exemplary embodiment. Hereinafter, a specific process of the method of manufacturing a semiconductor memory device according to the present exemplary embodiment will be mainly described, and a description of the method of manufacturing a semiconductor memory device according to the reference will be omitted. FIG. 6A to FIG. 6K The method of describing the exemplary embodiments is the same as the detailed description of the process and the general process.

[0108] refer to Fig. 8A , the lower etching barrier film 216b may be formed on the top surface of the peripheral circuit insulating layer 145. The lower etching barrier film 216b may be formed in a region on the top surface of the peripheral circuit insulating layer 145 where the stacked structure 210 and the intermediate connection structure 150 are to be formed. Although not specifically shown, the lower etching barrier film 216b may also be formed in a region where the peripheral connection structure is to be formed. The lower etching barrier film 216b may be formed of a material having an etching selectivity relative to the intermediate connection insulating layer 151. For example, the intermediate connection insulating layer 151 may be formed of a silicon oxide film, and the lower etching barrier film 216b may be formed of a silicon nitride film.

[0109] A region of the lower etching barrier film 216b corresponding to the intermediate connection insulating layer 151 may be etched to form a lower etching trench 216a. Thus, the lower etching barrier film 216b may be formed as a lower etching barrier layer 216. The lower etching trench 216a may expose a top surface of the peripheral connection structure.

[0110] The intermediate connection insulating film 151a may be formed in a region including the lower etching stopper layer 216 and the lower etching trench 216a. The intermediate connection insulating film 151a may fill the lower etching trench 216a and may be formed on the lower etching stopper layer 216 to have a predetermined height. The intermediate connection insulating film 151a may be formed to have a height greater than that of the stacked structure 210. The intermediate connection insulating film 151a may be formed of a material having an etching selectivity with respect to the lower etching stopper layer 216.

[0111] refer to Figure 8B , the region of the intermediate connection insulating film 151a where the lower etching stopper layer 216 is formed may be etched to form an intermediate connection insulating layer 151. The intermediate connection insulating layer 151 may be formed in a region except for the top surface of the lower etching stopper layer 216. The intermediate connection insulating layer 151 may be formed in a stripe type having a predetermined height and width and extending in the first direction D1.

[0112] refer to Figure 8C , the sub-substrate film 211c may be formed on the top surface of the lower etch barrier layer 216, the side surface of the intermediate connection insulating layer 151, and the top surface of the intermediate connection insulating layer 151. The sub-substrate film 211c may include a substrate lateral portion 211a and a substrate inclined portion 211b. The substrate lateral portion 211a may be formed on the top surface of the lower etch barrier layer 216 and the top surface of the intermediate connection insulating layer 151. The substrate inclined portion 211b may be formed on the side surface of the intermediate connection insulating layer 151.

[0113] refer to Fig.8D , a plurality of interlayer insulating films 112c and a plurality of interlayer sacrificial films 114c may be alternately formed on the top surface of the sub-substrate film 211c. The interlayer sacrificial films 114c may be formed to correspond in number to the number of gate electrodes 113 included in the stacked structure 210. Each of the interlayer insulating films 112c and the interlayer sacrificial films 114c may include a lateral portion and an inclined portion in the same manner as the sub-substrate film 211c. The uppermost interlayer insulating film 112c of the interlayer insulating films 112c may be formed as an etching barrier film. The height of the uppermost interlayer insulating film 112c formed above the lower etching barrier layer 216 may be less than the height of the intermediate connection insulating layer 151.

[0114] refer to Fig. 8E , the sub-substrate film 211c, the interlayer insulating film 112c, and the interlayer sacrificial film 114c, which may be stacked on the top surface and the side surface of the intermediate connection insulating layer 151, may be etched based on the height of the uppermost interlayer insulating film 112c. In this case, a portion of the uppermost interlayer insulating film 112c may also be etched. The sub-substrate film 211c and the interlayer insulating film 112c may be formed as the sub-substrate 211 and the interlayer insulating layer 112.

[0115] The upper portion of the lower etching stopper layer 216 and the upper portion of the intermediate connection insulating layer 151 can completely form a flat surface. In addition, the top surface of the interlayer insulating layer 112 and the top surface of the intermediate connection insulating layer 151 can be exposed. In addition, the side cross-section of the sub-substrate 211, the interlayer insulating layer 112, and the interlayer sacrificial film 114c can be exposed. That is, because the sub-substrate 211, the interlayer insulating layer 112, and the interlayer sacrificial film 114c formed on the side surface of the intermediate connection insulating layer 151 are formed to be inclined, when etching in the lateral direction, the side cross-section of the sub-substrate 211, the interlayer insulating layer 112, and the interlayer sacrificial film 114c can be exposed.

[0116] Can be used with reference Figures 6H to 6K The subsequent processes are performed in the same manner as the described processes, and a detailed description thereof will be omitted here.

[0117] By way of summary and review, example embodiments relate to providing a semiconductor memory device having high integration density and improved reliability and a method for manufacturing the device. That is, according to example embodiments, because a stacking process is used to form a connection region between cell array regions, delamination can be prevented from occurring in the cell array region, and voids can be prevented from forming in the connection region. Therefore, a semiconductor memory device having high integration density and improved reliability can be realized.

[0118] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted only in a general descriptive sense, and not for limiting purposes. In some cases, as of the time of filing of this application, it is clear to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: A peripheral circuit structure, including a peripheral circuit insulation layer; an intermediate connection structure, located on the peripheral circuit insulation layer, the intermediate connection structure comprising an intermediate connection insulation layer, and a bottom surface of the intermediate connection insulation layer contacts a top surface of the peripheral circuit insulation layer; A stacking structure, located on a side of the intermediate connecting structure; as well as a channel structure extending vertically through each of the stacked structures, At least one side surface of the intermediate connection insulating layer is an inclined surface, and a cross-sectional area of ​​the intermediate connection insulating layer decreases in an upward direction oriented away from the peripheral circuit insulating layer.

2. The semiconductor memory device according to claim 1, wherein: Each of the stacked structures comprises: A sub-substrate, wherein a substrate trench of the sub-substrate is connected to a lower portion of the intermediate connection insulating layer; interlayer insulating layers, stacked on the sub-substrate and spaced apart from each other; A gate electrode, stacked alternately with the interlayer insulating layer above the sub-substrate; an interlayer supporting layer located between the interlayer insulating layers and between the gate electrode and the intermediate connecting insulating layer; and The isolation wall vertically passes through the interlayer insulating layer, and the isolation wall is located between the gate electrode and the interlayer supporting layer.

3. The semiconductor memory device according to claim 2, wherein: Each of the interlayer insulating layers includes: an insulating lateral portion, the insulating lateral portion being parallel to the sub-substrate; and an insulating inclined portion, the insulating inclined portion being connected to the insulating lateral portion and being parallel to the inclined surface of the intermediate connecting insulating layer, and Each of the interlayer supporting layers includes: a supporting lateral portion parallel to the insulating lateral portion; and a supporting inclined portion connected to the supporting lateral portion and parallel to the insulating inclined portion.

4. The semiconductor memory device according to claim 2, wherein: The lower side surface of the intermediate connection insulating layer contacts the inner side surface of the substrate trench, and The side surface of the intermediate connection insulating layer exposed above the sub-substrate is the inclined surface.

5. The semiconductor memory device according to claim 2, wherein: The isolation wall is parallel to the channel structure.

6. The semiconductor memory device according to claim 2, wherein: The isolation wall extends to a top surface of the sub-substrate or to a predetermined depth from the top surface of the sub-substrate.

7. The semiconductor memory device according to claim 2, wherein: The spacer includes a material having an etching selectivity with respect to the interlayer supporting layer.

8. The semiconductor memory device according to claim 2, wherein: The uppermost interlayer insulating layer among the interlayer insulating layers is an etching stopper layer having an etching selectivity with respect to the intermediate connection insulating layer.

9. The semiconductor memory device according to claim 1, wherein: Each of the stacked structures comprises: a lower etching barrier layer, wherein a lower etching trench of the lower etching barrier layer is connected to a lower portion of the intermediate connection insulating layer; a sub-substrate, located on the lower etching stop layer; interlayer insulating layers stacked on the sub-substrate so as to be spaced apart from each other; A gate electrode, stacked alternately with the interlayer insulating layer above the sub-substrate; an interlayer supporting layer located between the interlayer insulating layers and between the gate electrode and the intermediate connecting insulating layer; and The isolation wall vertically passes through the interlayer insulating layer, and the isolation wall is located between the gate electrode and the interlayer supporting layer.

10. The semiconductor memory device according to claim 9, wherein: The sub-substrate comprises: a substrate lateral portion, the substrate lateral portion being parallel to the lower etching stop layer; and a substrate inclined portion, the substrate inclined portion being connected to the substrate lateral portion and being parallel to the inclined surface of the intermediate connection insulating layer, Each of the interlayer insulating layers includes: an insulating lateral portion, the insulating lateral portion being parallel to the substrate lateral portion; and an insulating inclined portion, the insulating inclined portion being connected to the insulating lateral portion and being parallel to the substrate inclined portion, and Each of the interlayer supporting layers includes: a supporting lateral portion parallel to the insulating lateral portion; and a supporting inclined portion connected to the supporting lateral portion and parallel to the insulating inclined portion.

11. The semiconductor memory device according to claim 1, wherein: The intermediate connection insulating layer includes a plurality of intermediate connection insulating layers having different lateral areas.

12. A semiconductor memory device comprising: A peripheral circuit structure, including a peripheral circuit insulation layer; an intermediate connection structure located on the peripheral circuit insulation layer and comprising an intermediate connection insulation layer having a cross-section having a decreasing width in an upward direction oriented away from the peripheral circuit insulation layer; a stacked structure located on a side of the intermediate connection insulating layer above the peripheral circuit insulating layer, each of the stacked structures comprising a plurality of layers, a bottom surface of a lowest layer of the plurality of layers in each stacked structure in contact with a top surface of the peripheral circuit insulating layer, and a bottom surface of a second-to-last lowest layer of the plurality of layers in each stacked structure in contact with a top surface of the lowest layer and a side surface of the intermediate connection insulating layer; as well as A channel structure vertically passes through the stack structure.

13. The semiconductor memory device according to claim 12, wherein: The lowermost layer in each stacked structure is a sub-substrate including a substrate trench, and the second-to-last lower layer in each stacked structure is an interlayer insulating layer, and A lower portion of the intermediate connection insulating layer is combined with the substrate trench, and a bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer.

14. The semiconductor memory device according to claim 13, wherein: Gate electrodes and interlayer insulating layers are alternately stacked on the sub-substrate, and The semiconductor memory device further includes: an interlayer supporting layer located between the interlayer insulating layers and between the gate electrode and the intermediate connecting insulating layer; and The isolation wall vertically passes through the interlayer insulating layer, and the isolation wall is located between the gate electrode and the interlayer supporting layer.

15. The semiconductor memory device according to claim 12, wherein: The lowermost layer in each stacked structure is a lower etching barrier layer including a lower etching trench, and the second-to-last lower layer in each stacked structure is a sub-substrate, and A lower portion of the intermediate connection insulating layer is combined with the lower etching trench, and a bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer.

16. The semiconductor memory device according to claim 15, wherein: Interlayer insulating layers and gate electrodes are alternately stacked on the sub-substrate, and The semiconductor memory device further includes: an interlayer supporting layer located between the interlayer insulating layers and between the gate electrode and the intermediate connecting insulating layer; and The isolation wall vertically passes through the interlayer insulating layer, and the isolation wall is located between the gate electrode and the interlayer supporting layer.

17. A method for manufacturing a semiconductor memory device, the method comprising: depositing an intermediate connection insulating layer on a top surface of the peripheral circuit insulating layer; forming a stacking structure on a side surface of the intermediate connection insulating layer; as well as forming a channel structure configured to vertically penetrate the stack structure, The bottom surface of the intermediate connection insulating layer contacts the top surface of the peripheral circuit insulating layer, and the cross-sectional area of ​​the intermediate connection insulating layer decreases upward, so that at least one side surface of the intermediate connection insulating layer is formed as an inclined surface.

18. The method according to claim 17, wherein: Forming a stacking structure includes: forming a sub-substrate film and an etching stopper film in sequence on the top surface of the peripheral circuit insulating layer; patterning the sub-substrate film and the etch stop film to form a sub-substrate and an etch stop layer, the sub-substrate comprising a substrate trench and the etch stop layer being disposed on a top surface of the sub-substrate; forming an intermediate connection insulating film on a region including a top surface of the etching stopper layer and the substrate trench, and etching the intermediate connection insulating film disposed on the etching stopper layer to form the intermediate connection insulating layer; removing the etching stopper layer, and alternately stacking interlayer insulating films and interlayer sacrificial films on the top surface of the sub-substrate and the side surface and top surface of the intermediate connection insulating layer; etching the interlayer insulating film and the interlayer sacrificial film stacked on the top surface and the side surface of the intermediate connection insulating layer based on the height of the uppermost interlayer insulating film among the interlayer insulating films formed on the sub-substrate to form an interlayer insulating layer and an interlayer sacrificial layer; forming the channel structure and forming isolation walls on lateral portions of the interlayer insulating layer and the interlayer sacrificial layer disposed on the top surface of the sub-substrate in a direction parallel to the side surface of the intermediate connection insulating layer, wherein the channel structure is configured to vertically penetrate the interlayer insulating layer and the interlayer sacrificial layer; removing a portion of the interlayer sacrificial layer disposed on an opposite side of the intermediate connection insulating layer relative to the isolation wall; and A gate electrode is formed in the removed portion of the interlayer sacrificial layer, and the remaining portion of the interlayer sacrificial layer is formed as an interlayer supporting layer.

19. The method according to claim 18, wherein: The interlayer sacrificial film is selectively etched with respect to the spacer.

20. The method according to claim 17, wherein: Forming the stacked structure includes: depositing a lower etch stopper film on a top surface of the peripheral circuit insulating layer, and etching a portion of the lower etch stopper film corresponding to the intermediate connection insulating layer to form a lower etch stopper layer including a lower etch trench; forming an intermediate connection insulating film on a region including the lower etching stopper layer and the lower etching trench; etching a region of the intermediate connection insulating film where the lower etching stop layer is formed to form the intermediate connection insulating layer; forming a sub-substrate film on a top surface of the lower etching stop layer and a side surface and a top surface of the intermediate connection insulating layer; alternately forming an interlayer insulating film and an interlayer sacrificial film on a top surface of the sub-substrate film; and The sub-substrate film, the interlayer insulating film, and the interlayer sacrificial film stacked on the top and side surfaces of the intermediate connection insulating layer are etched based on the height of the uppermost interlayer insulating film among the interlayer insulating films formed over the lower etching stopper layer.

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