Semiconductor device with alignment mark height maintained

Abstract

A semiconductor device may include: a gate electrode structure on a first region of a substrate including a first region and a second region; a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and side walls of the capping pattern; an alignment mark on the second region of the substrate, the alignment mark including an insulating material; and a filling structure on the second region of the substrate, the filling structure covering a side wall of the alignment mark and including a first filling pattern, a second filling pattern covering a lower surface and side walls of the first filling pattern, and a second etch stop pattern covering a lower surface and side walls of the second filling pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0083152 filed on Jul. 17, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor device. More specifically, embodiments of the present disclosure relate to a semiconductor device including a capping layer, which may cover an upper surface of a conductive pattern. Background Art

[0004] When forming an alignment mark by patterning an insulating layer during the manufacture of a semiconductor device, the height of the alignment mark should be maintained throughout the manufacturing process. However, in a polishing process performed after patterning the insulating layer, for example, a large portion of the alignment mark may be removed and its original height may not be maintained. Therefore, the alignment mark may not function properly due to the change in its height. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device having improved characteristics.

[0006] According to an embodiment, a semiconductor device is provided, comprising: a gate electrode structure arranged on a substrate; a capping structure covering the upper surface of the gate electrode structure, the capping structure comprising a capping pattern and a first etch stop pattern covering the lower surface and side walls of the capping pattern; an alignment mark arranged on the substrate, the alignment mark comprising an insulating material; and a filling structure arranged on the substrate, the filling structure covering the side walls of the alignment mark and comprising a first filling pattern, a second filling pattern covering the lower surface and side walls of the first filling pattern, and a second etch stop pattern covering the lower surface and side walls of the second filling pattern.

[0007] According to an embodiment, a semiconductor device is provided, comprising: a conductive structure disposed on a substrate; a capping structure covering an upper surface of the conductive structure, the capping structure comprising a capping pattern comprising silicon oxycarbide (SiOC) and a first etch stop pattern covering a lower surface and side walls of the capping pattern, the first etch stop pattern comprising a material having a first etch selectivity relative to the capping pattern; an alignment mark on the substrate, the alignment mark comprising a material having a second etch selectivity lower than the first etch selectivity relative to the capping pattern; and a filling structure disposed on the substrate, the filling structure covering a side wall of the alignment mark and comprising: a first filling pattern; a second filling pattern covering a lower surface and side walls of the first filling pattern, the second filling pattern comprising the same material as the capping pattern; and a second etch stop pattern covering a lower surface and side walls of the second filling pattern, the second etch stop pattern comprising the same material as the first etch stop pattern.

[0008] According to an embodiment, a semiconductor device is provided, comprising: an active area arranged on a substrate, the active area being defined by an isolation pattern that can be formed on the substrate; a gate electrode structure on the active area and the isolation pattern; a capping structure covering an upper surface of the gate electrode structure, the capping structure comprising a capping pattern including silicon oxycarbide (SiOC) and an etch stop pattern covering a lower surface and sidewalls of the capping pattern, the etch stop pattern comprising a material including silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN); and a source / drain layer on the active area adjacent to the gate electrode structure.

[0009] In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, the alignment mark may not be removed in a process such as CMP, so that the original height of the alignment mark may be maintained, and thus the semiconductor device may ensure components with original size and shape.

[0010] However, the embodiments may not be limited to the above-described effects, and may be variously extended without departing from the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 are plan views and cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Fig.21 , Fig. 22 , Fig.23 , Fig.24 and Fig.25 are plan views showing some stages in a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Hereinafter, a semiconductor device according to an embodiment of the present disclosure will be described more fully with reference to the accompanying drawings.

[0014] Figures 1 to 20 1 is a plan view and a cross-sectional view showing some stages in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Specifically, Figure 1 , Figure 4 , Figure 7 , Fig.10 and Fig.13 is a plan view, and Figures 2 to 3 , Figures 5 and 6 , Figures 8 to 9 , Figure 11 to Figure 12 and Figures 14 to 20 It is a cross-sectional view.

[0015] Figure 2 , Figure 8 , Fig.11 and Fig.14 are cross-sectional views taken along line AA′ of the corresponding plan view, Figure 3 , Figure 5 , Fig. 9 , Fig.12 and Figures 15 to 20 are cross-sectional views taken along line BB′ of the corresponding plan view, and Figure 6 It is a cross-sectional view taken along line CC′ of the corresponding plan view.

[0016] Reference Figures 1 to 3 , an upper portion of the substrate 100 including the first region I and the second region II may be partially etched to form an active fin 105. Therefore, the active fin 105 may protrude in a vertical direction substantially perpendicular to an upper surface of the substrate 100 and may include a material substantially the same as that of the substrate 100.

[0017] The substrate 100 may include semiconductor materials such as silicon, germanium, silicon germanium, etc. or III-V compounds such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0018] In an embodiment of the present disclosure, the first region I of the substrate 100 may be a chip region where a device is formed, and the second region II of the substrate 100 may be a dicing channel region surrounding the chip region. Alternatively, each of the first region I and the second region II of the substrate 100 may be a portion of the chip region where a device is formed.

[0019] In an embodiment of the present disclosure, the upper portion of the substrate 100 may be etched using a first etching mask to form active fins 105. The active fins 105 may extend in a first direction substantially parallel to the upper surface of the substrate 100, and a plurality of active fins 105 may be formed in a second direction substantially parallel to the upper surface of the substrate 100 and intersecting the first direction. In an embodiment of the present disclosure, the first direction and the second direction may be orthogonal to each other.

[0020] The first groove 110 may be formed between the active fins 105 in the second direction. That is, the active fins 105 may be spaced apart from each other by at least the width of the first groove 110 in the second direction.

[0021] The one or more active fins 105 may be etched for removal using a second etching mask. During the etching process, portions of the substrate 100 below the removed one or more active fins 105 may also be partially removed. In an embodiment of the present disclosure, one or more active fins 105 in the first region I of the substrate 100 and all active fins 105 in the second region II of the substrate 100 may be removed.

[0022] An isolation layer 120 may be formed on the substrate 100 to fill the first groove 110 and cover the remaining active fins 105, and an upper portion of the isolation layer may be removed to expose an upper portion of each active fin 105, so that an isolation pattern 120 may be formed to fill the gap between the fins 105 and to be formed above the first groove 110 on the first region I of the substrate 100 and to cover the second region II of the substrate 100.

[0023] The isolation layer may include an oxide, such as silicon oxide. In an embodiment of the present disclosure, an upper portion of the isolation layer may be removed by a chemical mechanical polishing (CMP) process and an etch-back process.

[0024] Due to the formation of the isolation pattern 120 , the active fin 105 may include a lower active pattern 105 b whose sidewall may be surrounded by the isolation pattern 120 and an upper active pattern 105 a protruding in a vertical direction from an upper surface of the isolation pattern 120 .

[0025] Reference Figures 4 to 6 , a dummy gate structure 160 may be formed on the active fin 105 and the isolation pattern 120 .

[0026] The dummy gate structure 160 may be formed by sequentially forming a dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer on the active fin 105 and the isolation pattern 120 , patterning the dummy gate mask layer to form a dummy gate mask 150 , and sequentially etching the dummy gate electrode layer and the dummy gate insulating layer using the dummy gate mask 150 .

[0027] Thus, a dummy gate structure 160 including the dummy gate insulating pattern 130 , the dummy gate electrode 140 , and the dummy gate mask 150 sequentially stacked on one another may be formed on the substrate 100 .

[0028] The dummy gate insulating layer may include an oxide, such as silicon oxide. The dummy gate electrode layer may include, for example, polysilicon. The dummy gate mask layer may include a nitride, such as silicon nitride.

[0029] The dummy gate insulating layer may be formed by, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. Alternatively, the dummy gate insulating layer may be formed on the upper active pattern 105a of the active fin 105 by a thermal oxidation process, in which case the dummy gate insulating layer may be formed only on the surface of the upper active pattern 105a. The dummy gate electrode layer and the dummy gate mask layer may also be formed by, for example, a CVD process, an ALD process, etc.

[0030] In an embodiment of the present disclosure, the dummy gate structure 160 may extend in the second direction in the first region I of the substrate 100 , and a plurality of dummy gate structures 160 may be formed in the first direction.

[0031] Reference Figures 7 to 9 A spacer layer may be formed on the active fin 105 and the isolation pattern 120 to cover the dummy gate structure 160, and the spacer layer may be anisotropically etched to form a gate spacer 170 on each of the opposite sidewalls of the dummy gate structure 160 in the first direction. A fin spacer 180 may also be formed on each of the opposite sidewalls of the upper active pattern 105a in the second direction.

[0032] The spacer layer may include a nitride, such as silicon nitride. In one embodiment, the spacer layer may have a stack structure including a nitride layer and an oxide layer.

[0033] An upper portion of the active fin 105 adjacent to the gate spacer 170 may be etched to form a second groove 190 .

[0034] Fig. 9It is shown that a portion of the upper active pattern 105a of the active fin 105 is etched to form the second groove 190, so that the lower surface of the second groove 190 is higher than the upper surface of the lower active pattern 105b, but it may not be limited thereto. That is, only the upper active pattern 105a may be etched to form the second groove 190, and the lower active pattern 105b may not be etched to form the second groove 190, so that the depth of the second groove 190 does not penetrate the lower active pattern 105b. Alternatively, a portion of the upper active pattern 105a and the lower active pattern 105b may be etched to form the second groove 190. Therefore, the lower surface of the second groove 190 may be lower than the height of the upper surface of the lower active pattern 105b on which the second groove 190 is not formed. In other words, the depth of the second groove 190 may penetrate the upper active pattern 105 a and enter the lower active pattern 105 b such that the depth of the second groove 190 is disposed below the top surface of the lower active pattern 105 b .

[0035] When forming the second groove 190 , the fin spacer 180 on each opposite sidewall of the upper active pattern 105 a may also be partially removed, so that a portion of the fin spacer 180 may remain, or the fin spacer 180 may be completely removed.

[0036] In an embodiment of the present disclosure, the etching process for forming the second groove 190 and the etching process for forming the gate spacer 170 and the fin spacer 180 may be performed in situ.

[0037] Reference Figures 10 to 12 , a source / drain layer 200 may be formed to fill the second groove 190 .

[0038] In an embodiment of the present disclosure, a selective epitaxial growth (SEG) process may be performed by using the surface of the active fin 105 exposed by the second groove 190 as a seed to form the source / drain layer 200 .

[0039] In an embodiment of the present disclosure, a SEG process may be performed using a silicon source gas, a germanium source gas, an etching gas, and a carrier gas, so a single crystal silicon germanium layer may be formed as the source / drain layer 200. The SEG process may also be performed using a P-type impurity source gas, so a single crystal silicon germanium layer doped with a P-type impurity may be formed as the source / drain layer 200.

[0040] Alternatively, the SEG process may be performed using a silicon source gas, a carbon source gas, an etching gas, and a carrier gas, so a single crystal silicon carbide layer may be formed as the source / drain layer 200. The SEG process may also be performed using an N-type impurity source gas, so a single crystal silicon carbide layer doped with N-type impurities may be formed as the source / drain layer 200. In some embodiments, the SEG process may be performed using a silicon source gas, an etching gas, and a carrier gas, so a single crystal silicon layer may be formed as the source / drain layer 200. The SEG process may also be performed using an N-type impurity source gas, so a single crystal silicon layer doped with N-type impurities may be formed as the source / drain layer 200.

[0041] The source / drain layer 200 may grow in vertical and horizontal directions to fill the second groove 190, and an upper portion of the source / drain layer 200 may contact a sidewall of the gate spacer 170. In an embodiment of the present disclosure, a cross section of the source / drain layer 200 taken along the second direction may have a shape similar to a pentagon.

[0042] In an embodiment of the present disclosure, when adjacent active fins 105 disposed in the second direction are close to each other, the source / drain layers 200 respectively grown on the adjacent active fins 105 may be merged with each other. Fig.11 It is shown that two source / drain layers 200 are grown on two adjacent active fins 105 , respectively, and the two source / drain layers 200 are merged to contact each other, but it is not limited thereto. Therefore, for example, more than two source / drain layers 200 may be merged with each other.

[0043] After forming a first interlayer insulating layer 210 covering the dummy gate structure 160, the gate spacer 170, the fin spacer 180, and the source / drain layer 200 to a sufficient height on the active fin 105 and the isolation pattern 120, the first interlayer insulating layer 210 may be planarized until the upper surface of the dummy gate electrode 140 may be exposed. During the planarization process, the dummy gate mask 150 may also be removed together with the first interlayer insulating layer 210.

[0044] The space between the merged source / drain layer 200 and the isolation pattern 120 may not be completely filled with the first interlayer insulating layer 210, and thus a gap or void 220 may be formed therein. Air may be disposed in the gap 220.

[0045] The first interlayer insulating layer 210 may include silicon oxide, such as Tosz (TOSZ). Alternatively, the first interlayer insulating layer 210 may include a low dielectric material having a dielectric constant less than that of silicon oxide (e.g., a dielectric constant of about 3.9). That is, the first interlayer insulating layer 210 may include an inorganic polymer, such as silicon oxide doped with fluorine or carbon, porous silicon oxide, spin-coated organic polymer, hydrogenated silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc. The first interlayer insulating layer 210 may have a structure in which a first layer including silicon oxide and a second layer including a low-k material are sequentially stacked. The planarization process may be performed by a CMP process and / or an etch-back process.

[0046] Reference Figures 13 to 15 The exposed dummy gate electrode 140 and the dummy gate insulation pattern 130 thereunder may be removed to form a first opening exposing the inner sidewalls of the gate spacer 170 and the surface of the active fin 105 , and a gate electrode structure 270 may be formed to fill the first opening.

[0047] In an embodiment of the present disclosure, the dummy gate electrode 140 and the dummy gate insulating pattern 130 thereunder may be removed by a dry etching process or a wet etching process, and the wet etching process may be performed using, for example, hydrogen fluoride (HF).

[0048] After performing a thermal oxidation process on the surface of the active fin 105 exposed through the first opening to form the interface pattern 230, a gate insulation layer and a work function control layer can be sequentially formed on the interface pattern 230, the isolation pattern 120, the gate spacer 170 and the first interlayer insulating layer 210, and a gate electrode layer can be formed on the work function control layer to fill the remaining portion of the first opening.

[0049] The work function control layer and the gate electrode layer may be formed by, for example, a CVD process, an ALD process, a physical vapor deposition (PVD) process, etc. The gate electrode layer may be further subjected to a thermal treatment process, such as a rapid thermal annealing (RTA) process, a spike RTA process, a flash RTA process, or a laser annealing process, etc.

[0050] Similar to the gate insulating layer or the gate electrode layer, the interface pattern 230 may be formed by a CVD process or an ALD process instead of a thermal oxidation process. In this case, the interface pattern 230 may be formed on the surface of the active fin 105, and may also be formed on the upper surface of the isolation pattern 120 on the first region I of the substrate 100 and the inner sidewall of the gate spacer 170. Alternatively, the interface pattern 230 may not be formed.

[0051] The gate electrode layer, the work function control layer and the gate insulation layer can be planarized until the upper surface of the first interlayer insulation layer 210 can be exposed to form a gate insulation pattern 240 and a work function control pattern 250 stacked sequentially on the upper surface of the interface pattern 230, the upper surface of the isolation pattern 120 and the inner side wall of the gate spacer 170, and a gate electrode 260 filling the remaining portion of the first opening can be formed on the work function control pattern 250.

[0052] The sequentially stacked interface pattern 230, gate insulation pattern 240, work function control pattern 250, and gate electrode 260 may form a gate electrode structure 270, and may form a transistor together with the source / drain layer 200. Depending on the conductivity type of the source / drain layer 200, the transistor may form a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor.

[0053] Reference Fig.16 , the upper portions of the gate electrode structure 270 and the gate spacer 170 may be removed to form the third groove 280, and the isolation pattern 120 on the second region II of the substrate 100 may be partially removed to form a second opening 285 exposing the upper surface of the isolation pattern 120. Alternatively, the isolation pattern 120 on the second region II of the substrate 100 may be removed to form the second opening 285 exposing the upper surface of the substrate 100, and this case will be referred to later. Fig.23 describe.

[0054] Thus, the alignment mark 215 may be formed on the second region II of the substrate 100 , ie, on a portion where the isolation pattern is not removed when the second opening 285 is formed.

[0055] In an embodiment of the present disclosure, the third groove 280 and the second opening 285 may be formed simultaneously by the same etching process (eg, dry etching process). Alternatively, the third groove 280 and the second opening 285 may be formed sequentially by different etching processes.

[0056] In an embodiment of the present disclosure, a first width W1 of the third groove 280 between the fin 105 and the first insulating layer 210 or the top surface of the fin 105 may be smaller than a second width W2 of the second opening 285 between the top surface of the alignment mark 215 and the top surface of the fin 105. That is, a first width W1 at the mouth of the third groove 280 may be smaller than a second width at the mouth of the second opening 285.

[0057] Reference Fig.17An etch stop layer 300 may be formed on the lower surface and sidewalls of the third groove 280 and the second opening 285 and on the upper surfaces of the first interlayer insulating layer 210 and the alignment mark 215 , and a first insulating layer 310 and a second insulating layer 320 may be sequentially stacked on the etch stop layer 300 .

[0058] In an embodiment of the present disclosure, an etch stop layer 300 may be conformally formed on the lower surface and side walls of the third groove 280 and the second opening 285, a first insulating layer 310 may be formed on the lower surface and side walls of the third groove 280 and the second opening 285 to fill the third groove 280 and partially fill the second opening 285, and a second insulating layer 320 may fill the remaining portion of the second opening 285.

[0059] The first insulating layer 310 may include a material having high insulation and a low etching rate, such as silicon oxycarbide (SiOC). Silicon oxycarbide (SiOC) is highly hydrophobic and therefore may not be easily polished in a subsequent polishing process. The first insulating layer 310 including silicon oxycarbide (SiOC) is not formed to a large thickness, so the first insulating layer 310 may not fill the entire portion of the second opening 285, but may partially fill the second opening 285 having a relatively large width.

[0060] The etch stop layer 300 may include a material having a high etch selectivity relative to the first insulating layer 310, for example, a nitride such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc. The second insulating layer 320 may include a material having a good gap filling property, for example, an oxide such as tetraethyl orthosilicate (TEOS).

[0061] Reference Fig.18 , the second insulating layer 320 and the first insulating layer 310 may be planarized. Therefore, a capping pattern 315 may be formed in the third groove 280 , and a first filling pattern 325 and a second filling pattern 317 covering a lower surface and sidewalls of the first filling pattern 325 may be formed in the second opening 285 .

[0062] In an embodiment of the present disclosure, the planarization process may include a CMP process, and the CMP process may be performed until the uppermost surface of the etch stop layer 300 may be exposed. The CMP process may be performed by using a portion of the etch stop layer 300 on the upper surfaces of the first interlayer insulating layer 210 and the alignment mark 215 as a polishing end point, and thus the alignment mark 215 may not be removed by the CMP process, and the original height of the alignment mark 215 may be maintained.

[0063] In the CMP process, the second opening 285 surrounding the alignment mark 215 may be filled with the etch stop layer 300 and the first and second insulating layers 310 and 320, and thus a relatively high pressure may not be applied to the second opening 285 compared to the first region I of the substrate 100. Therefore, the planarization process may be uniformly performed.

[0064] The slurry used in the planarization process may include an abrasive such as SiO x 、Al x O v 、Ce x O y etc., and the slurry may have a pH value, for example, in the range of about 2 to about 10.

[0065] Reference Fig.19 , the exposed portion of the etch stop layer 300 may be removed to form a first etch stop pattern 305 in the third groove 280 , and a second etch stop pattern 307 in the second opening 285 .

[0066] The exposed portion of the etch stop layer 300 may be removed by, for example, a wet etching process or a CMP process. The etch stop layer 300 may include, for example, nitride, and may have a high etching selectivity with respect to the alignment mark 215 including, for example, oxide. Therefore, the alignment mark 215 may not be removed during the removal of the exposed portion of the etch stop layer 300, and the original height of the alignment mark 215 may be maintained.

[0067] A first etch stop pattern 305 may be conformally formed on a lower surface and sidewalls of the third groove 280 that exposes the gate electrode structure 270 and the upper surfaces of the gate spacer 170 on the first region I of the substrate 100, and a capping pattern 315 may be formed on the first etch stop pattern 305 to fill the remaining portion of the third groove 280. The first etch stop pattern 305 and the capping pattern 315 may together form a capping structure 335. The gate electrode structure 270, the gate spacer 170, and the capping structure 335 may together form a gate structure.

[0068] The second etch stop pattern 307 may be conformally formed on the lower surface and sidewall of the second opening 285, the second opening 285 surrounds the alignment key 215 on the second region II of the substrate 100 and exposes the isolation pattern 120 or the upper surface of the substrate 100, the second filling pattern 317 may be formed on the second etch stop pattern 307, and the first filling pattern 325 filling the remaining portion of the second opening 285 may be formed on the second filling pattern 317. The second etch stop pattern 307, the first filling pattern 325, and the second filling pattern 317 may form a filling structure 340. Here, the terms "first" and "second" are merely to distinguish one element from another. For example, the second etch stop pattern 307 may be referred to as a first etch stop pattern, and the first etch stop pattern 305 may be referred to as a second etch stop pattern. Similarly, the first filling pattern 325 may be referred to as a second filling pattern, and the second filling pattern 317 may be referred to as a first filling pattern.

[0069] and Fig.18 and Fig.19 Unlike the process shown in , the second insulating layer 320 may be planarized until an upper surface of the first insulating layer 310 may be exposed, and upper portions of the first insulating layer 310 and the etch stop layer 300 may be removed.

[0070] Reference Fig. 20 After forming a second interlayer insulating layer 350 on the capping structure 335 , the first interlayer insulating layer 210 , the alignment mark 215 and the filling structure 340 , a first contact plug 380 may be formed through the second interlayer insulating layer 350 and the first interlayer insulating layer 210 to contact an upper surface of the source / drain layer 200 .

[0071] After forming the third interlayer insulating layer 390 on the first contact plug 380 and the second interlayer insulating layer 350 , a second contact plug 420 may be formed through the third interlayer insulating layer 390 , the second interlayer insulating layer 350 , and the capping structure 335 to contact an upper surface of the gate electrode structure 270 .

[0072] Specifically, a third opening may be formed through the second interlayer insulating layer 350 and the first interlayer insulating layer 210 to expose the upper surface of the source / drain layer 200, a first metal layer may be formed on the exposed source / drain layer 200, the sidewall of the third opening, and the upper surface of the second interlayer insulating layer 350, and a heat treatment process may be performed to form a metal silicide pattern 205 on the exposed source / drain layer 200. The first metal layer may include, for example, nickel, cobalt, titanium, etc., and thus the metal silicide pattern 205 may include, for example, nickel silicide, cobalt silicide, titanium silicide, etc.

[0073] After removing the unreacted portion of the first metal layer, a first barrier layer may be formed on the upper surface of the metal silicide pattern 205, the sidewall of the third opening, and the upper surface of the second interlayer insulating layer 350, a second metal layer may be formed on the first barrier layer to fill the remaining portion of the third opening, and the second metal layer and the first barrier layer may be planarized until the upper surface of the second interlayer insulating layer 350 may be exposed. Thus, a first barrier pattern 360 may be formed on the upper surface of the metal silicide pattern 205 and the sidewall of the third opening, and a second metal pattern 370 may be formed to fill the remaining portion of the third opening. The first barrier pattern 360 and the second metal pattern 370 may form a first contact plug 380 together.

[0074] After forming a fourth opening through the third interlayer insulating layer 390, the second interlayer insulating layer 350, and the capping structure 335 to expose the upper surface of the gate electrode structure 270, a second barrier layer may be formed on the upper surface of the gate electrode structure 270, the sidewall of the fourth opening, and the upper surface of the third interlayer insulating layer 390, a third metal layer may be formed on the second barrier layer to fill the remaining portion of the fourth opening, and the third metal layer and the second barrier layer may be planarized until the upper surface of the third interlayer insulating layer 390 may be exposed. Therefore, a second barrier pattern 400 may be formed on the upper surface of the gate electrode structure 270 and the sidewall of the fourth opening, and a third metal pattern 410 filling the remaining portion of the fourth opening may be formed on the second barrier pattern 400. The second barrier pattern 400 and the third metal pattern 410 may form a second contact plug 420 together.

[0075] The first and second barrier patterns 360 and 400 may include metal nitrides such as tantalum nitride, titanium nitride, or the like, and the second and third metal patterns 370 and 410 may include metals such as tungsten, copper, aluminum, or the like.

[0076] Through the above process, the manufacturing of the semiconductor device can be completed.

[0077] As described above, the width of the second opening 285 for forming the alignment mark 215 may be greater than the width of the third groove 280 for forming the capping pattern 315, the width of the third groove 280 may cover the gate electrode structure 270, and thus the capping pattern 315 formed by planarizing the first insulating layer 310 may completely fill the third groove 280, and the second filling pattern 317 formed by planarizing the first insulating layer 310 may not completely fill the second opening 285. However, in an embodiment of the present disclosure, a second insulating layer 320 filling the remaining portion of the second opening 285 may be further formed on the first insulating layer 310, so that the alignment mark 215 is not quickly polished due to the concentration of pressure on the alignment mark 215 during the CMP process.

[0078] In addition, an etch stop layer 300 having a high first etch selectivity relative to the first insulating layer 310 can be formed on the third groove 280 and the second opening 285, so that the alignment mark 215 having a second etch selectivity lower than the first etch selectivity relative to the first insulating layer 310 can not be polished and removed in the CMP process.

[0079] The embodiments herein may be applied not only to the gate electrode structure 270 , but also to any other type of conductive structure having a capping structure 335 thereon.

[0080] The semiconductor device may include a gate electrode structure 270 formed on a first region I of a substrate 100 including the first region I and the second region II, a capping structure 335 covering an upper surface of the gate electrode structure 270, an alignment mark 215 formed on the second region II of the substrate 100 and including an insulating material, and a filling structure 340 formed on the second region II of the substrate 100 and covering a sidewall of the alignment mark 215. The capping structure 335 may include a capping pattern 315, and a first etch stop pattern 305 covering a lower surface and a sidewall of the capping pattern 315, and the filling structure 340 may include a first filling pattern 325, a second filling pattern 317 covering a lower surface and a sidewall of the first filling pattern 325, and a second etch stop pattern 307 covering a lower surface and a sidewall of the second filling pattern 317.

[0081] In an embodiment of the present disclosure, the capping pattern 315 and the second filling pattern 317 may include the same material, such as silicon oxycarbide (SiOC), and the first etch stop pattern 305 and the second etch stop pattern 307 may include a material having a first etch selectivity relative to the capping pattern 315, such as silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN).

[0082] In an embodiment of the present disclosure, the alignment key 215 may include a material, such as oxide, having a second etch selectivity lower than the first etch selectivity with respect to the first insulating layer 310 , and the first filling pattern 325 may also include, for example, oxide.

[0083] In an embodiment of the present disclosure, the width of the filling structure 340 may be greater than the width of the capping structure 335 , and the lower surface of the filling structure 340 may be lower than the lower surface of the alignment key 215 .

[0084] Figure 21 to Figure 25 is a plan view showing some stages in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The method for manufacturing a semiconductor device includes Figures 1 to 20 The processes included in the method shown are basically the same or similar processes, so they are not described again here.

[0085] The semiconductor device may be a DRAM device, and a method of forming a gate structure of the DRAM device will be described below.

[0086] Reference Fig.21 , an upper portion of the substrate 500 including the first region I and the second region II may be etched to form a trench, and an isolation pattern 510 may be formed to fill the trench.

[0087] Thus, an active region 505 whose sidewalls may be surrounded by the isolation pattern 510 may be formed on the substrate 500 .

[0088] In an embodiment of the present disclosure, the first region I of the substrate 500 may be a chip region for forming a device, and the second region II of the substrate 500 may be a dicing channel region surrounding the chip region. Alternatively, each of the first region I and the second region II of the substrate 500 may be a portion of the chip region for forming a device.

[0089] Reference Fig. 22 , a gate electrode structure 540 may be formed through the active region 505 and an upper portion of the isolation pattern 510 .

[0090] The gate electrode structure 540 can be formed by forming a fourth groove extending through the upper portion of the active area 505 and the isolation pattern 510, forming a gate insulation layer on the inner sidewall of the fourth groove, the upper surface of the active area 505 and the upper surface of the isolation pattern 510, forming a gate electrode layer on the gate insulation layer to fill the fourth groove, and planarizing the gate electrode layer and the gate insulation layer until the upper surface of the active area 505 and the isolation pattern 510 can be exposed.

[0091] Thus, a gate electrode structure 540 including a gate insulation pattern 520 and a gate electrode 530 sequentially stacked may be formed in the fourth groove.

[0092] In an embodiment of the present disclosure, the gate electrode structure 540 may extend in a first direction, and a plurality of gate electrode structures 540 may be formed in a second direction crossing the first direction.

[0093] Reference Fig.23 , an upper portion of the gate electrode structure 540 may be removed to form a fifth groove 550 , and the isolation pattern 510 on the second region II of the substrate 500 may be partially removed to form a fifth opening 555 exposing the upper surface of the substrate 500 .

[0094] Thus, an alignment mark 515 may be formed on the second region II of the substrate 500 .

[0095] In an embodiment of the present disclosure, the fifth groove 550 and the fifth opening 555 may be formed simultaneously by the same etching process, such as a dry etching process. Alternatively, the fifth groove 550 and the fifth opening 555 may be formed sequentially by different etching processes.

[0096] In an embodiment of the present disclosure, the third width W3 at the mouth of the fifth groove 550 may be smaller than the fourth width W4 at the mouth of the fifth opening 555 .

[0097] refer to Fig.24 , can be executed with Fig.17 The process shown in is basically the same or similar process.

[0098] That is, an etch stop layer 560 may be formed on lower surfaces and sidewalls of the fifth groove 550 and the fifth opening 555 and upper surfaces of the active area 505 and the alignment mark 515 , and a first insulating layer 570 and a second insulating layer 580 may be sequentially stacked on the etch stop layer 560 .

[0099] In an embodiment of the present disclosure, an etch stop layer 560 may be conformally formed on the lower surface and side walls of the fifth groove 550 and the fifth opening 555, a first insulating layer 570 may be formed to fill the fifth groove 550 and partially fill the fifth opening 555 on the lower surface and side walls of the fifth opening 555, and a second insulating layer 580 may fill the remaining portion of the fifth opening 555.

[0100] The first insulating layer 570 may include a material having high insulation and a low etching rate such as silicon oxycarbide (SiOC), the etch stop layer 560 may include a material having a high etching selectivity relative to the first insulating layer 570, such as a nitride such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc., and the second insulating layer 580 may include a material having good gap filling properties, such as an oxide such as tetraethyl orthosilicate (TEOS).

[0101] refer to Fig.25 , can be executed with Figures 17 to 19 The process shown in is basically the same or similar process.

[0102] That is, the second insulating layer 580 and the first insulating layer 570 may be planarized. Thus, a capping pattern 575 may be formed in the fifth groove 550 , and a first filling pattern 585 and a second filling pattern 577 covering a lower surface and sidewalls of the first filling pattern 585 may be formed in the fifth opening 555 .

[0103] In an embodiment of the present disclosure, the planarization process may include a CMP process, and the CMP process may be performed until the uppermost surface of the etch stop layer 560 may be exposed. The CMP process may be performed by using a portion of the etch stop layer 560 on the upper surfaces of the active region 505 and the alignment mark 515 as a polishing endpoint, and thus the alignment mark 515 may not be removed by the CMP process, and the original height of the alignment mark 515 may be maintained.

[0104] In the CMP process, the fifth opening 555 surrounding the alignment mark 515 can be filled with the etching stop layer 560 and the first insulating layer 570 and the second insulating layer 580, so that no relatively high pressure is applied to the fifth opening 555 compared to the first region I of the substrate 500, and thus the planarization process can be performed uniformly.

[0105] The exposed portion of the etch stop layer 560 may be removed to form a first etch stop pattern 565 in the fifth groove 550 , and a second etch stop pattern 567 may be formed in the fifth opening 555 .

[0106] The exposed portion of the etch stop layer 560 may be removed by, for example, a wet etching process or a CMP process. The etch stop layer 560 may include, for example, nitride, and may have a high etching selectivity with respect to the alignment mark 515 including, for example, oxide. Therefore, the alignment mark 515 may not be removed during the removal of the exposed portion of the etch stop layer 560, and the original height of the alignment mark 515 may be maintained.

[0107] The first etch stop pattern 565 may be conformally formed on the lower surface and sidewalls of the fifth groove 550, the fifth groove 550 exposing the upper surface of the gate electrode structure 540 on the first region I of the substrate 500, and a capping pattern 575 filling the remaining portion of the fifth groove 550 may be formed on the first etch stop pattern 565. The first etch stop pattern 565 and the capping pattern 575 may together form a capping structure 595. The gate electrode structure 540 and the capping structure 595 may together form a gate structure 600.

[0108] The second etch stop pattern 567 may be conformally formed on the lower surface and sidewall of the fifth opening 555 that surrounds the alignment mark 515 on the second region II of the substrate 500 and exposes the upper surface of the substrate 500, a second filling pattern 577 may be formed on the second etch stop pattern 567, and a first filling pattern 585 filling a remaining portion of the fifth opening 555 may be formed on the second filling pattern 577. The second etch stop pattern 567, the first filling pattern 585, and the second filling pattern 577 may form a filling structure 610.

[0109] A bit line, a contact plug, a capacitor, etc. may be formed on the above structure using the alignment mark 515 with the original height maintained, to complete the manufacture of the semiconductor device.

[0110] The semiconductor device may include: an active area 505, which is defined on a first region I of a substrate 500 by an isolation pattern 510 formed on the substrate 500 including the first region I and the second region II; a gate electrode structure 540, extending through the upper portion of the active area 505 and the isolation pattern 510; a capping structure 595, covering the upper surface of the gate electrode structure 540; an alignment mark 515, which is formed on the second region II of the substrate 500 and includes an insulating material; and a filling structure 610, which is formed on the second region II of the substrate 100 and covers the sidewalls of the alignment mark 515.

[0111] In an embodiment of the present disclosure, the capping structure 595 may include a capping pattern 575, and a first etch stop pattern 565 covering the lower surface and side walls of the capping pattern 575, and the filling structure 610 may include a first filling pattern 585, a second filling pattern 577 covering the lower surface and side walls of the first filling pattern 585, and a second etch stop pattern 567 covering the lower surface and side walls of the second filling pattern 577.

[0112] The semiconductor device can be applied to various types of memory devices and systems including a capping layer that can cover the upper surface of the conductive pattern. For example, the semiconductor device can be applied to a logic device including a capping layer that can cover the upper surface of the conductive pattern, such as a central processing unit (CPU), a main processing unit (MPU) or an application processor (AP). In addition, the semiconductor device can be applied to a volatile memory device including a capping layer that can cover the upper surface of the conductive pattern, such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device, or a non-volatile memory device such as a flash memory device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, a resistive random access memory (RRAM) device, etc.

[0113] As noted above, although the disclosure has been described with reference to embodiments thereof, those skilled in the art will readily appreciate that many modifications are possible in the embodiments of the disclosure without materially departing from the novel teachings and advantages of the disclosure.

Claims

1. A semiconductor device, comprising: A gate electrode structure disposed on a substrate; A capping structure covering the upper surface of the gate electrode structure, the capping structure comprising: Covering pattern; and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern; An alignment mark disposed on the substrate, the alignment mark comprising an insulating material; and A filling structure is provided on the substrate, the filling structure covers the sidewall of the alignment mark, and the filling structure comprises: first fill pattern; a second filling pattern covering a lower surface and a side wall of the first filling pattern; and The second etch stop pattern covers the lower surface and sidewall of the second filling pattern.

2. The semiconductor device according to claim 1, wherein The capping pattern and the second filling pattern include the same material, and the first etch stop pattern and the second etch stop pattern include the same material.

3. The semiconductor device according to claim 2, wherein: The capping pattern and the second filling pattern include silicon oxycarbide, and the first etch stop pattern and the second etch stop pattern include silicon nitride, silicon oxynitride, or silicon carbonitride.

4. The semiconductor device according to claim 1, wherein: The alignment key and the first filling pattern include oxide.

5. The semiconductor device according to claim 1, wherein The width of the filling structure is greater than the width of the capping structure.

6. The semiconductor device according to claim 1, wherein A lower surface of the filling structure is lower than a lower surface of the alignment mark.

7. The semiconductor device according to claim 1, further comprising: a gate spacer covering the sidewalls of the gate electrode structure, Wherein, the capping structure covers the upper surface of the gate electrode structure and the upper surface of the gate spacer.

8. The semiconductor device according to claim 1, further comprising: A first contact plug extends through the capping structure to contact an upper surface of the gate electrode structure.

9. The semiconductor device according to claim 1, wherein: The gate electrode structure is formed on an active fin protruding from an upper surface of the substrate, and Wherein, the semiconductor device further comprises: a source / drain layer on the active fin adjacent to the gate electrode structure; and The second contact plug contacts the upper surface of the source / drain layer.

10. The semiconductor device according to claim 9, wherein The gate electrode structure includes an interface pattern, a gate insulation pattern, a work function control pattern, and a gate electrode sequentially stacked on a surface of the active fin.

11. A semiconductor device comprising: a conductive structure disposed on a substrate; A capping structure covering the upper surface of the conductive structure, the capping structure comprising: a capping pattern comprising silicon oxycarbide; and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, the first etch stop pattern comprising a material having a first etch selectivity with respect to the capping pattern; an alignment mark on the substrate, the alignment mark comprising a material having a second etch selectivity lower than the first etch selectivity with respect to the capping pattern; and A filling structure is provided on the substrate, the filling structure covers the sidewall of the alignment mark, and the filling structure comprises: first fill pattern; a second filling pattern covering a lower surface and sidewalls of the first filling pattern, the second filling pattern and the capping pattern comprising the same material; and A second etch stop pattern covers a lower surface and a sidewall of the second filling pattern, the first etch stop pattern and the second etch stop pattern comprising a same material.

12. The semiconductor device according to claim 11, wherein The first etch stop pattern and the second etch stop pattern include silicon nitride, silicon oxynitride, or silicon carbonitride.

13. The semiconductor device according to claim 11, wherein The alignment key and the first filling pattern include oxide.

14. The semiconductor device according to claim 11, wherein The width of the filling structure is greater than the width of the capping structure.

15. The semiconductor device according to claim 11, wherein A lower surface of the filling structure is lower than a lower surface of the alignment mark.

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