Light receiving element and ranging module

Abstract

The present invention provides a light-receiving element and a ranging module capable of improving performance. The light-receiving element comprises a light-receiving region and a separator. The light-receiving region includes a first voltage-applying portion to which a first voltage is applied; a first charge detection portion disposed around the first voltage-applying portion; a second voltage-applying portion to which a second voltage different from the first voltage is applied; and a second charge detection portion disposed around the second voltage-applying portion. The separator is disposed at the boundary between adjacent light-receiving regions to separate the light-receiving regions. The present invention is applicable to light-receiving elements.

Description

Technical Field

[0001] The present invention relates to a light receiving element and a distance measuring module, and in particular to a light receiving element and a distance measuring module capable of improving characteristics. Background Art

[0002] Distance measurement systems using indirect ToF (Time of Flight) are already known. These systems require sensors that can quickly distribute signal charges generated by receiving light reflected from an object using active light emitted by an LED (Light Emitting Diode) or laser at a specific phase, to different areas.

[0003] Therefore, a technique has been proposed that generates a current in a sensor substrate by directly applying a voltage to the substrate, thereby modulating a wide area within the substrate at high speed (see, for example, Patent Document 1). This type of sensor is also called a CAPD (Current Assisted Photonic Demodulator) sensor.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-86904

[0005] However, it is difficult to obtain a CAPD sensor with sufficient characteristics using the above-mentioned techniques.

[0006] For example, the above-mentioned CAPD sensor is a surface illumination type sensor in which wiring and the like are arranged on a surface of a substrate that receives light from the outside.

[0007] To ensure sufficient photoelectric conversion area, it's preferable to have no components, such as wiring, that would obstruct the optical path of incident light on the light-receiving side of the PD (photodiode), or photoelectric conversion unit. However, in surface-illuminated CAPD sensors, depending on their structure, charge extraction wiring, various control lines, and signal lines may have to be placed on the light-receiving side of the PD, limiting the photoelectric conversion area. This can result in insufficient photoelectric conversion area, and pixel sensitivity and other characteristics may be compromised.

[0008] Furthermore, when using CAPD sensors in locations exposed to external light, the external light component becomes a noise component for indirect ToF methods that use active light for distance measurement. Therefore, in order to obtain distance information with a sufficient signal-to-noise ratio (SN ratio), it is necessary to ensure a sufficient saturation signal (Qs). However, in surface-illuminated CAPD sensors, due to limitations in wiring layout, methods other than wiring capacitance, such as the provision of additional transistors, are necessary to ensure capacitance.

[0009] Furthermore, in surface-illuminated CAPD sensors, a signal extraction unit called a Tap is arranged on the side of the substrate where light is incident. On the other hand, when considering the photoelectric conversion within the Si substrate, although there are differences in the attenuation rate depending on the wavelength of the light, the proportion of photoelectric conversion caused on the light incident surface side is high. Therefore, in surface-type CAPD sensors, the probability of photoelectric conversion may become higher in the Inactive Tap area, which is the Tap area where no signal charge is distributed, among the Tap areas where the signal extraction unit is provided. In indirect ToF sensors, since distance measurement information is obtained using the signal distributed to each charge storage area according to the phase of the active light, the component that is directly photoelectrically converted in the Inactive Tap area becomes noise, resulting in the possibility of deterioration of distance measurement accuracy. In other words, the characteristics of the CAPD sensor may be degraded. Summary of the Invention

[0010] The present invention has been made in view of such circumstances, and an object of the present invention is to improve the characteristics.

[0011] A light receiving element according to a first aspect of the present invention includes:

[0012] Light receiving area, with:

[0013] A first voltage applying unit to which a first voltage is applied;

[0014] a first charge detection unit disposed around the first voltage applying unit;

[0015] a second voltage applying unit to which a second voltage different from the first voltage is applied; and

[0016] a second charge detection unit provided around the second voltage applying unit; and

[0017] a separation portion, the separation portion being arranged at a boundary between the adjacent light receiving areas to separate the light receiving areas;

[0018] The first voltage applying unit and the first charge detecting unit are shared by the light receiving region and another adjacent light receiving region at a boundary at one end of the light receiving region.

[0019] The second voltage applying section and the second charge detecting section are shared by the light receiving region and another adjacent light receiving region at a boundary of the other end of the light receiving region opposite to the one end.

[0020] In the first aspect of the present invention, the light receiving element is provided with:

[0021] Light receiving area, with:

[0022] A first voltage applying unit to which a first voltage is applied;

[0023] a first charge detection unit disposed around the first voltage applying unit;

[0024] a second voltage applying unit to which a second voltage different from the first voltage is applied; and

[0025] a second charge detection unit provided around the second voltage applying unit; and

[0026] a separation portion, the separation portion being arranged at a boundary between the adjacent light receiving areas to separate the light receiving areas;

[0027] The first voltage applying unit and the first charge detecting unit are shared by the light receiving region and another adjacent light receiving region at a boundary at one end of the light receiving region.

[0028] The second voltage applying section and the second charge detecting section are shared by the light receiving region and another adjacent light receiving region at a boundary of the other end of the light receiving region opposite to the one end.

[0029] The ranging module according to the second aspect of the present invention comprises:

[0030] Light receiving element;

[0031] a light source that emits light having a periodically varying brightness; and

[0032] The light emitting control unit controls the irradiation timing of the irradiation light.

[0033] The light receiving element comprises:

[0034] Light receiving area, with:

[0035] A first voltage applying unit to which a first voltage is applied;

[0036] a first charge detection unit disposed around the first voltage applying unit;

[0037] a second voltage applying unit to which a second voltage different from the first voltage is applied; and

[0038] a second charge detection unit provided around the second voltage applying unit; and

[0039] a separation portion, the separation portion being arranged at a boundary between the adjacent light receiving areas to separate the light receiving areas;

[0040] The first voltage applying unit and the first charge detecting unit are shared by the light receiving region and another adjacent light receiving region at a boundary at one end of the light receiving region.

[0041] The second voltage applying section and the second charge detecting section are shared by the light receiving region and another adjacent light receiving region at a boundary of the other end of the light receiving region opposite to the one end.

[0042] In a second aspect of the present invention, the ranging module includes:

[0043] Light receiving element;

[0044] a light source that emits light having a periodically varying brightness; and

[0045] The light emitting control unit controls the irradiation timing of the irradiation light.

[0046] The light receiving element comprises:

[0047] Light receiving area, with:

[0048] A first voltage applying unit to which a first voltage is applied;

[0049] a first charge detection unit disposed around the first voltage applying unit;

[0050] a second voltage applying unit to which a second voltage different from the first voltage is applied; and

[0051] a second charge detection unit provided around the second voltage applying unit; and

[0052] a separation portion, the separation portion being arranged at a boundary between the adjacent light receiving areas to separate the light receiving areas;

[0053] The first voltage applying unit and the first charge detecting unit are shared by the light receiving region and another adjacent light receiving region at a boundary at one end of the light receiving region.

[0054] The second voltage applying section and the second charge detecting section are shared by the light receiving region and another adjacent light receiving region at a boundary of the other end of the light receiving region opposite to the one end.

[0055] According to the first and second aspects of the present invention, the characteristics of the element can be improved.

[0056] In addition, the effects described here are not limitative, and any effect described in the present invention may be used. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 This is a block diagram showing a configuration example of a light-receiving element.

[0058] Figure 2 A diagram showing an example of a pixel structure.

[0059] Figure 3 This is a diagram showing a partial structural example of a signal extraction portion of a pixel.

[0060] Figure 4 This is a diagram explaining the improvement in sensitivity.

[0061] Figure 5 This is a diagram explaining the improvement in charge separation efficiency.

[0062] Figure 6 This is a diagram explaining the improvement in electron extraction efficiency.

[0063] Figure 7 This is a diagram explaining the moving speed of a signal carrier in the surface irradiation type.

[0064] Figure 8 This is a diagram explaining the moving speed of a signal carrier in a back-illuminated type.

[0065] Figure 9 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0066] Figure 10 This diagram explains the relationship between pixels and on-chip lenses.

[0067] Figure 11 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0068] Figure 12 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0069] Figure 13 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0070] Figure 14 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0071] Figure 15 This is a diagram showing another configuration example of a signal extraction portion of a pixel.

[0072] Figure 16 A diagram showing another structural example of a pixel.

[0073] Figure 17 A diagram showing another structural example of a pixel.

[0074] Figure 18 A diagram showing another structural example of a pixel.

[0075] Figure 19 A diagram showing another structural example of a pixel.

[0076] Figure 20 A diagram showing another structural example of a pixel.

[0077] Figure 21 A diagram showing another structural example of a pixel.

[0078] Figure 22 A diagram showing another structural example of a pixel.

[0079] Figure 23 A diagram showing another structural example of a pixel.

[0080] Figure 24 A diagram showing another structural example of a pixel.

[0081] Figure 25 A diagram showing another structural example of a pixel.

[0082] Figure 26 A diagram showing another structural example of a pixel.

[0083] Figure 27 A diagram showing another structural example of a pixel.

[0084] Figure 28 A diagram showing another structural example of a pixel.

[0085] Figure 29 A diagram showing another structural example of a pixel.

[0086] Figure 30 A diagram showing another structural example of a pixel.

[0087] Figure 31 is a diagram showing an equivalent circuit of a pixel.

[0088] Figure 32 is a diagram showing another equivalent circuit of a pixel.

[0089] Figure 33 This figure shows an example of the arrangement of voltage supply lines using a Periodic arrangement.

[0090] Figure 34 This figure shows an example of the arrangement of voltage supply lines using a mirror arrangement.

[0091] Figure 35 This figure explains the characteristics of the Periodic configuration and the Mirror configuration.

[0092] Figure 36 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0093] Figure 37 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0094] Figure 38 It is a cross-sectional view of a plurality of pixels in the ninth embodiment.

[0095] Figure 39 It is a cross-sectional view of a plurality of pixels in Modification 1 of the ninth embodiment.

[0096] Figure 40 It is a cross-sectional view of a plurality of pixels in the fifteenth embodiment.

[0097] Figure 41 It is a cross-sectional view of a plurality of pixels in the tenth embodiment.

[0098] Figure 42 This is a diagram illustrating five metal films of a multilayer wiring layer.

[0099] Figure 43 This is a diagram illustrating five metal films of a multilayer wiring layer.

[0100] Figure 44 This is a diagram illustrating a polysilicon layer.

[0101] Figure 45 It is a diagram showing a modified example of a reflective member formed on a metal film.

[0102] Figure 46 It is a diagram showing a modified example of a reflective member formed on a metal film.

[0103] Figure 47 This is a diagram illustrating the substrate structure of a light-receiving element.

[0104] Figure 48 is a cross-sectional view of multiple pixels.

[0105] Figure 49 is a diagram showing an equivalent circuit of a pixel.

[0106] Figure 50 This is a diagram for explaining the driving of the signal extraction unit.

[0107] Figure 51 is a cross-sectional view of multiple pixels.

[0108] Figure 52 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0109] Figure 53 is a cross-sectional view of multiple pixels.

[0110] Figure 54 This is a diagram for explaining the driving of the signal extraction unit.

[0111] Figure 55This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0112] Figure 56 is a cross-sectional view of multiple pixels.

[0113] Figure 57 This is a diagram for explaining the driving of the signal extraction unit.

[0114] Figure 58 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0115] Figure 59 is a cross-sectional view of multiple pixels.

[0116] Figure 60 is a cross-sectional view of multiple pixels.

[0117] Figure 61 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0118] Figure 62 is a cross-sectional view of multiple pixels.

[0119] Figure 63 is a cross-sectional view of multiple pixels.

[0120] Figure 64 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0121] Figure 65 is a cross-sectional view of multiple pixels.

[0122] Figure 66 is a cross-sectional view of multiple pixels.

[0123] Figure 67 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0124] Figure 68 is a cross-sectional view of multiple pixels.

[0125] Figure 69 is a cross-sectional view of multiple pixels.

[0126] Figure 70 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0127] Figure 71 is a cross-sectional view of multiple pixels.

[0128] Figure 72 is a cross-sectional view of multiple pixels.

[0129] Figure 73 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0130] Figure 74is a cross-sectional view of multiple pixels.

[0131] Figure 75 is a cross-sectional view of multiple pixels.

[0132] Figure 76 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0133] Figure 77 is a cross-sectional view of multiple pixels.

[0134] Figure 78 is a cross-sectional view of multiple pixels.

[0135] Figure 79 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0136] Figure 80 is a cross-sectional view of multiple pixels.

[0137] Figure 81 is a cross-sectional view of multiple pixels.

[0138] Figure 82 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0139] Figure 83 is a cross-sectional view of multiple pixels.

[0140] Figure 84 is a cross-sectional view of multiple pixels.

[0141] Figure 85 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0142] Figure 86 is a cross-sectional view of multiple pixels.

[0143] Figure 87 is a cross-sectional view of multiple pixels.

[0144] Figure 88 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0145] Figure 89 is a cross-sectional view of multiple pixels.

[0146] Figure 90 is a cross-sectional view of multiple pixels.

[0147] Figure 91 This is a diagram showing a pixel viewed from a direction perpendicular to the surface of the substrate.

[0148] Figure 92 is a cross-sectional view of multiple pixels.

[0149] Figure 93 is a cross-sectional view of multiple pixels.

[0150] Figure 94 This is a block diagram showing a configuration example of a distance measurement module.

[0151] Figure 95 This is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0152] Figure 96 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0153] Description of reference numerals:

[0154] 1: Light-receiving element; 20: Pixel array unit; 21: Tap driver unit; 22: Vertical driver unit; 51: Pixel; 61: Substrate; 62: On-chip lens; 66: Fixed charge film; 71-1, 71-2, 71: N+ semiconductor region; 73-1, 73-2, 73: P+ semiconductor region; 441-1, 441-2, 441: Isolation region; 471-1, 471-2, 471: Isolation region; 631: Reflection element; 721: Transfer transistor; 722: FD; 723: Reset transistor; 724: Amplifier transistor; 725: Select transistor; 727: Additional capacitor; 728: Switching transistor; 741: Voltage supply line; 811: Multi-layer wiring layer; 812: Interlayer insulating film; 813: Power supply line; 814: Voltage application wiring; 815: Reflective component; 816: Voltage application wiring; 817: Control line; M1 to M5: Metal films; 1001: Through-electrode; 1002: Insulating film; 1041: Transistor; 1101-1 to 1101-4, 1101: Inter-pixel light shielding portion; 1071: Transparent conductive film; 1161-1 to 1161-4, 1161: Contact; 1221: Pixel separation portion; 1254: Light receiving area; 1733: Oxide film; 5000: Distance measuring module; 5011: Light emitting portion; 5012: Light emitting control portion; 5013: Light receiving portion. DETAILED DESCRIPTION

[0155] Hereinafter, embodiments to which the present invention is applied will be described with reference to the drawings.

[0156] (First embodiment)

[0157] (Structural Example of Light Receiving Element)

[0158] The present invention makes it possible to improve characteristics such as pixel sensitivity by configuring the CAPD sensor as a back-illuminated type.

[0159] The present invention is also applicable to, for example, a light-receiving element constituting a distance-measuring system that measures distance using an indirect ToF method, an imaging device having such a light-receiving element, and the like.

[0160] For example, distance measurement systems can be applied to in-vehicle systems that are installed in a vehicle and measure the distance to an object located outside the vehicle, or to gesture recognition systems that measure the distance to an object such as a user's hand and recognize the user's gesture based on the measurement results. In this case, the results of gesture recognition can be used, for example, to operate a car navigation system.

[0161] Figure 1 This is a block diagram showing a configuration example of an embodiment of a light-receiving element to which the present technology is applied.

[0162] Figure 1 The light receiving element 1 shown is a back-illuminated CAPD sensor, and is provided in, for example, an imaging device having a distance measuring function.

[0163] The light-receiving element 1 includes a pixel array section 20 formed on a semiconductor substrate (not shown) and a peripheral circuit section integrated on the same semiconductor substrate as the pixel array section 20. The peripheral circuit section includes, for example, a tap driver 21, a vertical driver 22, a column processor 23, a horizontal driver 24, and a system controller 25.

[0164] The light receiving element 1 is further provided with a signal processing unit 31 and a data storage unit 32. The signal processing unit 31 and the data storage unit 32 may be mounted on the same substrate as the light receiving element 1 or may be arranged on a different substrate from the light receiving element 1 in the imaging device.

[0165] The pixel array unit 20 is configured such that pixels 51, which generate charges corresponding to the amount of received light and output signals corresponding to the charges, are arranged two-dimensionally in a matrix in row and column directions. Specifically, the pixel array unit 20 includes a plurality of pixels 51 that perform photoelectric conversion on incident light and output signals corresponding to the resulting charges. Here, the row direction refers to the horizontal direction in which the pixels 51 are arranged, and the column direction refers to the vertical direction in which the pixels 51 are arranged. In the figure, the row direction is horizontal, and the column direction is vertical.

[0166] Pixel 51 receives externally incident light, particularly infrared light, performs photoelectric conversion, and outputs a pixel signal corresponding to the resulting charge. Pixel 51 has a first tap TA, to which a predetermined voltage MIX0 (first voltage) is applied and detects the photoelectrically converted charge; and a second tap TB, to which a predetermined voltage MIX1 (second voltage) is applied and detects the photoelectrically converted charge.

[0167] The tap driving unit 21 supplies a predetermined voltage MIX0 to the first tap TA of each pixel 51 in the pixel array unit 20 via a predetermined voltage supply line 30, and supplies a predetermined voltage MIX1 to the second tap TB via the predetermined voltage supply line 30. Thus, two voltage supply lines 30 are arranged in one pixel column of the pixel array unit 20: a voltage supply line 30 for transmitting the voltage MIX0 and a voltage supply line 30 for transmitting the voltage MIX1.

[0168] In the pixel array unit 20, for the matrix-shaped pixel arrangement, pixel drive lines 28 are wired along the row direction for each pixel row, and two vertical signal lines 29 are wired along the column direction for each pixel column. For example, the pixel drive lines 28 transmit drive signals for driving when reading signals from the pixels. Figure 1 In FIG. 1 , the pixel drive line 28 is shown as one wiring line, but the number is not limited to one. One end of the pixel drive line 28 is connected to the output end corresponding to each row of the vertical drive unit 22 .

[0169] The vertical drive unit 22 is composed of a shift register, an address decoder, and the like, and drives all pixels of the pixel array unit 20 simultaneously or drives each pixel of the pixel array unit 20 in units of rows. In other words, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, constitutes a drive unit that controls the operation of each pixel of the pixel array unit 20.

[0170] The signals output from each pixel 51 in the pixel row in response to the drive control of the vertical drive unit 22 are input to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the pixel signals output from each pixel 51 via the vertical signal line 29 and temporarily holds the pixel signals after the signal processing.

[0171] Specifically, the column processing unit 23 performs noise removal processing, AD (Analog to Digital) conversion processing, and the like as signal processing.

[0172] The horizontal drive unit 24, which is composed of a shift register, an address decoder, etc., sequentially selects unit circuits corresponding to pixel columns of the column processing unit 23. Through the selection scanning of the horizontal drive unit 24, pixel signals processed for each unit circuit in the column processing unit 23 are sequentially output.

[0173] The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the driving of the tap driving unit 21, vertical driving unit 22, column processing unit 23, and horizontal driving unit 24 based on the various timing signals generated by the timing generator.

[0174] The signal processing unit 31 has at least a calculation processing function and performs various signal processing such as calculation processing based on the pixel signal output from the column processing unit 23. The data storage unit 32 temporarily stores data required for signal processing by the signal processing unit 31.

[0175] (Structural Example of Pixel)

[0176] Next, a configuration example of a pixel provided in the pixel array section 20 will be described. Figure 2 As shown.

[0177] Figure 2 FIG. 2 shows a cross section of one pixel 51 provided in the pixel array unit 20 . The pixel 51 receives light incident from the outside, particularly infrared light, performs photoelectric conversion, and outputs a signal corresponding to the resulting charge.

[0178] The pixel 51 includes a substrate 61 composed of a P-type semiconductor layer such as a silicon substrate, and an on-chip lens 62 formed on the substrate 61 .

[0179] For example, the thickness of the substrate 61 in the longitudinal direction of the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 61, is 20 μm or less. Of course, the thickness of the substrate 61 may be greater than 20 μm, and the thickness can be set according to the target characteristics of the light receiving element 1.

[0180] The substrate 61 is, for example, a high-resistance P-EPi substrate with a substrate concentration of 1E+13 or less, and the resistance (resistivity) of the substrate 61 is, for example, 500 [Ωcm] or more.

[0181] Here, regarding the relationship between the substrate concentration of the substrate 61 and the resistance, for example, when the substrate concentration is 6.48E+12 [cm 3 ], the resistance is 2000[Ωcm], and the substrate concentration is 1.30E+13[cm 3 ], the resistance is 1000[Ωcm], and the substrate concentration is 2.59E+13[cm 3 ] when the resistance is 500 [Ωcm] and the substrate concentration is 1.30E+14 [cm 3 ] when the resistance is 100 [Ωcm], etc.

[0182] exist Figure 2In the figure, the upper surface of substrate 61 is the back surface of substrate 61 and is the light incident surface of substrate 61 from outside. On the other hand, the lower surface of substrate 61 is the surface of substrate 61 and forms a multilayer wiring layer (not shown). A fixed charge film 66 composed of a single layer film or a stacked film with a positive fixed charge is formed on the light incident surface of substrate 61. On the upper surface of fixed charge film 66, an on-chip lens 62 is formed to focus light incident from outside and allow it to enter substrate 61. Fixed charge film 66 puts the light incident surface side of substrate 61 into a hole accumulation state, thereby suppressing the generation of dark current.

[0183] Furthermore, in the pixel 51, an inter-pixel light shielding film 63-1 and an inter-pixel light shielding film 63-2 are formed at the end portions of the pixel 51 on the fixed charge film 66 to prevent crosstalk between adjacent pixels. Hereinafter, when there is no need to specifically distinguish between the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2, they are simply referred to as the inter-pixel light shielding film 63.

[0184] In this example, light from the outside enters the substrate 61 via the on-chip lens 62, and the inter-pixel light-shielding film 63 is formed to prevent the light from entering the region of other pixels adjacent to the pixel 51 in the substrate 61. In other words, light from the outside that enters the on-chip lens 62 and travels toward the other pixels adjacent to the pixel 51 is shielded by the inter-pixel light-shielding film 63-1 and the inter-pixel light-shielding film 63-2, thereby preventing it from entering the other adjacent pixels.

[0185] Since the light-receiving element 1 is a back-illuminated CAPD sensor, the light incident surface of the substrate 61 is the so-called back surface, and no wiring layer consisting of wiring, etc., is formed on this back surface. In addition, a wiring layer is formed by laminating the portion of the surface of the substrate 61 opposite to the light incident surface. This wiring layer includes wiring for driving transistors formed in the pixels 51 and wiring for reading signals from the pixels 51.

[0186] On the side of the substrate 61 opposite to the light incident surface, that is, on the inner side of the lower surface in the figure, an oxide film 64, a signal extraction portion 65-1, and a signal extraction portion 65-2 are formed. The signal extraction portion 65-1 corresponds to Figure 1 The first tap TA described in the above description is equivalent to the signal extraction unit 65-2. Figure 1 The second tap TB is described in .

[0187] In this example, an oxide film 64 is formed in the center of the pixel 51 near the surface of the substrate 61 opposite to the light incident surface. A signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed at both ends of the oxide film 64 .

[0188] Here, the signal extraction portion 65-1 includes an N+ semiconductor region 71-1, which is an N-type semiconductor region, and an N- semiconductor region 72-1 having a lower donor impurity concentration than the N+ semiconductor region 71-1; a P+ semiconductor region 73-1, which is a P-type semiconductor region, and a P- semiconductor region 74-1 having a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Examples of donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) and arsenic (As), which are relative to Si. Examples of acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B), which are relative to Si. Elements that serve as donor impurities are called donor elements, and elements that serve as acceptor impurities are called acceptor elements.

[0189] exist Figure 2 In the embodiment, an N+ semiconductor region 71-1 is formed on the inner side of the surface of the substrate 61 opposite to the light incident surface, adjacent to the right side of the oxide film 64. Furthermore, an N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure so as to cover (surround) the N+ semiconductor region 71-1.

[0190] Furthermore, a P+ semiconductor region 73-1 is formed on the right side of the N+ semiconductor region 71-1. Furthermore, a P- semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 in the figure so as to cover (surround) the P+ semiconductor region 73-1.

[0191] Furthermore, an N+ semiconductor region 71-1 is formed on the right side of the P+ semiconductor region 73-1. Also, an N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure so as to cover (surround) the N+ semiconductor region 71-1.

[0192] Similarly, the signal extraction portion 65-2 has: an N+ semiconductor region 71-2 which is an N-type semiconductor region and an N- semiconductor region 72-2 whose donor impurity concentration is lower than that of the N+ semiconductor region 71-2; and a P- semiconductor region 73-2 which is a P-type semiconductor region and a P- semiconductor region 74-2 whose acceptor impurity concentration is lower than that of the P+ semiconductor region 73-2.

[0193] exist Figure 2 In the embodiment, an N+ semiconductor region 71-2 is formed on the inner side of the surface of the substrate 61 opposite to the light incident surface, adjacent to the left side of the oxide film 64. Furthermore, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the figure so as to cover (surround) the N+ semiconductor region 71-2.

[0194] Furthermore, a P+ semiconductor region 73-2 is formed on the left side of the N+ semiconductor region 71-2. Furthermore, a P- semiconductor region 74-2 is formed above the P+ semiconductor region 73-2 in the figure so as to cover (surround) the P+ semiconductor region 73-2.

[0195] Furthermore, an N+ semiconductor region 71-2 is formed on the left side of the P+ semiconductor region 73-2. Also, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the figure so as to cover (surround) the N+ semiconductor region 71-2.

[0196] On the inner portion of the surface of the substrate 61 opposite to the light incident surface, at the end portion of the pixel 51 , an oxide film 64 having the same structure as that of the center portion of the pixel 51 is formed.

[0197] Hereinafter, when there is no need to particularly distinguish between the signal extraction unit 65 - 1 and the signal extraction unit 65 - 2 , they are also simply referred to as the signal extraction unit 65 .

[0198] In addition, hereinafter, when there is no need to distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, they are also simply referred to as the N+ semiconductor region 71, and when there is no need to distinguish between the N- semiconductor region 72-1 and the N- semiconductor region 72-2, they are also simply referred to as the N- semiconductor region 72.

[0199] Furthermore, hereinafter, when there is no need to distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, they are also referred to as the P+ semiconductor region 73, and when there is no need to distinguish between the P- semiconductor region 74-1 and the P- semiconductor region 74-2, they are also referred to as the P- semiconductor region 74.

[0200] Furthermore, in substrate 61, a separating portion 75-1 is formed by an oxide film or the like between N+ semiconductor region 71-1 and P+ semiconductor region 73-1 to separate these regions. Similarly, a separating portion 75-2 is formed by an oxide film or the like between N+ semiconductor region 71-2 and P+ semiconductor region 73-2 to separate these regions. Hereinafter, when there is no need to specifically distinguish between separating portion 75-1 and separating portion 75-2, they will be simply referred to as separating portion 75.

[0201] The N+ semiconductor region 71 provided on the substrate 61 functions as a charge detection unit for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carrier generated by photoelectric conversion based on the substrate 61. In addition to the N+ semiconductor region 71, an N- semiconductor region 72 having a low donor impurity concentration is also included, which can be understood as a charge detection unit. Furthermore, the P+ semiconductor region 73 functions as a voltage application unit for injecting a large amount of carrier current into the substrate 61, that is, directly applying a voltage to the substrate 61 to generate an electric field within the substrate 61. In addition, in addition to the P+ semiconductor region 73, a P- semiconductor region 74 having a low acceptor impurity concentration is also included, which can be understood as a voltage application unit.

[0202] In the pixel 51 , a floating diffusion region FD (Floating Diffusion) portion (hereinafter particularly also referred to as FD portion A) not shown is directly connected to the N+ semiconductor region 71 - 1 . The FD portion A is further connected to the vertical signal line 29 via an amplifier transistor not shown.

[0203] Similarly, another FD portion (hereinafter, particularly also referred to as FD portion B) different from FD portion A is directly connected to N+ semiconductor region 71-2. FD portion B is further connected to vertical signal line 29 via an amplifier transistor (not shown), etc. Here, FD portion A and FD portion B are connected to different vertical signal lines 29.

[0204] For example, to measure the distance to an object using an indirect ToF method, an imaging device equipped with a light-receiving element 1 emits infrared light toward the object. When this infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 61 of the light-receiving element 1 receives the incident reflected light (infrared light) and performs photoelectric conversion. The tap driver 21 drives the first tap TA and second tap TB of the pixel 51, distributing a signal corresponding to the charge DET obtained through photoelectric conversion to the FD section A and FD section B.

[0205] For example, at a certain moment, the tap driving unit 21 applies voltage to the two P+ semiconductor regions 73 via contacts, etc. Specifically, for example, the tap driving unit 21 applies a voltage of MIX0 = 1.5V to the P+ semiconductor region 73-1 serving as the first tap TA, and applies a voltage of MIX1 = 0V to the P+ semiconductor region 73-2 serving as the second tap TB.

[0206] Then, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move toward the P+ semiconductor region 73-2, and electrons move toward the P+ semiconductor region 73-1.

[0207] Therefore, in this state, infrared light (reflected light) from the outside is incident on the substrate 61 through the on-chip lens 62. When the infrared light is photoelectrically converted into pairs of electrons and holes in the substrate 61, the resulting electrons are guided toward the P+ semiconductor region 73-1 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-1.

[0208] In this case, electrons generated by photoelectric conversion are used as a signal carrier for detecting a signal corresponding to the amount of infrared light incident on the pixel 51 , that is, the amount of infrared light received.

[0209] Thus, charges corresponding to the electrons moving into the N+ semiconductor region 71 - 1 are accumulated in the N+ semiconductor region 71 - 1 , and the charges are detected by the column processing unit 23 via the FD unit A, the amplifier transistor, the vertical signal line 29 , and the like.

[0210] That is, the accumulated charge DET0 in the N+ semiconductor region 71-1 is transferred to the FD portion A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge DET0 transferred to the FD portion A is read out by the column processing section 23 via the amplifier transistor and the vertical signal line 29. The column processing section 23 then performs processing such as A / D conversion on the readout signal, and the resulting pixel signal is supplied to the signal processing section 31.

[0211] This pixel signal represents the amount of charge corresponding to the electrons detected in the N+ semiconductor region 71 - 1 , that is, the amount of charge DET0 accumulated in the FD portion A. In other words, the pixel signal represents the amount of infrared light received by the pixel 51 .

[0212] In this case, similarly to the case of the N+ semiconductor region 71-1, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-2 may also be appropriately used for distance measurement.

[0213] Furthermore, at the next moment, a voltage is applied to the two P+ semiconductor regions 73 via contacts or the like by the tap driving unit 21 so as to generate an electric field in the opposite direction to the electric field generated so far in the substrate 61. Specifically, for example, a voltage of MIX0 = 0 V is applied to the P+ semiconductor region 73-1 serving as the first tap TA, and a voltage of MIX1 = 1.5 V is applied to the P+ semiconductor region 73-2 serving as the second tap TB.

[0214] As a result, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61 , and current flows from the P+ semiconductor region 73 - 2 to the P+ semiconductor region 73 - 1 .

[0215] In this state, infrared light (reflected light) from the outside is incident on the substrate 61 through the on-chip lens 62. When the infrared light is photoelectrically converted into pairs of electrons and holes in the substrate 61, the resulting electrons are guided toward the P+ semiconductor region 73-2 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-2.

[0216] Thus, charges corresponding to the electrons moving into the N+ semiconductor region 71 - 2 are accumulated in the N+ semiconductor region 71 - 2 , and the charges are detected by the column processing unit 23 via the FD unit B, the amplifier transistor, the vertical signal line 29 , and the like.

[0217] That is, the accumulated charge DET1 in the N+ semiconductor region 71-2 is transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charge DET1 transferred to the FD portion B is read out by the column processing section 23 via the amplifier transistor and the vertical signal line 29. The column processing section 23 then performs processing such as A / D conversion on the readout signal, and the resulting pixel signal is supplied to the signal processing section 31.

[0218] In this case, similarly to the case of the N+ semiconductor region 71-2, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-1 may also be appropriately used for distance measurement.

[0219] In this way, when pixel signals obtained by photoelectric conversion in different periods are obtained in the same pixel 51 , the signal processing unit 31 calculates distance information indicating the distance to the object based on these pixel signals and outputs the calculated distance information to the subsequent stage.

[0220] This method of allocating signal carriers to different N+ semiconductor regions 71 and calculating distance information based on signals corresponding to these signal carriers is called an indirect ToF method.

[0221] When Figure 2When the signal extraction portion 65 in the pixel 51 is observed from the top to the bottom, that is, from the direction perpendicular to the substrate 61, for example, Figure 3 As shown in FIG. 1 , a structure is formed in which the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71. Figure 3 In, with Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0222] exist Figure 3 In the example shown in FIG, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly closer to the end side from the center of the pixel 51. In particular, two signal extraction portions 65 are formed in the pixel 51.

[0223] Furthermore, a rectangular P+ semiconductor region 73 is formed at the center of each signal extraction portion 65. With this P+ semiconductor region 73 as the center, the P+ semiconductor region 73 is surrounded by a rectangular, more specifically, rectangular frame-shaped N+ semiconductor region 71. In other words, the N+ semiconductor region 71 is formed to surround the P+ semiconductor region 73.

[0224] Furthermore, in the pixel 51, an on-chip lens 62 is formed so as to focus infrared light incident from the outside on the center portion of the pixel 51, that is, the portion indicated by the arrow A11. In other words, the infrared light incident from the outside on the on-chip lens 62 is focused by the on-chip lens 62 on the position indicated by the arrow A11, that is, Figure 2 The oxide film 64 Figure 2 Upper middle position.

[0225] Therefore, infrared light is focused between the signal extraction section 65 - 1 and the signal extraction section 65 - 2 , thereby preventing infrared light from entering adjacent pixels 51 and causing crosstalk, and preventing infrared light from directly entering the signal extraction section 65 .

[0226] For example, if infrared light directly enters the signal extraction unit 65 , the charge separation efficiency, ie, Cmod (Contrast between active and inactive tap) and Modulation contrast will decrease.

[0227] Here, the signal extraction section 65 that reads out a signal corresponding to the charge DET obtained by photoelectric conversion, that is, the signal extraction section 65 that should detect the charge DET obtained by photoelectric conversion, is also called an active tap.

[0228] On the contrary, the signal extraction section 65 that does not basically read out a signal corresponding to the charge DET obtained by photoelectric conversion, that is, the signal extraction section 65 that is not an active tap, is also called an inactive tap.

[0229] In the above example, the signal extraction section 65 that applies a voltage of 1.5 V to the P+ semiconductor region 73 is an active tap, and the signal extraction section 65 that applies a voltage of 0 V to the P+ semiconductor region 73 is a passive tap.

[0230] Cmod is calculated using the following equation (1). Cmod represents the percentage of charge generated by photoelectric conversion of incident infrared light that can be detected in the N+ semiconductor region 71 of the signal extraction unit 65, which serves as the active tap. In other words, it is an indicator of whether a signal corresponding to the charge can be extracted, and represents the charge separation efficiency. In equation (1), I0 is the signal detected by one of the two charge detection units (P+ semiconductor region 73), and I1 is the signal detected by the other.

[0231] Cmod={|I0-I1| / (I0+I1)}×100· · · (1)

[0232] Therefore, for example, when infrared light incident from the outside enters the passive tap region and undergoes photoelectric conversion within the passive tap, there is a high probability that the signal carriers, i.e., electrons, generated by the photoelectric conversion will move to the N+ semiconductor region 71 within the passive tap. Consequently, the charges of some of the electrons obtained by the photoelectric conversion cannot be detected in the N+ semiconductor region 71 within the active tap, and Cmod, i.e., the charge separation efficiency, decreases.

[0233] Therefore, in pixel 51, by focusing infrared light near the center of pixel 51, located approximately equidistant from the two signal extraction units 65, the probability of externally incident infrared light being photoelectrically converted in the passive tap region can be reduced, thereby improving charge separation efficiency. Furthermore, in pixel 51, modulation contrast can also be improved. In other words, electrons obtained through photoelectric conversion can be easily guided to N+ semiconductor region 71 within the active tap.

[0234] According to the light receiving element 1 as described above, the following effects can be obtained.

[0235] Specifically, first, since the light receiving element 1 is a back-illuminated type, quantum efficiency (QE)×aperture ratio (FF (Fill Factor)) can be maximized, and the distance measurement characteristics of the light receiving element 1 can be improved.

[0236] For example, Figure 4As shown by arrow W11 , a typical surface illumination type image sensor is formed such that wiring 102 and wiring 103 are formed on the light incident surface side of PD 101 as a photoelectric conversion unit, on which light from the outside is incident.

[0237] Therefore, for example, part of light that is incident from the outside at a certain angle to the PD 101 as indicated by arrows A21 and A22 is blocked by the wiring 102 and the wiring 103 and does not enter the PD 101 .

[0238] In contrast, a back-illuminated image sensor has wirings 105 and 106 formed on a surface of a PD 104 serving as a photoelectric conversion unit opposite to a light incident surface where light from outside is incident, as indicated by arrow W12 .

[0239] Therefore, compared to surface-illuminated systems, a sufficient aperture ratio can be ensured. Specifically, light incident from the outside at a certain angle to PD 104, as indicated by arrows A23 and A24, can enter PD 104 without being blocked by wiring. This allows for greater light reception, improving pixel sensitivity.

[0240] The effect of improving pixel sensitivity by adopting such a back-illuminated type can also be obtained in the light-receiving element 1 of the back-illuminated CAPD sensor.

[0241] Furthermore, in a surface-illuminated CAPD sensor, for example, as indicated by arrow W13, a signal extraction unit 112, called a tap, is formed on the light incident surface side of the PD 111, which serves as a photoelectric converter. More specifically, a P+ semiconductor region and an N+ semiconductor region are formed as the tap. Furthermore, the surface-illuminated CAPD sensor is configured such that wiring 113, contacts connected to the signal extraction unit 112, and wiring 114, such as metal, are formed on the light incident surface side.

[0242] Therefore, for example, not only is a portion of light incident from the outside at a certain angle relative to PD111 as shown by arrows A25 and A26 blocked by wiring 113 and the like and does not enter PD111, but light incident perpendicularly to PD111 as shown by arrow A27 is also blocked by wiring 114 and does not enter PD111.

[0243] In contrast, a back-illuminated CAPD sensor is configured such that, for example, as indicated by arrow W14, a signal extraction unit 116 is formed on the surface of the photoelectric converter PD 115 opposite to the light incident surface where light from the outside is incident. Furthermore, wiring 117, contacts connected to the signal extraction unit 116, and wiring 118 such as metal are formed on the surface of the PD 115 opposite to the light incident surface.

[0244] Here, PD115 and Figure 2 The signal taking-out portion 116 corresponds to the substrate 61 shown in FIG. Figure 2 The signal extraction unit 65 shown corresponds to this.

[0245] In a back-illuminated CAPD sensor of this structure, a sufficient aperture ratio can be ensured compared to a front-illuminated CAPD sensor, thereby maximizing quantum efficiency (QE) × aperture ratio (FF) and improving ranging characteristics.

[0246] That is, for example, light incident from the outside at a certain angle to PD 115 as indicated by arrows A28 and A29 enters PD 115 without being blocked by wiring. Similarly, light incident perpendicularly to PD 115 as indicated by arrow A30 enters PD 115 without being blocked by wiring or the like.

[0247] In this way, back-illuminated CAPD sensors can receive not only light incident at a certain angle, but also light incident perpendicularly to the PD 115, which, in front-illuminated sensors, is reflected by wiring connected to the signal extraction unit (tap). This allows for greater light reception and improves pixel sensitivity. In other words, it maximizes quantum efficiency (QE) x aperture ratio (FF), resulting in improved ranging characteristics.

[0248] In particular, when the tap is arranged near the center of the pixel instead of at the outer edge of the pixel, a sufficient aperture ratio cannot be ensured in the surface-illuminated CAPD sensor, resulting in a decrease in the sensitivity of the pixel. However, in the light-receiving element 1 of the back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured regardless of the arrangement position of the tap, thereby improving the sensitivity of the pixel.

[0249] Furthermore, in the back-illuminated light-receiving element 1, since the signal extraction portion 65 is formed near the surface of the substrate 61 opposite to the light incident surface where infrared light from the outside is incident, the occurrence of photoelectric conversion of infrared light in the passive tap region can be reduced. This can improve Cmod, or charge separation efficiency.

[0250] Figure 5 Pixel cross-sectional views showing front-illuminated and back-illuminated CAPD sensors.

[0251] exist Figure 5 In the surface-illuminated CAPD sensor on the left, in the figure, the upper side of the substrate 141 is the light incident surface, and a wiring layer 152 including multiple layers of wiring, an inter-pixel light shielding portion 153, and an on-chip lens 154 are stacked on the light incident surface side of the substrate 141.

[0252] exist Figure 5 In the back-illuminated CAPD sensor on the right, a wiring layer 152 including multiple layers of wiring is formed on the lower side of the substrate 142 on the opposite side of the light incident surface in the figure, and an inter-pixel shading portion 153 and an on-chip lens 154 are stacked on the upper side of the substrate 142 on the light incident surface side.

[0253] In addition, Figure 5 The medium gray trapezoidal shape indicates a region where infrared light is collected by the on-chip lens 154 and the light intensity is high.

[0254] For example, in a surface-illuminated CAPD sensor, a region R11 containing an inactive tap and an active tap exists on the light-incident side of substrate 141. Therefore, a large portion of light directly enters the inactive tap, and if photoelectric conversion occurs in the inactive tap, the signal carrier generated by this photoelectric conversion cannot be detected in the N+ semiconductor region of the active tap.

[0255] In surface-illuminated CAPD sensors, the intensity of infrared light is high in region R11 near the light incident surface of substrate 141, increasing the probability of photoelectric conversion of infrared light within region R11. This increases the amount of infrared light incident near the passive tap, increasing the number of signal carriers that cannot be detected by the active tap, reducing charge separation efficiency.

[0256] In contrast, in a back-illuminated CAPD sensor, a region R12 where passive taps and active taps exist is located at a position of the substrate 142 away from the light incident surface, that is, near the surface opposite to the light incident surface. Figure 2 The substrate 61 shown corresponds.

[0257] In this example, since the region R12 is provided on the surface of the substrate 142 opposite to the light incident surface and the region R12 is located away from the light incident surface, the intensity of the incident infrared light is relatively weak near the region R12 .

[0258] The signal carrier obtained by photoelectric conversion in an area with strong infrared light intensity, such as near the center of the substrate 142 or near the light incident surface, is guided to the active tap by the electric field generated in the substrate 142 and detected in the N+ semiconductor area of the active tap.

[0259] On the other hand, near region R12, which includes the passive tap, the intensity of incident infrared light is relatively weak, so the probability of photoelectric conversion of infrared light within region R12 is reduced. Specifically, because the amount of infrared light incident near the passive tap is small, the number of signal carriers (electrons) generated near the passive tap through photoelectric conversion and moving toward the passive tap's N+ semiconductor region is reduced, thereby improving charge separation efficiency. Consequently, ranging characteristics can be improved.

[0260] Furthermore, in the back-illuminated light-receiving element 1 , since the substrate 61 can be made thinner, the extraction efficiency of electrons (charges) as signal carriers can be improved.

[0261] For example, in a surface irradiation type CAPD sensor, since the aperture ratio cannot be sufficiently ensured, Figure 6 As shown by arrow W31 , in order to ensure higher quantum efficiency and suppress the decrease in quantum efficiency×aperture ratio, the substrate 171 needs to be thickened to a certain extent.

[0262] As a result, in the region near the surface opposite to the light incident surface within the substrate 171, such as the region R21, the potential slope becomes gentle, and the electric field in the direction perpendicular to the substrate 171 becomes weak. In this case, the movement speed of the signal carrier slows down, and therefore, the time required from photoelectric conversion to detection of the signal carrier in the N+ semiconductor region of the active tap becomes longer. In addition, Figure 6 , the arrows in the substrate 171 represent the electric field in the substrate 171 in a direction perpendicular to the substrate 171 .

[0263] Furthermore, when the substrate 171 is thick, the distance that the signal carrier travels from a position in the substrate 171 away from the active tap to the N+ semiconductor region in the active tap becomes longer. Consequently, the time required from photoelectric conversion at a position away from the active tap to detection of the signal carrier in the N+ semiconductor region of the active tap further increases.

[0264] Figure 7 The relationship between the position in the thickness direction of the substrate 171 and the moving speed of the signal carrier is shown. The region R21 corresponds to the diffusion current region.

[0265] Thus, when substrate 171 becomes thicker, for example, when the driving frequency is high, that is, when the tap (signal extraction unit) switches between active and passive states at high speed, electrons generated in locations far from the active tap, such as region R21, cannot be fully introduced into the N+ semiconductor region of the active tap. In other words, if the tap is active for a short time, electrons (charges) generated in regions such as region R21 may not be detected by the N+ semiconductor region of the active tap, resulting in reduced electron extraction efficiency.

[0266] In contrast, in a back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured, so that, for example, Figure 6 As shown by the arrow W32, even if the substrate 172 is thinned, sufficient quantum efficiency × aperture ratio can be ensured. Figure 2 The arrows in the substrate 172 correspond to the substrate 61 , and the electric field in the direction perpendicular to the substrate 172 is represented.

[0267] Figure 8 The relationship between the position in the thickness direction of the substrate 172 and the moving speed of the signal carrier is shown.

[0268] As the thickness of substrate 172 is reduced in a direction perpendicular to substrate 172, the electric field perpendicular to substrate 172 becomes stronger, effectively utilizing only the electrons (charges) in the drift current region, where the signal carrier moves quickly, and not the electrons in the diffusion current region, where the signal carrier moves slowly. By utilizing only the electrons (charges) in the drift current region, the time required from photoelectric conversion to detection of the signal carrier in the N+ semiconductor region of the active tap is shortened. Furthermore, as the thickness of substrate 172 is reduced, the distance the signal carrier travels to the N+ semiconductor region within the active tap is also shortened.

[0269] Therefore, in a back-illuminated CAPD sensor, even when the driving frequency is high, signal carriers (electrons) generated in various regions within the substrate 172 can be sufficiently introduced into the N+ semiconductor region of the active tap, thereby improving the electron extraction efficiency.

[0270] Furthermore, by reducing the thickness of the substrate 172 , sufficient electron extraction efficiency can be ensured even at a high driving frequency, thereby improving high-speed driving resistance.

[0271] In particular, in a back-illuminated CAPD sensor, a voltage can be applied directly to substrate 172, i.e., substrate 61. This allows for a faster response time between active and passive tap switching, enabling high drive frequency. Furthermore, the ability to apply a voltage directly to substrate 61 widens the modulatable region within substrate 61.

[0272] Furthermore, in the back-illuminated light-receiving element 1 (CAPD sensor), a sufficient aperture ratio can be obtained, and thus pixels can be miniaturized accordingly, and the miniaturization resistance of pixels can be improved.

[0273] Furthermore, by configuring the light receiving element 1 as a back-illuminated type, the design of BEOL (Back End Of Line) capacitance can be liberalized, thereby increasing the degree of freedom in designing the saturation signal quantity (Qs).

[0274] (Variation 1 of the First Embodiment)

[0275] (Structural Example of Pixel)

[0276] In addition, the above is to take out the signal portion 65 in the substrate 61 as shown in FIG. Figure 3 As shown, the case where the N+ semiconductor region 71 and the P+ semiconductor region 73 are rectangular regions is described as an example. However, the shapes of the N+ semiconductor region 71 and the P+ semiconductor region 73 when viewed from a direction perpendicular to the substrate 61 may be any shapes.

[0277] Specifically, for example Figure 9 As shown, the N+ semiconductor region 71 and the P+ semiconductor region 73 may be circular. Figure 9 in Figure 3 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0278] Figure 9 The N+ semiconductor region 71 and the P+ semiconductor region 73 are shown when the portion of the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0279] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly toward the edge of the pixel 51. Specifically, two signal extraction portions 65 are formed in the pixel 51.

[0280] Furthermore, in each signal extraction portion 65 , a circular P+ semiconductor region 73 is formed at its center. The P+ semiconductor region 73 is surrounded by a circular, more specifically, annular N+ semiconductor region 71 , with the P+ semiconductor region 73 as the center.

[0281] Figure 10 Is in Figure 9 The illustrated plan view shows a portion of the pixel array section 20 in which the pixels 51 of the signal extraction section 65 are two-dimensionally arranged in a matrix, with the on-chip lens 62 overlapping.

[0282] like Figure 10 As shown, the on-chip lens 62 is formed in units of pixels. In other words, a unit area where one on-chip lens 62 is formed corresponds to one pixel.

[0283] In addition, Figure 2 In the embodiment, a separation portion 75 formed of an oxide film or the like is arranged between the N+ semiconductor region 71 and the P+ semiconductor region 73 , but the separation portion 75 is optional.

[0284] (Variation 2 of the First Embodiment)

[0285] (Structural Example of Pixel)

[0286] Figure 11 It is a plan view showing a modified example of the planar shape of the signal extraction portion 65 in the pixel 51 .

[0287] The planar shape of the signal extraction portion 65 is formed as Figure 3 The rectangle shown, Figure 9 In addition to the circular shape shown, it can also be formed into Figure 11 The octagonal shape shown.

[0288] also, Figure 11 A plan view is shown in which a separation portion 75 formed of an oxide film or the like is formed between the N+ semiconductor region 71 and the P+ semiconductor region 73 .

[0289] Figure 11 The line AA' shown here indicates the Figure 37 The cross-sectional line, BB' line represents the cross-sectional line described later. Figure 36 cross-section line.

[0290] (Second embodiment)

[0291] (Structural Example of Pixel)

[0292] Furthermore, the above description takes as an example the structure in which the P+ semiconductor region 73 in the signal extraction portion 65 is surrounded by the N+ semiconductor region 71 , but the N+ semiconductor region may also be surrounded by the P+ semiconductor region.

[0293] In this case, the pixel 51 is, for example, Figure 12 In addition, Figure 12 in Figure 3 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0294] Figure 12 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0295] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, a signal extraction portion 65-1 is formed in a portion slightly above the center of the pixel 51, and a signal extraction portion 65-2 is formed in a portion slightly below the center of the pixel 51. In particular, in this example, the formation position of the signal extraction portion 65 in the pixel 51 is the same as that in FIG. Figure 3 Same situation as the location.

[0296] In the signal taking-out section 65-1, Figure 3The rectangular N+ semiconductor region 201-1 corresponding to the N+ semiconductor region 71-1 is formed in the center of the signal extraction portion 65-1. Figure 3 The P+ semiconductor region 73-1 shown is surrounded by a rectangular, more specifically, rectangular frame-shaped, P+ semiconductor region 202-1. That is, the P+ semiconductor region 202-1 is formed to surround the N+ semiconductor region 201-1.

[0297] Similarly, in the signal taking-out section 65-2, Figure 3 The rectangular N+ semiconductor region 201-2 corresponding to the N+ semiconductor region 71-2 is formed in the center of the signal extraction portion 65-2. Figure 3 The P+ semiconductor region 73 - 2 is shown surrounded by a rectangle, more specifically, a rectangular frame-shaped P+ semiconductor region 202 - 2 .

[0298] In the following, when there is no need to distinguish between the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2, they are simply referred to as the N+ semiconductor region 201. In the following, when there is no need to distinguish between the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2, they are simply referred to as the P+ semiconductor region 202.

[0299] The signal taking-out portion 65 is formed as Figure 12 In the case of the structure shown, it is also formed as Figure 3 As in the case of the structure shown, the N+ semiconductor region 201 functions as a charge detection unit that detects the amount of signal carrier, and the P+ semiconductor region 202 functions as a voltage application unit for directly applying a voltage to the substrate 61 to generate an electric field.

[0300] (Variation 1 of the Second Embodiment)

[0301] (Structural Example of Pixel)

[0302] In addition, with Figure 9 Even in the case where the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202 , the shapes of the N+ semiconductor region 201 and the P+ semiconductor region 202 may be any shapes.

[0303] That is, for example, Figure 13 As shown in FIG. 2 , the N+ semiconductor region 201 and the P+ semiconductor region 202 are formed into a circular shape. Figure 13 in Figure 12 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0304] Figure 13 The N+ semiconductor region 201 and the P+ semiconductor region 202 are shown when the portion of the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0305] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly toward the edge of the pixel 51. Specifically, two signal extraction portions 65 are formed in the pixel 51.

[0306] Furthermore, in each signal extraction portion 65 , a circular N+ semiconductor region 201 is formed at its center. The N+ semiconductor region 201 is surrounded by a circular, more specifically, annular P+ semiconductor region 202 .

[0307] (Third embodiment)

[0308] (Structural Example of Pixel)

[0309] Furthermore, the N+ semiconductor region and the P+ semiconductor region formed in the signal extraction portion 65 may also be linear (rectangular).

[0310] In this case, for example, pixel 51 is Figure 14 In addition, Figure 14 in Figure 3 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0311] Figure 14 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0312] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, a signal extraction portion 65-1 is formed in a portion slightly above the center of the pixel 51, and a signal extraction portion 65-2 is formed in a portion slightly below the center of the pixel 51. In particular, in this example, the formation position of the signal extraction portion 65 in the pixel 51 is the same as that in FIG. Figure 3 Same situation as the location.

[0313] In the signal taking-out section 65-1, Figure 3 The linear P+ semiconductor region 231 corresponding to the P+ semiconductor region 73-1 is formed at the center of the signal extraction portion 65-1. Figure 3The N+ semiconductor region 71-1 shown corresponds to the linear N+ semiconductor region 232-1 and the N+ semiconductor region 232-2. That is, the P+ semiconductor region 231 is formed at a position sandwiched between the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2.

[0314] In addition, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 232 - 1 and the N+ semiconductor region 232 - 2 , they are also simply referred to as the N+ semiconductor region 232 .

[0315] exist Figure 3 In the example, the P+ semiconductor region 73 is formed to be surrounded by the N+ semiconductor region 71, but in Figure 14 In the example, a P+ semiconductor region 231 is formed to be sandwiched between two adjacent N+ semiconductor regions 232 .

[0316] Similarly, in the signal taking-out section 65-2, Figure 3 The linear P+ semiconductor region 233 corresponding to the P+ semiconductor region 73-2 is formed at the center of the signal extraction portion 65-2. Figure 3 The N+ semiconductor region 71 - 2 shown corresponds to the linear N+ semiconductor region 234 - 1 and the linear N+ semiconductor region 234 - 2 .

[0317] In the following, when there is no need to particularly distinguish between the N+ semiconductor region 234 - 1 and the N+ semiconductor region 234 - 2 , they are also simply referred to as the N+ semiconductor region 234 .

[0318] exist Figure 14 In the signal extraction section 65, the P+ semiconductor region 231 and the P+ semiconductor region 233 serve as Figure 3 The voltage applying portion corresponding to the P+ semiconductor region 73 shown in the figure functions as the voltage applying portion, and the N+ semiconductor region 232 and the N+ semiconductor region 234 function as the voltage applying portion corresponding to the P+ semiconductor region 73. Figure 3 The charge detection portion functions as shown in the N+ semiconductor region 71. In this case, for example, both the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2 are connected to the FD portion A.

[0319] In addition, the horizontal lengths of the linear P+ semiconductor region 231 , N+ semiconductor region 232 , P+ semiconductor region 233 and N+ semiconductor region 234 in the figure may be arbitrary lengths, and these regions may not have the same length.

[0320] (Fourth embodiment)

[0321] (Structural Example of Pixel)

[0322] Furthermore, in Figure 14 In the example, the structure in which the P+ semiconductor region 231 and the P+ semiconductor region 233 are sandwiched between the N+ semiconductor region 232 and the N+ semiconductor region 234 is described as an example, but conversely, the shape in which the N+ semiconductor region is sandwiched between the P+ semiconductor region can also be formed.

[0323] In such a case, for example, pixel 51 is Figure 15 In addition, Figure 15 in Figure 3 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0324] Figure 15 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when the signal extraction unit 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0325] In this example, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly closer to the end of the pixel 51 from the center. In particular, in this example, the formation positions of the two signal extraction portions 65 in the pixel 51 are aligned with each other. Figure 3 Same situation as the location.

[0326] In the signal taking-out section 65-1, Figure 3 The linear N+ semiconductor region 261 corresponding to the N+ semiconductor region 71-1 is formed at the center of the signal extraction portion 65-1. Figure 3 The P+ semiconductor region 73-1 shown corresponds to the linear P+ semiconductor region 262-1 and the P+ semiconductor region 262-2. That is, the N+ semiconductor region 261 is formed at a position sandwiched between the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2.

[0327] In the following, when there is no need to particularly distinguish between the P+ semiconductor region 262 - 1 and the P+ semiconductor region 262 - 2 , they are also simply referred to as the P+ semiconductor region 262 .

[0328] Similarly, in the signal taking-out section 65-2, Figure 3 The linear N+ semiconductor region 263 corresponding to the N+ semiconductor region 71-2 is formed at the center of the signal extraction portion 65-2. Figure 3The P+ semiconductor region 73 - 2 shown corresponds to the linear P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 .

[0329] In the following, when there is no need to particularly distinguish between the P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 , they are simply referred to as the P+ semiconductor region 264 .

[0330] exist Figure 15 In the signal extraction portion 65, the P+ semiconductor region 262 and the P+ semiconductor region 264 serve as Figure 3 The voltage applying portion corresponding to the P+ semiconductor region 73 shown in the figure functions as the voltage applying portion, and the N+ semiconductor region 261 and the N+ semiconductor region 263 function as the voltage applying portion corresponding to the P+ semiconductor region 73. Figure 3 The charge detection portion corresponding to the N+ semiconductor region 71 shown in the figure functions. In addition, the horizontal lengths of the linear N+ semiconductor region 261, P+ semiconductor region 262, N+ semiconductor region 263, and P+ semiconductor region 264 in the figure can be any length, and these regions do not have to be the same length.

[0331] (Fifth embodiment)

[0332] (Structural Example of Pixel)

[0333] Furthermore, in the above description, an example is described in which two signal extraction sections 65 are provided in each pixel constituting the pixel array section 20 . However, the number of signal extraction sections provided in a pixel may be one or three or more.

[0334] For example, when a signal extraction portion is formed in the pixel 51, the structure of the pixel is as follows. Figure 16 In addition, Figure 16 in Figure 3 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0335] Figure 16 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0336] In this example, a pixel 51 provided in the pixel array unit 20 and pixels 291 - 1 to 291 - 3 are shown as pixels 51 adjacent to the pixel 51 and are distinguished from each other by reference numerals. One signal extraction unit is formed in each of these pixels.

[0337] That is, in the pixel 51, a signal extraction portion 65 is formed in the central portion of the pixel 51. Furthermore, in the signal extraction portion 65, a circular P+ semiconductor region 301 is formed at its center, and the P+ semiconductor region 301 is surrounded by a circular, more specifically, annular, N+ semiconductor region 302, with the P+ semiconductor region 301 as the center.

[0338] Here, the P+ semiconductor region 301 and Figure 3 The P+ semiconductor region 73 shown in FIG. 1 functions as a voltage applying portion. Figure 3 The P+ semiconductor region 301 and the N+ semiconductor region 302 correspond to each other and function as a charge detection unit.

[0339] Furthermore, pixels 291 - 1 to 291 - 3 located around the pixel 51 also have the same structure as that of the pixel 51 .

[0340] Specifically, for example, a signal extraction portion 303 is formed in the center of pixel 291-1. Furthermore, a circular P+ semiconductor region 304 is formed at the center of signal extraction portion 303. This P+ semiconductor region 304 is surrounded by a circular, more specifically, annular, N+ semiconductor region 305, centered around the P+ semiconductor region 304.

[0341] These P+ semiconductor region 304 and N+ semiconductor region 305 correspond to the P+ semiconductor region 301 and the N+ semiconductor region 302 , respectively.

[0342] In the following, when there is no need to particularly distinguish between the pixels 291 - 1 to 291 - 3 , they are simply referred to as pixels 291 .

[0343] In this way, when each pixel forms a signal extraction unit (tap), when the distance to the object is to be measured using the indirect ToF method, several adjacent pixels are used to calculate distance information based on pixel signals obtained for these pixels.

[0344] For example, when focusing on pixel 51, while the signal extraction unit 65 of pixel 51 is set as an active tap, each pixel is driven so that the signal extraction units 303 of several pixels 291 adjacent to pixel 51, including, for example, pixel 291-1, become passive taps.

[0345] As an example, the pixel 291 - 1 and the pixel 291 - 3 are driven so that the signal extraction portions of the pixels adjacent to the pixel 51 in the vertical direction and the horizontal direction in the figure become passive taps.

[0346] Thereafter, when the applied voltage is switched so that the signal extraction section 65 of the pixel 51 becomes a passive tap, the signal extraction sections 303 of several pixels 291 adjacent to the pixel 51 including the pixel 291 - 1 become active taps.

[0347] Then, distance information is calculated based on the pixel signal read out from the signal extraction section 65 when the signal extraction section 65 is in the active tap state and the pixel signal read out from the signal extraction section 303 when the signal extraction section 303 is in the active tap state.

[0348] In this manner, even when the number of signal extraction units (tap) provided in a pixel is set to one, it is possible to perform distance measurement using mutually adjacent pixels by the indirect ToF method.

[0349] (Sixth embodiment)

[0350] (Structural Example of Pixel)

[0351] Furthermore, as described above, three or more signal extraction portions (taps) may be provided in each pixel.

[0352] For example, when four signal extraction units (taps) are provided in a pixel, the pixel structure of each pixel in the pixel array unit 20 is as follows: Figure 17 In addition, Figure 17 in Figure 16 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0353] Figure 17 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0354] Figure 17 The cross-sectional view of the CC' line shown is as described later. Figure 36 shown.

[0355] In this example, the pixel 51 and the pixel 291 provided in the pixel array unit 20 are shown, and four signal extraction units are formed in each of these pixels.

[0356] That is, in pixel 51, a signal taking-out section 331-1, a signal taking-out section 331-2, a signal taking-out section 331-3, and a signal taking-out section 331-4 are formed at positions between the center of pixel 51 and the ends of pixel 51, that is, at the lower left position, the upper left position, the upper right position, and the lower right position of the center of pixel 51 in the figure.

[0357] The above-mentioned signal extraction units 331-1 to 331-4 are Figure 16The signal extraction unit 65 shown corresponds to this.

[0358] For example, in the signal extraction portion 331 - 1 , a circular P+ semiconductor region 341 is formed at its center. The P+ semiconductor region 341 is surrounded by a circular, more specifically, annular N+ semiconductor region 342 , with the P+ semiconductor region 341 as the center.

[0359] Here, the P+ semiconductor region 341 and Figure 16 The P+ semiconductor region 301 shown in FIG. 1 functions as a voltage applying portion. Figure 16 The P+ semiconductor region 341 and the N+ semiconductor region 342 may have any shape.

[0360] Furthermore, signal extraction sections 331-2 through 331-4 have the same structure as signal extraction section 331-1, each including a P+ semiconductor region functioning as a voltage application section and an N+ semiconductor region functioning as a charge detection section. Furthermore, pixel 291, formed around pixel 51, has the same structure as pixel 51.

[0361] In addition, hereinafter, when there is no need to particularly distinguish between the signal extraction unit 331 - 1 to the signal extraction unit 331 - 4 , they are also simply referred to as the signal extraction unit 331 .

[0362] In this way, when four signal extraction units are provided in each pixel, for example, when distance measurement is performed using an indirect ToF method, distance information is calculated using the four signal extraction units in the pixel.

[0363] As an example, when focusing on pixel 51, for example, while signal extraction section 331-1 and signal extraction section 331-3 are set as active taps, pixel 51 is driven so that signal extraction section 331-2 and signal extraction section 331-4 become passive taps.

[0364] Thereafter, the voltage applied to each signal extraction section 331 is switched. That is, the pixel 51 is driven so that the signal extraction section 331-1 and the signal extraction section 331-3 become passive taps, and the signal extraction section 331-2 and the signal extraction section 331-4 become active taps.

[0365] Then, the distance information is calculated based on the pixel signals read out from the signal taking-out section 331-1 and the signal taking-out section 331-3 when the signal taking-out section 331-1 and the signal taking-out section 331-3 are set as active taps, and the pixel signals read out from the signal taking-out section 331-2 and the signal taking-out section 331-4 when the signal taking-out section 331-2 and the signal taking-out section 331-4 are set as active taps.

[0366] (Seventh embodiment)

[0367] (Structural Example of Pixel)

[0368] Furthermore, a signal extraction portion (tap) may be shared between adjacent pixels in the pixel array section 20 .

[0369] In this case, each pixel of the pixel array section 20 is, for example, Figure 18 In addition, Figure 18 in Figure 16 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0370] Figure 18 1 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of a signal extraction section provided in a pixel of a portion of the pixel array section 20 is viewed from a direction perpendicular to the substrate.

[0371] In this example, a pixel 51 and a pixel 291 provided in the pixel array unit 20 are shown, and two signal extraction units are formed in each of these pixels.

[0372] For example, in the pixel 51 , the signal extraction portion 371 is formed at the upper end portion of the pixel 51 in the figure, and the signal extraction portion 372 is formed at the lower end portion of the pixel 51 in the figure.

[0373] Signal extraction unit 371 is shared by pixel 51 and pixel 291-1. That is, signal extraction unit 371 serves as a tap for pixel 51 and also serves as a tap for pixel 291-1. Furthermore, signal extraction unit 372 is shared by pixel 51 and a pixel (not shown) adjacent to the lower side of pixel 51 in the figure.

[0374] In the signal taking-out portion 371, a Figure 14 The linear P+ semiconductor region 381 corresponding to the P+ semiconductor region 231 shown in FIG. Moreover, a linear P+ semiconductor region 381 is formed at the upper and lower positions of the P+ semiconductor region 381 in such a manner as to sandwich the P+ semiconductor region 381. Figure 14 The N+ semiconductor region 232 shown corresponds to a linear N+ semiconductor region 382 - 1 and an N+ semiconductor region 382 - 2 .

[0375] In particular, in this example, the P+ semiconductor region 381 is formed at the boundary between the pixel 51 and the pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in the region within the pixel 51, and the N+ semiconductor region 382-2 is formed in the region within the pixel 291-1.

[0376] Here, the P+ semiconductor region 381 functions as a voltage application unit, and the N+ semiconductor regions 382-1 and 382-2 function as charge detection units. In the following, when there is no need to specifically distinguish between the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2, they are simply referred to as the N+ semiconductor region 382.

[0377] The P+ semiconductor region 381 and the N+ semiconductor region 382 may have any shape. Furthermore, the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 may be connected to the same FD portion or to different FD portions.

[0378] A linear P+ semiconductor region 383 , an N+ semiconductor region 384 - 1 , and an N+ semiconductor region 384 - 2 are formed in the signal extraction portion 372 .

[0379] These P+ semiconductor region 383, N+ semiconductor region 384-1, and N+ semiconductor region 384-2 correspond to P+ semiconductor region 381, N+ semiconductor region 382-1, and N+ semiconductor region 382-2, respectively, and have the same configuration, shape, and function. Hereinafter, when there is no need to specifically distinguish between N+ semiconductor region 384-1 and N+ semiconductor region 384-2, they are simply referred to as N+ semiconductor region 384.

[0380] When the signal extraction unit (tap) is shared between adjacent pixels as described above, it is also possible to Figure 3 The same operation as in the example shown is performed by indirect ToF ranging.

[0381] In such Figure 18 When the signal extraction unit is shared among pixels as shown, the distance between the P+ semiconductor regions, which form a pair for generating an electric field, i.e., a current, is increased, such as the distance between P+ semiconductor regions 381 and 383. In other words, by sharing the signal extraction unit among pixels, the distance between the P+ semiconductor regions can be maximized.

[0382] This makes it difficult for current to flow between the P+ semiconductor regions, thereby reducing the power consumption of the pixel and contributing to miniaturization of the pixel.

[0383] In addition, while the example described here is one in which a single signal extraction section is shared by two adjacent pixels, a single signal extraction section may also be shared by three or more adjacent pixels. Furthermore, when a signal extraction section is shared by two or more adjacent pixels, only the charge detection section for detecting the signal carrier or only the voltage application section for generating the electric field may be shared within the signal extraction section.

[0384] (Eighth Embodiment)

[0385] (Structural Example of Pixel)

[0386] Furthermore, it is not necessary to particularly provide an on-chip lens and an inter-pixel light shielding portion for each pixel such as the pixel 51 provided in the pixel array section 20 .

[0387] Specifically, for example, the pixel 51 can be formed as Figure 19 In addition, Figure 19 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0388] Figure 19 The structure of the pixel 51 shown is different from that of the pixel 51 in that the on-chip lens 62 is not provided. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0389] exist Figure 19 The pixel 51 shown does not have an on-chip lens 62 on the light incident side of the substrate 61, thereby further reducing the attenuation of infrared light incident from the outside on the substrate 61. This increases the amount of infrared light that can be received by the substrate 61, and improves the sensitivity of the pixel 51.

[0390] (Variation 1 of the Eighth Embodiment)

[0391] (Structural Example of Pixel)

[0392] In addition, the structure of the pixel 51 may be formed as follows, for example Figure 20 In addition, Figure 20 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0393] Figure 20 The structure of the pixel 51 shown is different from that of the pixel 51 in that the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2 are not provided. Figure 2 The pixel 51 shown is different from the Figure 2 The structure of pixel 51 is the same.

[0394] exist Figure 20 In the example shown, since the inter-pixel shading film 63 is not provided on the light incident surface side of the substrate 61, the crosstalk suppression effect is reduced, but since the infrared light shielded by the inter-pixel shading film 63 also enters the substrate 61, the sensitivity of the pixel 51 can be improved.

[0395] Furthermore, it is of course also possible to provide neither the on-chip lens 62 nor the inter-pixel light shielding film 63 in the pixel 51 .

[0396] (Variation 2 of the Eighth Embodiment)

[0397] (Structural Example of Pixel)

[0398] In addition, for example Figure 21 As shown in FIG, the thickness of the on-chip lens in the optical axis direction can also be optimized. Figure 21 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0399] Figure 21 The structure of the pixel 51 shown is different from that of the pixel 51 in that an on-chip lens 411 is provided instead of the on-chip lens 62. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0400] exist Figure 21 In the pixel 51 shown, an on-chip lens 411 is formed on the light incident surface side of the substrate 61, that is, on the upper side in the figure. Figure 2 Compared with the on-chip lens 62 shown, the thickness in the optical axis direction, that is, the thickness in the vertical direction in the figure, is thinner.

[0401] Typically, the thickness of the on-chip lens provided on the surface of substrate 61 contributes to the collection of light incident on the on-chip lens. However, by thinning on-chip lens 411, the transmittance can be increased accordingly, thereby improving the sensitivity of pixel 51. Therefore, the thickness of on-chip lens 411 can be appropriately determined based on the thickness of substrate 61, the position where infrared light is to be collected, and other factors.

[0402] (Ninth embodiment)

[0403] (Structural Example of Pixel)

[0404] Furthermore, a separation region may be provided between pixels formed in the pixel array unit 20 to improve separation characteristics between adjacent pixels and suppress crosstalk.

[0405] In such a case, the pixel 51 is, for example, Figure 22 In addition, Figure 22 in Figure 2The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0406] Figure 22 The structure of the pixel 51 shown is different from that of the pixel 51 in that the separation region 441-1 and the separation region 441-2 are provided in the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0407] exist Figure 22 In the illustrated pixel 51, a separation region 441-1 and a separation region 441-2 are formed by a light-shielding film or the like at the boundaries between the pixel 51 and other adjacent pixels within the substrate 61, i.e., at the left and right ends of the pixel 51 in the figure. The separation regions 441-1 and 441-2 are separated from each other by a light-shielding film or the like. Hereinafter, when there is no need to specifically distinguish between the separation regions 441-1 and 441-2, they are simply referred to as the separation regions 441.

[0408] For example, when forming the isolation region 441, a long groove (trench) is formed in the substrate 61 with a predetermined depth from the light incident surface side of the substrate 61, that is, the upper side in the figure, toward the lower side in the figure (perpendicular to the surface of the substrate 61), and a light shielding film is embedded in the groove portion to form the isolation region 441. The isolation region 441 functions as a pixel isolation region, shielding infrared light that enters the substrate 61 from the light incident surface and is directed toward other pixels adjacent to the pixel 51.

[0409] By forming the buried isolation region 441 in this manner, the infrared light separation characteristics between pixels can be improved, and the occurrence of crosstalk can be suppressed.

[0410] (Variation 1 of the Ninth Embodiment)

[0411] (Structural Example of Pixel)

[0412] Furthermore, in the case where the pixel 51 forms a buried separation region, for example, Figure 23 As shown in FIG. 4 , a separation region 471-1 and a separation region 471-2 may be provided that penetrate the entire substrate 61. Figure 23 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0413] Figure 23 The structure of the pixel 51 shown is different from that of the pixel 51 in that the separation region 471-1 and the separation region 471-2 are provided in the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure. That is, Figure 23 The pixel 51 shown is constructed as follows: Figure 22The separation region 441 of the pixel 51 shown is replaced by a separation region 471 - 1 and a separation region 471 - 2 .

[0414] exist Figure 23 In the illustrated pixel 51, a separation region 471-1 and a separation region 471-2 are formed by a light-shielding film or the like at the boundaries between the pixel 51 and other adjacent pixels within the substrate 61, i.e., at the left and right ends of the pixel 51 in the figure. These separation regions penetrate the entire substrate 61. Hereinafter, when there is no need to specifically distinguish between the separation region 471-1 and the separation region 471-2, they are simply referred to as the separation region 471.

[0415] For example, when forming the isolation region 471, long grooves (trench) are formed on the surface of the substrate 61 opposite to the light incident surface, that is, the lower surface in the figure, extending upward in the figure. These grooves are formed so as to penetrate the substrate 61 until they reach the light incident surface of the substrate 61. Furthermore, the isolation region 471 is formed by embedding a light shielding film in the grooves thus formed.

[0416] Such a buried isolation region 471 can also improve the infrared light separation characteristics between pixels and suppress the occurrence of crosstalk.

[0417] (Tenth embodiment)

[0418] (Structural Example of Pixel)

[0419] Furthermore, the thickness of the substrate forming the signal extraction portion 65 can be determined based on various characteristics of the pixel and the like.

[0420] Thus, for example Figure 24 As shown, the substrate 501 constituting the pixel 51 can be made larger than Figure 2 The substrate 61 shown is thick. Figure 24 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0421] Figure 24 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 501 is provided instead of the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0422] That is, in Figure 24 In the illustrated pixel 51, an on-chip lens 62 and a fixed charge film 66 are formed on the light incident side of the substrate 501, and a light shielding film 63 is formed between pixels. Furthermore, an oxide film 64, a signal extraction portion 65, and a separator 75 are formed near the surface of the substrate 501 opposite the light incident side.

[0423] The substrate 501 is composed of a P-type semiconductor substrate with a thickness of, for example, 20 μm or more. The substrate 501 and the substrate 61 differ only in thickness. The positions where the oxide film 64, the signal extraction portion 65 and the separation portion 75 are formed are the same in the substrate 501 and the substrate 61.

[0424] Furthermore, the film thicknesses of various layers (films) formed appropriately on the light incident surface side of the substrate 501 and the substrate 61 may be optimized according to the characteristics of the pixel 51 .

[0425] (Eleventh embodiment)

[0426] (Structural Example of Pixel)

[0427] Furthermore, in the above, an example in which the substrate constituting the pixel 51 is constituted by a P-type semiconductor substrate has been described, but for example, Figure 25 As shown in FIG, it is composed of an N-type semiconductor substrate. Figure 25 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0428] Figure 25 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 531 is provided instead of the substrate 61. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0429] exist Figure 25 In the illustrated pixel 51 , an on-chip lens 62 , a fixed charge film 66 , and an inter-pixel light shielding film 63 are formed on the light incident surface side of a substrate 531 composed of an N-type semiconductor layer such as a silicon substrate.

[0430] Furthermore, an oxide film 64, a signal extraction portion 65, and a separator 75 are formed near the surface of the substrate 531 on the side opposite to the light incident surface. The oxide film 64, the signal extraction portion 65, and the separator 75 are formed at the same positions in the substrate 531 and the substrate 61, and the structure of the signal extraction portion 65 is also the same in the substrate 531 and the substrate 61.

[0431] The thickness of the substrate 531 in the longitudinal direction in the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 531 , is 20 μm or less, for example.

[0432] The substrate 531 is a high-resistance N-EPi substrate with a substrate concentration of 1E+13 or less, and the resistance (resistivity) of the substrate 531 is, for example, 500 [Ωcm] or more. This reduces power consumption in the pixel 51.

[0433] Here, for the relationship between the substrate concentration and the resistance of the substrate 531, for example, when the substrate concentration is 2.15E+12[cm3], the resistance is 2000[Ωcm], when the substrate concentration is 4.30E+12[cm3], the resistance is 1000[Ωcm], when the substrate concentration is 8.61E+12[cm3], the resistance is 500[Ωcm], and when the substrate concentration is 4.32E+13[cm3], the resistance is 100[Ωcm], etc.

[0434] Thus, even if the substrate 531 of the pixel 51 is set as an N-type semiconductor substrate, Figure 2 The same actions as in the example shown can also achieve the same effects.

[0435] (Twelfth embodiment)

[0436] (Structural Example of Pixel)

[0437] Furthermore, with reference Figure 24 The same as the example described above, the thickness of the N-type semiconductor substrate can also be determined based on various characteristics of the pixel.

[0438] Thus, for example, Figure 26 As shown, the substrate 561 constituting the pixel 51 is made Figure 25 The substrate 531 shown is thick. Figure 26 in Figure 25 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0439] Figure 26 The structure of the pixel 51 shown is different from that of the pixel 51 in that a substrate 561 is provided instead of the substrate 531. Figure 25 The pixel 51 shown is different from the Figure 25 The pixel 51 has the same structure.

[0440] That is, in Figure 26 In the illustrated pixel 51, an on-chip lens 62, a fixed charge film 66, and an inter-pixel light shielding film 63 are formed on the light incident surface side of a substrate 561. Furthermore, an oxide film 64, a signal extraction portion 65, and a separation portion 75 are formed near the surface of the substrate 561 opposite to the light incident surface side.

[0441] Substrate 561 is composed of an N-type semiconductor substrate with a thickness of, for example, 20 μm or more. The only difference between substrate 561 and substrate 531 is the thickness of the substrate. The positions where the oxide film 64, the signal extraction portion 65 and the separation portion 75 are formed are the same in substrate 561 and substrate 531.

[0442] (Thirteenth embodiment)

[0443] (Structural Example of Pixel)

[0444] Furthermore, for example, by applying a bias voltage to the light incident surface side of the substrate 61 , the electric field in the direction perpendicular to the surface of the substrate 61 (hereinafter also referred to as the Z direction) within the substrate 61 may be strengthened.

[0445] In this case, the pixel 51 is formed as, for example Figure 27 In addition, Figure 27 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0446] Figure 27 A represents Figure 2 In the pixel 51 shown, the arrow in the substrate 61 of the pixel 51 indicates the intensity of the electric field in the Z direction in the substrate 61 .

[0447] In contrast, Figure 27 B shows the structure of the pixel 51 when a bias (voltage) is applied to the light incident surface of the substrate 61 . Figure 27 The structure of pixel 51 of B is basically the same as Figure 2 The pixel 51 shown has the same structure, but a P+ semiconductor region 601 is newly formed on the light incident surface side interface of the substrate 61 .

[0448] By applying a voltage of 0 V or less (negative bias) to the P + semiconductor region 601 formed on the light incident surface side interface of the substrate 61 from inside or outside the pixel array unit 20 , the electric field in the Z direction is intensified. Figure 27 The arrows in the substrate 61 of the pixel 51 of B represent the intensity of the electric field in the Z direction in the substrate 61. Figure 27 The thickness ratio of the arrow drawn in the substrate 61 of B Figure 27 The arrows for pixel A 51 are thicker, and the electric field in the Z direction is stronger. Thus, by applying a negative bias to the P+ semiconductor region 601 formed on the light incident surface side of the substrate 61 to strengthen the electric field in the Z direction, the electron extraction efficiency in the signal extraction unit 65 can be improved.

[0449] Furthermore, the structure for applying a voltage to the light incident surface of substrate 61 is not limited to the structure provided with P+ semiconductor region 601, and may be any other structure. For example, a negative bias voltage may be applied by forming a transparent electrode film laminated between the light incident surface of substrate 61 and on-chip lens 62 and applying a voltage to the transparent electrode film.

[0450] (Fourteenth embodiment)

[0451] (Structural Example of Pixel)

[0452] Furthermore, in order to increase the sensitivity of the pixel 51 to infrared rays, a large-area reflective member may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0453] In such a case, the pixel 51 is, for example, Figure 28 In addition, Figure 28 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are appropriately omitted.

[0454] Figure 28 The structure of the pixel 51 shown is different from that of the pixel 51 in that a reflective member 631 is provided on the surface of the substrate 61 opposite to the light incident surface. Figure 2 The pixel 51 is different, and other aspects are the same Figure 2 The pixel 51 has the same structure.

[0455] exist Figure 28 In the example of FIG, a reflecting member 631 that reflects infrared light is provided so as to cover the entire surface of the substrate 61 opposite to the light incident surface.

[0456] The reflective member 631 may be any member as long as it has a high reflectivity for infrared light. For example, a metal such as copper or aluminum provided in a multilayer wiring layer stacked on the surface of the substrate 61 opposite to the light incident surface may be used as the reflective member 631. Alternatively, a reflective structure such as polysilicon or an oxide film may be formed on the surface of the substrate 61 opposite to the light incident surface to serve as the reflective member 631.

[0457] Thus, by providing the reflective member 631 in the pixel 51, infrared light that enters the substrate 61 from the light incident surface via the on-chip lens 62 but passes through the substrate 61 without undergoing photoelectric conversion is reflected by the reflective member 631 and reenters the substrate 61. This increases the amount of infrared light that undergoes photoelectric conversion in the substrate 61, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel 51 to infrared light.

[0458] (Fifteenth embodiment)

[0459] (Structural Example of Pixel)

[0460] Furthermore, in order to suppress erroneous detection of light in nearby pixels, a light shielding member having a large area may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0461] In this case, the pixel 51 can be configured, for example, to Figure 28 The reflecting member 631 shown is replaced by a light shielding member. Figure 28In the pixel 51 shown, the reflective member 631 covering the entire surface of the substrate 61 opposite to the light incident surface is used as a light shielding member 631' for shielding infrared light. Figure 28 The reflective component 631 of the pixel 51 is replaced.

[0462] The light-shielding member 631' can be any member as long as it has a high infrared light shielding rate. For example, a metal such as copper or aluminum provided in a multilayer wiring layer stacked on the side opposite to the light incident surface of the substrate 61 can be used as the light-shielding member 631'. Alternatively, a light-shielding structure such as polysilicon or an oxide film can be formed on the side opposite to the light incident surface of the substrate 61 to serve as the light-shielding member 631'.

[0463] By providing light shielding member 631' on pixel 51, infrared light that enters substrate 61 from the light incident surface via on-chip lens 62, passes through substrate 61 without undergoing photoelectric conversion, and is prevented from being scattered by the wiring layer and entering nearby pixels. This prevents erroneous light detection in nearby pixels.

[0464] In addition, the light shielding member 631 ′ can also serve as the reflecting member 631 by being formed of a material containing metal, for example.

[0465] (Sixteenth embodiment)

[0466] (Structural Example of Pixel)

[0467] Furthermore, a P-well region composed of a P-type semiconductor region may be provided instead of the oxide film 64 in the substrate 61 of the pixel 51 .

[0468] In such a case, the pixel 51 is, for example, Figure 29 In addition, Figure 29 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0469] Figure 29 The structure of the pixel 51 shown is different from that of the pixel 51 in that a P-well region 671, a separation portion 672-1, and a separation portion 672-2 are provided instead of the oxide film 64. Figure 2 The pixel 51 shown is different from the Figure 2 The pixel 51 has the same structure.

[0470] exist Figure 29In the example, a P-well region (Pwell) 671 composed of a P-type semiconductor region is formed on the side of the substrate 61 opposite to the light incident surface, that is, in the central portion of the inner side of the lower side in the figure. In addition, a separation portion 672-1 for separating these regions is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 for separating these regions is also formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. Figure 29 In the pixel 51 shown, the P-semiconductor region 74 is a region wider in the upper direction in the figure than the N-semiconductor region 72 .

[0471] (Seventeenth embodiment)

[0472] (Structural Example of Pixel)

[0473] Furthermore, in addition to the oxide film 64 in the substrate 61 of the pixel 51 , a P-well region composed of a P-type semiconductor region may be provided.

[0474] In such a case, the pixel 51 is, for example, Figure 30 In addition, Figure 30 in Figure 2 The corresponding parts are marked with the same drawing marks and their descriptions are omitted as appropriate.

[0475] Figure 30 The structure of the pixel 51 shown is different from that of the pixel 51 in that a new P-well region 701 is provided. Figure 2 The pixel 51 shown is different from the Figure 2 The structure of the pixel 51 is the same. Figure 30 In the example, a P-well region 701 composed of a P-type semiconductor region is formed on the upper side of the oxide film 64 in the substrate 61.

[0476] As described above, according to the present invention, by configuring the CAPD sensor as a back-illuminated type, characteristics such as pixel sensitivity can be improved.

[0477] (Equivalent Circuit Structure Example of Pixel)

[0478] Figure 31 denoted as an equivalent circuit of the pixel 51 .

[0479] The pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplifying transistor 724A, and a selecting transistor 725A for the signal taking-out portion 65 - 1 including the N + semiconductor region 71 - 1 and the P + semiconductor region 73 - 1 .

[0480] Furthermore, the pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplifying transistor 724B, and a selecting transistor 725B for the signal taking-out portion 65 - 2 including the N + semiconductor region 71 - 2 and the P + semiconductor region 73 - 2 .

[0481] The tap driver 21 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is 1.5 V, and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 serve as voltage application sections to which the first voltage or the second voltage is applied.

[0482] The N+ semiconductor regions 71 - 1 and 71 - 2 are charge detection portions that detect and accumulate charges generated by photoelectric conversion of light incident on the substrate 61 .

[0483] When the drive signal TRG supplied to the gate electrode is activated, the transfer transistor 721A is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-1 to the FD 722A. When the drive signal TRG supplied to the gate electrode is activated, the transfer transistor 721B is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-2 to the FD 722B.

[0484] FD722A temporarily holds the charge DET0 supplied from the N+ semiconductor region 71-1. FD722B temporarily holds the charge DET1 supplied from the N+ semiconductor region 71-2. Figure 2 The FD part A described above corresponds to FD722B, and the FD part B corresponds to FD722B.

[0485] When the drive signal RST supplied to its gate electrode becomes active, the reset transistor 723A is turned on in response, thereby resetting the potential of the FD 722A to a predetermined level (power supply voltage VDD). When the drive signal RST supplied to its gate electrode becomes active, the reset transistor 723B is turned on in response, thereby resetting the potential of the FD 722B to a predetermined level (power supply voltage VDD). Furthermore, when the reset transistors 723A and 723B are activated, the transfer transistors 721A and 721B are also activated simultaneously.

[0486] The amplifier transistor 724A is connected to the vertical signal line 29A via the source electrode via the select transistor 725A, thereby forming a load MOS transistor and a source follower circuit for the constant current source circuit portion 726A connected to one end of the vertical signal line 29A. The amplifier transistor 724B is connected to the vertical signal line 29B via the source electrode via the select transistor 725B, thereby forming a load MOS transistor and a source follower circuit for the constant current source circuit portion 726B connected to one end of the vertical signal line 29B.

[0487] The selection transistor 725A is connected between the source of the amplifier transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate electrode is activated, the selection transistor 725A is turned on and outputs the pixel signal output from the amplifier transistor 724A to the vertical signal line 29A.

[0488] The selection transistor 725B is connected between the source of the amplifier transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate electrode is activated, the selection transistor 725B turns on and outputs the pixel signal output from the amplifier transistor 724B to the vertical signal line 29B.

[0489] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by, for example, the vertical drive section 22 .

[0490] (Another equivalent circuit structure example of a pixel)

[0491] Figure 32 Another equivalent circuit of the pixel 51 is shown.

[0492] exist Figure 32 In, with Figure 31 Corresponding parts are marked with the same drawing reference numerals, and their descriptions are omitted as appropriate.

[0493] Figure 32 The equivalent circuit for Figure 31 In the equivalent circuit of FIG, an additional capacitor 727 and a switching transistor 728 for controlling the connection between the additional capacitor and the switching transistor 728 are added to both the signal extraction units 65-1 and 65-2.

[0494] Specifically, the additional capacitor 727A is connected between the transfer transistor 721A and the FD 722A via the switching transistor 728A, and the additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B via the switching transistor 728B.

[0495] When the drive signal FDG supplied to the gate electrode is activated, the switching transistor 728A is turned on, thereby connecting the additional capacitor 727A to the FD 722A. When the drive signal FDG supplied to the gate electrode is activated, the switching transistor 728B is turned on, thereby connecting the additional capacitor 727B to the FD 722B.

[0496] For example, when incident light is high in intensity, the vertical drive unit 22 activates the switching transistors 728A and 728B to connect the FD 722A to the additional capacitor 727A and the FD 722B to the additional capacitor 727B. This allows more charge to be stored during high illumination.

[0497] On the other hand, at low illumination with a small amount of incident light, the vertical drive unit 22 sets the switching transistors 728A and 728B to an inactive state, and disconnects the additional capacitors 727A and 727B from the FDs 722A and 722B, respectively.

[0498] like Figure 31 As in the equivalent circuit of , the additional capacitor 727 can be omitted, but by providing the additional capacitor 727 and using them separately according to the amount of incident light, a high dynamic range can be ensured.

[0499] (Arrangement Example of Voltage Supply Lines)

[0500] Next, refer to Figures 33 to 35 , the configuration of the voltage supply lines for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the voltage application section of the signal extraction section 65 of each pixel 51 will be described. Figure 33 and Figure 34 The voltage supply line 741 is shown with Figure 1 The voltage supply line 30 shown corresponds.

[0501] In addition, Figure 33 and Figure 34 In the embodiment, the structure of the signal extraction unit 65 of each pixel 51 adopts Figure 9 The circular structure shown is used for illustration, but other structures are of course possible.

[0502] Figure 33 A is a plan view showing a first arrangement example of the voltage supply lines.

[0503] In the first arrangement example, with respect to the plurality of pixels 51 arranged two-dimensionally in a matrix, the voltage supply line 741 - 1 or 741 - 2 is arranged in the vertical direction between two pixels adjacent in the horizontal direction (at the boundary).

[0504] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, which is one of the two signal extraction sections 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, which is the other of the two signal extraction sections 65 in the pixel 51.

[0505] In this first configuration example, two voltage supply lines 741 - 1 and 741 - 2 are arranged in two pixel columns. Therefore, in the pixel array section 20 , the number of arranged voltage supply lines 741 is substantially equal to the number of columns of pixels 51 .

[0506] Figure 33 B is a plan view showing a second arrangement example of the voltage supply lines.

[0507] In the second arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are arranged in the vertical direction with respect to one pixel column of a plurality of pixels 51 arranged two-dimensionally in a matrix.

[0508] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, which is one of the two signal extraction sections 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, which is the other of the two signal extraction sections 65 in the pixel 51.

[0509] In this second configuration example, two voltage supply lines 741-1 and 741-2 are arranged for one pixel column, so four voltage supply lines 741 are arranged for two pixel columns. In the pixel array section 20, the number of voltage supply lines 741 arranged is approximately twice the number of columns of pixels 51.

[0510] exist Figure 33 In the configuration examples A and B, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, which is a Periodic configuration (periodic configuration) that is periodically repeated relative to the pixels arranged in the vertical direction.

[0511] exist Figure 33 In the first configuration example of A, the number of voltage supply lines 741 - 1 and 741 - 2 arranged with respect to the pixel array section 20 can be reduced.

[0512] Figure 33Compared with the first configuration example, although the second configuration example of B has more wirings, the number of signal extraction units 65 connected to one voltage supply line 741 is 1 or 2, so the load on the wiring can be reduced, which is effective in high-speed driving and when the total number of pixels in the pixel array unit 20 is large.

[0513] Figure 34 A is a plan view showing a third arrangement example of the voltage supply lines.

[0514] The third configuration example is Figure 33 This is the same as the first configuration example of A, and is an example in which two voltage supply lines 741 - 1 and 741 - 2 are configured for two pixel columns.

[0515] The third configuration example is Figure 33 The difference from the first arrangement example of A is that the signal extraction sections 65-1 and 65-2 are connected to different destinations in two pixels arranged in the vertical direction.

[0516] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, but in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1.

[0517] Figure 34 B is a plan view showing a fourth arrangement example of the voltage supply lines.

[0518] The fourth configuration example is Figure 33 The second configuration example of B is the same as that of FIG. 1 , and is an example in which two voltage supply lines 741 - 1 and 741 - 2 are configured for two pixel columns.

[0519] The fourth configuration example is Figure 33 The second arrangement example of B is different in that the signal extraction sections 65 - 1 and 65 - 2 are connected to different destinations in two pixels arranged in the vertical direction.

[0520] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, but in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal taking-out portion 65-1.

[0521] exist Figure 34 In the third configuration example of A, the number of voltage supply lines 741 - 1 and 741 - 2 arranged with respect to the pixel array section 20 can be reduced.

[0522] Figure 34 Compared with the third configuration example, although the fourth configuration example of B has more wiring lines, the number of signal extraction parts 65 connected to one voltage supply line 741 is 1 or 2, so the wiring load can be reduced, which is effective in high-speed driving and when the total number of pixels in the pixel array part 20 is large.

[0523] Figure 34 Both the arrangement examples A and B are mirror arrangements (mirror arrangements) in which the connection destination of two vertically adjacent pixels is mirror-inverted.

[0524] In the Periodic configuration, such as Figure 35 As shown in Figure 1, the voltages applied to the two adjacent signal extraction units 65 across the pixel boundary are different, causing charge exchange between adjacent pixels. This improves charge transfer efficiency compared to a mirror configuration, but results in worse crosstalk between adjacent pixels.

[0525] On the other hand, in the Mirror configuration, such as Figure 35 As shown in Figure B, the voltage applied to two adjacent signal extraction units 65 across a pixel boundary is the same, thus suppressing the exchange of charge between adjacent pixels. Therefore, the charge transfer efficiency is lower than that of the Periodic configuration, but the crosstalk characteristics between adjacent pixels are better than those of the Periodic configuration.

[0526] (Cross-sectional Structure of Multiple Pixels in Fourteenth Embodiment)

[0527] exist Figure 2 In the cross-sectional structure of the pixel shown in FIG. 1 , the multilayer wiring layer formed on the surface side opposite to the light incident surface of the substrate 61 is omitted from illustration.

[0528] Therefore, in the following, in the several embodiments described above, cross-sectional views of a plurality of adjacent pixels are shown without omitting the multilayer wiring layer.

[0529] First, in Figure 36 and Figure 37 Shown in Figure 28 FIG. 1 is a cross-sectional view of a plurality of pixels according to a fourteenth embodiment.

[0530] Figure 28 The fourteenth embodiment shown has a pixel structure including a large-area reflective member 631 on the side of the substrate 61 opposite to the light incident surface.

[0531] Figure 36 Equivalent to Figure 11 The cross-sectional view at line BB', Figure 37 Equivalent to Figure 11 In addition, Figure 17 The cross-sectional view at the CC' line can also be Figure 36 shown.

[0532] like Figure 36 As shown, in each pixel 51 , an oxide film 64 is formed in the center portion, and a signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed on both sides of the oxide film 64 .

[0533] In the signal extraction section 65-1, an N+ semiconductor region 71-1 and an N- semiconductor region 72-1 are formed around the P+ semiconductor region 73-1 and the P- semiconductor region 74-1, surrounding these regions. The P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-1 is arranged above the P+ semiconductor region 73-1 (on the side of the on-chip lens 62) so as to cover the P+ semiconductor region 73-1, and the N- semiconductor region 72-1 is arranged above the N+ semiconductor region 71-1 (on the side of the on-chip lens 62) so as to cover the N+ semiconductor region 71-1. In other words, the P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are arranged on the multilayer wiring layer 811 side within the substrate 61, while the N- semiconductor region 72-1 and the P- semiconductor region 74-1 are arranged on the side of the on-chip lens 62 within the substrate 61. Furthermore, between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1, a separation portion 75-1 is formed by an oxide film or the like to separate these regions.

[0534] In the signal extraction section 65-2, an N+ semiconductor region 71-2 and an N- semiconductor region 72-2 are formed around the P+ semiconductor region 73-2 and the P- semiconductor region 74-2, surrounding the P+ semiconductor region 73-2 and the P- semiconductor region 74-2. The P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-2 is arranged above the P+ semiconductor region 73-2 (on the side of the on-chip lens 62) so as to cover the P+ semiconductor region 73-2, and the N- semiconductor region 72-2 is arranged above the N+ semiconductor region 71-2 (on the side of the on-chip lens 62) so as to cover the N+ semiconductor region 71-2. In other words, the P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are arranged on the multilayer wiring layer 811 side within the substrate 61, while the N- semiconductor region 72-2 and the P- semiconductor region 74-2 are arranged on the side of the on-chip lens 62 within the substrate 61. Furthermore, a separation portion 75 - 2 is also formed between the N + semiconductor region 71 - 2 and the P + semiconductor region 73 - 2 by an oxide film or the like to separate these regions.

[0535] The oxide film 64 is also formed between the N+ semiconductor region 71-1 of the signal extraction portion 65-1 of a given pixel 51 and the N+ semiconductor region 71-2 of the signal extraction portion 65-2 of the adjacent pixel 51, which is a boundary region between adjacent pixels 51.

[0536] On the light incident surface side of the substrate 61 ( Figure 36 and Figure 37 A fixed charge film 66 is formed at the interface of the upper surface in the middle.

[0537] like Figure 36 As shown, when the on-chip lens 62 formed for each pixel on the light incident surface side of the substrate 61 is divided in the height direction into a raised portion 821 whose thickness increases uniformly throughout the entire pixel and a curved surface portion 822 whose thickness varies depending on the position within the pixel, the thickness of the raised portion 821 is formed to be thinner than the thickness of the curved surface portion 822. The thicker the raised portion 821, the more easily obliquely incident light is reflected by the inter-pixel light shielding film 63. Therefore, by thinning the raised portion 821, even obliquely incident light can be taken into the substrate 61. Furthermore, the thicker the curved surface portion 822, the more effectively it can focus incident light at the center of the pixel.

[0538] A multilayer wiring layer 811 is formed on the side of the substrate 61 opposite to the light incident surface where the on-chip lens 62 is formed for each pixel. In other words, the substrate 61 as a semiconductor layer is arranged between the on-chip lens 62 and the multilayer wiring layer 811. The multilayer wiring layer 811 is composed of five layers of metal films M1 to M5 and an interlayer insulating film 812 therebetween. Figure 36In the figure, the outermost metal film M5 among the five metal films M1 to M5 of the multilayer wiring layer 811 is located in an invisible position because it is not shown in the figure, but it is located in the position from which it is connected. Figure 36 The cross-sectional view of the cross-sectional view observed in different directions is Figure 37 .

[0539] like Figure 37 As shown, the pixel transistor Tr is formed in the pixel boundary region of the interface portion between the multilayer wiring layer 811 and the substrate 61. The pixel transistor Tr is Figure 31 and Figure 32 Any one of the transfer transistor 721 , reset transistor 723 , amplification transistor 724 , and selection transistor 725 shown.

[0540] The metal film M1 closest to the substrate 61 among the five metal films M1 to M5 of the multilayer wiring layer 811 includes a power supply line 813 for supplying a power supply voltage, a voltage application wiring 814 for applying a predetermined voltage to the P+ semiconductor region 73-1 or 73-2, and a reflective member 815 as a member for reflecting incident light. Figure 36 In the metal film M1, the wiring other than the power line 813 and the voltage application wiring 814 becomes the reflective component 815. In order to prevent the drawings from becoming complicated, some of the drawings are omitted. The reflective component 815 is a virtual wiring set for the purpose of reflecting incident light, which is equivalent to Figure 28 The reflecting member 815 is arranged below the N+ semiconductor regions 71-1 and 71-2 in such a manner as to overlap with the N+ semiconductor regions 71-1 and 71-2 of the charge detection portion when viewed from above. Figure 28 In the case where the reflecting member 631 of the fourteenth embodiment is replaced with the light shielding member 631' of the fifteenth embodiment, Figure 36 Part of the reflective component 815 becomes the light shielding component 631'.

[0541] Furthermore, in the metal film M1, a charge extraction wiring ( ) connecting the N+ semiconductor region 71 and the transfer transistor 721 is formed in order to transfer the charge accumulated in the N+ semiconductor region 71 to the FD 722. Figure 36 (not shown in the figure).

[0542] In this example, the reflective member 815 (reflective member 631 ) and the charge extraction wiring are arranged in the same layer of the metal film M1 , but they are not necessarily limited to being arranged in the same layer.

[0543] The metal film M2, the second layer from the substrate 61 side, includes, for example, a voltage application wiring 816 connected to the voltage application wiring 814 of the metal film M1, a control line 817 for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, a drive signal FDG, and the like, and a ground line. Furthermore, an FD 722B and an additional capacitor 727A are formed in the metal film M2.

[0544] In the metal film M3 that is the third layer from the substrate 61 side, for example, the vertical signal line 29 , a VSS wiring for shielding, and the like are formed.

[0545] In the metal films M4 and M5 of the fourth and fifth layers from the substrate 61 side, for example, voltage supply lines 741-1 and 741-2 are formed for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 as the voltage applying portion of the signal extraction portion 65. Figure 33 、 Figure 34 ).

[0546] In addition, the planar configuration of the five metal films M1 to M5 of the multilayer wiring layer 811 will be referred to. Figure 42 and Figure 43 This will be described later.

[0547] (Cross-sectional Structure of Multiple Pixels in Ninth Embodiment)

[0548] Figure 38 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 22 FIG. 1 is a cross-sectional view of a pixel structure according to a ninth embodiment.

[0549] Figure 22 The ninth embodiment shown is a pixel structure in which a long groove (trench) is formed in the pixel boundary portion within the substrate 61 from the back side (light incident surface) of the substrate 61 to a predetermined depth and a light shielding film is buried to form a separation area 441.

[0550] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0551] (Cross-sectional Structure of Multiple Pixels in Modification 1 of Ninth Embodiment)

[0552] Figure 39 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 23 FIG. 1 is a cross-sectional view of a pixel structure according to a first modification of the ninth embodiment.

[0553] Figure 23The modified example 1 of the ninth embodiment shown has a pixel structure in which a separation region 471 penetrating the entire substrate 61 is provided at a pixel boundary portion within the substrate 61 .

[0554] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0555] (Cross-sectional Structure of Multiple Pixels in Sixteenth Embodiment)

[0556] Figure 40 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 29 A cross-sectional view of a pixel structure according to a sixteenth embodiment is shown.

[0557] Figure 29 The sixteenth embodiment shown has a structure in which a P-well region 671 is provided in the central portion of the inner side of the substrate 61, on the side opposite to the light incident surface, that is, the lower side in the figure. Furthermore, a separation portion 672-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 is formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. The P-well region 671 is also formed at the pixel boundary portion of the lower side of the substrate 61.

[0558] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0559] (Cross-sectional Structure of Multiple Pixels in Tenth Embodiment)

[0560] Figure 41 It is expressed for multiple pixels without omitting multiple wiring layers. Figure 24 FIG. 1 is a cross-sectional view of a pixel structure according to a tenth embodiment.

[0561] Figure 24 The tenth embodiment shown has a pixel structure in which a thick substrate 501 is provided instead of the substrate 61 .

[0562] The other structures including the signal extraction parts 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are similar to Figure 36 The structures shown are the same.

[0563] (Example of Planar Arrangement of Five-Layer Metal Films M1 to M5)

[0564] Next, refer to Figure 42 and Figure 43 right Figures 36 to 41An example of a planar arrangement of five metal films M1 to M5 of the multilayer wiring layer 811 will be described.

[0565] Figure 42 A represents a planar configuration example of the first metal film M1 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0566] Figure 42 B shows a planar arrangement example of the second metal film M2 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0567] Figure 42 C represents a planar configuration example of the third metal film M3 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0568] Figure 43 A represents a planar configuration example of the fourth metal film M4 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0569] Figure 43 B shows a planar configuration example of the fifth metal film M5 among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0570] In addition, Figure 42 A to C and Figure 43 In A and B, the dotted line represents the area of pixel 51, and the Figure 11 The regions of the octagonal signal extraction portions 65-1 and 65-2 are shown.

[0571] exist Figure 42 A to C and Figure 43 In A and B of FIG. 1 , the longitudinal direction of the drawing is the vertical direction of the pixel array section 20 , and the lateral direction of the drawing is the horizontal direction of the pixel array section 20 .

[0572] like Figure 42 As shown in FIG. 1A , a reflective member 631 that reflects infrared light is formed on the metal film M1 that is the first layer of the multilayer wiring layer 811. In the region of the pixel 51, two reflective members 631 are formed with respect to the signal extraction portions 65-1 and 65-2, respectively. The two reflective members 631 of the signal extraction portion 65-1 are formed symmetrically with respect to the two reflective members 631 of the signal extraction portion 65-2 with respect to the vertical direction.

[0573] Furthermore, a pixel transistor wiring region 831 is provided between the reflective members 631 of adjacent pixels 51 in the horizontal direction. Wiring is formed in the pixel transistor wiring region 831 to connect the pixel transistors Tr such as the transfer transistor 721, the reset transistor 723, the amplifier transistor 724, or the select transistor 725. The wiring for the pixel transistors Tr is also formed symmetrically in the vertical direction with respect to the center line (not shown) between the two signal extraction units 65-1 and 65-2.

[0574] Furthermore, wiring such as a ground line 832, a power line 833, and a ground line 834 is formed between the reflective members 631 of adjacent pixels 51 in the vertical direction. These wirings are also formed symmetrically in the vertical direction with respect to the midline between the two signal extraction units 65-1 and 65-2.

[0575] In this way, the first metal film M1 is symmetrically arranged in the region on the signal extraction portion 65-1 side and the region on the signal extraction portion 65-2 side within the pixel. This allows for evenly adjusting the wiring load in the signal extraction portions 65-1 and 65-2. This reduces driving variations between the signal extraction portions 65-1 and 65-2.

[0576] In the first metal film M1, a large-area reflective member 631 is formed below the signal extraction portions 65-1 and 65-2 formed on the substrate 61. This allows infrared light that enters the substrate 61 via the on-chip lens 62 but passes through the substrate 61 without undergoing photoelectric conversion to be reflected by the reflective member 631 and re-enters the substrate 61. This increases the amount of infrared light that undergoes photoelectric conversion within the substrate 61, thereby improving the quantum efficiency (QE), or in other words, the sensitivity of the pixel 51 to infrared light.

[0577] On the other hand, in the first metal film M1, by disposing a light shielding member 631' in the same region as the reflective member 631 instead of the reflective member 631, infrared light that enters the substrate 61 from the light incident surface via the on-chip lens 62, passes through the substrate 61 without undergoing photoelectric conversion, and is prevented from being scattered in the wiring layer and incident on nearby pixels. This prevents erroneous light detection in nearby pixels.

[0578] like Figure 42 As shown in FIG. 8B , in the metal film M2 serving as the second layer of the multilayer wiring layer 811, a control line region 851 is provided between the signal extraction portions 65-1 and 65-2. Control lines 841 to 844, etc., which transmit predetermined signals in the horizontal direction, are formed in the control line region 851. The control lines 841 to 844 are, for example, lines that transmit the drive signal TRG, the drive signal RST, the select signal SEL, or the drive signal FDG.

[0579] By arranging the control line region 851 between the two signal extraction sections 65, the influence on the signal extraction sections 65-1 and 65-2 becomes equal, and the driving variation between the signal extraction sections 65-1 and 65-2 can be reduced.

[0580] Furthermore, a capacitor region 852, where FD 722B and additional capacitor 727A are formed, is located in a predetermined region of the second metal film M2, separate from the control line region 851. In capacitor region 852, the metal film M2 is patterned into a comb-like shape to form FD 722B and additional capacitor 727A.

[0581] By disposing the FD 722B or the additional capacitor 727A in the second-layer metal film M2 , the pattern of the FD 722B or the additional capacitor 727A can be freely arranged according to desired wiring capacitance in design, thereby improving the degree of design freedom.

[0582] like Figure 42 As shown in FIG. 3 , in the metal film M3 serving as the third layer of the multilayer wiring layer 811, at least a vertical signal line 29 is formed for transmitting the pixel signal output from each pixel 51 to the column processing unit 23. To increase the readout speed of the pixel signal, three or more vertical signal lines 29 can be arranged for one pixel column. In addition to the vertical signal line 29, a shielded wiring can also be arranged to reduce coupling capacitance.

[0583] In the fourth and fifth metal films M4 and M5 of the multilayer wiring layer 811 , voltage supply lines 741 - 1 and 741 - 2 are formed for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73 - 1 and 73 - 2 of the signal extraction portion 65 of each pixel 51 .

[0584] Figure 43 The metal films M4 and M5 shown in A and B represent the use of Figure 33 A shows the case of the voltage supply line 741 of the first configuration example.

[0585] The voltage supply line 741-1 of the metal film M4 is connected to the voltage applying wiring 814 (eg, Figure 36 ) is connected to the voltage applying wiring 814 and the P+ semiconductor region 73-1 of the signal taking-out portion 65-1 of the pixel 51. Similarly, the voltage supply line 741-2 of the metal film M4 is connected to the voltage applying wiring 814 (for example, Figure 36 ) is connected, and the voltage applying wiring 814 is connected to the P+ semiconductor region 73-2 of the signal taking-out portion 65-2 of the pixel 51.

[0586] The voltage supply lines 741-1 and 741-2 of the metal film M5 are connected to the tap driver 21 in the periphery of the pixel array unit 20. The voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 are connected at predetermined positions on both metal films in a planar region via a through-hole (not shown). A predetermined voltage MIX0 or MIX1 from the tap driver 21 is transmitted through the voltage supply lines 741-1 and 741-2 of the metal film M5, supplied to the voltage supply lines 741-1 and 741-2 of the metal film M4, and then supplied from the voltage supply lines 741-1 and 741-2 to the voltage application wiring 814 of the metal film M1 via the metal films M3 and M2.

[0587] By setting the light receiving element 1 as a back-illuminated CAPD sensor, for example Figure 43 As shown in A and B of FIG, the voltage supply lines 741-1 and 741-2 for applying a predetermined voltage MIX0 or MIX1 to the signal extraction unit 65 of each pixel 51 can be arranged in a vertical direction, and the wiring width and layout of the drive wiring can be freely designed. In addition, wiring suitable for high-speed driving and wiring that takes load reduction into consideration can be achieved.

[0588] (Example of Planar Arrangement of Pixel Transistors)

[0589] Figure 44 Yes Figure 42 A is a plan view showing the overlap between the first metal film M1 and the polysilicon layer formed thereon, such as the gate electrode of the pixel transistor Tr.

[0590] Figure 44 A is to make Figure 44 The metal film M1 of C Figure 44 The top view of the polysilicon layer of B coincides with the top view of Figure 44 B is a top view of only the polysilicon layer. Figure 44 C is a top view of only the metal film M1. Figure 44 The top view of the metal film M1 of C and Figure 42 The same top view as shown in A, but with hatching omitted.

[0591] As reference Figure 42 As described in FIG. 1A , a pixel transistor wiring region 831 is formed between the reflective components 631 of each pixel.

[0592] The pixel transistors Tr corresponding to the signal taking-out sections 65-1 and 65-2 are, for example, Figure 44 It is configured in the pixel transistor wiring area 831 as shown in B.

[0593] exist Figure 44In B, with the middle line (not shown) of the two signal taking-out parts 65-1 and 65-2 as a reference, the gate electrodes of reset transistors 723A and 723B, transfer transistors 721A and 721B, switching transistors 728A and 728B, selection transistors 725A and 725B, and amplification transistors 724A and 724B are formed from the side close to the middle line.

[0594] connect Figure 44 The wiring between the pixel transistors Tr of the metal film M1 shown in C is also formed symmetrically in the vertical direction with respect to the middle line (not shown) between the two signal extraction portions 65-1 and 65-2.

[0595] In this way, by symmetrically arranging the plurality of pixel transistors Tr in the pixel transistor wiring region 831 in the region on the signal extraction section 65-1 side and the region on the signal extraction section 65-2 side, driving variations between the signal extraction sections 65-1 and 65-2 can be reduced.

[0596] (Modification of Reflection Member 631)

[0597] Next, refer to Figure 45 and Figure 46 A modification of the reflective member 631 formed on the metal film M1 will be described.

[0598] In the above example, if Figure 42 As shown in FIG. 1A , a large-area reflective member 631 is arranged in a region surrounding the signal extraction portion 65 within the pixel 51 .

[0599] In contrast, the reflective member 631 is, for example, Figure 45 As shown in Figure A, a grid-shaped pattern can also be used. Forming the reflective component 631 in a grid-shaped pattern eliminates pattern anisotropy and reduces the XY anisotropy of the reflective capability. In other words, forming the reflective component 631 in a grid-shaped pattern reduces the reflection of incident light in a biased area, facilitating isotropic reflection, thereby improving ranging accuracy.

[0600] Alternatively, in addition, the reflective member 631 may be, for example, Figure 45 As shown in FIG. 1B , the reflective member 631 may be arranged in a stripe pattern. By forming the reflective member 631 in a stripe pattern, the pattern of the reflective member 631 can also be used as a wiring capacitor, thereby achieving a structure that maximizes the dynamic range.

[0601] in addition, Figure 45 B is an example of a vertical stripe shape, but a horizontal stripe shape may also be used.

[0602] Alternatively, in addition, the reflective member 631 may be, for example, Figure 45 As shown in FIG. 3 , the reflective member 631 is disposed only in the center region of the pixel, more specifically, only between the two signal extraction units 65. Thus, by forming the reflective member 631 in the center region of the pixel instead of forming the reflective member 631 at the pixel ends, the reflective member 631 can improve the sensitivity of the center region of the pixel, and can suppress the component reflected toward adjacent pixels when oblique light is incident, thereby achieving a structure that prioritizes suppression of crosstalk.

[0603] In addition, the reflective member 631 is, for example, Figure 46 As shown in A, a part of the pattern may be arranged in a comb-tooth shape, thereby allocating a part of the metal film M1 to the wiring capacitance of the FD722 or the additional capacitor 727. Figure 46 In Figure A, the comb-teeth shape within the solid circled regions 861 to 864 constitutes at least a portion of the FD 722 or the additional capacitor 727. The FD 722 or the additional capacitor 727 can also be appropriately separated and arranged in the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflective member 631, the FD 722, or the additional capacitor 727.

[0604] Figure 46 B shows the pattern of the metal film M1 without the reflective member 631. To increase the amount of infrared light photoelectrically converted in the substrate 61 and improve the sensitivity of the pixel 51, the reflective member 631 is preferably provided, but it is also possible to adopt a structure without the reflective member 631.

[0605] Figure 45 and Figure 46 The arrangement example of the reflecting member 631 shown can also be applied to the light shielding member 631 ′.

[0606] (Example of substrate structure of light-receiving element)

[0607] Figure 1 The light receiving element 1 can be used Figure 47 Any one of the substrate structures A to C.

[0608] Figure 47 A shows an example in which the light receiving element 1 is constituted by a semiconductor substrate 911 and a supporting substrate 912 thereunder.

[0609] In this case, a pixel array region 951 corresponding to the pixel array unit 20 , a control circuit 952 for controlling each pixel in the pixel array region 951 , and a logic circuit 953 including a signal processing circuit for pixel signals are formed on the upper semiconductor substrate 911 .

[0610] The control circuit 952 includes the aforementioned tap driving unit 21, vertical driving unit 22, horizontal driving unit 24, and the like. The logic circuit 953 includes a column processing unit 23 that performs A / D conversion processing on pixel signals, a signal processing unit 31 that performs distance calculation processing based on the ratio of pixel signals obtained by two or more signal extraction units 65 within a pixel, calibration processing, and the like.

[0611] Alternatively, in addition, the light receiving element 1 may be Figure 47 As shown in FIG. 1B , a structure may be formed in which a first semiconductor substrate 921 having a pixel array region 951 and a control circuit 952 and a second semiconductor substrate 922 having a logic circuit 953 are stacked. Furthermore, the first semiconductor substrate 921 and the second semiconductor substrate 922 are electrically bonded, for example, via a through hole or a Cu-Cu metal bond.

[0612] Alternatively, in addition, the light receiving element 1 may be Figure 47 As shown in FIG. C, a first semiconductor substrate 931 having only a pixel array region 951 formed therein and a second semiconductor substrate 932 having a regional control circuit 954 formed therein, which includes a control circuit for controlling each pixel and a signal processing circuit for processing pixel signals, arranged per pixel or per region of multiple pixels, may be stacked. The first semiconductor substrate 931 and the second semiconductor substrate 932 are electrically bonded, for example, via a through-hole or a Cu-Cu metal bond.

[0613] like Figure 47 By providing a control circuit and a signal processing circuit per pixel or per region, as in the case of the light-receiving element 1 of FIG. 1 , it is possible to set the optimal drive timing and gain for each divided control unit, thereby obtaining optimized distance information regardless of distance and reflectivity. Furthermore, by driving only a portion of the pixel array region 951 rather than the entire region to calculate distance information, power consumption can be reduced depending on the operating mode.

[0614] (Eighteenth embodiment)

[0615] (Structural Example of Pixel)

[0616] Next, based on the first to seventeenth embodiments described above, other embodiments will be further described.

[0617] In the thirteenth embodiment, referring to Figure 27 An example is described in which one of the two signal extraction sections 65 provided in the pixel 51 is set as an active tap and the other is set as a passive tap, and a negative bias is applied to the light incident surface of the substrate 61 .

[0618] In this case, by applying a negative bias voltage, the electric field is strengthened, which can improve the efficiency of electron extraction. However, if no voltage is applied to the P+ semiconductor region 73 of the signal extraction part 65 on the side of the active tap within the pixel 51 and it is set in a floating state, power consumption can be reduced.

[0619] In this case, the cross-sectional structure of the pixel 51 is as follows: Figure 48 shown.

[0620] Figure 48 With the above Figure 36 Etc. also show that Figure 11 The BB' line corresponds to a cross-sectional view of multiple pixels.

[0621] In addition, Figure 48 In, with Figure 36 The corresponding parts are marked with the same figure marks, and the description of the parts is appropriately omitted.

[0622] If Figure 48 The structure of the pixel 51 shown is similar to Figure 36 Compared with the structure of the pixel 51 shown in FIG. Figure 48 In the pixel 51 shown, at the boundary (pixel boundary) of the adjacent pixels 51, there are newly formed: a through electrode 1001 that penetrates the P-type semiconductor layer, i.e., the substrate 61, to separate the adjacent pixels 51; and an insulating film 1002 that covers the periphery (side wall) of the through electrode 1001.

[0623] The through-electrode 1001 is formed of a metal material such as tungsten (W), aluminum (Al), copper (Cu), or polysilicon, etc. The insulating film 1002 is formed of an oxide film (SiO 2 ), for example.

[0624] The through-electrode 1001 is formed at the boundary portion of the pixel 51 and functions as a pixel separation portion that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Furthermore, it can be understood that the through-electrode 1001 including the insulating film 1002 at the periphery and the insulating film 1002 constitute the pixel separation portion.

[0625] The through-electrode 1001 is electrically connected to a voltage applying wiring 1011 of the metal film M1 , which is the metal film closest to the substrate 61 in the multilayer wiring layer 811 , and a predetermined bias (voltage) is applied to the through-electrode 1001 via the voltage applying wiring 1011 .

[0626] Here, the bias voltage applied to the through-electrode 1001 is set to a voltage different from the voltage applied to the P+ semiconductor region 73 of the signal extraction section 65 serving as an active tap. More specifically, the bias voltage applied to the through-electrode 1001 is set to, for example, a voltage of 0 V or less, that is, a negative bias voltage. Thus, the through-electrode 1001, which is negatively biased, can function as a voltage applying section.

[0627] By forming a groove from the surface side or back side of the substrate 61 to the opposite side substrate surface using dry etching, etc., after forming the insulating film 1002, polysilicon or metal material to become the through electrode 1001 is buried, thereby forming the through electrode 1001 and the insulating film 1002.

[0628] By providing the through-electrode 1001 penetrating the substrate 61 in this manner, it is possible to strengthen the electric field in the direction parallel to the surface of the substrate 61 .

[0629] In addition, Figure 48 In the illustrated pixel 51, the two signal extraction sections 65 alternately function as active taps during the accumulation of charges generated by photoelectric conversion on the substrate 61. Furthermore, while one signal extraction section 65 in the pixel 51 functions as an active tap, the P+ semiconductor region 73 of the other signal extraction section 65 is in a floating state.

[0630] With this arrangement, a current corresponding to the negative bias of the through-electrode 1001 flows in the substrate 61 , but a current due to the potential difference between one signal extraction section 65 and the other signal extraction section 65 as active taps does not flow.

[0631] This reduces the amount of current (the total amount of hole current) generated in the substrate 61, compared to a case where a voltage such as 0 V is applied to the P+ semiconductor region 73 of the other signal extraction section 65 when one signal extraction section 65 functions as an active tap. Consequently, power consumption in the substrate 61 can be reduced.

[0632] Furthermore, when the signal extraction section 65, which is not an active tap, is in a floating state, the efficiency of charge (electron) transfer can be improved compared to when a voltage such as 0V is applied to the signal extraction section 65, enabling highly accurate distance detection. In other words, the characteristics of the CAPD sensor can be improved. This is because when the signal extraction section 65, which is not an active tap, is in a floating state, no electric field is generated between the two signal extraction sections 65, resulting in a shorter path for charges (electrons) to travel to the N+ semiconductor region 71 of the signal extraction section 65, which is the active tap.

[0633] (Equivalent Circuit Structure Example of Pixel)

[0634] When the signal extraction unit 65 which is not an active tap is placed in a floating state as described above, the equivalent circuit of the pixel 51 is as follows. Figure 49 In addition, Figure 49 In, with Figure 1 or Figure 31 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0635] Figure 49 The equivalent circuit structure of the pixel 51 shown is as follows: Figure 31 The equivalent circuit of the pixel 51 shown in the figure has a structure in which a transistor 1041A and a transistor 1041B are newly provided.

[0636] exist Figure 49 In the illustrated example, a transistor 1041A is provided between the P+ semiconductor region 73 - 1 and the voltage supply line 30 , and a transistor 1041B is provided between the P+ semiconductor region 73 - 2 and the voltage supply line 30 .

[0637] More specifically, for example, a semiconductor region 73-1 is provided between the P+ semiconductor region 73-1 and the transistor 1041A. Figure 48 The voltage applying wiring 814 or the voltage applying wiring 816 is shown. Similarly, for example, the voltage applying wiring 814 or the voltage applying wiring 816 is provided between the P+ semiconductor region 73-2 and the transistor 1041B.

[0638] In the following description, when there is no need to particularly distinguish between the transistor 1041A and the transistor 1041B, they are simply referred to as the transistor 1041 .

[0639] The transistor 1041A and the transistor 1041B are controlled by the tap driving unit 21 and function as switches.

[0640] That is, the tap driving unit 21 activates the driving signal (voltage) supplied to the gate electrode of the transistor 1041 to turn on the transistor 1041 (conductive state), thereby applying a desired voltage such as 1.5V or 0V to the P+ semiconductor region 73 .

[0641] In contrast, the tap driving unit 21 inactivates the driving signal (voltage) supplied to the gate electrode of the transistor 1041, thereby turning off the transistor 1041 (non-conducting state), thereby electrically disconnecting the P+ semiconductor region 73 from the voltage supply line 30. Consequently, the P+ semiconductor region 73 is placed in a floating state.

[0642] Note that the transistor 1041 may be driven to be turned on and off by the vertical driving section 22 instead of the tap driving section 21 .

[0643] (Pixel Driving Example)

[0644] Next, Figure 48 An example of driving the pixel 51 shown will be described.

[0645] During the accumulation of the charge generated by the photoelectric conversion on the substrate 61, the tap driving unit 21 performs, for example, Figure 50 The driving of the signal taking-out section 65 is controlled as shown.

[0646] exist Figure 50 In the figure, the portion indicated by arrow Q11 represents voltage MIX0 applied to P+ semiconductor region 73-1 of signal extraction section 65-1, and the portion indicated by arrow Q12 represents voltage MIX1 applied to P+ semiconductor region 73-2 of signal extraction section 65-2. In particular, the shaded portions of voltage MIX0 and voltage MIX1 indicated by arrows Q11 and Q12 represent a floating state.

[0647] Furthermore, the portion indicated by arrow Q13 represents a voltage applied to the through-electrode 1001 serving as a voltage application portion, that is, a bias voltage applied to the light incident surface (back surface).

[0648] In this example, as indicated by arrow Q13 , a constant voltage of 0 V or less, that is, a constant negative bias voltage is continuously applied to the through-electrode 1001 as a voltage application portion.

[0649] On the other hand, in the P+ semiconductor region 73 - 1 , a state in which a positive voltage such as 1.5 V is applied as the voltage MIX0 and a floating state are alternately repeated.

[0650] Specifically, when the tap driver 21 sets the signal extraction unit 65-1 as an active tap, the transistor 1041A is turned on, and a positive voltage of 1.5 V or the like is applied to the P+ semiconductor region 73-1. Furthermore, when the tap driver 21 sets the signal extraction unit 65-1 as an inactive tap, the transistor 1041A is turned off, and the P+ semiconductor region 73-1 is placed in a floating state.

[0651] Similarly, in the P+ semiconductor region 73 - 2 , a state in which a positive voltage such as 1.5 V is applied as the voltage MIX1 and a floating state are alternately repeated.

[0652] In particular, when the tap driver 21 applies a positive voltage to the P+ semiconductor region 73-1, the P+ semiconductor region 73-2 is placed in a floating state, and when a positive voltage is applied to the P+ semiconductor region 73-2, the P+ semiconductor region 73-1 is placed in a floating state. Such a tap driver 21 can function as a voltage control unit that controls the application of voltage to the P+ semiconductor region 73.

[0653] Furthermore, the floating mode and the normal mode can be switched appropriately by the tap driving unit 21 .

[0654] Here, the so-called floating mode means: Figure 50 As described above, this is a mode in which the P+ semiconductor region 73 of the signal extraction portion 65 that is not an active tap is placed in a floating state.

[0655] That is, in the floating mode, a voltage of 1.5 V or the like is applied to the P+ semiconductor region 73 of the signal extraction portion 65 serving as an active tap, so that the P+ semiconductor region 73 of the signal extraction portion 65 not serving as an active tap is placed in a floating state, and a negative bias is applied to the through-electrode 1001 .

[0656] The normal mode refers to a mode in which the P+ semiconductor region 73 of the signal extraction portion 65 that is not an active tap is not placed in a floating state.

[0657] That is, in normal mode, a voltage of 1.5 V or the like is applied to the P+ semiconductor region 73 of the signal extraction portion 65 serving as an active tap, and a voltage of 0 V or the like is applied to the P+ semiconductor region 73 of the signal extraction portion 65 serving as a passive tap, which is not an active tap. That is, at each moment, voltage MIX1 and voltage MIX0 are different voltages.

[0658] Furthermore, in the normal mode, a negative bias may be applied to the through-electrode 1001, or the through-electrode 1001 may be in a floating state without applying a negative bias. For example, the negative bias applied to the through-electrode 1001 may be the same as the voltage applied to the P+ semiconductor region 73 of the passive tap.

[0659] The tap driving unit 21 can switch the mode as appropriate to perform driving in either the above-described floating mode or the normal mode.

[0660] (Variation 1 of the Eighteenth Embodiment)

[0661] (Structural Example of Pixel)

[0662] Furthermore, when a negative bias is applied to the substrate 61 to float the P+ semiconductor region 73 of the signal extraction portion 65 which is not an active tap, the electric field in the depth direction (Z direction) perpendicular to the surface of the substrate 61 can be strengthened.

[0663] In this case, the cross-sectional structure of the pixel 51 is, for example, as shown in FIG. Figure 51 shown.

[0664] Figure 51 With the above Figure 36 Etc. also show that Figure 11 The BB' line is equivalent to a cross-sectional view of multiple pixels. Figure 51 In, with Figure 48 The corresponding parts are marked with the same symbols, and the description of the parts is appropriately omitted.

[0665] If Figure 51 The structure of the pixel 51 shown is similar to Figure 48 Compared with the structure of the pixel 51 shown in FIG. Figure 51 In the illustrated pixel 51, a transparent electrode, namely a transparent conductive film 1071, is newly formed on the upper surface of the fixed charge film 66 formed on the light incident surface of the substrate 61. That is, the transparent conductive film 1071 is formed on the surface of the substrate 61 on the on-chip lens 62 side.

[0666] The transparent conductive film 1071 is connected to the through-electrode 1001 at the boundary of the pixel 51. As the transparent conductive film 1071, a material such as ITO (Indium-tin-oxide), ZnO, SnO, Cd2SnO4, or TiO2:Nb can be used.

[0667] The through-electrode 1001 is connected to the voltage applying wiring 1011. Therefore, when a negative bias is applied to the voltage applying wiring 1011, the negative bias is applied to the fixed charge film 66 via the through-electrode 1001 and the transparent conductive film 1071. Therefore, in this example, the through-electrode 1001 and the transparent conductive film 1071 function as a voltage applying unit.

[0668] exist Figure 51 In the example shown, Figure 48 In the same manner as in the example shown, the tap drive unit 21 refers to Figure 50 The signal taking-out unit 65 is driven as described above. Figure 51 In the illustrated example, the tap driving unit 21 can switch between a normal mode and a floating mode.

[0669] exist Figure 51 In the pixel 51 shown, since the transparent conductive film 1071 is formed on the upper surface of the fixed charge film 66, the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap) can be strengthened. Figure 48 Compared with the example shown, the electron extraction efficiency can be further improved.

[0670] Furthermore, if the fixed charge film 66 is not formed on the light incident surface of the substrate 61 in the pixel 51, an insulating film composed of an oxide film or the like can be formed on the light incident surface of the substrate 61, and a negative bias voltage can be applied to the insulating film via the through electrode 1001 and the transparent conductive film 1071. The insulating film is not limited to a single-layer film and may be a stacked film.

[0671] Furthermore, for Figure 51 While the example in which the transparent conductive film 1071 is electrically connected to the through-electrode 1001 is described, the transparent conductive film 1071 may be configured not to be electrically connected to the through-electrode 1001. In this case, a negative bias may be applied only to the transparent conductive film 1071. Furthermore, only the transparent conductive film 1071 may be provided without the through-electrode 1001.

[0672] (Nineteenth embodiment)

[0673] (Structural Example of Pixel)

[0674] In addition, when driving in floating mode, an inter-pixel shading portion for applying a bias voltage can be provided on each side of the pixel 51 so as to obtain a higher effect by enhancing the electric field from the side wall of the pixel 51, that is, enhancing the electric field in a direction parallel to the surface of the substrate 61.

[0675] In this case, for example Figure 52 As shown in FIG. 1 , a structure is formed in which an inter-pixel light shielding portion is formed between pixels 51. Figure 52 In, with Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0676] Figure 52 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0677] In this example, inter-pixel light shielding portions 1101 - 1 to 1101 - 4 are provided at the boundaries between the pixel 51 and other pixels 51 .

[0678] Specifically, an inter-pixel light shielding portion 1101 - 1 is provided at the upper boundary of the pixel 51 in the figure, and an inter-pixel light shielding portion 1101 - 2 is provided at the lower boundary of the pixel 51 in the figure.

[0679] That is, the inter-pixel light shielding portion 1101-1 is formed at the pixel boundary on the side of the signal extraction portion 65-1 in the direction in which the two signal extraction portions 65 in the pixel 51 are arranged. In contrast, the inter-pixel light shielding portion 1101-2 is formed at the pixel boundary on the side of the signal extraction portion 65-2 in the direction in which the two signal extraction portions 65 in the pixel 51 are arranged.

[0680] Furthermore, an inter-pixel light shielding portion 1101-3 is provided at the left boundary of the pixel 51 in the drawing, and an inter-pixel light shielding portion 1101-4 is provided at the right boundary of the pixel 51 in the drawing. That is, these inter-pixel light shielding portions 1101-3 and 1101-4 are formed at the pixel boundary in a direction perpendicular to the direction in which the two signal extraction portions 65 in the pixel 51 are arranged.

[0681] In the following, when there is no need to particularly distinguish between the inter-pixel light shielding portion 1101 - 1 to the inter-pixel light shielding portion 1101 - 4 , they are simply referred to as the inter-pixel light shielding portion 1101 .

[0682] These four inter-pixel light shielding portions 1101 are DTI (Deep Trench Isolation) trench structures that separate adjacent pixels 51. For example, the inter-pixel light shielding portions 1101 are formed of metal materials such as tungsten (W), aluminum (Al), copper (Cu), or polysilicon.

[0683] Here, the four inter-pixel light shielding portions 1101-1 to 1101-4 are electrically separated. Alternatively, for example, the inter-pixel light shielding portions 1101-3 and 1101-4 of a pixel 51 may be electrically connected to the inter-pixel light shielding portions 1101-3 and 1101-4 of other pixels 51 adjacent to the pixel 51 in the vertical direction in the figure.

[0684] For example, Figure 52 In the example shown, the inter-pixel light shielding portions 1101 - 1 to 1101 - 4 function as pixel separation portions that separate adjacent pixels 51 and also function as voltage application portions to which a voltage such as a negative bias is applied.

[0685] Specifically, for example, a constant voltage of 0 V or less, that is, a constant (fixed) negative bias voltage is always applied to the inter-pixel light shielding portion 1101 - 3 and the inter-pixel light shielding portion 1101 - 4 .

[0686] In addition, when the signal extraction unit 65-1 is an active tap, a voltage higher than the voltage around the inter-pixel light shielding unit 1101-1, for example, 1.5 V, is applied to the inter-pixel light shielding unit 1101-1 provided on the side of the signal extraction unit 65-1. In addition, the voltage applied to the inter-pixel light shielding unit 1101-1 can be set to be the same as the voltage MIX0.

[0687] In this manner, the electric field in the vicinity of the signal extraction portion 65 - 1 serving as an active tap can be further strengthened, thereby improving the efficiency of electron extraction.

[0688] On the other hand, when the signal extraction section 65-1 is not in an active tap state, that is, when the P+ semiconductor region 73-1 of the signal extraction section 65-1 is in a floating state, the inter-pixel light shielding section 1101-1 is also in a floating state.

[0689] In this way, in order to make the voltage applied to the inter-pixel light shielding portion 1101-1 the same as the voltage applied to the P+ semiconductor region 73-1, for example, as long as not only the P+ semiconductor region 73-1 but also the inter-pixel light shielding portion 1101-1 are connected to the P+ semiconductor region 73-1, the voltage applied to the inter-pixel light shielding portion 1101-1 is the same as the voltage applied to the P+ semiconductor region 73-1. Figure 49 The transistor 1041A shown is connected.

[0690] On the other hand, the voltage applied to the inter-pixel light shielding portion 1101-2 provided on the signal extraction portion 65-2 side only needs to be the same as the voltage applied to the P+ semiconductor region 73-2 of the signal extraction portion 65-2. In other words, the voltage applied to the inter-pixel light shielding portion 1101-2 only needs to be opposite to the voltage applied to the inter-pixel light shielding portion 1101-1.

[0691] Specifically, when a voltage of 1.5V or the like is applied to the inter-pixel light shielding portion 1101-1, the inter-pixel light shielding portion 1101-2 is in a floating state. Conversely, when the inter-pixel light shielding portion 1101-1 is in a floating state, a voltage of 1.5V or the like is applied to the inter-pixel light shielding portion 1101-2.

[0692] In order to control the voltage application state of the inter-pixel light shielding portion 1101-2, for example, not only the P+ semiconductor region 73-2 but also the inter-pixel light shielding portion 1101-2 can be connected to the P+ semiconductor region 73-2. Figure 49 The transistor 1041B shown is connected.

[0693] In addition, with Figure 52 The cross-sectional view of a plurality of pixels corresponding to the line DD' in the pixel 51 shown is as follows. Figure 53 In addition, Figure 53 In, with Figure 1 、 Figure 51 ,or Figure 52 The corresponding parts are marked with the same symbols and their descriptions are omitted as appropriate.

[0694] Figure 53 The structure of the pixel 51 shown mainly replaces Figure 51 The structure of the pixel 51 shown in FIG. 1 is different from that of the through electrode 1001 and the insulating film 1002 in that the inter-pixel light shielding portion 1101 and the insulating films 1131-1 and 1131-2 are provided. Figure 51The structure of the pixel 51 shown is different. In the following, when there is no need to distinguish between the insulating film 1131 - 1 and the insulating film 1131 - 2 , they are simply referred to as the insulating film 1131 .

[0695] exist Figure 53 In the example, the area outside the pixel array section 20 on the semiconductor substrate constituting the light receiving element 1 becomes the peripheral circuit section 1132. The pixel array section 20 is composed of an effective pixel area 1133 where a plurality of pixels 51 are arranged and an OPB pixel area 1134 surrounding the effective pixel area 1133.

[0696] In such Figure 53 The pixel array section 20 shown in FIG. 1 is not formed with the through electrode 1001, so a negative bias cannot be applied to the fixed charge film 66 via the through electrode 1001. Figure 53 In the example shown, a negative bias is supplied to the transparent conductive film 1071 from a voltage application wiring 1135 formed in the peripheral circuit section 1132 outside the pixel array section 20 via a through electrode 1136 , and a negative bias is applied to the fixed charge film 66 from the transparent conductive film 1071 .

[0697] That is, in Figure 53 In the illustrated example, a voltage application wiring 1135 is formed in the multilayer wiring layer 811 of the peripheral circuit portion 1132, which is located outside the pixel array portion 20, and a negative bias is supplied to the voltage application wiring 1135. Furthermore, a through-electrode 1136, whose outer periphery is covered by an insulating film 1137, is formed in the peripheral circuit portion 1132 of the substrate 61. The through-electrode 1136 is connected to the transparent conductive film 1071 at the light incident surface of the substrate 61.

[0698] In such a pixel 51, a negative bias voltage supplied from the voltage application wiring 1135 of the multilayer wiring layer 811 is applied to the fixed charge film 66 via the through electrode 1136 and the transparent conductive film 1071. This strengthens the electric field in the depth direction from the light incident surface of the substrate 61 toward the signal extraction portion 65 (tap).

[0699] In addition, although the example in which a negative bias is applied to the transparent conductive film 1071 is described here, a negative bias does not necessarily need to be applied to the transparent conductive film 1071 .

[0700] In addition, in the substrate 61, at the boundaries of adjacent pixels 51, there are formed: an inter-pixel shading portion 1101, which separates and shields the adjacent pixels 51 from the surface on the side of the P-type semiconductor layer, i.e., the multi-layer wiring layer 811 of the substrate 61, to a specified depth; and an insulating film 1131, which covers the outer periphery (side wall) of the inter-pixel shading portion 1101.

[0701] In particular, here, the inter-pixel light shielding portion 1101 - 1 is covered with the insulating film 1131 - 1 , and the inter-pixel light shielding portion 1101 - 2 is covered with the insulating film 1131 - 2 .

[0702] The insulating film 1131 is formed of, for example, an oxide film (SiO2). The inter-pixel light shielding portion 1101 functions as a pixel separator that separates the semiconductor layer (substrate 61) of adjacent pixels 51. Alternatively, the inter-pixel light shielding portion 1101, including the peripheral insulating film 1131, and the insulating film 1131 can be understood as constituting the pixel separator.

[0703] The inter-pixel light shielding portion 1101 - 1 and the inter-pixel light shielding portion 1101 - 2 are connected to the voltage applying wiring 1138 - 1 and the voltage applying wiring 1138 - 2 of the metal film M1 , which is the metal film closest to the substrate 61 in the multilayer wiring layer 811 .

[0704] More specifically, the inter-pixel light shielding portion 1101-1 is connected to the transistor 1041A via the voltage applying wiring 1138-1, etc., and the inter-pixel light shielding portion 1101-2 is connected to the transistor 1041B via the voltage applying wiring 1138-2, etc. Hereinafter, when there is no need to specifically distinguish between the voltage applying wiring 1138-1 and the voltage applying wiring 1138-2, they are simply referred to as the voltage applying wiring 1138.

[0705] By using dry etching or the like, a groove is formed from the surface side of the substrate 61 (the multi-layer wiring layer 811 side) to a predetermined depth. After forming the insulating film 1131, polysilicon or metal material to become the inter-pixel shading portion 1101 is buried, thereby forming the inter-pixel shading portion 1101 and the insulating film 1131.

[0706] Although only the inter-pixel light shielding portion 1101-1 and the inter-pixel light shielding portion 1101-2 are shown here, the inter-pixel light shielding portion 1101-3 and the inter-pixel light shielding portion 1101-4 also have the same structure as the inter-pixel light shielding portion 1101-1 and the inter-pixel light shielding portion 1101-2 described above. In other words, the surfaces of the inter-pixel light shielding portion 1101-3 and the inter-pixel light shielding portion 1101-4 are also covered with the insulating film 1131.

[0707] Here, the inter-pixel light shielding portion 1101 and the insulating film 1131 are formed to a predetermined depth from the front surface. However, these inter-pixel light shielding portions 1101 and the insulating film 1131 may be provided so as to penetrate the substrate 61 from the front surface to the back surface (light incident surface). In this case, for example, the inter-pixel light shielding portions 1101-3 and 1101-4 may be electrically connected to the transparent conductive film 1071.

[0708] Furthermore, the inter-pixel light shielding portion 1101 and the insulating film 1131 can be formed to a predetermined depth from the back side (light incident side) of the substrate 61 .

[0709] (Pixel Driving Example)

[0710] Next, Figure 52 An example of driving the pixel 51 shown will be described.

[0711] During the accumulation of the charge generated by the photoelectric conversion on the substrate 61, the tap driving unit 21 performs, for example, Figure 54 The driving of the signal taking-out section 65 is controlled as shown.

[0712] exist Figure 54 , the portion indicated by arrow Q21 represents the voltage MIX0 applied to the P+ semiconductor region 73-1 of the signal extraction unit 65-1 and the voltage applied to the inter-pixel light shielding portion 1101-1. In particular, the characters "DTIU" represent the inter-pixel light shielding portion 1101-1.

[0713] The portion indicated by arrow Q22 represents voltage MIX1 applied to the P+ semiconductor region 73-2 of the signal extraction unit 65-2 and voltage applied to the inter-pixel light shielding portion 1101-2. In particular, the characters "DTID" represent the inter-pixel light shielding portion 1101-2.

[0714] In addition, the oblique line portion in the portion indicated by the arrow Q21 and the arrow Q22 indicates a floating state.

[0715] The portion indicated by arrow Q23 represents a voltage (bias) applied to the transparent conductive film 1071, the inter-pixel light shielding portion 1101-3, and the inter-pixel light shielding portion 1101-4. In particular, the characters "DTILR" represent the inter-pixel light shielding portion 1101-3 and the inter-pixel light shielding portion 1101-4.

[0716] In this example, as indicated by arrow Q23 , a constant voltage of 0 V or less, that is, a constant negative bias voltage, is continuously applied to the transparent conductive film 1071 , the inter-pixel light shielding portion 1101 - 3 , and the inter-pixel light shielding portion 1101 - 4 .

[0717] Alternatively, different voltages may be applied to the transparent conductive film 1071 , the inter-pixel light shielding portion 1101 - 3 , and the inter-pixel light shielding portion 1101 - 4 .

[0718] On the other hand, in the P+ semiconductor region 73 - 1 and the inter-pixel light shielding portion 1101 - 1 , a state in which a positive voltage such as 1.5 V is applied and a floating state are repeated alternately.

[0719] Specifically, when the signal extraction unit 65 - 1 is set to an active tap, the tap driving unit 21 turns on the transistor 1041A and applies a positive voltage such as 1.5 V to the P + semiconductor region 73 - 1 and the inter-pixel light shielding unit 1101 - 1 .

[0720] Furthermore, when the signal extraction unit 65 - 1 is not in active tap mode, the tap driving unit 21 turns off the transistor 1041A and places the P + semiconductor region 73 - 1 and the inter-pixel light shielding unit 1101 - 1 in a floating state.

[0721] Similarly, in the P+ semiconductor region 73 - 2 and the inter-pixel light shielding portion 1101 - 2 , a state in which a positive voltage such as 1.5 V is applied and a floating state are repeated alternately.

[0722] In particular, when the tap driving unit 21 applies a positive voltage to the P+ semiconductor region 73-1 and the inter-pixel light shielding portion 1101-1, the P+ semiconductor region 73-2 and the inter-pixel light shielding portion 1101-2 are placed in a floating state. Conversely, when the tap driving unit 21 applies a positive voltage to the P+ semiconductor region 73-2 and the inter-pixel light shielding portion 1101-2, the P+ semiconductor region 73-1 and the inter-pixel light shielding portion 1101-1 are placed in a floating state.

[0723] In addition, when such a drive is performed, Figure 52 The pixel 51 shown Figure 52 In the pixel 51 adjacent to the upper side, an inter-pixel light shielding portion 1101-1 is provided adjacent to the signal extraction portion 65-2. Therefore, in such a pixel 51, the timing of applying a positive voltage and the timing of entering a floating state can be the same for the adjacent signal extraction portion 65-2 and the inter-pixel light shielding portion 1101-1. In this case, the timing of applying a positive voltage and the timing of entering a floating state are the same for the adjacent signal extraction portion 65-1 and the inter-pixel light shielding portion 1101-2. Furthermore, the inter-pixel light shielding portion 1101-1 and the inter-pixel light shielding portion 1101-2 can be provided adjacent to each other at the boundary between two pixels 51.

[0724] In addition, Figure 52 In the pixel 51 shown, the floating mode and the normal mode can be appropriately switched by the tap driving unit 21 .

[0725] By referring to Figure 54 The driving described above, similar to the eighteenth embodiment, can reduce current consumption and improve charge (electron) transfer efficiency, enabling high-precision distance detection. In other words, it can improve the characteristics of the CAPD sensor.

[0726] (Twentieth embodiment)

[0727] (Structural Example of Pixel)

[0728] Furthermore, in the eighteenth and nineteenth embodiments, examples are described in which the through-electrode 1001 and the transparent conductive film 1071 function as a voltage applying unit during driving in the floating mode. However, the through-electrode 1001 and the transparent conductive film 1071 do not need to be provided.

[0729] In this case, for example, Figure 55 As shown in FIG, a multilayer wiring layer 811 is provided, and the contact connected to the ground line is used as a voltage applying portion. Figure 55 In, with Figure 3 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0730] Figure 55 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0731] In this example, transistors are drawn at the left-right boundary of the pixel 51. Contacts 1161-1 to 1161-4 connected to the ground line 832, the ground line 834, and the like are provided at the left-right boundary of the pixel 51.

[0732] The contacts 1161 - 1 to 1161 - 4 are formed of a metal material such as copper (Cu). In the following, when there is no need to distinguish between the contacts 1161 - 1 to 1161 - 4 , they are simply referred to as contacts 1161 .

[0733] The contact 1161 is connected to a wiring having a constant voltage, such as the ground line 832, and can therefore be used as a voltage applying unit for applying a voltage to the substrate 61. Here, for example, a constant voltage such as 0V is always applied to the contact 1161.

[0734] Therefore, for example, a current flows between the signal extraction portion 65 serving as an active tap and the contact 1161 , and thus the efficiency of transferring electric charges (electrons) can be improved.

[0735] In addition, here, the example in which the contact 1161 functioning as the voltage applying portion is provided at the left and right boundaries in the figure in the pixel 51 is described. However, the contact 1161 functioning as the voltage applying portion may be provided at the upper and lower boundaries of the pixel 51 in the figure, or may be provided at the upper, lower, left, and right boundaries of the pixel 51 in the figure.

[0736] In addition, with Figure 55 The cross-sectional view of a plurality of pixels corresponding to the line EE' in the pixel 51 shown is as follows. Figure 56 In addition, Figure 56 In, with Figure 37 The corresponding parts are marked with the same figure marks and their descriptions are omitted as appropriate.

[0737] Figure 56 The structure of the pixel 51 shown is relative to Figure 37 The structure of the pixel 51 shown is a structure in which a contact 1161 is provided instead of a transistor. This is because the contact 1161 is provided at a cross-sectional position of the multilayer wiring layer 811 corresponding to the line EE', instead of a transistor.

[0738] In this example, contacts 1161 are formed at the boundary between adjacent pixels 51 in the multilayer wiring layer 811. Contacts 1161 are connected to the ground line of the metal film M1, etc. In particular, contacts 1161 are arranged at the boundary between the multilayer wiring layer 811 and the substrate 61, and P+ semiconductor regions 1191 are formed in portions adjacent to contacts 1161 within the substrate 61 so as to cover the portions of contacts 1161.

[0739] With such a structure, a constant voltage is always applied to the substrate 61 via the contact 1161 .

[0740] (Pixel Driving Example)

[0741] Next, Figure 55 An example of driving the pixel 51 shown will be described.

[0742] During the accumulation of the charge generated by the photoelectric conversion on the substrate 61, the tap driving unit 21 performs, for example, Figure 57 The driving of the signal taking-out section 65 is controlled as shown.

[0743] exist Figure 57 In the figure, the portion indicated by arrow Q31 represents voltage MIX0 applied to P+ semiconductor region 73-1 of signal extraction section 65-1, and the portion indicated by arrow Q32 represents voltage MIX1 applied to P+ semiconductor region 73-2 of signal extraction section 65-2. In particular, the shaded portions of voltage MIX0 and voltage MIX1 indicated by arrows Q31 and Q32 indicate a floating state.

[0744] In addition, the portion indicated by arrow Q33 represents the voltage applied to the contact 1161 , which is the voltage applying portion.

[0745] In this example, as indicated by arrow Q33 , a constant voltage such as 0 V is continuously applied to contact 1161 .

[0746] On the other hand, in the P+ semiconductor region 73 - 1 , a state in which a positive voltage such as 1.5 V is applied as the voltage MIX0 and a floating state are alternately repeated.

[0747] Specifically, when the signal extraction unit 65-1 is in the active tap state, the tap driver 21 turns on the transistor 1041A and applies a positive voltage of 1.5 V or the like to the P+ semiconductor region 73-1. Furthermore, when the signal extraction unit 65-1 is not in the active tap state, the tap driver 21 turns off the transistor 1041A and places the P+ semiconductor region 73-1 in a floating state.

[0748] Similarly, in the P+ semiconductor region 73 - 2 , a state in which a positive voltage such as 1.5 V is applied to the P+ semiconductor region 73 - 2 as the voltage MIX1 and a floating state are alternately repeated.

[0749] In particular, the tap driving unit 21 puts the P+ semiconductor region 73-2 into a floating state when a positive voltage is applied to the P+ semiconductor region 73-1, and puts the P+ semiconductor region 73-1 into a floating state when a positive voltage is applied to the P+ semiconductor region 73-2.

[0750] By referring to Figure 57 The driving described above can reduce current consumption and improve charge (electron) transfer efficiency, similarly to the eighteenth embodiment, enabling high-precision distance detection. In other words, it can improve the characteristics of the CAPD sensor.

[0751] Furthermore, in the twentieth embodiment, the tap driving unit 21 may be configured to switch between the floating mode and the normal mode as appropriate.

[0752] In addition, in the eighteenth to twentieth embodiments described above, for example, Figure 48 、 Figure 51 、 Figure 53 、 Figure 56 6 illustrates an example in which a reflective member 815 is provided on the multilayer wiring layer 811. Specifically, in this example, the reflective member 815 is provided so as to overlap the N+ semiconductor region 71 when viewed from above, that is, when viewed perpendicular to the surface of the substrate 61. However, a light shielding member 631' may be provided in place of the reflective member 815. In this case, the light shielding member 631' is provided so as to overlap the N+ semiconductor region 71 when viewed from above.

[0753] (Twenty-first embodiment)

[0754] (Structural Example of Pixel)

[0755] The substrate 61 and the multilayer wiring layer 811 constituting the pixel 51 are provided with structures such as an oxide film, a metal material, and a gate electrode.

[0756] Therefore, if the infrared light focused by the on-chip lens 62 and incident on the substrate 61 is reflected by these structures, the reflected light will enter the adjacent areas of other pixels 51, resulting in reduced pixel sensitivity or crosstalk. In addition, if crosstalk occurs, the resolution of the depth image generated by the light-receiving element 1 during distance measurement, that is, the distance measurement accuracy, will be reduced.

[0757] Therefore, in the present invention, by providing a pixel separator at the boundary of each pixel 51 to separate the light-receiving area of each pixel 51, pixel sensitivity can be improved and crosstalk can be suppressed. In other words, CAPD sensor characteristics such as sensitivity and ranging accuracy can be improved. The light-receiving area referred to here refers to the area within the substrate 61 where photoelectric conversion occurs.

[0758] Below, refer to Figures 58 to 93 An example of the structure of the pixel 51 for suppressing a decrease in pixel sensitivity and crosstalk will be described.

[0759] In addition, Figures 58 to 93 In, with Figure 3 、 Figure 36 、 Figure 37 ,or Figure 42 The corresponding parts are marked with the same reference numerals and their descriptions are omitted as appropriate. Figures 58 to 93 In the drawings, the same reference numerals are given to corresponding parts, and their descriptions are omitted as appropriate.

[0760] First, refer to Figures 58 to 60 The structure of the pixel 51 according to the twenty-first embodiment will be described.

[0761] Figure 58 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0762] In this example, a pixel separation portion 1221 is formed at the boundary portion of adjacent pixels 51 in a manner that surrounds the area of each pixel 51 when viewed from above, that is, the light-receiving area of the pixel 51, and functions as a pixel separation area that separates the area of the pixel 51 (light-receiving area).

[0763] A pixel transistor wiring region 831 is provided in a portion near a pixel boundary in the multilayer wiring layer 811 of the pixel 51 .

[0764] Furthermore, transistors and the like for driving the pixels 51 are formed at the boundary between the substrate 61 and the multilayer wiring layer 811 .

[0765] Specifically, for example, a reset transistor 723A connected to the N+ semiconductor region 71-1, a reset transistor 723B connected to the transfer transistor 721A and the N+ semiconductor region 71-2, and a transfer transistor 721B are formed at the boundary between the substrate 61 and the multilayer wiring layer 811.

[0766] When viewed from a direction perpendicular to the surface of the substrate 61, that is, in a plan view, transistors for driving the pixels 51 are arranged in the pixel transistor wiring region 831. Therefore, the pixel transistor wiring region 831 can be said to be a transistor region where transistors are formed in a plan view.

[0767] exist Figure 58 In the example shown, when viewed from a direction perpendicular to the surface of the substrate 61, the pixel separation unit 1221 is configured at a position offset from the transistor, etc., so that the configuration position of the transistor, etc. for driving the pixel 51 is different from the configuration position of the pixel separation unit 1221.

[0768] In other words, the pixel separation portion 1221 is provided in a region different from the pixel transistor wiring region 831 , that is, the transistor region, when viewed in a plan view.

[0769] Here, in Figure 59 as well as Figure 60 Shown in Figure 58 The cross section corresponding to the F1-F1' line and the cross section corresponding to the G1-G1' line.

[0770] Figure 59 as well as Figure 60 The structure of the pixel 51 shown is: no Figure 36 as well as Figure 37 The on-chip lens 62 and the fixed charge film 66 in the structure of the pixel 51 shown are replaced with a new structure including an on-chip lens 1251 , an oxide film 1252 , and a fixed charge film 1253 .

[0771] like Figure 59 As shown, in each pixel 51, an on-chip lens 1251 is arranged adjacent to the light incident surface side of the substrate 61, that is, the side opposite to the multilayer wiring layer 811. The on-chip lens 1251 collects infrared light incident from the outside and guides it into the substrate 61.

[0772] In each pixel 51, the portion of the substrate 61 that constitutes one pixel 51 serves as a light receiving region 1254. The light receiving regions 1254 of adjacent pixels 51 are separated by a pixel separation unit 1221 composed of an oxide film 1252 and a portion of the fixed charge film 1253.

[0773] Here, when viewed from a direction perpendicular to the surface of the substrate 61, that is, when viewed from above, the light receiving region 1254 is surrounded by the pixel separator 1221. In other words, the pixel separator 1221 is formed at the boundary between adjacent light receiving regions 1254.

[0774] exist Figure 59 In the example shown, the oxide film 1252 is formed to cover the surface of the substrate 61 on the on-chip lens 1251 side. Furthermore, at the boundary between adjacent pixels 51, the oxide film 1252 penetrates the substrate 61, thereby separating the light receiving areas 1254 of the adjacent pixels 51.

[0775] Furthermore, inside the substrate 61 , a region between the P-type semiconductor region constituting the substrate 61 and the oxide film 1252 , that is, a surface portion of the oxide film 1252 is covered with the fixed charge film 1253 .

[0776] In particular, in this example, the portion of the groove structure in the oxide film 1252 and the fixed charge film 1253 that is long in a direction perpendicular to the surface of the substrate 61, that is, the portion that penetrates the substrate 61 and separates the light receiving area 1254 between adjacent pixels 51 and functions as FTI (Full Trench Isolation), becomes the pixel separation portion 1221.

[0777] In addition, although it is described here that the pixel separation portion 1221 is composed of the oxide film 1252 and the fixed charge film 1253 , it can also be understood that the pixel separation portion 1221 is composed of only the oxide film 1252 .

[0778] Furthermore, the pixel separation unit 1221 may be formed not from the oxide film 1252 but from a metal material and a fixed charge film 1253 covering the metal material, or from both a metal material and an oxide film. In other words, the pixel separation unit 1221 may be formed from at least one of an oxide film, a fixed charge film, and a metal material.

[0779] Pixel separators 1221 are formed at the boundaries of pixels 51. Therefore, even if infrared light incident on substrate 61 from on-chip lens 1251 is reflected by structures such as oxide film 64, transistor gate electrodes, or metal materials, the pixel separators 1221 prevent the reflected light from entering adjacent pixels 51.

[0780] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0781] In addition, Figure 59In the example shown, the pixel separation portion 1221 is formed at a position offset from the position where the transistor is formed in the lateral direction of the figure. In other words, the pixel separation portion 1221 is not arranged directly above the transistor.

[0782] For example, if the pixel isolation portion 1221 is formed directly above a transistor, leakage current from the fixed charge film 1253 of the pixel isolation portion 1221 may occur in the transistor, more specifically, in the P-well portion of the transistor covering the substrate 61 .

[0783] Therefore, in this embodiment, the pixel separation portion 1221 is formed at a position offset from immediately above the transistor, thereby suppressing the occurrence of the above-mentioned leakage current.

[0784] In more detail, the pixel separation portion 1221 is formed at a position away from the P-well portion covering the transistor, but the pixel separation portion 1221 may be formed to penetrate a portion of the P-well.

[0785] Furthermore, in Figure 59 In the example shown, since the pixel separation portion 1221 is formed at a position offset in accordance with the position of the transistor, the inter-pixel light shielding film 63 and the on-chip lens 1251 are also arranged offset in accordance therewith.

[0786] That is, the inter-pixel light shielding film 63 is Figure 59 is configured to be located on the upper side (directly above) of the pixel separation unit 1221. Figure 59 As shown, it is configured so that when viewed from a direction parallel to the surface of the substrate 61, the center of the on-chip lens 1251, that is, the position of the optical axis of the on-chip lens 1251 becomes a position approximately in the middle of the two pixel separation parts 1221 arranged at both ends of the pixel 51 (the side walls of the pixel 51).

[0787] In other words, if Figure 58 As shown, the on-chip lens 1251 is arranged so that the optical axis of the on-chip lens 1251 is approximately located at the center of a rectangular area surrounded by the pixel separator 1221 at the boundary of the pixel 51. This increases the amount of light guided by the on-chip lens 1251 into the light-receiving area 1254 (the amount of light received), thereby improving sensitivity characteristics.

[0788] In addition, with Figure 58 The cross-sectional view of the pixel 51 taken along the line G1-G1' is shown in FIG. Figure 60 As shown. Figure 60 In, with Figure 59Similarly, the portion of the oxide film 1252 and the fixed charge film 1253 having a groove structure extending in a direction perpendicular to the surface of the substrate 61 serves as the pixel separation portion 1221. The pixel separation portion 1221 separates the light receiving area 1254 between adjacent pixels 51. In particular, the pixel separation portion 1221 penetrates the portion of the oxide film 64 and reaches the multilayer wiring layer 811.

[0789] According to the above Figures 58 to 60 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0790] In addition, Figure 59 In the above description, an example is described in which the arrangement position of the on-chip lens 1251 is shifted according to the formation position of the pixel separation unit 1221.

[0791] However, the on-chip lens 1251 can also be configured so that when viewed from a direction perpendicular to the surface of the substrate 61, the position of the optical axis of the on-chip lens 1251 becomes approximately in the middle of the two signal extraction parts 65 within the pixel 51, or more specifically, the two N+ semiconductor regions 71.

[0792] In this way, infrared light can be collected at a position between the signal extraction portion 65 - 1 and the signal extraction portion 65 - 2 , and the extraction efficiency of electrons in the signal extraction portion 65 can be made substantially uniform.

[0793] Furthermore, in e.g. Figure 58 In the example shown, the signal extraction sections 65 may be arranged with a staggered arrangement so that the position between the signal extraction section 65 - 1 and the signal extraction section 65 - 2 becomes the position of the optical axis of the on-chip lens 1251 .

[0794] (Twenty-second embodiment)

[0795] (Structural Example of Pixel)

[0796] Next, refer to Figures 61 to 63 The structure of the pixel 51 according to the twenty-second embodiment will be described.

[0797] Figure 61 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0798] In this example, a pixel isolation portion 1281 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0799] Furthermore, in this example, the pixel transistor wiring region 831 of the multilayer wiring layer 811 within the pixel 51, more specifically, the transistor region where transistors are formed, is also surrounded by the pixel separation portion 1281. In other words, the pixel separation portion 1281 is provided at both ends of the pixel transistor wiring region 831 (transistor region) in the left-right direction in the figure.

[0800] exist Figure 61 In, also with Figure 58 Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement position of the transistors and the like for driving the pixels 51 is different from the arrangement position of the pixel separation unit 1281. In other words, the pixel separation unit 1281 is arranged at a position offset from the transistors and the like.

[0801] By forming the pixel separation portion 1281 so as to surround (sandwich) the transistor region, the light receiving region and the transistor region can be separated, thereby preventing infrared light from entering the gate electrode portion of the transistor.

[0802] Here, in Figure 62 as well as Figure 63 Shown in Figure 61 The cross section corresponding to the F2-F2' line and the cross section corresponding to the G2-G2' line.

[0803] Figure 62 as well as Figure 63 The structure of the pixel 51 shown is not provided Figure 36 as well as Figure 37 The fixed charge film 66 in the structure of the pixel 51 shown in FIG. 5 is replaced by a structure in which an oxide film 1311 and a fixed charge film 1312 are newly provided.

[0804] like Figure 62 As shown, in each pixel 51 , a portion of the substrate 61 that constitutes one pixel 51 and is surrounded by the pixel separation unit 1281 and where the signal extraction unit 65 is disposed serves as a light receiving region 1254 .

[0805] Here, the pixel separation portion 1281 is composed of the oxide film 1311 and a portion of the fixed charge film 1312 .

[0806] That is, in Figure 62 In the example shown, the oxide film 1311 is formed to cover the surface of the substrate 61 on the side of the on-chip lens 62. Furthermore, the oxide film 1311 penetrates the substrate 61 at the boundary between adjacent pixels 51. Furthermore, the region of the transistor in the substrate 61 is surrounded by the oxide film 1311 formed so as to penetrate the substrate 61, thereby preventing infrared light from entering the transistor.

[0807] Inside the substrate 61 , a region between the P-type semiconductor region constituting the substrate 61 and the oxide film 1311 , that is, a surface portion of the oxide film 1311 is covered with the fixed charge film 1312 .

[0808] In particular, in this example, the portion of the oxide film 1311 and the fixed charge film 1312 having a groove structure extending in a direction perpendicular to the surface of the substrate 61 , that is, the portion of the FTI structure penetrating the substrate 61 , becomes the pixel separation portion 1281 .

[0809] In addition, although it is described here that the pixel separation portion 1281 is composed of the oxide film 1311 and the fixed charge film 1312 , it can be understood that the pixel separation portion 1281 is composed of only the oxide film 1311 .

[0810] In addition, the pixel separation portion 1281 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[0811] exist Figure 62 In the example shown, a pixel separation portion 1281 is formed at the boundary portion of the pixel 51. Figure 59 Similarly to the example shown, it is possible to prevent reflected light of infrared light incident from the on-chip lens 62 into the substrate 61 from being incident on the adjacent pixel 51 .

[0812] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0813] Furthermore, the transistor region in substrate 61 is surrounded by pixel separator 1281, and inter-pixel light shielding film 63 is disposed directly above the region surrounded by pixel separator 1281. This prevents infrared light collected by on-chip lens 62 from entering the transistor, particularly the gate electrode of the transistor.

[0814] This prevents infrared light from being reflected at the gate electrode portion of the transistor, thereby suppressing the occurrence of crosstalk and the reduction in pixel sensitivity.

[0815] Furthermore, in Figure 62 In the example shown, Figure 59 As in the example shown, the pixel separation portion 1281 is formed at a position offset from the transistor, and therefore, the occurrence of leakage current in the P-well portion covering the transistor can be suppressed.

[0816] In addition, with Figure 61 The cross-sectional view of the pixel 51 taken along the line G2-G2' is shown in FIG. Figure 63 As shown. Figure 63 In, with Figure 62Similarly, the portion of the oxide film 1311 and the fixed charge film 1312 having the groove structure extending in the direction perpendicular to the surface of the substrate 61 serves as the pixel separation portion 1281. The pixel separation portion 1281 separates the light receiving region 1254 between adjacent pixels 51. In particular, the pixel separation portion 1281 penetrates the portion of the oxide film 64 and reaches the multilayer wiring layer 811.

[0817] According to the above Figures 61 to 63 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0818] (Twenty-third embodiment)

[0819] (Structural Example of Pixel)

[0820] Reference Figures 64 to 66 The structure of the pixel 51 according to the twenty-third embodiment will be described.

[0821] Figure 64 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0822] In this example, a pixel isolation portion 1341 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0823] exist Figure 64 In, with Figure 58 Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement position of the transistors and the like for driving the pixels 51 is different from the arrangement position of the pixel separator 1341. That is, the pixel separator 1341 is arranged at a position offset from the transistors and the like.

[0824] In addition, the pixel separation unit 1341 and Figure 58 The pixel separation portion 1221 shown is different in that the pixel separation portion 1221 penetrates the substrate 61 , whereas the pixel separation portion 1341 does not penetrate the substrate 61 .

[0825] Here, in Figure 65 as well as Figure 66 Shown in Figure 64 The cross section corresponding to the F3-F3' line and the cross section corresponding to the G3-G3' line.

[0826] Figure 65 as well as Figure 66 The structure of the pixel 51 shown is instead of Figure 59 as well as Figure 60The oxide film 1252 and the fixed charge film 1253 in the structure of the pixel 51 shown are replaced by the oxide film 1371 and the fixed charge film 1372 .

[0827] like Figure 65 As shown, in each pixel 51 , an on-chip lens 1251 is arranged on the light incident surface side of the substrate 61 . In each pixel 51 , a portion of the substrate 61 that constitutes one pixel 51 serves as a light receiving region 1254 .

[0828] Furthermore, the light receiving regions 1254 of the adjacent pixels 51 are separated by the pixel separation portion 1341 formed of the oxide film 1371 and a portion of the fixed charge film 1372 .

[0829] That is, in Figure 65 In the illustrated example, the oxide film 1371 is formed so as to cover the surface of the substrate 61 on the on-chip lens 1251 side.

[0830] Furthermore, an oxide film 1371 is formed at the boundary between adjacent pixels 51 from the light incident surface side (on-chip lens 1251 side) of the substrate 61 to a predetermined depth, thereby separating the light receiving areas 1254 of the adjacent pixels 51.

[0831] Furthermore, inside the substrate 61 , a region between the P-type semiconductor region constituting the substrate 61 and the oxide film 1371 , that is, a surface portion of the oxide film 1371 is covered with the fixed charge film 1372 .

[0832] In particular, in this example, the portion of the oxide film 1371 and the fixed charge film 1372 that is formed to a predetermined depth in a direction perpendicular to the surface of the substrate 61 and functions as a DTI groove structure that separates the light receiving area 1254 between adjacent pixels 51 becomes the pixel separation portion 1341.

[0833] In addition, although it is described here that the pixel separation portion 1341 is composed of the oxide film 1371 and the fixed charge film 1372 , it can also be understood that the pixel separation portion 1341 is composed of only the oxide film 1371 .

[0834] In addition, the pixel separation portion 1341 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[0835] exist Figure 65 In the example shown, a pixel separator 1341 is formed at the boundary portion of the pixel 51, so that Figure 59 Similarly to the example shown, it is possible to suppress the reflected light of the infrared light incident from the on-chip lens 1251 into the substrate 61 from being incident on the adjacent pixel 51 .

[0836] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0837] In addition, Figure 65 In the example shown, Figure 59 As in the example shown, the pixel separation portion 1341 is formed at a position offset from the transistor, and leakage current in the P-well portion covering the transistor can be suppressed.

[0838] Especially in Figure 59 In the example shown, the pixel separation portion 1221 penetrates the substrate 61. Therefore, in the transistor, leakage current may occur from the fixed charge film 1253 via the P-well portion formed at the bottom of the substrate 61, that is, on the multilayer wiring layer 811 side of the substrate 61, and covering the transistor.

[0839] In contrast, in Figure 65 In the example shown, the depth of the pixel isolation portion 1341 can be adjusted so that the pixel isolation portion 1341 is formed at a position sufficiently separated from the P-well portion covering the transistor. This can reliably prevent the occurrence of leakage current.

[0840] Furthermore, in Figure 65 In the example shown, Figure 59 Similarly to the example in , the inter-pixel light shielding film 63 and the on-chip lens 1251 are arranged in coordination with the pixel separation units 1341 arranged in a staggered manner.

[0841] Therefore, in Figure 65 In the case shown, with Figure 59 Similarly to the case in , the amount of light (received light amount) guided into the light receiving area 1254 by the on-chip lens 1251 can be increased, and the sensitivity characteristics can be improved.

[0842] In addition, with Figure 64 The cross-sectional view of the pixel 51 taken along line G3-G3' is shown in FIG. Figure 66 As shown. Figure 66 In, with Figure 65 Similarly, the portion of the oxide film 1371 and the fixed charge film 1372 having the groove structure extending in the direction perpendicular to the surface of the substrate 61 serves as the pixel separation portion 1341. In particular, the pixel separation portion 1341 is formed to a predetermined depth, and in this example, the pixel separation portion 1341 does not reach the portion of the oxide film 64.

[0843] According to the above Figures 64 to 66 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0844] In addition, Figures 64 to 66 In the example shown, the on-chip lens 1251 is arranged so that the optical axis of the on-chip lens 1251 is approximately midway between the two signal extraction sections 65 within the pixel 51. Alternatively, the signal extraction sections 65 may be staggered so that the optical axis of the on-chip lens 1251 is positioned between the two signal extraction sections 65.

[0845] (Twenty-fourth embodiment)

[0846] (Structural Example of Pixel)

[0847] Reference Figures 67 to 69 The structure of the pixel 51 according to the twenty-fourth embodiment will be described.

[0848] Figure 67 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0849] In this example, a pixel isolation portion 1341 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0850] exist Figure 67 In, with Figure 64 The illustrated example is different in that the pixel separation portion 1341 is provided directly above the pixel transistor wiring region 831 , that is, directly above the transistor.

[0851] Here, in Figure 68 as well as Figure 69 Shown in Figure 67 The cross section corresponding to the F4-F4' line and the cross section corresponding to the G4-G4' line.

[0852] Figure 68 as well as Figure 69 The structure of the pixel 51 shown is similar to Figure 65 as well as Figure 66 Compared with the structure of the pixel 51 shown in FIG. 1 , the on-chip lens 62 is provided instead of the on-chip lens 1251, and the position of the pixel separation unit 1341 is different. Figure 65 as well as Figure 66 The structure of pixel 51 is different, but the other aspects are the same structure.

[0853] like Figure 68 As shown, in each pixel 51 , an on-chip lens 62 is disposed on the light incident surface side of the substrate 61 . The on-chip lens 62 is disposed so that the optical axis of the on-chip lens 62 is located between two signal extraction units 65 in the pixel 51 .

[0854] Furthermore, a pixel separation portion 1341 composed of an oxide film 1371 and a portion of the fixed charge film 1372 is disposed directly above the transistor. The pixel separation portion 1341 having such a trench structure separates the light receiving regions 1254 of adjacent pixels 51 .

[0855] In particular, here, the pixel separation portion 1341 is not structured to penetrate the substrate 61. Therefore, even if the pixel separation portion 1341 is arranged directly above the transistor, the pixel separation portion 1341 is sufficiently separated from the P-well portion, and the occurrence of leakage current can be suppressed.

[0856] Therefore, in Figure 68 In the example shown, the on-chip lens 62 does not need to be staggered, and can be arranged so that its optical axis is located between the two signal extraction sections 65. This makes it possible to make the electron extraction efficiency of the two signal extraction sections 65 in the pixel 51 substantially equal.

[0857] In addition, with Figure 67 The cross-sectional view of the pixel 51 taken along line G4-G4' is shown in FIG. Figure 69 shown. Figure 69 The cross section of the pixel 51 is shown only in place of Figure 66 The on-chip lens 1251 in the embodiment is provided with an on-chip lens 62. Figure 66 The cross section shown is different, and the other aspects become Figure 66 The same structure is shown in cross section.

[0858] According to the above Figures 67 to 69 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0859] (Twenty-fifth embodiment)

[0860] (Structural Example of Pixel)

[0861] Reference Figures 70 to 72 The structure of the pixel 51 according to the twenty-fifth embodiment will be described.

[0862] Figure 70 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0863] In this example, a pixel isolation portion 1401 functioning as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between the pixels 51 so as to surround the regions of two pixels 51 adjacent to each other in the vertical direction in the figure.

[0864] Alternatively, the area surrounded by the pixel separator 1401 and provided with four signal extraction units 65 can be considered as one pixel. In this case, four signal extraction units 65 are formed in the light-receiving area of one pixel on the substrate 61, and this light-receiving area is surrounded by the pixel separator 1401 and separated from the light-receiving areas of other pixels.

[0865] In this example, the pixel separation unit 1401 is configured at a position offset from the transistor, etc. so that when viewed from a direction perpendicular to the surface of the substrate 61, the configuration position of the transistor, etc. for driving the pixel 51 and the configuration position between the pixel separation unit 1401 become different positions.

[0866] For example, when measuring the distance to an object using an indirect ToF method, if more than two stages are used for measurement, the number of operations for reading out the charge accumulated in the signal extraction unit 65 can be reduced, thereby increasing the frame rate during distance measurement.

[0867] At this time, in order to reduce the number of readout operations, it is necessary to use each pixel 51 (signal extraction unit 65) separately. If the multiple pixels 51 used in the distance measurement of the same object are used as units and the pixel separation unit 1401 surrounds the above-mentioned multiple pixels 51, the sensitivity characteristics can be improved.

[0868] Here, the phase refers to the time when one signal extraction section 65 serves as an active tap and the signal extraction section 65 accumulates charges obtained by photoelectric conversion, that is, the phase when the signal extraction section 65 serves as an active tap.

[0869] Now, for example, the distance to an object is measured by receiving reflected light from an object in response to one pulse of infrared light using one pixel 51. In particular, here, four-stage measurement is performed using two signal extraction units 65 (taps) in one pixel 51.

[0870] In this case, for example, in the initial stage, i.e., stage 1, one signal extraction unit 65 of a pixel 51, i.e., the first tap, is set as an active tap, and in the subsequent stage 2, the other signal extraction unit 65, i.e., the second tap, is set as an active tap. The charges accumulated in the first and second taps are read out, for example, after the second stage is completed.

[0871] Then, in the third stage following the second stage, the first tap is set as the active tap again, and in the final fourth stage, the second tap is set as the active tap. Then, for example, when the fourth stage is completed, the charges accumulated in the first and second taps are read out.

[0872] When four levels of charges (pixel signals) are read out in this manner, the distance to the object can be determined based on the signals corresponding to these read charges.

[0873] The method of using the above two taps to accumulate charge in four stages and calculate the distance to the object is called 2-tap 4-stage processing. If generalized, the method of using n different taps to accumulate charge in m stages and calculate the distance to the object is called n-tap m-stage processing.

[0874] For example, when the above-described two-tap four-stage process is performed, the number of times the charge is read out is two.

[0875] In contrast, consider using two pixels 51, that is, four signal extraction units 65 (taps) to perform four-tap, four-stage processing. In this case, when the four different taps are set as the first to fourth taps, it is sufficient to drive the first to fourth taps in each of the first to fourth stages so that each tap becomes an active tap.

[0876] In this case, each tap becomes an active tap only once during the four-stage period, and therefore, charge only needs to be read out once.

[0877] Therefore, for example, if a 4-tap 4-stage process is performed, the number of readouts can be reduced compared to a 2-tap 4-stage process. In this example, the readout speed during distance measurement, ie, the frame rate, can be doubled.

[0878] Here, in Figure 70 In the case where the distance to the object is obtained by using four signal extraction units 65 arranged in the vertical direction, for example, by four-tap four-stage processing, as shown in FIG. Figure 70 As shown, two pixels 51 used for measuring the distance to the same object can be surrounded by the pixel separation unit 1401. In this case, the area surrounded by the pixel separation unit 1401 can be understood as one pixel.

[0879] In this way, the reflected light from the same object is incident on the area surrounded by the pixel separation unit 1401, so that the deviation of sensitivity and the decrease of sensitivity can be suppressed compared with separating the area for each pixel 51. In other words, the sensitivity characteristics can be improved. Figure 70 The use of the light-receiving element 1 having the structure shown is not limited to measuring the distance to an object, but may be used for any other purpose.

[0880] Here, Figure 71 as well as Figure 72 Shown in Figure 70 The cross section equivalent to the F5-F5' line and the cross section equivalent to the G5-G5' line.

[0881] Figure 71 as well as Figure 72 The structure of the pixel 51 shown is: no Figure 36 as well as Figure 37 The on-chip lens 62 and the fixed charge film 66 in the structure of the pixel 51 shown in FIG. 5 are replaced with an on-chip lens 1431 , an oxide film 1432 , and a fixed charge film 1433 .

[0882] like Figure 71 As shown, in each pixel 51, an on-chip lens 1431 is arranged adjacent to the light incident surface side of the substrate 61, that is, the side opposite to the multilayer wiring layer 811. The on-chip lens 1431 collects infrared light incident from the outside and guides it into the substrate 61.

[0883] In particular, Figure 71 In the cross section shown, one on-chip lens 1431 is provided for one pixel 51 arranged in the horizontal direction in the figure.

[0884] In addition, the light receiving areas of the adjacent pixels 51 are separated by the pixel separation portion 1401 composed of the oxide film 1432 and a part of the fixed charge film 1433. Figure 71 In the cross section shown, a pixel separator 1401 is formed at a position of a boundary between pixels 51 arranged in the horizontal direction in the figure, and the light receiving areas of these pixels 51 are separated.

[0885] exist Figure 71 In the example shown, the oxide film 1432 is formed to cover the surface of the substrate 61 on the side of the on-chip lens 1431. Furthermore, at the boundary between adjacent pixels 51, the oxide film 1432 penetrates the substrate 61, thereby separating the light-receiving areas of the adjacent pixels 51. Furthermore, within the substrate 61, the surface of the oxide film 1432 is partially covered by the fixed charge film 1433.

[0886] The portion of the oxide film 1432 and the fixed charge film 1433 having a groove structure extending in a direction perpendicular to the surface of the substrate 61 , that is, the portion functioning as FTI that penetrates the substrate 61 and separates the light receiving areas between adjacent pixels 51 , becomes the pixel separation portion 1401 .

[0887] In addition, although it is described here that the pixel separation portion 1401 is composed of the oxide film 1432 and the fixed charge film 1433 , it can also be understood that the pixel separation portion 1401 is composed of only the oxide film 1432 .

[0888] Note that the pixel separation portion 1401 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[0889] Since the pixel separation portion 1401 is formed at the boundary portion of the pixel 51, Figure 59 Similarly to the example shown, it is possible to prevent reflected light of infrared light incident from the on-chip lens 1431 into the substrate 61 from being incident on the pixel 51 used for measuring the distance to a different object.

[0890] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0891] In addition, Figure 71 In the example shown, Figure 59 As in the example shown, the pixel separation portion 1401 is formed at a position offset from the transistor, and thus it is possible to suppress the occurrence of leakage current in the P-well portion covering the transistor.

[0892] Furthermore, in this example, Figure 59 Similarly to the example in , the inter-pixel light shielding film 63 and the on-chip lens 1431 are arranged in conjunction with the pixel separation units 1401 arranged in a staggered manner.

[0893] Therefore, in Figure 71 In the case shown, with Figure 59 Similarly to the case in , the amount of light guided into the light receiving area by the on-chip lens 1431 (the amount of received light) can be increased, and the sensitivity characteristics can be improved.

[0894] In addition, with Figure 70 The cross-sectional view of the pixel 51 taken along line G5-G5' is shown in FIG. Figure 72 As shown. Figure 72 In FIG. 1 , two pixels 51 arranged in the horizontal direction in the figure are used for measuring the distance to the same object, and therefore, a pixel separator 1401 is formed at a boundary between these two pixels 51 and other pixels 51 .

[0895] In other words, the area of the two pixels 51 arranged horizontally in the figure in the substrate 61 is surrounded by the pixel separation unit 1401, and the area of the two pixels 51 arranged horizontally and the areas of other pixels 51 adjacent to the two pixels 51 are separated by the pixel separation unit 1401.

[0896] In addition, Figure 72 In the cross section shown, one on-chip lens 1431 is provided for two pixels 51 arranged in the horizontal direction in the figure, that is, two pixels 51 used for measuring the distance to the same object. Figure 70 In the example shown, the Figure 70One on-chip lens 1431 is provided for two pixels 51 arranged in the vertical direction, that is, two pixels 51 surrounded by the pixel separation unit 1401 and used for measuring the distance to the same object.

[0897] According to the above Figures 70 to 72 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0898] In addition, Figure 71 , an example is described in which the arrangement position of the on-chip lens 1431 is shifted to match the formation position of the pixel separator 1401. However, the on-chip lens 1431 may be arranged so that the optical axis of the on-chip lens 1431 is approximately midway between two pixels 51 when viewed from a direction perpendicular to the surface of the substrate 61.

[0899] Furthermore, in e.g. Figure 70 In the example shown, for the two pixels 51 surrounded by the pixel separation unit 1401, the signal extraction units 65 can also be staggered so that the position between the signal extraction unit 65-1 of the pixel 51 located on the lower side of the figure and the signal extraction unit 65-2 of the pixel 51 located on the upper side of the figure becomes the position of the optical axis of the on-chip lens 1431.

[0900] (Twenty-sixth embodiment)

[0901] (Structural Example of Pixel)

[0902] Reference Figures 73 to 75 The structure of the pixel 51 according to the twenty-sixth embodiment will be described.

[0903] Figure 73 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0904] In this example, a pixel separation unit 1461 is formed at the boundary between two pixels 51, surrounding the regions of two pixels 51 adjacent to each other in the left-right direction in the figure. The region surrounded by the pixel separation unit 1461 and in which the four signal extraction units 65 are provided can also be understood as a single pixel.

[0905] In this example, the pixel separation unit 1461 is configured at a position offset from the transistor, etc. so that when viewed from a direction perpendicular to the surface of the substrate 61, the configuration position of the transistor, etc. for driving the pixel 51 and the configuration position between the pixel separation unit 1461 become different positions.

[0906] exist Figure 70In the description, an example is described in which two pixels 51 adjacent to each other in the vertical direction are used to measure the distance to the same object using the indirect ToF method.

[0907] In contrast, in Figure 73 In the example shown, for example, two pixels 51 adjacent to each other in the left-right direction in the figure, i.e., two pixels 51 surrounded by the pixel separator 1461, can be used in the measurement of the distance to the same object by the indirect ToF method. In this case, the area surrounded by the pixel separator 1461 can also be understood as one pixel. In addition, Figure 73 The use of the light-receiving element 1 having the structure shown is not limited to measuring the distance to an object, but may be used for any other purpose.

[0908] By surrounding the two pixels 51 for measuring the distance to the same object by the pixel separation unit 1461, Figure 70 Similarly to the example shown, it is possible to suppress variations in sensitivity and decreases in sensitivity, that is, to improve sensitivity characteristics.

[0909] Here, in Figure 74 as well as Figure 75 Shown in Figure 73 The cross section corresponding to the F6-F6' line and the cross section corresponding to the G6-G6' line.

[0910] Figure 74 as well as Figure 75 The structure of the pixel 51 shown is: no Figure 36 as well as Figure 37 The on-chip lens 62 and the fixed charge film 66 in the structure of the pixel 51 shown in FIG. 1 are replaced with an on-chip lens 1481 , an oxide film 1482 , and a fixed charge film 1483 .

[0911] like Figure 74 As shown, in each pixel 51, an on-chip lens 1481 is arranged adjacent to the light incident surface side of the substrate 61, that is, the side opposite to the multilayer wiring layer 811. The on-chip lens 1481 collects infrared light incident from the outside and guides it into the substrate 61.

[0912] In particular, Figure 74 In the cross section shown, one on-chip lens 1481 is provided for two pixels 51 arranged in the horizontal direction in the figure.

[0913] In addition, the light receiving area of the pixel 51 is separated by the pixel separation portion 1461 composed of the oxide film 1482 and a part of the fixed charge film 1483 .

[0914] In this example, two pixels 51 arranged in the horizontal direction in the figure are used for measuring the distance to the same object. Therefore, a pixel separator 1461 is formed at a boundary between the two pixels 51 and other pixels 51 .

[0915] In other words, the area of the two pixels 51 arranged horizontally in the figure in the substrate 61 is surrounded by the pixel separation unit 1461, and the area of the two pixels 51 arranged horizontally and the areas of other pixels 51 adjacent to the two pixels 51 are separated by the pixel separation unit 1461.

[0916] exist Figure 74 In the example shown, the oxide film 1482 is formed to cover the surface of the substrate 61 on the side facing the on-chip lens 1481. Furthermore, at the boundary between adjacent pixels 51 used for distance measurement of different objects, the oxide film 1482 penetrates the substrate 61, thereby separating the light-receiving areas of the adjacent pixels 51. Furthermore, within the substrate 61, the surface of the oxide film 1482 is partially covered with a fixed charge film 1483.

[0917] The portion of the oxide film 1482 and the fixed charge film 1483 having a groove structure that is long in a direction perpendicular to the surface of the substrate 61 , that is, the portion that penetrates the substrate 61 and functions as FTI to separate the light receiving area between adjacent pixels 51 , becomes the pixel separation portion 1461 .

[0918] In addition, although it is described here that the pixel separation portion 1461 is composed of the oxide film 1482 and the fixed charge film 1483 , it can also be understood that the pixel separation portion 1461 is composed of only the oxide film 1482 .

[0919] In addition, the pixel separation portion 1461 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[0920] The pixel separation portion 1461 is formed at the boundary portion of the pixels 51 used for measuring the distances to different objects. Figure 59 Similarly to the example shown, it is possible to prevent reflected light of infrared light incident from the on-chip lens 1481 into the substrate 61 from being incident on the pixel 51 used for measuring the distance to a different object.

[0921] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0922] In addition, Figure 74 In the example shown, Figure 59As in the example shown, the pixel separation portion 1461 is formed at a position offset from the transistor, and thus it is possible to suppress the occurrence of leakage current in the P-well portion covering the transistor.

[0923] Furthermore, in this example, Figure 59 Similarly to the example in , the inter-pixel light shielding film 63 and the on-chip lens 1481 are arranged in conjunction with the pixel separation portion 1461 arranged in a staggered manner.

[0924] Therefore, in Figure 74 In the case shown, with Figure 59 Similarly to the case in , the amount of light guided into the light receiving area by the on-chip lens 1481 (the amount of light received) can be increased, and the sensitivity characteristics can be improved.

[0925] In addition, with Figure 73 The cross-sectional view of the pixel 51 taken along line G6-G6' is shown in FIG. Figure 75 As shown. Figure 75 In FIG, a pixel separation portion 1461 is formed at the boundary portion between adjacent pixels 51. Figure 75 In the cross section shown, one on-chip lens 1481 is provided for one pixel 51 .

[0926] Thus, in e.g. Figure 73 In the example shown, for Figure 73 One on-chip lens 1481 is provided for two pixels 51 arranged in the left-right direction, that is, two pixels 51 surrounded by the pixel separator 1461 and used for measuring the distance to the same object.

[0927] According to the above Figures 73 to 75 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0928] In addition, Figure 74 , the example in which the arrangement position of the on-chip lens 1481 is shifted to match the formation position of the pixel separator 1461 is described. However, the on-chip lens 1481 may be arranged so that, when viewed from a direction perpendicular to the surface of the substrate 61, the optical axis of the on-chip lens 1481 is positioned approximately in the middle of the four signal extraction units 65 within the area surrounded by the pixel separator 1461, that is, at a position approximately equidistant from each signal extraction unit 65.

[0929] Furthermore, for example Figure 73 In the example shown, the four signal extraction sections 65 may be staggered so that the approximate center of the four signal extraction sections 65 surrounded by the pixel separation section 1461 coincides with the optical axis of the on-chip lens 1481 .

[0930] (Twenty-seventh embodiment)

[0931] (Structural Example of Pixel)

[0932] Reference Figures 76 to 78 The structure of the pixel 51 according to the twenty-seventh embodiment will be described.

[0933] Figure 76 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0934] In this example, a pixel separation portion 1511 is formed at the boundary portion of each pixel 51 to surround the region of four adjacent pixels 51. The pixel separation portion 1511 functions as a pixel separation region for separating the region of the pixels 51. Furthermore, the region surrounded by the pixel separation portion 1511 and provided with the eight signal extraction portions 65 can be understood as one pixel.

[0935] In this example, the pixel separation unit 1511 is configured at a position offset from the transistor, etc. so that when viewed from a direction perpendicular to the surface of the substrate 61, the configuration position of the transistor, etc. for driving the pixel 51 and the configuration position between the pixel separation unit 1511 become different positions.

[0936] exist Figure 70 In the description, an example is described in which two adjacent pixels 51 are used to measure the distance to the same object using the indirect ToF method.

[0937] In contrast, in Figure 76 In the example shown, for example, four adjacent pixels 51, that is, four pixels 51 surrounded by a pixel separator 1511, are used in the distance measurement to the same object by the indirect ToF method. In this case, the area surrounded by the pixel separator 1511 can also be understood as one pixel. Figure 76 The use of the light-receiving element 1 having the structure shown is not limited to measuring the distance to an object, but may be used for any other purpose.

[0938] Thus, by surrounding the four pixels 51 used for measuring the distance to the same object using the pixel separation unit 1511, Figure 70 Similarly to the example shown, it is possible to suppress variations in sensitivity and decreases in sensitivity, that is, to improve sensitivity characteristics.

[0939] In addition, Figure 76 In the example shown, for example, 8-tap 8-stage processing can be performed using 4 pixels 51. In this case, the readout speed during distance measurement can be quadrupled compared to the case of 2-tap 8-stage processing.

[0940] Here, in Figure 77 as well as Figure 78 Shown in Figure 76 The cross section corresponding to the F7-F7' line and the cross section corresponding to the G7-G7' line.

[0941] Figure 77 as well as Figure 78 The structure of the pixel 51 shown is: no Figure 36 as well as Figure 37 The on-chip lens 62 and the fixed charge film 66 in the structure of the pixel 51 shown in FIG. 1 are replaced with an on-chip lens 1541 , an oxide film 1542 , and a fixed charge film 1543 .

[0942] like Figure 77 As shown, in each pixel 51, an on-chip lens 1541 is arranged adjacent to the light incident surface side of the substrate 61, that is, the side opposite to the multilayer wiring layer 811. The on-chip lens 1541 collects infrared light incident from the outside and guides it into the substrate 61.

[0943] In particular, Figure 77 In the cross section shown, one on-chip lens 1541 is provided for two pixels 51 arranged in the horizontal direction in the figure.

[0944] Furthermore, the light receiving region of the pixel 51 is separated by the pixel separation portion 1511 composed of the oxide film 1542 and a part of the fixed charge film 1543 .

[0945] In this example, two pixels 51 arranged in the horizontal direction in the figure are used for distance measurement of the same object, and therefore a pixel separator 1511 is formed at a boundary between the two pixels 51 and other pixels 51 .

[0946] In other words, the area of the two pixels 51 arranged horizontally in the figure in the substrate 61 is surrounded by the pixel separation unit 1511, and the area of the two pixels 51 arranged horizontally and the areas of other pixels 51 adjacent to the two pixels 51 are separated by the pixel separation unit 1511.

[0947] exist Figure 77 In the example shown, the oxide film 1542 is formed to cover the surface of the substrate 61 on the side facing the on-chip lens 1541. Furthermore, at the boundary between adjacent pixels 51 used for distance measurement of different objects, the oxide film 1542 penetrates the substrate 61, thereby separating the light-receiving areas of the adjacent pixels 51. Furthermore, within the substrate 61, the surface of the oxide film 1542 is partially covered with a fixed charge film 1543.

[0948] The portion of the oxide film 1542 and the fixed charge film 1543 having a groove structure that is long in a direction perpendicular to the surface of the substrate 61, that is, the portion that penetrates the substrate 61 and functions as FTI to separate the light receiving area between adjacent pixels 51, becomes the pixel separation portion 1511.

[0949] In addition, although it is described here that the pixel separation portion 1511 is composed of the oxide film 1542 and the fixed charge film 1543 , it can also be understood that the pixel separation portion 1511 is composed of only the oxide film 1542 .

[0950] In addition, the pixel separation portion 1511 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[0951] A pixel separator 1511 is formed at the boundary of the pixels 51 used for measuring the distances to different objects. Figure 59 Similarly to the example shown, it is possible to prevent reflected light of infrared light incident from the on-chip lens 1541 into the substrate 61 from being incident on the pixel 51 used for measuring the distance to a different object.

[0952] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[0953] In addition, Figure 77 In the example shown, Figure 59 As in the example shown, the pixel separation portion 1511 is formed at a position offset from the transistor, and thus it is possible to suppress the occurrence of leakage current in the P-well portion covering the transistor.

[0954] Furthermore, in this example, Figure 59 Similarly to the example in , an inter-pixel light shielding film 63 and an on-chip lens 1541 are arranged in conjunction with the pixel separation units 1511 arranged in a staggered manner.

[0955] Therefore, in Figure 77 In the case shown, with Figure 59 Similarly to the case in , the amount of light guided into the light receiving area by the on-chip lens 1541 (the amount of received light) can be increased, and the sensitivity characteristics can be improved.

[0956] In addition, with Figure 76 The cross-sectional view of the pixel 51 taken along line G7-G7' is shown in FIG. Figure 78 As shown. Figure 78 In the diagram, two pixels 51 arranged in the horizontal direction are used for measuring the distance to the same object. Therefore, a pixel separator 1511 is formed at a boundary between the two pixels 51 and other pixels 51 .

[0957] In other words, the area of the two pixels 51 arranged horizontally in the figure in the substrate 61 is surrounded by the pixel separation unit 1511, and the area of the two pixels 51 arranged horizontally and the areas of other pixels 51 adjacent to the above-mentioned two pixels 51 are separated by the pixel separation unit 1511.

[0958] In addition, Figure 78 In the cross section shown in FIG. 1 , one on-chip lens 1541 is provided for two pixels 51 arranged in the horizontal direction in the figure, that is, two pixels 51 used for measuring the distance to the same object. Figure 76 In the illustrated example, one on-chip lens 1541 is provided for four adjacent pixels 51 , that is, four pixels 51 surrounded by a pixel separation unit 1511 and used for measuring the distance to the same object.

[0959] According to the above Figures 76 to 78 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[0960] In addition, Figure 77 In the example of staggering the configuration position of the on-chip lens 1541 in accordance with the formation position of the pixel separation unit 1511, the on-chip lens 1541 is described. However, the on-chip lens 1541 may be configured so that the position of the optical axis of the on-chip lens 1541 becomes approximately the middle position between the four pixels 51 when viewed from a direction perpendicular to the surface of the substrate 61. Conversely, in Figure 77 In the cross section shown, the signal extraction sections 65 of the four pixels 51 may be arranged with shifts so that the optical axis of the on-chip lens 1541 is positioned approximately midway between two pixels 51 .

[0961] (Twenty-eighth embodiment)

[0962] (Structural Example of Pixel)

[0963] Reference Figures 79 to 81 The structure of the pixel 51 according to the twenty-eighth embodiment will be described.

[0964] Figure 79 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0965] In this example, a pixel isolation portion 1571 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0966] exist Figure 79 In, with Figure 58Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement positions of the transistors and the like for driving the pixels 51 are different from the arrangement positions of the pixel separator 1571. That is, the pixel separator 1571 is arranged at a position offset from the transistors and the like.

[0967] Here, in Figure 80 as well as Figure 81 Shown in Figure 79 The cross section corresponding to the line F8-F8' and the cross section corresponding to the line G8-G8'.

[0968] Figure 80 as well as Figure 81 The structure of the pixel 51 shown is: Figure 59 as well as Figure 60 The fixed charge film 1253 in the structure of the pixel 51 shown in the figure is replaced by a fixed charge film 1253A. Figure 80 as well as Figure 81 The structure of the pixel 51 shown is the same as that of the pixel 51 except for the fixed charge film 1253A. Figure 59 as well as Figure 60 The same structure as the example shown.

[0969] Specifically, in Figure 59 In the embodiment, at the boundary portion of the pixel 51, a fixed charge film 1253 is formed on the surface of the oxide film 1252 penetrating the substrate 61. Figure 80 In the embodiment, at the boundary portion of the pixel 51 , the fixed charge film 1253 is not formed on the surface portion of the oxide film 1252 penetrating the substrate 61 .

[0970] exist Figure 80 In the embodiment, the oxide film 1252 is formed to cover the surface of the substrate 61 on the on-chip lens 1251 side, and the fixed charge film 1253A is formed to cover the surface of the oxide film 1252 on the inner side of the substrate 61 except for the pixel boundary portion.

[0971] Therefore, in Figure 80 Not formed Figure 59 The portion of the fixed charge film 1253 that constitutes the pixel separation unit 1221, that is, the FTI portion, is Figure 80 middle, Figure 59 The portion of the fixed charge film 1253 shown, which is different from the FTI portion, becomes a fixed charge film 1253A.

[0972] exist Figure 80In the example shown, the portion of the oxide film 1252 having a groove structure that is long in a direction perpendicular to the surface of the substrate 61 , that is, the portion that penetrates the substrate 61 and separates the light receiving area 1254 between adjacent pixels 51 and functions as FTI becomes the pixel separation portion 1571 .

[0973] For example, in Figure 59 In the illustrated structure, if the pixel separation portion 1221 is not sufficiently separated from the P-well portion covering the transistor, leakage current may occur from the fixed charge film 1253 to the transistor via the P-well portion.

[0974] In contrast, in Figure 80 In the example shown, a fixed charge film is not formed in the portion near the P-well covering the transistor, and thus the occurrence of leakage current can be prevented.

[0975] In addition, with Figure 79 The cross-sectional view of the pixel 51 taken along line G8-G8' is shown in FIG. Figure 81 As shown. Figure 81 In, with Figure 80 Similarly, the portion of the oxide film 1252 having a groove structure extending in a direction perpendicular to the surface of the substrate 61 serves as a pixel separator 1571, and the pixel separator 1571 separates the light receiving region 1254 from the adjacent pixel 51. In particular, the pixel separator 1571 here penetrates the oxide film 64 and reaches the multilayer wiring layer 811.

[0976] According to the above Figures 79 to 81 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can prevent the occurrence of leakage current.

[0977] (Twenty-ninth embodiment)

[0978] (Structural Example of Pixel)

[0979] Reference Figures 82 to 84 The structure of the pixel 51 according to the twenty-ninth embodiment will be described.

[0980] Figure 82 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0981] In this example, a pixel isolation portion 1601 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0982] exist Figure 82 In, with Figure 58Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement positions of the transistors and the like for driving the pixels 51 are different from the arrangement position of the pixel separator 1601. In other words, the pixel separator 1601 is arranged at a position offset from the transistors and the like.

[0983] Here, in Figure 83 as well as Figure 84 Shown in Figure 82 The cross section corresponding to the F9-F9' line and the cross section corresponding to the G9-G9' line.

[0984] Figure 83 as well as Figure 84 The structure of the pixel 51 shown is relative to Figure 59 as well as Figure 60 The structure of the pixel 51 shown is further provided with an N-type semiconductor region 1641. That is, Figure 83 as well as Figure 84 The structure of the pixel 51 shown is the same as that of the pixel 51 except for the N-type semiconductor region 1641. Figure 59 as well as Figure 60 The same structure as the example shown.

[0985] exist Figure 83 In the embodiment, an N-type semiconductor region 1641 is formed in the portion of the oxide film 1252 and the fixed charge film 1253 that is long in the direction perpendicular to the surface of the substrate 61, that is, in the portion of the FTI structure that penetrates the substrate 61, so as to cover the surface of the fixed charge film 1253. The N-type semiconductor region 1641 is formed by, for example, implantation.

[0986] In this example, the portion formed by each of a portion of the oxide film 1252 and the fixed charge film 1253 and the N-type semiconductor region 1641, which penetrates the substrate 61 and functions as the FTI to separate the light-receiving region 1254 between adjacent pixels 51, constitutes the pixel separation unit 1601. In this case, it can be understood that the pixel separation unit 1601 is formed by only the oxide film 1252, or it can be understood that the pixel separation unit 1601 is formed by only the oxide film 1252 and the fixed charge film 1253.

[0987] By providing such a pixel separation unit 1601 , it is possible to prevent the occurrence of leakage current by PN separation and to achieve separation of the light receiving region 1254 between the pixels 51 .

[0988] For example, Figure 59 In the example shown, if the pixel separation portion 1221 is not sufficiently separated from the P-well portion covering the transistor, leakage current may occur from the fixed charge film 1253 to the transistor via the P-well portion.

[0989] Therefore, in Figure 83 In the example shown, the surface (peripheral) portion of the FTI is separated by the N-type semiconductor region 1641, and a fixed voltage of, for example, 0V to 2.8V is applied to the N-type semiconductor region 1641, thereby utilizing the reverse bias of the PN junction to prevent leakage current from occurring.

[0990] The fixed voltage applied to the N-type semiconductor region 1641 only needs to be a voltage greater than the voltage applied to the substrate 61. Here, the example in which the substrate 61 is formed of a P-type semiconductor layer has been described. However, if the substrate 61 is formed of an N-type semiconductor layer, a P-type semiconductor region may be formed instead of the N-type semiconductor region 1641.

[0991] In addition, with Figure 82 The cross-sectional view of the pixel 51 taken along line G9-G9' is shown in FIG. Figure 84 As shown. Figure 84 In, with Figure 83 Similarly, the portion of the oxide film 1252 and the fixed charge film 1253, and the N-type semiconductor region 1641 that penetrates the substrate 61 and functions as the FTI becomes the pixel separation unit 1601. Furthermore, the pixel separation unit 1601 separates the light-receiving region 1254 between adjacent pixels 51. In particular, the oxide film 1252, the fixed charge film 1253, and the portion of the N-type semiconductor region 1641 that constitute the pixel separation unit 1601 penetrate the oxide film 64 and reach the multilayer wiring layer 811.

[0992] According to the above Figures 82 to 84 The pixel 51 of the structure shown in FIG. 1 can improve characteristics such as sensitivity and ranging accuracy (resolution), and can prevent the occurrence of leakage current. Figure 83 as well as Figure 84 In the example shown, a structure may be formed in which the fixed charge film 1253 is not provided.

[0993] (Thirtieth embodiment)

[0994] (Structural Example of Pixel)

[0995] Reference Figures 85 to 87 The structure of the pixel 51 according to the 30th embodiment will be described.

[0996] Figure 85 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[0997] In this example, a pixel isolation portion 1221 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[0998] exist Figure 85 In, with Figure 58 Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement position of the transistors and the like for driving the pixels 51 is different from the arrangement position of the pixel separator 1221. In other words, the pixel separator 1221 is arranged at a position offset from the transistors and the like.

[0999] Here, in Figure 86 as well as Figure 87 Shown in Figure 85 The cross section equivalent to the F10-F10' line and the cross section equivalent to the G10-G10' line.

[1000] Figure 85 as well as Figure 86 The structure of the pixel 51 shown is not provided with Figure 59 as well as Figure 60 The structure of the oxide film 64 in the pixel 51 shown is the same as that of the pixel 51 except for the above. Figure 59 as well as Figure 60 The structure of pixel 51 is the same as that of the pixel 51.

[1001] By adopting a structure in which the oxide film 64 is not provided within the pixel 51, that is, within the light-receiving region 1254 of the pixel 51, infrared light incident from the on-chip lens 1251 into the interior of the substrate 61 is prevented from being partially reflected by the oxide film 64 and incident on adjacent pixels 51. Consequently, the occurrence of crosstalk and a decrease in pixel sensitivity can be further suppressed, and characteristics of the CAPD sensor, such as sensitivity characteristics and ranging accuracy (resolution), can be improved.

[1002] (Thirty-first embodiment)

[1003] (Structural Example of Pixel)

[1004] Reference Figures 88 to 90 The structure of the pixel 51 according to the thirty-first embodiment will be described.

[1005] Figure 88 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[1006] In this example, a pixel isolation portion 1701 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[1007] exist Figure 88 In, also with Figure 58 Similarly, when viewed from a direction perpendicular to the surface of the substrate 61, the arrangement positions of the transistors and the like for driving the pixels 51 are further different from the arrangement position of the pixel separator 1701. In other words, the pixel separator 1701 is arranged at a position offset from the transistors and the like.

[1008] Here, Figure 89 as well as Figure 90 Shown in Figure 88 The cross section corresponding to the F11-F11' line and the cross section corresponding to the G11-G11' line.

[1009] Figure 89 as well as Figure 90 The structure of the pixel 51 shown is formed by replacing Figure 59 as well as Figure 60 In the structure of the pixel 51 shown in the figure, the oxide film 1252 and the fixed charge film 1253 are replaced by an oxide film 1731 , a fixed charge film 1732 , and an oxide film 1733 .

[1010] exist Figure 89 In the example shown, the oxide film 1731 is formed to cover the surface of the substrate 61 on the side of the on-chip lens 1251. Furthermore, at the boundary between adjacent pixels 51, the oxide film 1731 is formed from the on-chip lens 1251 side of the substrate 61 to a predetermined depth in the direction toward the multilayer wiring layer 811. As a result, the light-receiving regions 1254 of the adjacent pixels 51 are separated.

[1011] Furthermore, inside the substrate 61 , a region between the P-type semiconductor region constituting the substrate 61 and the oxide film 1731 , that is, a surface portion of the oxide film 1731 is covered with the fixed charge film 1732 .

[1012] In particular, in this example, the portion of the oxide film 1731 and the fixed charge film 1732 that is long in the direction perpendicular to the surface of the substrate 61 and functions as FTI to separate the light receiving area 1254 between adjacent pixels 51 becomes the pixel separation unit 1701.

[1013] In addition, although it is described here that the pixel separation portion 1701 is composed of the oxide film 1731 and the fixed charge film 1732 , it can also be understood that the pixel separation portion 1701 is composed of only the oxide film 1731 .

[1014] Note that the pixel separation portion 1701 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[1015] In addition, Figure 89In the example shown, an oxide film 1733 is provided between the pixel isolation portion 1701 and the multilayer wiring layer 811 in the substrate 61. Specifically, the oxide film 1733 is formed between the surface of the substrate 61 facing the multilayer wiring layer 811 and the pixel isolation portion 1701. This oxide film 1733 is formed simultaneously with the oxide film 64.

[1016] In addition, with Figure 88 The cross-sectional view of the pixel 51 taken along line G11-G11' is shown in FIG. Figure 90 As shown. Figure 90 In FIG. 1 , a portion of the oxide film 64 becomes an oxide film 1733 , and the oxide film 1733 is connected to the oxide film 1731 and the fixed charge film 1732 constituting the pixel separation portion 1701 .

[1017] exist Figure 90 In the cross section shown, the light receiving region 1254 is separated between adjacent pixels 51 by the pixel separation unit 1701 .

[1018] In such Figure 89 as well as Figure 90 In the illustrated structure, the oxide film 1731 and the fixed charge film 1732 constituting the pixel isolation unit 1701 functioning as an FTI are formed from the light incident surface side (on-chip lens 1251 side) of the substrate 61. Furthermore, in the substrate 61, the oxide film 1733 is connected to the pixel isolation unit 1701 functioning as an FTI and penetrates the fixed charge layer.

[1019] By providing the oxide film 1733 between the pixel isolation portion 1701 and the multilayer wiring layer 811 in this manner, it is possible to suppress the occurrence of leakage current flowing from the fixed charge film 1732 to the transistor via the P-well portion covering the transistor.

[1020] According to the above Figures 88 to 90 The pixel 51 having the structure shown can improve characteristics such as sensitivity and ranging accuracy (resolution), and can also suppress the occurrence of leakage current.

[1021] In addition, Figure 89 , the example in which the arrangement position of the on-chip lens 1251 is shifted to match the formation position of the pixel separation unit 1701 is described. However, the on-chip lens 1251 may be arranged so that, when viewed from a direction perpendicular to the surface of the substrate 61, the optical axis of the on-chip lens 1251 is approximately midway between the two signal extraction units 65 within the pixel 51.

[1022] By setting it in this way, infrared light can be collected at a position between the signal extraction portion 65 - 1 and the signal extraction portion 65 - 2 , and the extraction efficiency of electrons in the signal extraction portion 65 can be made substantially uniform.

[1023] Furthermore, for example Figure 88 In the example shown, the signal extraction sections 65 may be arranged with a staggered arrangement so that the position between the signal extraction section 65 - 1 and the signal extraction section 65 - 2 becomes the position of the optical axis of the on-chip lens 1251 .

[1024] (Thirty-second embodiment)

[1025] (Structural Example of Pixel)

[1026] Reference Figures 91 to 93 The structure of the pixel 51 according to the thirty-second embodiment will be described.

[1027] Figure 91 This is a diagram showing the pixel 51 as viewed from a direction perpendicular to the surface of the substrate 61 .

[1028] In this example, a pixel isolation portion 1761 that functions as a pixel isolation region for isolating the region of the pixel 51 is formed at a boundary portion between adjacent pixels 51 so as to surround the region of each pixel 51 .

[1029] Here, Figure 92 as well as Figure 93 Zhongyu Figure 91 The cross section corresponding to the F12-F12' line and the cross section corresponding to the G12-G12' line.

[1030] Figure 92 as well as Figure 93 The structure of the pixel 51 shown is formed as follows: Figure 59 as well as Figure 60 In the structure of the pixel 51, the oxide film 1252 and the fixed charge film 1253 are replaced by a structure including an oxide film 1801, a fixed charge film 1802, an oxide film 1803, and a fixed charge film 1804.

[1031] like Figure 92 As shown, an oxide film 1801 is formed to cover the surface of the substrate 61 on the on-chip lens 1251 side, and a fixed charge film 1802 is formed directly below the oxide film 1801, that is, on the multilayer wiring layer 811 side, to cover the surface of the oxide film 1801.

[1032] In addition, at the pixel boundary portion of the substrate 61 , an oxide film 1803 is formed to separate adjacent pixels 51 from the surface of the substrate 61 on the multilayer wiring layer 811 side to a predetermined depth, and a fixed charge film 1804 is formed to cover the surface of the oxide film 1803 .

[1033] exist Figure 92In the embodiment, the portion of the trench structure composed of the oxide film 1803 and the fixed charge film 1804 that functions as the DTI becomes the pixel separation portion 1761 , and the light receiving regions 1254 of the adjacent pixels 51 are separated by the pixel separation portion 1761 .

[1034] In addition, although it is described here that the pixel separation portion 1761 is composed of the oxide film 1803 and the fixed charge film 1804 , it can also be understood that the pixel separation portion 1761 is composed of only the oxide film 1803 .

[1035] In addition, the pixel separation portion 1761 may be formed of a metal material and a fixed charge film, or may be formed of a metal material and an oxide film.

[1036] exist Figure 92 In the example shown, a pixel separator 1761 is formed at the boundary portion of the pixel 51, so that Figure 59 Similarly to the example shown, it is possible to suppress the reflected light of the infrared light incident from the on-chip lens 1251 into the substrate 61 from being incident on the adjacent pixel 51 .

[1037] This can suppress the occurrence of crosstalk and a decrease in pixel sensitivity, and improve the characteristics of the CAPD sensor such as sensitivity characteristics and distance measurement accuracy (resolution).

[1038] In addition, Figure 92 In the example shown, Figure 59 As in the example shown, the pixel separation portion 1761 is formed at a position offset from the transistor, and therefore, the occurrence of leakage current in the P-well portion covering the transistor can be suppressed.

[1039] Furthermore, in Figure 92 In the example shown, Figure 59 Similarly to the example in , the inter-pixel light shielding film 63 and the on-chip lens 1251 are arranged in conjunction with the pixel separation units 1761 arranged in a staggered manner.

[1040] Therefore, in Figure 92 In the case shown, with Figure 59 Similarly to the case in , the amount of light (received light amount) guided into the light receiving area 1254 by the on-chip lens 1251 can be increased, and the sensitivity characteristics can be improved.

[1041] In addition, with Figure 91 The cross-sectional view of the pixel 51 taken along line G12-G12' is shown in FIG. Figure 93 As shown. Figure 93 In FIG. 1 , the oxide film 1803 and the fixed charge film 1804 constituting the pixel separation portion 1761 are formed to penetrate the oxide film 64 from the surface of the substrate 61 on the multilayer wiring layer 811 side to a position of a predetermined depth.

[1042] In manufacturing Figure 92 as well as Figure 93 In the case of the pixel 51 having the structure shown, first, an oxide film 64 is formed on the substrate 61, and then a groove (trench) is formed in the pixel boundary portion of the substrate 61 from the surface side (the multilayer wiring layer 811 side) by dry etching.

[1043] Then, after forming the pixel separation portion 1761 in the groove portion formed in the substrate 61, annealing treatment, that is, defect repair, is performed, and then a P well covering the transistor and a signal extraction portion 65 are formed.

[1044] Therefore, by repairing pixel defects through annealing during the manufacture of the substrate 61 , it is possible to obtain a substrate 61 with fewer defects.

[1045] In addition, assuming that DTI is formed from the light incident surface side of the substrate 61 (on-chip lens 1251 side), when the substrate 61 is dry-etched to form DTI, the P well and signal extraction part 65 covering the transistor have already been formed, and therefore annealing cannot be performed.

[1046] In contrast, in Figure 92 、 Figure 93 In the structure shown, annealing can be performed after forming the pixel separation portion 1761 and before forming the P-well and the signal extraction portion 65 , thereby obtaining a light-receiving element 1 with fewer pixel defects.

[1047] In addition, Figures 91 to 93 In the example shown, the on-chip lens 1251 can be arranged so that the optical axis of the on-chip lens 1251 is approximately midway between the two signal extraction sections 65 within the pixel 51. Alternatively, the signal extraction sections 65 can be staggered so that the optical axis of the on-chip lens 1251 is positioned midway between the two signal extraction sections 65.

[1048] In addition, in the twenty-first embodiment to the thirty-second embodiment described above, for example, Figure 59 、 Figure 62 、 Figure 65 、 Figure 68 , etc., describe an example in which a reflective member 815 is provided on the multilayer wiring layer 811. Specifically, in this example, when viewed from above, that is, when viewed from a direction perpendicular to the surface of the substrate 61, the reflective member 815 is provided so as to overlap with the N+ semiconductor region 71. However, a light shielding member 631' may be provided in place of the reflective member 815. In this case, the light shielding member 631' is provided so as to overlap with the N+ semiconductor region 71 when viewed from above.

[1049] (Configuration example of a distance measurement module)

[1050] Figure 94 Is to use Figure 1 1 is a block diagram showing a configuration example of a distance measuring module in which the light receiving element 1 outputs distance measurement information.

[1051] The distance measuring module 5000 includes a light emitting unit 5011 , a light emission control unit 5012 , and a light receiving unit 5013 .

[1052] The light-emitting unit 5011 includes a light source that emits light of a predetermined wavelength, and emits illumination light with periodically varying brightness, which is then directed toward an object. For example, the light-emitting unit 5011 includes a light-emitting diode (LED) that emits infrared light with a wavelength in the range of 780 nm to 1000 nm as a light source. The light-emitting unit 5011 generates the illumination light in synchronization with a rectangular wave illumination control signal CLKp supplied from the illumination control unit 5012.

[1053] Furthermore, the light emission control signal CLKp is not limited to a rectangular wave as long as it is a periodic signal. For example, the light emission control signal CLKp may be a sine wave.

[1054] The light control unit 5012 supplies a light control signal CLKp to the light emitting unit 5011 and the light receiving unit 5013 to control the timing of the light emission. The frequency of the light control signal CLKp is, for example, 20 megahertz (MHz). The frequency of the light control signal CLKp is not limited to 20 MHz and may also be 5 MHz, for example.

[1055] The light receiving unit 5013 receives reflected light from an object, calculates distance information for each pixel based on the light reception result, generates and outputs a depth image that represents the distance to the object using a grayscale value for each pixel.

[1056] The above-mentioned light receiving element 1 is used in the light receiving unit 5013. As the light receiving element 1 of the light receiving unit 5013, for example, based on the light emission control signal CLKp, the distance information is calculated for each pixel according to the signal intensity detected by the respective charge detection units (N+ semiconductor region 71) of the signal extraction units 65-1 and 65-2 of each pixel 51 of the pixel array unit 20.

[1057] As described above, the light receiving unit 5013 of the distance measuring module 5000 that obtains and outputs the distance information to the subject by the indirect ToF method can be assembled Figure 1 By employing the light receiving element 1 of each of the above-described embodiments as the light receiving portion 5013 of the distance measuring module 5000, specifically, employing a back-illuminated light receiving element with improved pixel sensitivity, the distance measuring characteristics of the distance measuring module 5000 can be improved.

[1058] (Application example to mobile objects)

[1059] The technology of the present invention (the present technology) can be applied to a variety of products. For example, the technology of the present invention can be implemented as a device installed in any mobile object, such as an automobile, electric vehicle, hybrid vehicle, motorcycle, bicycle, personal mobility device, aircraft, drone, ship, or robot.

[1060] Figure 95 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present invention can be applied.

[1061] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 96 In the example shown, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. The functional configuration of integrated control unit 12050 includes a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface 12053.

[1062] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a braking device that generates the vehicle's braking force.

[1063] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a controller for keyless entry systems, smart key systems, power windows, and various lights such as headlights, taillights, brake lights, indicators, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[1064] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture images outside the vehicle and receive the captured images. The vehicle exterior information detection unit 12030 can also perform object detection processing, such as people, vehicles, obstacles, signs, or text on the road, or distance detection processing based on the received images.

[1065] The imaging unit 12031 is a photosensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as both an image and distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared.

[1066] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver status detection unit 12041 is connected to the in-vehicle information detection unit 12040 to detect the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration level, or determine whether the driver is drowsy.

[1067] The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on vehicle interior and exterior information obtained from the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, or vehicle departure warning.

[1068] In addition, the microcomputer 12051 can control the driving force generating device, control mechanism or braking device based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for the purpose of automatic driving, etc., which is independent of the driver's operation.

[1069] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform coordinated control for the purpose of preventing glare, such as switching from high beam to low beam.

[1070] The audio and video output unit 12052 can send an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the passengers of the vehicle or the outside of the vehicle. Figure 96 In the example of FIG, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[1071] Figure 96 This is a diagram showing an example of the installation position of the camera unit 12031.

[1072] Figure 96 In FIG, the vehicle 12100 includes the imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as the imaging unit 12031 .

[1073] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front bumper, side mirrors, rear bumper, trunk lid, and the upper portion of the front windshield within the vehicle 12100. Camera 12101 on the front bumper and camera 12105 on the upper portion of the front windshield within the vehicle primarily capture images of the front of vehicle 12100. Cameras 12102 and 12103 on the side mirrors primarily capture images of the sides of vehicle 12100. Camera 12104 on the rear bumper or trunk lid primarily captures images of the rear of vehicle 12100. The images of the front captured by cameras 12101 and 12105 are primarily used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[1074] In addition, Figure 96shows an example of the imaging ranges of the cameras 12101 to 12104. Imaging range 12111 represents the imaging range of the camera 12101 installed on the front bumper, imaging ranges 12112 and 12113 represent the imaging ranges of the cameras 12102 and 12103 installed on the side mirrors, respectively, and imaging range 12114 represents the imaging range of the camera 12104 installed on the rear bumper or tailgate. For example, by overlaying the image data captured by the cameras 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

[1075] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[1076] For example, based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 calculates the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change in this distance (relative speed to the vehicle 12100). This allows the microcomputer 12051 to identify the closest three-dimensional object on the path of the vehicle 12100, particularly one traveling in the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to the preceding vehicle and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). This enables coordinated control aimed at autonomous driving, which allows the vehicle to travel independently of the driver's operation.

[1077] For example, based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data related to three-dimensional objects into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, and extract these data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that are visually visible to the driver of the vehicle 12100 and those that are difficult to visually identify. The microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk exceeds a set value, indicating a potential collision, the microcomputer 12051 outputs an alert to the driver via the audio speaker 12061 and display unit 12062, and initiates forced deceleration and evasive steering via the drive system control unit 12010, thereby providing driving assistance to avoid collisions.

[1078] At least one of the imaging units 12101 to 12104 may also be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104, the audio and video output unit 12052 controls the display unit 12062 to display a square outline for emphasis overlaid on the recognized pedestrian. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[1079] The above describes an example of a vehicle control system to which the technology of the present invention can be applied. The technology of the present invention can be applied to the camera unit 12031 in the structure described above. Specifically, for example, Figure 1 The light receiving element 1 shown is applied to the imaging unit 12031, and characteristics such as sensitivity can be improved.

[1080] The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present technology.

[1081] For example, it is naturally possible to appropriately combine two or more of the above-described embodiments. Specifically, the number and placement of signal extraction units within a pixel, the shape of the signal extraction units and whether they are shared, the presence or absence of on-chip lenses, the presence or absence of inter-pixel light shielding, the presence or absence of isolation regions, the thickness of on-chip lenses and substrates, the type and film design of the substrate, the presence or absence of a bias voltage toward the light incident surface, the presence or absence of a reflective component, and the like can be appropriately selected based on which characteristic, such as the sensitivity of the pixel, is prioritized.

[1082] Furthermore, while the above embodiments describe an example using electrons as signal carriers, holes generated by photoelectric conversion can also be used as signal carriers. In this case, as long as the charge detection unit for detecting the signal carriers is composed of a P+ semiconductor region and the voltage application unit for generating an electric field within the substrate is composed of an N+ semiconductor region, the charge detection unit provided in the signal extraction unit can detect the holes as signal carriers.

[1083] According to the present technology, by configuring the CAPD sensor as a back-illuminated light-receiving element, it is possible to improve the distance measurement characteristics.

[1084] Furthermore, while the above embodiment describes a driving method in which a voltage is directly applied to the P+ semiconductor region 73 formed on the substrate 61, thereby causing the photoelectrically converted charge to move via the generated electric field, the present technology is not limited to this driving method and may also be applied to other driving methods. For example, a driving method may also be employed in which a predetermined voltage is applied to the gates of the first and second transfer transistors, respectively, formed on the substrate 61, thereby distributing the photoelectrically converted charge to the first floating diffusion region via the first transfer transistor or to the second floating diffusion region via the second transfer transistor for accumulation. In this case, the first and second transfer transistors formed on the substrate 61 function as first and second voltage application units, respectively, for applying the predetermined voltage to the gates, and the first and second floating diffusion regions formed on the substrate 61 function as first and second charge detection units, respectively, for detecting the charge generated by the photoelectric conversion.

[1085] In other words, in a drive method in which a voltage is directly applied to the P+ semiconductor region 73 formed on the substrate 61, and the resulting electric field causes the photoelectrically converted charge to ...

Claims

1. A light receiving element, characterized in that: have: Light receiving area, with: A first voltage applying unit to which a first voltage is applied; a first charge detection unit disposed around the first voltage applying unit; a second voltage applying unit to which a second voltage different from the first voltage is applied; as well as a second charge detection unit disposed around the second voltage applying unit; as well as a separation portion, the separation portion being arranged at a boundary between the adjacent light receiving areas to separate the light receiving areas; The first voltage applying unit and the first charge detecting unit are shared by the light receiving region and another adjacent light receiving region at a boundary at one end of the light receiving region. The second voltage applying section and the second charge detecting section are shared by the light receiving region and another adjacent light receiving region at a boundary of the other end of the light receiving region opposite to the one end.

2. The light receiving element according to claim 1, wherein The light receiving element further comprises: On-chip lens; wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer, The light receiving region and the separation portion are formed in the semiconductor layer.

3. The light receiving element according to claim 2, wherein The wiring layer has at least one layer including a reflective member. The reflecting member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

4. The light receiving element according to claim 2, wherein The wiring layer includes at least one layer having a light shielding member, The light shielding member is provided so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

5. The light receiving element according to claim 2, wherein The device further includes a transistor region in which a transistor connected to the first charge detection portion and a transistor connected to the second charge detection portion are provided.

6. The light receiving element according to claim 5, wherein The isolation portion is provided in a region different from the transistor region in a plan view.

7. The light receiving element according to claim 5 or 6, wherein: The separation portion is provided at both ends of the transistor region.

8. The light receiving element according to claim 1, wherein The light receiving area is surrounded by the separation portion in a plan view.

9. The light receiving element according to claim 2, wherein The on-chip lens is arranged so that the optical axis position of the on-chip lens is substantially at the center of the region surrounded by the separation portion.

10. The light receiving element according to claim 2, wherein The on-chip lens is arranged so that the optical axis position of the on-chip lens is substantially midway between the first charge detection portion and the second charge detection portion.

11. The light receiving element according to claim 1, wherein A plurality of the first voltage applying sections and the first charge detecting sections, and a plurality of the second voltage applying sections and the second charge detecting sections are formed in the light receiving region.

12. The light receiving element according to claim 2, wherein The separation portion is formed to penetrate the semiconductor layer.

13. The light receiving element according to claim 2, wherein The separation portion is formed to a predetermined depth from a surface of the semiconductor layer on the wiring layer side.

14. The light receiving element according to claim 2, wherein The separation portion is formed to a predetermined depth from a surface of the semiconductor layer on the on-chip lens side.

15. The light receiving element according to claim 14, wherein An oxide film is formed between a surface of the semiconductor layer on the wiring layer side and the isolation portion.

16. The light receiving element according to claim 1, wherein The separation portion is formed of at least an oxide film.

17. The light receiving element according to claim 1, wherein The separation portion is formed of at least a fixed charge film.

18. The light receiving element according to claim 1, wherein The separation portion is formed of at least a metal material.

19. The light receiving element according to claim 1, wherein The separation portion is formed of at least an N-type semiconductor region or a P-type semiconductor region.

20. The light receiving element according to claim 2, wherein The semiconductor layer is a P-type semiconductor layer, The separation portion is formed of at least an N-type semiconductor region, and a voltage greater than a voltage applied to the semiconductor layer is applied to the N-type semiconductor region.

21. The light receiving element according to claim 1, wherein No oxide film is formed in the light receiving area.

22. The light receiving element according to claim 2, wherein The first voltage applying section and the second voltage applying section are respectively composed of a first P-type semiconductor region and a second P-type semiconductor region formed in the semiconductor layer.

23. The light receiving element according to claim 2, wherein The first voltage applying section and the second voltage applying section are respectively constituted by a first transfer transistor and a second transfer transistor formed in the semiconductor layer.

24. A ranging module, characterized in that: have: The light receiving element according to any one of claims 1 to 23; a light source that emits light having a periodically varying brightness; and The light emission control unit controls the irradiation timing of the irradiation light.

Images