A stepped cascade structure

Abstract

The present invention discloses a ladder cascade structure, including a main board and a plurality of sub-boards, wherein the main board includes a main board circuit and a main board output terminal interface board, wherein the interface terminal CS1-interface terminal CS8 of the main board circuit is connected to the interface terminal CS1-interface terminal CS8 of the main board output terminal interface board through a wire pin, and the bus of the main board circuit is connected to the bus port of the main board output terminal interface board through a wire pin. The ladder cascade structure proposed by the present invention only needs to design corresponding sub-boards according to different point requirements, and each sub-board no longer has a distinction of chip select signals, thereby reducing the types of PCB boards to the greatest extent. At the same time, during the assembly operation, the additional operation step of configuring the chip select signal is omitted, thus saving manpower and time, and at the same time, there is no need to consider the installation order of each sub-board, and the comprehensive fool-proof design is efficient and reliable.

Description

Technical Field

[0001] The invention relates to the field of grating technology, and in particular to a step cascade structure. Background Art

[0002] For the application of safety gratings, the window sizes of different devices (the size that needs to be detected by the safety grating) may be different, which requires the same series of safety gratings to provide sub-models with various length points (the number of infrared tubes) to meet the diverse market needs. For example, a certain grating has a basic model with 8 points, and the grating manufacturer generally provides 10 points, 12 points, 14 points... and other series of products corresponding to this model, which maximizes the application range and enables most customers to find a model that suits the actual needs of their equipment.

[0003] To achieve this, the most direct way is to design a corresponding PCB board for each point specification in the same series. If a PCB is designed for each specification of the product, on the one hand, it will take a lot of manpower, material resources and time to design a wide variety of PCB boards; on the other hand, the entire PCB board is too long, which is not conducive to storage and transportation, and the price is not competitive if the size is too large; at the same time, in order to meet the strict delivery time of customers, each PCB board will have a certain amount of inventory, and the more types of PCB boards, the greater the total inventory and the more maintenance costs. Based on the above problems, a ladder cascade structure is proposed. Summary of the invention

[0004] The object of the present invention is to provide a stepped cascade structure, which has the advantages of minimizing the types of PCB boards, saving manpower and time, and being efficient and reliable, so as to solve the problems proposed in the above background technology that the PCB boards required to be designed are of various types, inconvenient to store and transport, and have high maintenance costs.

[0005] To achieve the above object, the present invention provides the following technical solutions: a ladder cascade structure, comprising a main board and a plurality of sub-boards, wherein the main board comprises a main board circuit and a main board output terminal interface board, wherein interface terminals CS1 to CS8 of the main board circuit are connected to interface terminals CS1 to CS8 of the main board output terminal interface board through line pins, and a bus of the main board circuit is connected to a bus port of the main board output terminal interface board through line pins;

[0006] The plurality of sub-boards are respectively recorded as sub-board A, sub-board B, sub-board C, sub-board D, sub-board E, sub-board F, sub-board G and sub-board H, and sub-board A, sub-board B, sub-board C, sub-board D, sub-board E, sub-board F, sub-board G and sub-board H all include a sub-board input terminal interface board, a sub-board output terminal interface board and a sub-board circuit;

[0007] The interface terminals CS1-CS8 of the sub-board input terminal interface board of the sub-board A are connected to the interface terminals CS1-CS8 of the main board output terminal interface board in sequence, and the bus terminals of the sub-board input terminal interface board of the sub-board A are connected to the bus terminals of the main board output terminal interface board; the interface terminal CS1 of the sub-board input terminal interface board of the sub-board A is connected to the input end of the sub-board circuit, the interface terminals CS2-CS8 of the sub-board input terminal interface board of the sub-board A are connected to the interface terminals CS1-CS7 of the sub-board output terminal interface board in sequence, the sub-board input terminal interface board bus of the sub-board A is connected to the bus terminal of the sub-board output terminal interface board through the wire pin, and the output end of the sub-board circuit of the sub-board A is connected to the bus;

[0008] The interface terminals CS1-interface terminals CS7 of the sub-board output terminal interface board of the sub-board A are connected in sequence with the interface terminals CS1-interface terminals CS7 of the sub-board input terminal interface board of the sub-board B, and the bus terminals of the sub-board output terminal interface board of the sub-board A are connected with the bus terminals of the sub-board input terminal interface board of the sub-board B; the interface terminal CS2 of the sub-board B is connected to the input end of its sub-board circuit, the interface terminals CS3-interface terminals CS8 of the sub-board B are connected to the interface terminals CS1-interface terminals CS6 of its sub-board output terminal interface board, and the bus terminals of the sub-board input terminal interface board of the sub-board B are connected to the bus terminals of its sub-board output terminal interface board;

[0009] The interface terminal CS7 of the sub-board input terminal interface board of the sub-board G is connected to the input end of its sub-board circuit 203, the interface terminal CS8 of the sub-board input terminal interface board of the sub-board G is connected to the interface terminal CS1 of its sub-board output terminal interface board, and the bus terminal of the sub-board input terminal interface board of the sub-board G is connected to the bus terminal of its sub-board output terminal interface board; the interface terminal CS1 of the sub-board output terminal interface board of the sub-board G is connected to the interface terminal CS1 of the sub-board H, the interface terminal CS8 of the sub-board input terminal interface board of the sub-board H is connected to the input end of its sub-board circuit, the bus terminal of the sub-board input terminal interface board of the sub-board H is connected to the bus terminal of its sub-board output terminal interface board, and the output end of its sub-board circuit is connected to the bus terminal.

[0010] Preferably, the sub-board A, sub-board B, sub-board C, sub-board D, sub-board E, sub-board F, sub-board G and sub-board H are of the same size and model.

[0011] Preferably, the bus includes a power line, a data line and an address line.

[0012] Preferably, the model of the mainboard output terminal interface board is the same as the model of the daughterboard output terminal interface board, and matches the interface terminal of the daughterboard input terminal interface board.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: the ladder cascade structure proposed in the present invention only needs to design corresponding sub-boards according to different point requirements, and each sub-board no longer has a distinction in chip select signals, thereby minimizing the types of PCB boards. At the same time, during assembly operations, the additional operation steps of configuring chip select signals are omitted, saving manpower and time. At the same time, there is no need to consider the installation order of each sub-board, and the comprehensive fool-proof design is efficient and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is the step cascade principle diagram of the present invention;

[0015] Figure 2 It is a cascade state diagram of the main board, sub-board A and sub-board B of the present invention;

[0016] Figure 3 This is the schematic diagram of the conventional cascade method;

[0017] Figure 4 This is the physical switch control schematic.

[0018] In the figure: 1. main board; 11. main board circuit; 12. main board output terminal interface board; 2. daughter board; 21. daughter board A; 22. daughter board B; 23. daughter board C; 24. daughter board D; 25. daughter board E; 26. daughter board F; 27. daughter board G; 28. daughter board H; 201. daughter board input terminal interface board; 202. daughter board output terminal interface board; 203. daughter board circuit. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1-2 A stepped cascade structure includes a main board 1 and several sub-boards 2, the main board 1 includes a main board circuit 11 and a main board output terminal interface board 12, the interface terminals CS1-interface terminals CS8 of the main board circuit 11 are connected to the interface terminals CS1-interface terminals CS8 of the main board output terminal interface board 12 through wire pins, and the bus of the main board circuit 11 is connected to the bus port of the main board output terminal interface board 12 through wire pins, wherein the bus includes a power line, a data line and an address line.

[0021] Several sub-boards 2 are respectively recorded as sub-board A21, sub-board B22, sub-board C23, sub-board D24, sub-board E25, sub-board F26, sub-board G27 and sub-board H28. The size and model of sub-board A21, sub-board B22, sub-board C23, sub-board D24, sub-board E25, sub-board F26, sub-board G27 and sub-board H28 are the same. Sub-board A21, sub-board B22, sub-board C23, sub-board D24, sub-board E25, sub-board F26, sub-board G27 and sub-board H28 all include a sub-board input terminal interface board 201, a sub-board output terminal interface board 202 and a sub-board circuit 203, wherein the model of the main board output terminal interface board 12 is the same as the model of the sub-board output terminal interface board 202, and matches the interface terminal of the sub-board input terminal interface board 201.

[0022] Wherein: the interface terminals CS1 to CS8 of the sub-board input terminal interface board 201 of the sub-board A21 are connected in sequence with the interface terminals CS1 to CS8 of the mainboard output terminal interface board 12, and the bus terminals of the sub-board input terminal interface board 201 of the sub-board A21 are connected with the bus terminals of the mainboard output terminal interface board 12; the sub-board input terminal interface board of the sub-board A21

[0023] The interface terminal CS1 of 201 is connected to the input end of the sub-board circuit 203, the interface terminals CS2-CS8 of the sub-board input terminal interface board 201 of the sub-board A21 are staggered in sequence and connected to the interface terminals CS1-CS7 of the sub-board output terminal interface board 202, the sub-board input terminal interface board 201 bus of the sub-board A21 is connected to the bus terminal of the sub-board output terminal interface board 202 through a wire pin, and the output end of the sub-board circuit 203 of the sub-board A21 is connected to the bus.

[0024] Among them: the interface terminal CS1-interface terminal CS7 of the sub-board output terminal interface board 202 of the sub-board A21 is connected in sequence with the interface terminal CS1-interface terminal CS7 of the sub-board input terminal interface board 201 of the sub-board B22, and the bus terminal of the sub-board output terminal interface board 202 of the sub-board A21 is connected with the bus terminal of the sub-board input terminal interface board 201 of the sub-board B22; the interface terminal CS2 of the sub-board B22 is connected to the input end of its sub-board circuit 203, the interface terminal CS3-interface terminal CS8 of the sub-board B22 is connected to the interface terminal CS1-interface terminal CS6 of its sub-board output terminal interface board 202, and the bus terminal of the sub-board input terminal interface board 201 of the sub-board B22 is connected to the bus terminal of its sub-board output terminal interface board 202.

[0025] And so on:

[0026] The interface terminal CS7 of the sub-board input terminal interface board 201 of the sub-board G27 is connected to the input end of its sub-board circuit 203, the interface terminal CS8 of the sub-board input terminal interface board 201 of the sub-board G27 is connected to the interface terminal CS1 of its sub-board output terminal interface board 202, and the bus terminal of the sub-board input terminal interface board 201 of the sub-board G27 is connected to the bus terminal of its sub-board output terminal interface board 202; the interface terminal CS1 of the sub-board output terminal interface board 202 of the sub-board G27 is connected to the interface terminal CS1 of the sub-board H28, the interface terminal CS8 of the sub-board input terminal interface board 201 of the sub-board H28 is connected to the input end of its sub-board circuit 203, the bus terminal of the sub-board input terminal interface board 201 of the sub-board H28 is connected to the bus terminal of its sub-board output terminal interface board 202, and the output end of its sub-board circuit 203 is connected to the bus terminal.

[0027] In this step-cascade structure, each sub-board 2 connects its own chip select pin to the first pin of the sub-board output terminal interface board 202, and the remaining chip select signals are staggered and connected in sequence starting from the first pin of the sub-board input terminal interface board 201, thereby realizing that the chip select signal output by the main board 1 increases by one level on its sub-board output terminal interface board 202 when passing through each sub-board 2. The whole is similar to a ladder, with cumulative increases one level at a time, ensuring that each sub-board 2 is connected to a different chip select signal, and the connections are made in sequence without confusion. When the maximum number of sub-boards 2 that can be cascaded is reached (i.e., sub-board H28), the last chip select signal is used. This cascade method only requires the design of corresponding sub-boards 2 according to different point requirements, and each sub-board

[0028] 2 There is no longer a distinction between chip select signals, which minimizes the types of PCB boards. At the same time, during assembly, the extra operation steps of configuring chip select signals are omitted, saving manpower and time. At the same time, there is no need to consider the installation order of each daughter board 2. The comprehensive fool-proof design is efficient and reliable.

[0029] As a comparative illustration, see Figure 3 :

[0030] Figure 3It is the most common cascade method. Its bus includes power lines, data lines, and address lines. The chip select signal is drawn separately. The input terminals and output terminals of the daughter board are all directly connected to the corresponding pins using parallel lines. Correspondingly, the chip select signal of each daughter board circuit needs to be connected to different pins of the input terminal to achieve a unique mapping relationship between the chip select signal and each daughter board. This means that the circuit of each daughter board is different. The chip select pin of the first daughter board is connected to the first pin of the input terminal, the chip select pin of the second daughter board is connected to the second pin of the input terminal, and so on. In the above cascade method, all daughter board circuits are different. Each daughter board with each number of points must be further subdivided into various chip select connection models, such as a certain system The column grating specification definition includes 8 chip select signals, which means that 8 daughter boards can be cascaded. The number of points on the daughter boards includes 2 points, 4 points, 6 points, and 8 points. Then, the first three types of points can be defined as cascaded in the last section, so the chip select signal can be fixed on CS8, and the 8-point daughter board belongs to the middle part and is the most commonly used general type. Therefore, 8 8-point daughter boards need to be designed, which are connected to CS1, CS2, CS3... in turn. In this way, including the main board, 12 PCB boards still need to be designed. Moreover, they cannot be used incorrectly during cascade assembly. For the same 8-point daughter board, only one board for each chip select connection can be used, and the installation order cannot be wrong, otherwise it will be inconsistent with the control logic of the main board, which will cause functional abnormalities.

[0031] As a comparison, see Figure 4 :

[0032] The daughter board circuit manually selects which chip select signal to connect to through a physical switch. The physical switch can be a miniature dip switch, a low-resistance resistor, or even a tin bridge. In this way, each daughter board does not need to distinguish the chip select signal, which greatly reduces the types of PCB boards. At the same time, when cascading and assembling, there is no need to consider the selection and cascading sequence of the daughter board. It is only necessary to install the main board and the daughter board according to the required total number of points, and then adjust the chip select switch of each daughter board in sequence to achieve the correct mapping relationship between the chip select signal and each daughter board. Similarly, because the chip select switch needs to be manually adjusted later, there is a risk of operational errors, and manual work also requires additional labor costs.

[0033] contrast Figure 3 and Figure 4 It can be seen that this ladder cascade structure only needs to design corresponding daughter boards according to different point requirements. Each daughter board no longer has a distinction in chip select signals, which minimizes the types of PCB boards. At the same time, during assembly operations, the additional operation steps of configuring chip select signals are omitted, saving manpower and time. At the same time, there is no need to consider the installation order of each daughter board. The comprehensive fool-proof design is efficient and reliable.

[0034] In summary, the ladder cascade structure proposed in the present invention only needs to design corresponding sub-boards according to different point requirements. Each sub-board no longer has a distinction in chip select signals, which minimizes the types of PCB boards. At the same time, during assembly operations, the additional operation steps of configuring chip select signals are omitted, saving manpower and time. At the same time, there is no need to consider the installation order of each sub-board. The design is fully fool-proof and efficient and reliable.

[0035] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A step cascade structure, characterized in that: The invention comprises a main board (1) and a plurality of sub-boards (2), wherein the main board (1) comprises a main board circuit (11) and a main board output terminal interface board (12), wherein interface terminals CS1 to CS8 of the main board circuit (11) are connected to interface terminals CS1 to CS8 of the main board output terminal interface board (12) via wire pins, and a bus of the main board circuit (11) is connected to a bus port of the main board output terminal interface board (12) via wire pins; The plurality of sub-boards (2) are respectively denoted as sub-board A (21), sub-board B (22), sub-board C (23), sub-board D (24), sub-board E (25), sub-board F (26), sub-board G (27) and sub-board H (28); the sub-board A (21), sub-board B (22), sub-board C (23), sub-board D (24), sub-board E (25), sub-board F (26), sub-board G (27) and sub-board H (28) all include a sub-board input terminal interface board (201), a sub-board output terminal interface board (202) and a sub-board circuit (203); The interface terminals CS1 to CS8 of the sub-board input terminal interface board (201) of the sub-board A (21) are sequentially connected to the interface terminals CS1 to CS8 of the main board output terminal interface board (12), and the bus terminals of the sub-board input terminal interface board (201) of the sub-board A (21) are connected to the bus terminals of the main board output terminal interface board (12); the interface terminal CS1 of the sub-board input terminal interface board (201) of the sub-board A (21) is connected to the input end of the sub-board circuit (203), the interface terminals CS2 to CS8 of the sub-board input terminal interface board (201) of the sub-board A (21) are sequentially staggered and connected to the interface terminals CS1 to CS7 of the sub-board output terminal interface board (202), the bus of the sub-board input terminal interface board (201) of the sub-board A (21) is connected to the bus terminals of the sub-board output terminal interface board (202) through line pins, and the output end of the sub-board circuit (203) of the sub-board A (21) is connected to the bus; The interface terminals CS1-CS7 of the sub-board output terminal interface board (202) of the sub-board A (21) are connected in sequence with the interface terminals CS1-CS7 of the sub-board input terminal interface board (201) of the sub-board B (22); the bus terminals of the sub-board output terminal interface board (202) of the sub-board A (21) are connected with the bus terminals of the sub-board input terminal interface board (201) of the sub-board B (22); the interface terminals CS2 of the sub-board B (22) are connected to the input end of its sub-board circuit (203); the interface terminals CS3-CS8 of the sub-board B (22) are connected to the interface terminals CS1-CS6 of its sub-board output terminal interface board (202); and the bus terminals of the sub-board input terminal interface board (201) of the sub-board B (22) are connected to the bus terminals of its sub-board output terminal interface board (202); The interface terminal CS7 of the sub-board input terminal interface board (201) of the sub-board G (27) is connected to the input end of its sub-board circuit (203); the interface terminal CS8 of the sub-board input terminal interface board (201) of the sub-board G (27) is connected to the interface terminal CS1 of its sub-board output terminal interface board (202); the bus terminal of the sub-board input terminal interface board (201) of the sub-board G (27) is connected to the bus terminal of its sub-board output terminal interface board (202); the interface terminal CS1 of the sub-board output terminal interface board (202) of the sub-board G (27) is connected to the interface terminal CS1 of the sub-board H (28); the interface terminal CS8 of the sub-board input terminal interface board (201) of the sub-board H (28) is connected to the interface terminal CS1 of its sub-board circuit (203); The input end of the sub-board input terminal interface board (201) of the sub-board H (28) is connected to the bus terminal of its sub-board output terminal interface board (202), and the output end of its sub-board circuit (203) is connected to the bus terminal. The sub-board A (21), sub-board B (22), sub-board C (23), sub-board D (24), sub-board E (25), sub-board F (26), sub-board G (27) and sub-board H (28) are of the same size and model. The bus includes a power line, a data line and an address line. The model of the mainboard output terminal interface board (12) is the same as that of the sub-board output terminal interface board (202), and matches the interface terminal of the sub-board input terminal interface board (201).

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