Chip edge structure and manufacturing method

Abstract

The present invention relates to the field of semiconductor device technology, and in particular to a chip edge structure and a manufacturing method thereof. The chip edge structure comprises an edge main structure layer, a passivation layer and an organic film layer, wherein the passivation layer is arranged on the surface of the edge main structure layer along a preset direction, and the passivation layer has at least one recessed area; the organic film layer is arranged on the surface of the passivation layer along a preset direction, and fills each recessed area. Since the organic film layer fills the recessed area of ​​the passivation layer, the organic film layer can be firmly solidified with the passivation layer, and therefore, the passivation layer is not prone to peeling or falling off during the process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a chip edge structure and a manufacturing method thereof. Background Art

[0002] Power devices such as Schottky diodes can operate at voltages of several hundred volts or even several thousand volts. When power devices operate under such high electric fields, the degree of insulation between them and the environment is a relatively important design factor.

[0003] In order to have excellent insulation properties, traditional processes deposit one or more passivation layers on power devices. The passivation layer can be used to reduce electrical stress, mechanical stress, water vapor or chemical corrosion on the metal surface of the power device.

[0004] In the process of realizing the present invention, the inventors found that the conventional technology has at least the following problems: although the power device has good electrical characteristics, the passivation layer of the power device will generate additional stress with the underlying material during other process steps, such as back grinding or cutting, causing the passivation layer to easily peel or even fall off. The fall-off of the passivation layer often occurs at the corners of the power device chip. Summary of the invention

[0005] An object of an embodiment of the present invention is to provide a chip edge structure and a manufacturing method, wherein the passivation layer has better firmness.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present invention provides a chip edge structure, including:

[0008] Edge main structure layer;

[0009] A passivation layer is arranged on the surface of the edge main structure layer along a preset direction, and the passivation layer has at least one recessed area;

[0010] The organic film layer is arranged on the surface of the passivation layer along the preset direction and fills each of the recessed areas.

[0011] In a second aspect, an embodiment of the present invention provides a junction terminal extension structure, comprising any one of the chip edge structures described above.

[0012] In a third aspect, an embodiment of the present invention provides a power device, comprising any one of the chip edge structures described.

[0013] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising the power device.

[0014] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a chip edge structure, the method comprising:

[0015] Providing an edge main structure layer;

[0016] Depositing a passivation layer on the surface of the edge main structure layer;

[0017] Patterning the passivation layer to form at least one recessed area;

[0018] An organic film layer is formed on the surface of the passivation layer, and the organic film layer fills each of the recessed areas.

[0019] In the chip edge structure and manufacturing method provided by various embodiments of the present invention, the passivation layer is stacked on the surface of the edge main structure layer along a preset direction, and the surface of the passivation layer is provided with at least one recessed area, and the organic film layer is stacked on the surface of the passivation layer along a preset direction and fills each of the recessed areas. Since the organic film layer fills the recessed areas of the passivation layer, the organic film layer can be firmly solidified with the passivation layer, so the passivation layer is not prone to peeling or falling off during the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0021] Figure 1 is a schematic diagram of a chip edge structure provided by an embodiment of the present invention;

[0022] Figure 2 is a cross-sectional view of the edge main structure layer after the passivation layer is formed according to the first embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of forming a recessed area by dry etching a passivation layer according to the first embodiment of the present invention;

[0024] Figure 4 is a cross-sectional view of a recessed area filled with an organic film layer provided in a first embodiment of the present invention;

[0025] Figure 5 is a cross-sectional view of an edge main structure layer after a passivation layer is formed according to a second embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of forming a first recessed portion of a recessed region by dry etching a passivation layer according to a second embodiment of the present invention;

[0027] Figure 7is a schematic diagram of forming a second recessed portion of a recessed region by wet etching an interlayer dielectric provided by a second embodiment of the present invention;

[0028] Figure 8 is a cross-sectional view of a recessed area filled with an organic film layer provided in a second embodiment of the present invention;

[0029] Fig. 9 is a cross-sectional view of an edge main structure layer after a passivation layer is formed according to a third embodiment of the present invention;

[0030] Fig.10 is a schematic diagram of the initial shape of the recessed area formed by dry etching the passivation layer and the interlayer dielectric provided by the third embodiment of the present invention;

[0031] Fig.11 is a schematic diagram of the final shape of the recessed area formed by wet etching the interlayer dielectric provided by the third embodiment of the present invention;

[0032] Fig.12 is a cross-sectional view of a recessed area filled with an organic film layer provided in a third embodiment of the present invention;

[0033] Fig.13 is a cross-sectional view of the edge main structure layer after forming the first passivation layer and the second passivation layer provided in the fourth embodiment of the present invention;

[0034] Fig.14 is a schematic diagram of forming a first recessed portion of a recessed region by dry etching a second passivation layer according to a fourth embodiment of the present invention;

[0035] Fig.15 is a schematic diagram of forming a second recessed portion of a recessed region by wet etching a first passivation layer according to a fourth embodiment of the present invention;

[0036] Fig.16 is a cross-sectional view of a recessed area filled with an organic film layer provided in a fourth embodiment of the present invention;

[0037] Fig.17 is a schematic diagram of forming an initial shape of a recessed area by dry etching the second passivation layer and the first passivation layer according to a fifth embodiment of the present invention;

[0038] Fig.18 is a schematic diagram of the final shape of the recessed area formed by wet etching the first passivation layer and the interlayer dielectric provided by the fifth embodiment of the present invention;

[0039] Fig.19 is a cross-sectional view of a recessed area filled with an organic film layer provided in a fifth embodiment of the present invention;

[0040] Fig. 20 is a schematic diagram of a planar pattern of a recessed area in a strip shape provided by an embodiment of the present invention;

[0041] Fig.21 is a schematic diagram of a planar pattern of a recessed area provided by an embodiment of the present invention in the form of a dotted line;

[0042] Fig. 22 is a schematic diagram of a planar pattern of a recessed area in a dot matrix provided by an embodiment of the present invention;

[0043] Fig.23 is a flow chart of a method for manufacturing a chip edge structure provided by an embodiment of the present invention;

[0044] Fig.24 yes Fig.23 A schematic flow chart of a second embodiment of S53;

[0045] Fig.25 yes Fig.23 A schematic flow chart of a third embodiment of S53;

[0046] Fig.26 yes Fig.23 Schematic diagram of the process of S52;

[0047] Fig. 27 yes Fig.23 A schematic flow chart of a fourth embodiment of S53;

[0048] Fig.28 yes Fig.23 FIG. 5 is a flow chart of the fifth embodiment of S53. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] Although the embodiments of the present invention use terms such as first, second, etc. to represent each element, it is understood that these elements should not be limited by the above terms. The above terms are only used to distinguish one element from another element. For example, the first element can be named as the second element, and similarly, the second element can be named as the first element, and the above-mentioned naming is not used to limit the scope of protection of the present invention. In addition, the number of each element represented by the first, second, etc. includes the singular and the plural, unless the context clearly indicates otherwise.

[0051] When the terms "include" and "comprising" are used in the embodiments of the present invention, they specify the existence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0052] The term "substrate" used in the embodiments of the present invention may include any semiconductor structure having a semiconductor surface. In some embodiments, the substrate includes a silicon carbide substrate (SiC substrate) or a silicon (Si) substrate or a gallium nitride (GaN) substrate. In other embodiments, the substrate may also include silicon germanium (SiGe), germanium (Ge) or gallium arsenide (GaAs).

[0053] The term “horizontal” referred to in the embodiments of the present invention is intended to describe a surface substantially parallel to a semiconductor substrate, for example, a surface of a silicon carbide substrate.

[0054] The term “vertical” referred to in the embodiments of the present invention is intended to describe an orientation substantially parallel to a normal direction of a surface of a semiconductor substrate.

[0055] As shown below, the positional relationship between the layers of one or more interlayer materials involved in the embodiments of the present invention is expressed using terms such as "stacked" or "formed" or "applied" or "set". It can be understood by those skilled in the art that any term such as "stacked" or "formed" or "applied" can cover all ways, types and technologies of "stacked". For example, sputtering, electroplating, molding, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), evaporation, hybrid physical-chemical vapor deposition (Hybrid Physical-Chemical Vapor Deposition, HPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), etc.

[0056] The chip edge structure provided in the embodiment of the present invention can be formed in a junction termination extension (JTE), and the junction termination extension structure can be a single-region JTE or a multi-region JTE. It is understandable that the chip edge structure can also be combined with various types of active regions and metal electrodes to form power devices of various types and specifications, for example, power devices include Schottky Barrier Diodes (SBDs), JBS diodes, bipolar insulated gate field effect transistors (IGBTs), metal oxide insulated gate field effect transistors (MOSs), thyristors (SCRs), and the like.

[0057] It can also be understood that power devices can also be combined with other discrete components (such as power devices, capacitors, inductors, processors, etc.) to form functional circuits that implement specific electrical functions, for example, an intelligent power module (IPM) composed of IGBT transistors and other discrete components, or a half-wave rectifier bridge or full-wave rectifier bridge composed of multiple diodes, or a half-bridge drive circuit or full-bridge drive circuit composed of multiple MOS tubes, etc.

[0058] However, it can be further understood that the functional circuit composed of power devices can also be combined with other functional circuits or power structures or physical structures to form an electronic device that can realize specific functions. For example, an intelligent power module is combined with an engine to realize the power output of a drone.

[0059] So far, the chip edge structure provided by the embodiment of the present invention can be applied to any suitable industry field, and the examples given in the embodiment of the present invention are not intended to limit the protection scope of the present invention.

[0060] The following will be described in detail with reference to the accompanying drawings of the specification. It will be appreciated by those skilled in the art that the accompanying drawings of the specification are used as exemplary multiple cross-sectional views and other schematic diagrams of idealized embodiments of the present invention to describe embodiments of the present invention, and therefore, those skilled in the art can expect changes in the shapes of the drawings due to manufacturing techniques and / or tolerances. Therefore, the embodiments of the present invention should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, such as those caused by manufacturing. For example, a recessed region shown as dry etching or wet etching will have different binary changes depending on the different degrees of reduction formed. Therefore, the regions shown in the figures are actually schematic, and their shapes are not intended to represent the precise shape of the region of the device, and are not intended to limit the scope of protection of the present invention. For various layers and regions, embodiments of the present invention are described with reference to specific polarity conductivity types. However, as will be appreciated by those skilled in the art, the polarity of the layers and regions can be reversed to provide devices of opposite polarity.

[0061] See also Figure 1 The chip edge structure 100 includes: an edge main structure layer 200 , a passivation layer 300 and an organic film layer 400 .

[0062] The edge main structure layer 200 is a basic structure layer for realizing the semiconductor function of the power device.

[0063] The passivation layer 300 is arranged on the surface 20 of the edge main structure layer 200 along a preset direction, and the passivation layer 300 has a recessed area 31, wherein the number of the recessed areas 31 may be one or more. In this embodiment, it can be understood by those skilled in the art that: for the purpose of the invention of the embodiment of the present invention, the preset direction is to arrange the passivation layer 300 on the surface 20 of the edge main structure layer 200 to form a reasonable direction capable of realizing the electrical function of the power device, for example, the direction substantially parallel to the surface 20 of the edge main structure layer 200 is the horizontal direction, the preset direction is the direction of the normal line substantially perpendicular to the horizontal direction, and by selecting the corresponding setting method, the passivation layer 300 is arranged on the surface 20 of the edge main structure layer 200 in the vertical direction.

[0064] In some embodiments, the passivation layer 300 may be a single layer or multiple layers. The passivation layer 300 is made of a passivation material, for example, the passivation layer 300 is made of plasma enhanced tetraethylorthosilicate (PETEOS) or plasma enhanced nitride (PENit).

[0065] The organic film layer 400 is disposed on the surface 32 of the passivation layer 300 along a preset direction, and the organic film layer 400 fills each recessed area 31. For example, following the above example, the organic film layer 400 is disposed on the surface 32 of the passivation layer 300 along a vertical direction, and when disposed, the organic film layer 400 flows into each recessed area 31, so that the organic film layer 400 fills each recessed area 31.

[0066] After the organic film layer 400 is filled into each recessed area 31 , the organic film layer 400 can be firmly solidified with the passivation layer 300 . Therefore, the passivation layer 300 is not prone to peeling or falling off during the process.

[0067] In some embodiments, the organic film layer 400 may be a polyimide layer, or other suitable organic layer. Generally, polyimide has the characteristics of light weight, flexibility, heat resistance and chemical resistance, and is suitable for protecting silicon carbide power devices. Polyimide is generally used together with a plasma enhanced chemical vapor deposition material to form a multi-layer passivation layer, for example, polyimide is used together with plasma enhanced tetraethyl orthosilicate or plasma enhanced nitride to obtain more ideal electrical and mechanical properties.

[0068] In some embodiments, see Figure 2The edge main structure layer 200 includes: a substrate 21 (Substrate), an epitaxial layer 22 (Epitaxy), a doped junction region 23 (Doped junction region), an interlayer dielectric 24 (Interlayerdielectric, ILD) and a top metal layer 25 (Top metal layer).

[0069] The substrate 21 can be made of various types of semiconductor materials, such as a silicon carbide substrate. As an example, the substrate 21 can be formed of silicon carbide of a first conductivity type (e.g., N-type or P-type). The substrate 21 is highly doped silicon carbide with a thickness of 350um and a resistivity in the range of 0.02Ω·cm to 0.03Ω·cm. Among them, the semiconductor type of the substrate is determined by the majority carriers in the semiconductor. If the majority carriers of the first conductivity type are holes, the first conductivity type is P-type, the heavily doped first conductivity type is P+ type, and the lightly doped first type is P-type; if the majority carriers of the first conductivity type are electrons, the first conductivity type is N-type, the heavily doped first conductivity type is N+ type, and the lightly doped first type is N-type. If the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.

[0070] The epitaxial layer 22 is disposed on the surface of the substrate 21 along a preset direction. As an example, the epitaxial layer 22 is a first conductive type (e.g., N-type or P-type) silicon carbide grown on the substrate 21. The epitaxial layer 22 is lightly doped silicon carbide with a thickness in the range of 5um to 30um and a doping concentration in the range of 1e15cm -3 to 2e16cm -3 within the range.

[0071] The doped junction region 23 is disposed in the surface region of the epitaxial layer 22 and extends from the surface of the epitaxial layer 22 toward the substrate 21. For example, the doped junction region 23 is doped on a portion of the surface of the epitaxial layer 22 along a preset direction by ion implantation and diffusion. As an example, the doped junction region 23 is a second conductivity type (for example, P type or N type) with a higher doping concentration than the epitaxial layer 22. The junction depth of the doped junction region 23 is in the range of 0.3um to 1.2um, and the doping concentration is in the range of 1e18cm -3 to 1e20cm -3 within the range.

[0072] The interlayer dielectric 24 is disposed on a portion of the surface of the epitaxial layer 22 along a preset direction, and the interlayer dielectric 24 is in contact with the doped junction region 23. The interlayer dielectric 24 is deposited on the surface of the epitaxial layer 22 and patterned to expose the contact region 241. The interlayer dielectric 24 may be formed of a suitable oxide, such as a silane (SiH4)-based oxide or a tetraethyl orthosilicate (TEOS)-based oxide. The oxide used as the interlayer dielectric 24 may be formed by a suitable process, including but not limited to low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, etc.

[0073] In some embodiments, the interlayer dielectric 24 is formed by depositing plasma enhanced tetraethyl orthosilicate, and the thickness of the interlayer dielectric 24 is in the range of 1 um to 2 um.

[0074] The top metal layer 25 is disposed on the surface of the doped junction region 23 along a preset direction, and the top metal layer 25 contacts the interlayer dielectric 24, so that at least a portion of the interlayer dielectric 24 is sandwiched between the doped junction region 23 and the top metal layer 25 along the preset direction. The top metal layer 25 is a metal layer, for example, the metal material used by the top metal layer 25 includes aluminum (Al), titanium (Ti), nickel (Ni), or can be a multilayer metal layer formed by two or more of the above metals. In some embodiments, the top metal layer 25 is aluminum, and its thickness is in the range of 1um to 4um.

[0075] Figure 2 Scribe lines 26 are also shown.

[0076] The passivation layer 300 is disposed on the surface of the interlayer dielectric 24 and the top metal layer 25 along a preset direction. For example, in some embodiments, a single-layer passivation layer 300 is formed by depositing plasma-enhanced tetraethyl orthosilicate, and the thickness of the passivation layer 300 is in the range of 1um to 2um. In other embodiments, a single-layer passivation layer 300 of plasma-enhanced nitride may also be deposited on the surface of the single-layer passivation layer 300 of plasma-enhanced tetraethyl orthosilicate, so that a double-layer passivation layer 300 is formed. It is understandable that those skilled in the art can deposit multiple layers of passivation layer 300 according to the teachings of the present invention and in combination with business needs, and are not limited to the examples of single-layer or double-layer passivation layer 300 shown above or below.

[0077] See also Figure 3, the passivation layer 300 is patterned, etched and forms a recessed area 31. In some embodiments, the recessed area 31 may also be referred to as an anchor zone. As an example, a single-layer passivation layer 300 is etched by dry etching. During the etching process, the reactive ions 33 react with the plasma-enhanced tetraethyl orthosilicate of the passivation layer 300 for a fixed time specified in the process recipe, thereby removing a specific thickness of the plasma-enhanced tetraethyl orthosilicate in the passivation layer 300.

[0078] See also Figure 4 , an organic film layer 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recessed area 31. As an example, the thickness of the organic film layer 400 is 4um to 8um.

[0079] Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100 .

[0080] The difference from the above embodiments is that, in some embodiments, the recessed area 31 is formed on the passivation layer 300 and the interlayer dielectric 24. Each recessed area 31 includes a first recessed portion 311 and a second recessed portion 312, the first recessed portion 311 is connected to the second recessed portion 312, and the maximum width of the second recessed portion 312 is greater than the maximum width of the first recessed portion 311 in a direction perpendicular to the preset direction, that is, in a horizontal direction substantially parallel to the surface 21 of the edge main structure layer 200.

[0081] See also Figure 5 , a plasma enhanced nitride is deposited on the surfaces of the interlayer dielectric 24 and the top metal layer 25 along a preset direction to form a passivation layer 300 , wherein the thickness of the passivation layer 300 is in the range of 0.5 um to 2 um.

[0082] See also Figure 6 The passivation layer 300 is patterned by dry etching to form a first recessed portion 311. During the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the passivation layer 300 for a fixed time specified in the process recipe, thereby removing a specific thickness of the plasma enhanced nitride in the passivation layer 300 and stopping at the interlayer dielectric 24.

[0083] See also Figure 7, the interlayer dielectric 24 is etched to form a second recessed portion 312. As an example, the interlayer dielectric 24 is patterned by wet etching to form the second recessed portion 312. The wet etching method mainly uses hydrofluoric acid as a reactant. During the wet etching process, the hydrofluoric acid 34 isotropically removes the plasma enhanced tetraethyl orthosilicate in a specific thickness in the interlayer dielectric 24 according to the fixed time specified in the process recipe. Due to the high selectivity between plasma enhanced tetraethyl orthosilicate and plasma enhanced nitride under the wet etching method, the shape of the passivation layer 300 will not be changed.

[0084] Please refer again Figure 7 The first recess 311 is located on the passivation layer 300, and the second recess 312 is in contact with the interlayer dielectric 24. For example, the surface of the interlayer dielectric 24 can serve as the bottom of the second recess 312. In some embodiments, the second recess 312 can also extend into the interlayer dielectric 24.

[0085] See also Figure 8 , an organic film layer 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recessed area 31. As an example, the thickness of the organic film layer 400 is 4um to 8um.

[0086] Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100 .

[0087] Different from the above embodiments, in some embodiments, the initial shape of the recessed region 31 may be formed on the passivation layer 300 and the interlayer dielectric 24 , and the final shape of the recessed region 31 may be formed later.

[0088] See also Fig. 9 , by depositing plasma enhanced nitride on the surface of the interlayer dielectric 24 and the top metal layer 25 along a preset direction to form a passivation layer 300, where the thickness of the passivation layer 300 is in the range of 0.5um to 2um, and then the passivation layer 300 is patterned by photolithography and reactive ion etching.

[0089] See also Fig.10 , the passivation layer 300 and the interlayer dielectric 24 are patterned by dry etching to form the initial shape of the recessed area 31. As an example, during the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the passivation layer 300 and the plasma enhanced tetraethyl orthosilicate of the interlayer dielectric 24 according to the fixed time specified in the process recipe, thereby removing the plasma enhanced nitride of the passivation layer 300 and the plasma enhanced tetraethyl orthosilicate of the interlayer dielectric 24.

[0090] See also Fig.11 The interlayer dielectric 24 is patterned by wet etching to form the final shape of the recessed area 31. As an example, during the wet etching process, the hydrofluoric acid 34 isotropically removes the plasma enhanced tetraethyl orthosilicate in a specific thickness in the interlayer dielectric 24 according to the fixed time specified in the process recipe. Due to the high selectivity between the plasma enhanced tetraethyl orthosilicate and the plasma enhanced nitride under the wet etching method, the shape of the passivation layer 300 will not be changed.

[0091] See also Fig.12 , an organic film layer 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recessed area 31. As an example, the thickness of the organic film layer 400 is 4um to 8um.

[0092] Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100 .

[0093] The difference from the above embodiments is that when the number of the passivation layer is more than 2, the formation method of the recessed area 31 is different.

[0094] See also Fig.13 The passivation layer 300 includes: a first passivation layer 301 and a second passivation layer 302 , wherein the second passivation layer 302 is provided with a first recessed portion 311 , and the first passivation layer 301 is provided with a second recessed portion 312 .

[0095] The first passivation layer 301 is disposed along a preset direction on the surface of the edge main structure layer 200. As an example, the first passivation layer 301 is formed by depositing plasma enhanced tetraethyl orthosilicate on the surface of the interlayer dielectric 24 and the top metal layer 25 along a preset direction, and the thickness of the first passivation layer 301 is in the range of 1um to 2um.

[0096] The second passivation layer 302 is disposed on the surface of the first passivation layer 301 along a preset direction. As an example, the second passivation layer 302 is formed by depositing plasma enhanced nitride on the surface of the first passivation layer 301 along a preset direction. The thickness of the second passivation layer 302 is in the range of 0.5um to 2um. Then, the first passivation layer 301 and the second passivation layer 302 are patterned by photolithography and reactive ion etching.

[0097] See also Fig.14 , the second passivation layer 302 is patterned by dry etching to form a first recessed portion 311. As an example, during the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the second passivation layer 302 for a fixed time specified in the process recipe, thereby removing the plasma enhanced nitride of the second passivation layer 302 and stopping at the first passivation layer 301.

[0098] See also Fig.15 The first passivation layer 301 is patterned by wet etching to form a second recessed portion 312. As an example, during the wet etching process, hydrofluoric acid 34 isotropically removes a specific thickness of plasma-enhanced tetraethyl orthosilicate in the first passivation layer 301 for a fixed time specified in the process recipe. Due to the high selectivity between plasma-enhanced tetraethyl orthosilicate and plasma-enhanced nitride under the wet etching method, the shape of the second passivation layer 302 will not be changed. The second recessed portion 312 extends into the interlayer dielectric 24.

[0099] See also Fig.16 , an organic film layer 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recessed area 31. As an example, the thickness of the organic film layer 400 is 4um to 8um. The difference from the above-mentioned embodiments is that after the polyimide is filled into the second recessed portion 312, the polyimide can firmly solidify the first passivation layer 301, the second passivation layer 302 and the interlayer dielectric 24.

[0100] Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100 .

[0101] The difference from the above embodiments is that the initial shape of the recessed area 31 can be formed on the second passivation layer 302 and the first passivation layer 301 , and the final shape of the recessed area 31 is formed later.

[0102] The formation process of the first passivation layer 301 and the second passivation layer 302 may refer to the above embodiment, which will not be described again.

[0103] See also Fig.17 , the second passivation layer 302 and the first passivation layer 301 are patterned and processed respectively by dry etching to form the initial shape of the recessed area 31. As an example, during the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the second passivation layer 302 and the plasma enhanced tetraethyl orthosilicate of the first passivation layer 301 according to the fixed time specified in the process recipe, thereby removing the plasma enhanced nitride of the second passivation layer 302 and the plasma enhanced tetraethyl orthosilicate of the first passivation layer 301 to form the initial shape of the recessed area 31. During dry etching, the reactive ions 33 can etch a portion of the thickness of the first passivation layer 301, and the remaining portion of the thickness of the first passivation layer 301 is etched by wet etching; the reactive ions 33 can also etch the entire thickness of the first passivation layer 301 in a penetrating manner; the reactive ions 33 can even continue to etch a portion of the thickness of the interlayer dielectric 24 after etching the first passivation layer 301.

[0104] See also Fig.18 The first passivation layer 301 is patterned by wet etching to form the final shape of the recessed area 31. As an example, during the wet etching process, the hydrofluoric acid 34 isotropically removes the plasma enhanced tetraethyl orthosilicate in a specific thickness in the first passivation layer 301 and the plasma enhanced tetraethyl orthosilicate in the interlayer dielectric 24 according to the fixed time specified in the process recipe. Due to the high selectivity between the plasma enhanced tetraethyl orthosilicate and the plasma enhanced nitride under the wet etching method, the shape of the second passivation layer 302 will not be changed.

[0105] See also Fig.19 , an organic film layer 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recessed area 31. As an example, the thickness of the organic film layer 400 is 4um to 8um.

[0106] Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100 .

[0107] In the above-mentioned embodiments, the connection between the first recessed portion 311 and the second recessed portion 312 may be a step transition or a curved surface transition. Since the maximum width of the second recessed portion 312 is greater than the maximum width of the first recessed portion 311, after the polyimide fills the first recessed portion 311 and the second recessed portion 312, the polyimide can be more firmly solidified with the passivation layer 300 or the passivation layer 300 and the interlayer dielectric 24 or the first passivation layer 301 and the second passivation layer 302 or the first passivation layer 301, the second passivation layer 302 and the interlayer dielectric 24.

[0108] In the above embodiments, the planar pattern of each recessed area 31 (anchor area) includes a plurality of rows of stripes, dotted lines or dot matrixes. Generally, the number of rows of the planar pattern of the recessed area 31 is 1 to 5.

[0109] See also Fig. 20 The plane pattern of the recessed area 31 is in the shape of a strip, and the strip surrounds the entire junction terminal extension structure of the chip. As an example, the plane pattern of the recessed area 31 is formed by two rows of strips, the width of the strips is in the range of 3um to 7um, and the distance between the strips is in the range of 3um to 10um.

[0110] See also Fig.21The plane pattern of the recessed area 31 is in the form of a dotted line, and the dotted line surrounds the entire junction terminal extension structure of the chip, and each row of dotted lines can be aligned or staggered. As an example, the plane pattern of the recessed area 31 is formed by two rows of dotted lines staggered with each other, the width and spacing of the dotted lines are both in the range of 3um to 7um, the length of the dotted lines is in the range of 5um to 10um, and the distance between the dotted lines is in the range of 3um to 10um.

[0111] See also Fig. 22 The plane pattern of the recessed area 31 is in a dot matrix shape, and the dot matrix surrounds the entire junction terminal extension structure of the chip, and each row of dot matrix shapes can be aligned or staggered. As an example, the plane pattern of the recessed area 31 is formed by two rows of dot matrix shapes staggered with each other, and the diameter and spacing of the dot matrix shapes are both in the range of 3um to 7um, and the distance between the dot matrix shapes is in the range of 3um to 10um.

[0112] So far, this article takes a single passivation layer or a double passivation layer as an example to provide the structural principle and generation principle of the chip edge structure of the above-mentioned various embodiments. It can be understood that the embodiments listed in this article are to assist in explaining the chip edge structure and are not used to limit the protection scope of the present invention. A person skilled in the art can also generate a chip edge structure including three passivation layers or four passivation layers, etc. according to the content taught by the present invention. For example, on the surface of the second passivation layer 302 described in each embodiment of this article, a third passivation layer is deposited again, wherein the material of the first passivation layer is the same as that of the third passivation layer, and the material of the first passivation layer and the third passivation layer is different from the material of the second passivation layer. For another example, a fourth passivation layer is deposited again on the surface of the third passivation layer, wherein the material of the first passivation layer is the same as that of the third passivation layer, the material of the second passivation layer is the same as that of the fourth passivation layer, and the material of the first passivation layer is different from the material of the second passivation layer. By analogy, a person skilled in the art can generate a chip edge structure with more passivation layers under the content taught by the present invention, which will not be repeated here.

[0113] As another aspect of the present invention, the present invention provides a method for manufacturing a chip edge structure. Fig.23 , the method S500 for manufacturing a chip edge structure includes:

[0114] S51, providing an edge main structure layer;

[0115] S52, depositing a passivation layer on the surface of the edge main structure layer;

[0116] S53, patterning the passivation layer to form at least one recessed area;

[0117] S54, forming an organic film layer on the surface of the passivation layer, and the organic film layer fills each recessed area.

[0118] Since the organic film layer fills the recessed area of ​​the passivation layer, the organic film layer can be firmly solidified with the passivation layer, so the organic film layer or the passivation layer is not likely to fall off during the process.

[0119] In some embodiments, S53 includes: patterning the passivation layer by dry etching to form at least one recessed region.

[0120] In some embodiments, the edge main structure layer includes a substrate, an epitaxial layer, a doped junction region, an interlayer dielectric and a top metal layer, the epitaxial layer is arranged on the surface of the substrate, the doped junction region is arranged in the surface area of ​​the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate, the interlayer dielectric is arranged on a portion of the surface of the epitaxial layer and contacts the doped junction region, the top metal layer is arranged on the surface of the doped junction region and contacts the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer.

[0121] In some embodiments, each recessed region includes a first recessed portion and a second recessed portion, and the passivation layer and the interlayer dielectric are made of different materials. Fig.24 , S53 includes:

[0122] S531, patterning the passivation layer by dry etching to form a first recessed portion;

[0123] S532, patterning the interlayer dielectric by wet etching to form a second recessed portion.

[0124] In some embodiments, the first passivation layer and the interlayer dielectric are made of different materials. The passivation layer is plasma enhanced nitride, and the interlayer dielectric is plasma enhanced tetraethyl orthosilicate. Fig.25 , S53 includes:

[0125] S533, patterning the passivation layer and the interlayer dielectric by dry etching to form an initial shape of the recessed area;

[0126] S534, patterning the interlayer dielectric by wet etching to form a final shape of the recessed area.

[0127] In some embodiments, the passivation layer includes a first passivation layer and a second passivation layer. Fig.26 , S52 includes:

[0128] S521, depositing a first passivation layer on the surface of the interlayer dielectric and the top metal layer;

[0129] S522 , depositing a second passivation layer on the surface of the first passivation layer.

[0130] In some embodiments, each recessed region includes a first recessed portion and a second recessed portion, and the first passivation layer and the second passivation layer are made of different materials. Fig. 27 , S53 includes:

[0131] S535, patterning the second passivation layer by dry etching to form a first recessed portion;

[0132] S536, patterning the first passivation layer by wet etching to form a second recessed portion.

[0133] In some embodiments, each recessed region includes a first recessed portion and a second recessed portion, the first passivation layer and the second passivation layer are made of different materials, the first passivation layer and the interlayer dielectric are made of the same material, the first passivation layer and the interlayer dielectric are both made of plasma enhanced tetraethyl orthosilicate, and the second passivation layer is made of plasma enhanced nitride. Fig.28 , S53 includes:

[0134] S537, patterning the second passivation layer and the first passivation layer respectively by dry etching to form an initial shape of the recessed area;

[0135] S538, patterning the first passivation layer by wet etching to form a final shape of the recessed area.

[0136] It should be noted that, in each of the above embodiments, there is not necessarily a certain order between the above steps. A person skilled in the art can understand, based on the description of the embodiments of the present invention, that in different embodiments, the above steps may have different execution orders, that is, they may be executed in parallel, may be executed interchangeably, and so on.

[0137] It should be noted that for technical details that are not described in detail in the embodiment of the method for manufacturing the chip edge structure, reference may be made to the chip edge structure provided in the embodiment of the present invention.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip edge structure, characterized in that: include: Edge main structure layer; A passivation layer is arranged on the surface of the edge main structure layer along a preset direction, and the passivation layer has at least one recessed area; an organic film layer, arranged on the surface of the passivation layer along the preset direction and filling each of the recessed areas, each of the recessed areas comprising a first recessed portion and a second recessed portion, the first recessed portion being connected to the second recessed portion, the maximum width of the second recessed portion being greater than the maximum width of the first recessed portion in a direction perpendicular to the preset direction, and the second recessed portion being located below the first recessed portion; Wherein, the passivation material used in the passivation layer is plasma enhanced tetraethyl orthosilicate or plasma enhanced nitride.

2. The chip edge structure according to claim 1, characterized in that: The edge main structure layer comprises: substrate; an epitaxial layer, arranged on the surface of the substrate along the preset direction; A doped junction region is disposed in a surface region of the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate; An interlayer dielectric, disposed on a portion of the surface of the epitaxial layer along the preset direction and in contact with the doped junction region; A top metal layer is disposed on the surface of the doped junction region along the preset direction and contacts the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer along the preset direction.

3. The chip edge structure according to claim 2, characterized in that: The second recess is in contact with the interlayer dielectric.

4. The chip edge structure according to claim 1, characterized in that: The passivation layer comprises: A first passivation layer is arranged on the surface of the edge main structure layer along the preset direction; The second passivation layer is arranged on the surface of the first passivation layer along the preset direction, wherein the second passivation layer is provided with the first recessed portion, and the first passivation layer is provided with the second recessed portion.

5. The chip edge structure according to claim 2, characterized in that: The substrate includes any one of the following: a silicon carbide substrate, a silicon substrate and a gallium nitride substrate.

6. The chip edge structure according to any one of claims 1 to 5, characterized in that: The organic film layer includes a polyimide layer.

7. The chip edge structure according to any one of claims 1 to 5, characterized in that: The planar pattern of each of the concave areas includes one or more rows of stripe patterns, dotted line patterns or dot matrix patterns.

8. A method for manufacturing a chip edge structure, characterized in that: The method comprises: Providing an edge main structure layer; Depositing a passivation layer on the surface of the edge main structure layer; Patterning the passivation layer to form at least one recessed area; forming an organic film layer on the surface of the passivation layer along a preset direction, so that the organic film layer fills each of the recessed areas; Wherein, each of the recessed areas includes a first recessed portion and a second recessed portion, the first recessed portion is connected to the second recessed portion, and in a direction perpendicular to the preset direction, the maximum width of the second recessed portion is greater than the maximum width of the first recessed portion, and the second recessed portion is located below the first recessed portion.

9. The method according to claim 8, characterized in that The patterning process of the passivation layer to form at least one recessed area comprises: The passivation layer is patterned by dry etching to form at least one recessed area.

10. The method according to claim 8, characterized in that The edge main structure layer includes a substrate, an epitaxial layer, a doped junction region, an interlayer dielectric and a top metal layer, the epitaxial layer is arranged on the surface of the substrate, the doped junction region is arranged in the surface area of ​​the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate, the interlayer dielectric is arranged on a portion of the surface of the epitaxial layer and in contact with the doped junction region, the top metal layer is arranged on the surface of the doped junction region and in contact with the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer.

11. The method according to claim 10, characterized in that The passivation layer is plasma enhanced nitride, and the interlayer dielectric is plasma enhanced tetraethyl orthosilicate.

12. The method according to claim 10, characterized in that The passivation layer includes a first passivation layer and a second passivation layer; Wherein, depositing a passivation layer on the surface of the edge main structure layer comprises: Depositing the first passivation layer on the surface of the interlayer dielectric and the top metal layer; The second passivation layer is deposited on the surface of the first passivation layer.

13. The method according to claim 12, characterized in that The first passivation layer and the second passivation layer are made of different materials; The patterning of the passivation layer to form at least one recessed area comprises: Patterning the second passivation layer by dry etching to form the first recessed portion; The first passivation layer is patterned by wet etching to form the second recessed portion.

14. The method according to claim 12, characterized in that The first passivation layer and the second passivation layer are made of different materials, and the first passivation layer and the interlayer dielectric are made of the same material; The patterning of the passivation layer to form at least one recessed area comprises: Patterning the second passivation layer and the first passivation layer respectively by dry etching to form an initial shape of the recessed area; The first passivation layer is patterned by wet etching to form a final shape of the recessed area.

15. The method according to claim 13 or 14, characterized in that The first passivation layer and the interlayer dielectric are both plasma enhanced tetraethyl orthosilicate, and the second passivation layer is plasma enhanced nitride.

16. A chip edge structure, characterized in that: include: The edge main structure layer comprises a substrate, an epitaxial layer, a doped junction layer, an interlayer dielectric and a top metal layer, wherein the epitaxial layer is arranged on the surface of the substrate along a preset direction, and the doped junction region is arranged in the surface region of the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate; The interlayer dielectric is disposed on a portion of the surface of the epitaxial layer along the preset direction and is in contact with the doped junction region; The top metal layer is disposed on the surface of the doped junction region along the preset direction and contacts the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer along the preset direction; A passivation layer is arranged on the surface of the edge main structure layer along a preset direction, and the passivation layer has at least one recessed area; An organic film layer is arranged on the surface of the passivation layer along the preset direction and fills each of the recessed areas, each of the recessed areas includes a first recessed portion; The interlayer dielectric is provided with a second recessed portion, the first recessed portion is connected to the second recessed portion, the organic film layer fills the second recessed portion, and in a direction perpendicular to the preset direction, the maximum width of the second recessed portion is greater than the maximum width of the first recessed portion; Wherein, the passivation material used in the passivation layer is plasma enhanced tetraethyl orthosilicate or plasma enhanced nitride.

17. A method for manufacturing a chip edge structure, characterized in that: The method comprises: Providing an edge body structure layer, wherein the edge body structure layer comprises a substrate, an epitaxial layer, a doped junction region, an interlayer dielectric and a top metal layer, the epitaxial layer is arranged on the surface of the substrate, the doped junction region is arranged in the surface region of the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate, the interlayer dielectric is arranged on a portion of the surface of the epitaxial layer and contacts the doped junction region, the top metal layer is arranged on the surface of the doped junction region and contacts the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer; Depositing a passivation layer on the surface of the edge main structure layer; Patterning the passivation layer to form at least one recessed area; forming an organic film layer on the surface of the passivation layer along a preset direction, so that the organic film layer fills each of the recessed areas; Each of the recessed areas includes a first recessed portion, the interlayer dielectric is provided with a second recessed portion, the organic film layer fills the second recessed portion, the first recessed portion is connected to the second recessed portion, in a direction perpendicular to the preset direction, the maximum width of the second recessed portion is greater than the maximum width of the first recessed portion, and the second recessed portion is located below the first recessed portion; The passivation layer is made of a different material than the interlayer dielectric; The patterning of the passivation layer to form at least one recessed area comprises: Patterning the passivation layer by dry etching to form the first recessed portion; The interlayer dielectric is patterned by wet etching to form the second recessed portion.

18. A method for manufacturing a chip edge structure, characterized in that: The method comprises: Providing an edge body structure layer, wherein the edge body structure layer comprises a substrate, an epitaxial layer, a doped junction region, an interlayer dielectric and a top metal layer, the epitaxial layer is arranged on the surface of the substrate, the doped junction region is arranged in the surface region of the epitaxial layer and extends from the surface of the epitaxial layer toward the substrate, the interlayer dielectric is arranged on a portion of the surface of the epitaxial layer and contacts the doped junction region, the top metal layer is arranged on the surface of the doped junction region and contacts the interlayer dielectric, so that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer; Depositing a passivation layer on the surface of the edge main structure layer; Patterning the passivation layer to form at least one recessed area; forming an organic film layer on the surface of the passivation layer along a preset direction, so that the organic film layer fills each of the recessed areas; Each of the recessed areas includes a first recessed portion, the interlayer dielectric is provided with a second recessed portion, the organic film layer fills the second recessed portion, the first recessed portion is connected to the second recessed portion, in a direction perpendicular to the preset direction, the maximum width of the second recessed portion is greater than the maximum width of the first recessed portion, and the second recessed portion is located below the first recessed portion; The passivation layer is made of a different material than the interlayer dielectric; The patterning of the passivation layer to form at least one recessed area comprises: Patterning the passivation layer and the interlayer dielectric by dry etching to form an initial shape of the recessed area; The interlayer dielectric is patterned by wet etching to form a final shape of the recessed area.

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